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AM243x MCU+ SDK
09.00.00
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34 #ifndef CSLR_SOC_DEFINES_H_
35 #define CSLR_SOC_DEFINES_H_
53 #if defined(__aarch64__)
54 #define CSL_CACHE_L1P_LINESIZE (64U)
55 #define CSL_CACHE_L1D_LINESIZE (64U)
56 #define CSL_CACHE_L2_LINESIZE (64U)
57 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
58 #define CSL_CACHE_L1P_LINESIZE (32U)
59 #define CSL_CACHE_L1D_LINESIZE (32U)
60 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M')
70 #define CSL_CORE_ID_M4FSS0_0 (0U)
71 #define CSL_CORE_ID_R5FSS0_0 (1U)
72 #define CSL_CORE_ID_R5FSS0_1 (2U)
73 #define CSL_CORE_ID_R5FSS1_0 (3U)
74 #define CSL_CORE_ID_R5FSS1_1 (4U)
75 #define CSL_CORE_ID_A53SS0_0 (5U)
76 #define CSL_CORE_ID_A53SS0_1 (6U)
77 #define CSL_CORE_ID_MAX (7U)
87 #define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)
89 #define CSL_ARM_R5_CLUSTER_GROUP_ID_1 ((uint32_t) 0x01U)
99 #define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)
101 #define CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)
105 #define CSL_EPWM_PER_CNT (9U)
110 #define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)