This design implements Sigma delta interface on TI Sitara™ AM64x/AM243x. ICSS SDFM is a Sigma delta filter for phase current measurement. Only two lines are required for each channel, differential pair each for SDFM clock & SDFM data. Clock is provided by external device or internal device and data comes from sigma delta modulator in form of digital bit stream.
The Sigma delta filter is implemented on TI Sitara™ Devices. Design is split into three parts – Sigma delta hardware support in PRU, firmware running in PRU and driver running in ARM. Application is supposed to use the ICSS SDFM driver APIs to leverage SDFM functionality. SDK example uses the SDFM hardware capability in Slice 1 of PRU-ICSSG0.
Parameter | Default Value | Details |
---|---|---|
Normal current OSR | 64 | Tested with 16, 32, 64, 128 and 256 |
Over current OSR | 16 | Tested with 16, 32, 64, 128 and 256 |
Sigma Delta Modulator Clock | 20 MHz | Tested with 5MHz, 10MHz and 20MHz from clock from PRU-ICSSG ECAP and 5MHz clock from SoC EPWM1 |
Simulated EPWM frequency | 8 KHz | Tested up to 20KHz |
IEP frequency | 300 MHz | Tested with 200MHz, 225MHz and 300MHz |
Refer section 6.4.5.2.2.3.5 Sigma Delta (SD) Decimation Filtering in Technical Reference Manual(TRM) of AM243x for details.
Following section describes the firmware implementation of Sigma Delta Decimation Filter on PRU-ICSS.
This section describes normal current implementation. Its implementation is trigger based. It starts execution when the trigger point is acquired (first time CMP4 event hits) and performs four continuous samplings to bring the accumulator and differntiator registers to stable state for the configured normal current OSR.
Initially the CMP4 register is configured with the first sample trigger start time and then until the next third continuous normal current sample it is updated with the normal current OSR sampling time. At the end of the fourth normal current sample again, it is updated with the second sample start time if double update is enabled otherwise with the first sample trigger start time.
Normal current sampling is done per EPWM cycle.
Normal current sampling is done twice in one EPWM cycle.
This section describes the over current implementation. It performs continuous sampling (free run) and when the sample value crosses the high or low threshold, the corresponding GPIO pin goes high.
This section describes the EPWM to SDFM synchronization and trigger timing for each EPWM cycle. At the end of the every EPWM cycle, the EPWM generates a sync out event that resets the IEP timer. The firmware initiates normal current sampling at the sample trigger point in each EPWM cycle. It takes four consecutive samples to bring the accumulator and differentiator registers to stable state. It takes the first sample at the trigger point and the next three samples, each after ONE_SAMPLE_TIME. Here ONE_SAMPLE_TIME is: OSR*(1/SD_CLK)
Pin name | Signal name | Function |
---|---|---|
GPIO_HIGH_TH_CH0 | MCU_SPI0_D1/B6 | Ch0 High threshold output |
GPIO_LOW_TH_CH0 | MCU_SPI1_D0/C7 | Ch0 low threshold output |
GPIO_HIGH_TH_CH1 | MCU_SPI1_CS0/A7 | Ch1 High threshold output |
GPIO_LOW_TH_CH1 | MCU_SPI1_CLK/D7 | Ch1 low threshold output |
GPIO_HIGH_TH_CH2 | MCU_SPI1_D1/C8 | Ch2 High threshold output |
GPIO_LOW_TH_CH2 | MCU_SPI0_CLK/E6 | Ch2 Low threshold output |
SD0_D | PIN_PRG0_PRU0_GPO1 | Channel0 data input |
SD1_D | PIN_PRG0_PRU0_GPO3 | Channel1 data input |
SD2_D | PIN_PRG0_PRU0_GPO5 | Channel2 data input |
PRG0_ECAP0_IN_APWM_OUT | PIN_PRG0_PRU1_GPO15 | ECAP output frequency |
GPIO_MTR_1_PWM_EN | GPMC0_AD15/Y20 | Enable EPWM0 on 3-axis board |
SD8_CLK | PIN_PRG0_PRU0_GPO16 | Comman SDFM clock input pin |
Pin name | Signal name | Function |
---|---|---|
GPIO_HIGH_TH_CH0 | PRG1_PRU0_GPO18 | (J7.64)Ch0 High threshold output |
GPIO_LOW_TH_CH0 | PRG0_PRU1_GPO11 | (J7.70)Ch0 low threshold output |
GPIO_HIGH_TH_CH1 | PRG1_PRU0_GPO17 | (J7.65)Ch1 High threshold output |
GPIO_LOW_TH_CH1 | PRG1_PRU0_GPO7 | (J7.66)Ch1 low threshold output |
GPIO_HIGH_TH_CH2 | PRG0_PRU1_GPO1 | (J7.67)Ch2 High threshold output |
GPIO_LOW_TH_CH2 | PRG0_PRU1_GPO2 | (J7.68)Ch2 Low threshold output |
SD0_D | PIN_PRG0_PRU0_GPO1 | (J4.32)Channel0 data input |
SD1_D | PIN_PRG0_PRU0_GPO3 | (J2.19)Channel1 data input |
SD2_D | PIN_PRG0_PRU0_GPO5 | (J2.13)Channel2 data input |
PRG0_ECAP0_IN_APWM_OUT | PIN_PRG0_PRU1_GPO15 | (J6.59)ECAP output frequency |
SD8_CLK | PIN_PRG0_PRU0_GPO16 | (J1.7)Comman SDFM clock input pin |