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AM263x MCU+ SDK
09.02.00
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Go to the documentation of this file.
66 #include <sdl/include/hw_types.h>
67 #include <sdl/include/sdl_types.h>
69 #include <sdl/stc/v0/soc/sdl_soc_stc.h>
109 #define STC_MSS_INTERVAL_NUM (uint32_t)(1U)
110 #define STC_MSS_LP_SCAN_MODE (uint32_t)(0U)
111 #define STC_MSS_CODEC_SPREAD_MODE (uint32_t)(1U)
112 #define STC_MSS_CAP_IDLE_CYCLE (uint32_t)(3U)
113 #define STC_MSS_SCANEN_HIGH_CAP_IDLE_CYCLE (uint32_t)(3U)
114 #define STC_MSS_MAX_RUN_TIME (uint32_t)(0xFFFFFFFFU)
115 #define STC_MSS_CLK_DIV (uint32_t)(1U)
116 #define STC_ROM_START_ADDRESS (uint32_t)(0U)
117 #define STC_pROM_START_ADDRESS (uint32_t)(1U)
124 #define STC_DSS_INTERVAL_NUM (uint32_t)(1U)
125 #define STC_DSS_LP_SCAN_MODE (uint32_t)(0U)
126 #define STC_DSS_CODEC_SPREAD_MODE (uint32_t)(1U)
127 #define STC_DSS_CAP_IDLE_CYCLE (uint32_t)(3U)
128 #define STC_DSS_SCANEN_HIGH_CAP_IDLE_CYCLE (uint32_t)(3U)
129 #define STC_DSS_MAX_RUN_TIME (uint32_t)(0xFFFFFFFFU)
130 #define STC_DSS_CLK_DIV (uint32_t)(1U)
131 #define STC_ROM_START_ADDRESS (uint32_t)(0U)
132 #define STC_pROM_START_ADDRESS (uint32_t)(1U)
425 #define SDL_STC_STCGCR0 (0x00000000U)
426 #define SDL_STC_STCGCR1 (0x00000004U)
427 #define SDL_STC_STCTPR (0x00000008U)
428 #define SDL_STC_CADDR (0x0000000CU)
429 #define SDL_STC_STCCICR (0x00000010U)
430 #define SDL_STC_STCGSTAT (0x00000014U)
431 #define SDL_STC_STCFSTAT (0x00000018U)
432 #define SDL_STC_STCSCSCR (0x0000001CU)
433 #define SDL_STC_CADDR2 (0x00000020U)
434 #define SDL_STC_CLKDIV (0x00000024U)
435 #define SDL_STC_SEGPLR (0x00000028U)
436 #define SDL_STC_SEG0_START_ADDR (0x0000002CU)
437 #define SDL_STC_SEG1_START_ADDR (0x00000030U)
438 #define SDL_STC_SEG2_START_ADDR (0x00000034U)
439 #define SDL_STC_SEG3_START_ADDR (0x00000038U)
449 #define SDL_STC_STCGCR0_INTCOUNT_B16_MASK (0xFFFF0000U)
450 #define SDL_STC_STCGCR0_INTCOUNT_B16_SHIFT (16U)
451 #define SDL_STC_STCGCR0_INTCOUNT_B16_MAX (0xFFFF0000U)
453 #define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MASK (0x00000700U)
454 #define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_SHIFT (8U)
455 #define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MAX (0x00000700U)
457 #define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MASK (0x000000E0U)
458 #define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_SHIFT (5U)
459 #define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MAX (0x000000E0U)
461 #define SDL_STC_STCGCR0_RS_CNT_B1_MASK (0x00000003U)
462 #define SDL_STC_STCGCR0_RS_CNT_B1_SHIFT (0U)
467 #define SDL_STC_SEG0_CORE_SEL_MASK (0x00000F00U)
468 #define SDL_STC_SEG0_CORE_SEL_SHIFT (8U)
469 #define SDL_STC_SEG0_CORE_SEL_ENABLE (0x1U)
472 #define SDL_STC_CODEC_SPREAD_MODE_MASK (0x00000040U)
473 #define SDL_STC_CODEC_SPREAD_MODE_SHIFT (6U)
474 #define SDL_STC_CODEC_SPREAD_MODE_ENABLE (0x1U)
475 #define SDL_STC_CODEC_SPREAD_MODE_DISABLE (0x0U)
477 #define SDL_STC_LP_SCAN_MODE_MASK (0x00000020U)
478 #define SDL_STC_LP_SCAN_MODE_SHIFT (5U)
479 #define SDL_STC_LP_SCAN_MODE_ENABLE (0x1U)
480 #define SDL_STC_LP_SCAN_MODE_DISABLE (0x0U)
483 #define SDL_STC_ROM_ACCESS_INV_MASK (0x00000010U)
484 #define SDL_STC_ROM_ACCESS_INV_SHIFT (4U)
485 #define SDL_STC_ROM_ACCESS_INV_DISABLE (0x0U)
487 #define SDL_STC_ST_ENA_B4_MASK (0x0000000FU)
488 #define SDL_STC_ST_ENA_B4_SHIFT (0x00000000U)
489 #define SDL_STC_ST_ENA_B4_ENABLE (0xAU)
495 #define SDL_STC_TO_PRELOAD_MASK (0xFFFFFFFFU)
496 #define SDL_STC_TO_PRELOAD_SHIFT (0x00000000U)
497 #define SDL_STC_TO_PRELOAD_MAX (0xFFFFFFFFU)
501 #define SDL_STC_ADDR1_MASK (0xFFFFFFFFU)
502 #define SDL_STC_ADDR1_SHIFT (0x00000000U)
507 #define SDL_STC_CORE2_ICOUNT_MASK (0xFFFF0000U)
508 #define SDL_STC_CORE2_ICOUNT_SHIFT (16U)
510 #define SDL_STC_CORE1_ICOUNT_MASK (0x0000FFFFU)
511 #define SDL_STC_CORE1_ICOUNT_SHIFT (0x00000000U)
516 #define SDL_STC_ST_ACTIVE_MASK (0x00000F00U)
517 #define SDL_STC_ST_ACTIVE_SHIFT (8U)
518 #define SDL_STC_ST_ACTIVE_ENABLE (0xAU)
521 #define SDL_STC_TEST_FAIL_MASK (0x00000002U)
522 #define SDL_STC_TEST_FAIL_SHIFT (1U)
523 #define SDL_STC_TEST_FAIL_ENABLE (0x1U)
524 #define SDL_STC_TEST_FAIL_DISABLE (0x0U)
526 #define SDL_STC_TEST_DONE_MASK (0x00000001U)
527 #define SDL_STC_TEST_DONE_SHIFT (0U)
528 #define SDL_STC_TEST_DONE_ENABLE (0x1U)
529 #define SDL_STC_TEST_DONE_DISABLE (0x0U)
533 #define SDL_STC_FSEG_ID_MASK (0x00000018U)
534 #define SDL_STC_FSEG_ID_SHIFT (3U)
537 #define SDL_STC_TO_ER_B1_MASK (0x00000004U)
538 #define SDL_STC_TO_ER_B1_SHIFT (2U)
539 #define SDL_STC_TO_ER_B1_ENABLE (0x1U)
540 #define SDL_STC_TO_ER_B1_DISABLE (0x0U)
542 #define SDL_STC_CPU2_FAIL_B1_MASK (0x00000002U)
543 #define SDL_STC_CPU2_FAIL_B1_SHIFT (0x1U)
544 #define SDL_STC_CPU2_FAIL_B1_ENABLE (0x1U)
545 #define SDL_STC_CPU2_FAIL_B1_DISABLE (0x0U)
547 #define SDL_STC_CPU1_FAIL_B1_MASK (0x00000001U)
548 #define SDL_STC_CPU1_FAIL_B1_SHIFT (0U)
549 #define SDL_STC_CPU1_FAIL_B1_ENABLE (0x1U)
550 #define SDL_STC_CPU1_FAIL_B1_DISABLE (0x0U)
554 #define SDL_STC_FAULT_INS_B1_MASK (0x00000010U)
555 #define SDL_STC_FAULT_INS_B1_SHIFT (4U)
556 #define SDL_STC_FAULT_INS_B1_ENABLE (0x1U)
557 #define SDL_STC_FAULT_INS_B1_DISABLE (0x0U)
560 #define SDL_STC_SELF_CHECK_KEY_B4_MASK (0x0000000FU)
561 #define SDL_STC_SELF_CHECK_KEY_B4_SHIFT (0U)
562 #define SDL_STC_SELF_CHECK_KEY_B4_ENABLE (0xAU)
563 #define SDL_STC_SELF_CHECK_KEY_B4_DISABLE (0U)
569 #define SDL_STC_ADDR2_MASK (0xFFFFFFFFU)
570 #define SDL_STC_ADDR2_SHIFT (0x00000000U)
574 #define SDL_STC_CLKDIV0_MASK (0x07000000U)
575 #define SDL_STC_CLKDIV0_SHIFT (24U)
576 #define SDL_STC_CLKDIV1_MASK (0x00070000U)
577 #define SDL_STC_CLKDIV1_SHIFT (16U)
578 #define SDL_STC_CLKDIV2_MASK (0x00000700U)
579 #define SDL_STC_CLKDIV2_SHIFT (8U)
580 #define SDL_STC_CLKDIV3_MASK (0x00000007U)
581 #define SDL_STC_CLKDIV3_SHIFT (0U)
585 #define SDL_STC_SEGPLR_MASK (0x00000003U)
586 #define SDL_STC_SEGPLR_SHIFT (0U)
590 #define SDL_STC_SEG0_START_ADDR_MASK (0x000FFFFFU)
591 #define SDL_STC_SEG0_START_ADDR_SHIFT (0U)
595 #define SDL_STC_SEG1_START_ADDR0_MASK (0x000FFFFFU)
596 #define SDL_STC_SEG1_START_ADDR0_SHIFT (0U)
600 #define SDL_STC_SEG2_START_ADDR0_MASK (0x000FFFFFU)
601 #define SDL_STC_SEG2_START_ADDR0_SHIFT (0U)
605 #define SDL_STC_SEG3_START_ADDR0_MASK (0x000FFFFFU)
606 #define SDL_STC_SEG3_START_ADDR0_SHIFT (0U)
609 #define SDL_MSS_STC_RESET_MASK (0x00000004U)
610 #define SDL_MSS_STC_RESET_SHIFT (2U)
612 #define SDL_MSS_STC_RESET_CLEAR_MASK (0x00000007)
613 #define SDL_MSS_STC_RESET_CLEAR_SHIFT (0U)
614 #define SDL_MSS_STC_RESET_CLEAR_ENABLE (0x7U)
617 #define SDL_DSS_STC_RESET_MASK (0x00000020U)
618 #define SDL_DSS_STC_RESET_SHIFT (5U)
622 #define SDL_DSS_DSP_ICFG_PDCCMD_GEMPD_MASK (0x00010000U)
623 #define SDL_DSS_DSP_ICFG_PDCCMD_GEMPD_SHIFT (16U)
volatile uint32_t CORE1_CURMISR_8
Definition: stc/v0/sdl_stc.h:377
volatile uint32_t STCSCSCR
Definition: stc/v0/sdl_stc.h:343
volatile uint32_t CORE1_CURMISR_24
Definition: stc/v0/sdl_stc.h:409
volatile uint32_t CORE1_CURMISR_13
Definition: stc/v0/sdl_stc.h:387
volatile uint32_t CORE1_CURMISR_4
Definition: stc/v0/sdl_stc.h:369
int32_t SDL_STC_getStatus(SDL_STC_Inst instance)
This API is used to get status for STC result.
@ SDL_STC_COMPLETED_FAILURE
Definition: stc/v0/sdl_stc.h:203
uint32_t intervalNum
Definition: stc/v0/sdl_stc.h:171
volatile uint32_t CORE1_CURMISR_0
Definition: stc/v0/sdl_stc.h:361
volatile uint32_t CORE1_CURMISR_14
Definition: stc/v0/sdl_stc.h:389
@ SDL_STC_NEG_TEST
Definition: stc/v0/sdl_stc.h:218
volatile uint32_t CORE1_CURMISR_18
Definition: stc/v0/sdl_stc.h:397
volatile uint32_t SEG0_START_ADDR
Definition: stc/v0/sdl_stc.h:351
SDL_STC_TestResult
Definition: stc/v0/sdl_stc.h:199
volatile uint32_t CORE1_CURMISR_21
Definition: stc/v0/sdl_stc.h:403
volatile uint32_t CORE1_CURMISR_25
Definition: stc/v0/sdl_stc.h:411
volatile uint32_t STC_CADDR2
Definition: stc/v0/sdl_stc.h:345
volatile uint32_t CORE1_CURMISR_10
Definition: stc/v0/sdl_stc.h:381
@ SDL_STC_NOT_COMPLETED
Definition: stc/v0/sdl_stc.h:205
volatile uint32_t CORE1_CURMISR_3
Definition: stc/v0/sdl_stc.h:367
uint32_t codecSpreadMode
Definition: stc/v0/sdl_stc.h:158
volatile uint32_t CORE1_CURMISR_15
Definition: stc/v0/sdl_stc.h:391
volatile uint32_t CORE1_CURMISR_9
Definition: stc/v0/sdl_stc.h:379
volatile uint32_t CORE1_CURMISR_11
Definition: stc/v0/sdl_stc.h:383
void SDL_STC_dspInit(void)
This API is used to initialize all the required configuration in RCM & CTRL Module for performing DSP...
SDL_STC_Inst
Definition: sdl_stc_soc.h:79
uint32_t capIdleCycle
Definition: stc/v0/sdl_stc.h:160
volatile uint32_t STCGSTAT
Definition: stc/v0/sdl_stc.h:339
Structure containing parameters for STC module configuration.
Definition: stc/v0/sdl_stc.h:154
@ SDL_STC_TEST
Definition: stc/v0/sdl_stc.h:216
volatile uint32_t CORE1_CURMISR_22
Definition: stc/v0/sdl_stc.h:405
volatile uint32_t CORE1_CURMISR_17
Definition: stc/v0/sdl_stc.h:395
static int32_t SDL_STC_runTest(SDL_STC_Inst instance)
This API is used to enable the STC module.
uint32_t stcDiagnostic
Definition: stc/v0/sdl_stc.h:183
volatile uint32_t CORE1_CURMISR_2
Definition: stc/v0/sdl_stc.h:365
uint32_t faultInsert
Definition: stc/v0/sdl_stc.h:181
volatile uint32_t CORE1_CURMISR_6
Definition: stc/v0/sdl_stc.h:373
volatile uint32_t CORE1_CURMISR_7
Definition: stc/v0/sdl_stc.h:375
volatile uint32_t CORE1_CURMISR_19
Definition: stc/v0/sdl_stc.h:399
Definition: stc/v0/sdl_stc.h:169
@ INVALID_TEST
Definition: stc/v0/sdl_stc.h:220
volatile uint32_t CORE1_CURMISR_12
Definition: stc/v0/sdl_stc.h:385
volatile uint32_t STC_CLKDIV
Definition: stc/v0/sdl_stc.h:347
volatile uint32_t SEG1_START_ADDR
Definition: stc/v0/sdl_stc.h:353
@ SDL_STC_NOT_RUN
Definition: stc/v0/sdl_stc.h:207
static void SDL_Delay(void)
This API is used to execute asm nop operation.
uint32_t maxRunTime
Definition: stc/v0/sdl_stc.h:173
int32_t SDL_STC_selfTest(SDL_STC_Inst instance, SDL_STC_TestType testType, SDL_STC_Config *pConfig)
This API is used to run the STC module.
@ SDL_STC_COMPLETED_SUCCESS
Definition: stc/v0/sdl_stc.h:201
static void SDL_STC_delay(int32_t count)
This API is used to provide delay for processor core.
volatile uint32_t STCTPR
Definition: stc/v0/sdl_stc.h:333
SDL_STC_TestType
Definition: stc/v0/sdl_stc.h:214
static int32_t SDL_STC_configure(SDL_STC_Inst instance, SDL_STC_Config *pConfig, SDL_STC_TestType testType)
This API is used to configure STC module.
@ INVALID_RESULT
Definition: stc/v0/sdl_stc.h:209
volatile uint32_t CORE1_CURMISR_5
Definition: stc/v0/sdl_stc.h:371
volatile uint32_t STCGCR1
Definition: stc/v0/sdl_stc.h:331
volatile uint32_t STCCICR
Definition: stc/v0/sdl_stc.h:337
volatile uint32_t CORE1_CURMISR_20
Definition: stc/v0/sdl_stc.h:401
uint32_t clkDiv
Definition: stc/v0/sdl_stc.h:175
SDL_STC_ScanModeconfig modeConfig
Definition: stc/v0/sdl_stc.h:185
volatile uint32_t STCFSTAT
Definition: stc/v0/sdl_stc.h:341
This file contains the macro definations for Register layer.
uint32_t scanEnHighCap_idleCycle
Definition: stc/v0/sdl_stc.h:162
Definition: stc/v0/sdl_stc.h:327
volatile uint32_t CORE1_CURMISR_26
Definition: stc/v0/sdl_stc.h:413
volatile uint32_t STC_CADDR
Definition: stc/v0/sdl_stc.h:335
volatile uint32_t SEG3_START_ADDR
Definition: stc/v0/sdl_stc.h:357
volatile uint32_t CORE1_CURMISR_1
Definition: stc/v0/sdl_stc.h:363
volatile uint32_t CORE1_CURMISR_23
Definition: stc/v0/sdl_stc.h:407
volatile uint32_t CORE1_CURMISR_27
Definition: stc/v0/sdl_stc.h:415
uint32_t romStartAddress
Definition: stc/v0/sdl_stc.h:177
volatile uint32_t STC_SEGPLR
Definition: stc/v0/sdl_stc.h:349
volatile uint32_t STCGCR0
Definition: stc/v0/sdl_stc.h:329
volatile uint32_t SEG2_START_ADDR
Definition: stc/v0/sdl_stc.h:355
uint32_t pRomStartAdd
Definition: stc/v0/sdl_stc.h:179
volatile uint32_t CORE1_CURMISR_16
Definition: stc/v0/sdl_stc.h:393
uint32_t lpScanMode
Definition: stc/v0/sdl_stc.h:156