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AM263x MCU+ SDK
09.02.00
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63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
66 #include <drivers/hw_include/cslr_epwm.h>
79 #define EPWM_SYNC_OUT_SOURCE_M ((uint16_t)CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK |\
80 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK |\
81 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK |\
82 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK |\
83 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK |\
84 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK |\
85 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK)
94 #define EPWM_SYNC_OUT_PULSE_ON_SOFTWARE CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK
95 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK
97 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_B CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK
99 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_C CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK
101 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_D CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK
103 #define EPWM_SYNC_OUT_PULSE_ON_DCA_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK
105 #define EPWM_SYNC_OUT_PULSE_ON_DCB_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK
107 #define EPWM_SYNC_OUT_PULSE_ON_ALL EPWM_SYNC_OUT_SOURCE_M
389 #define EPWM_TIME_BASE_STATUS_COUNT_DOWN (0U)
390 #define EPWM_TIME_BASE_STATUS_COUNT_UP (1U)
793 #define EPWM_DB_INPUT_EPWMA (0U)
794 #define EPWM_DB_INPUT_EPWMB (1U)
796 #define EPWM_DB_INPUT_DB_RED (2U)
877 #define EPWM_TZ_SIGNAL_CBC1 (0x1U)
878 #define EPWM_TZ_SIGNAL_CBC2 (0x2U)
880 #define EPWM_TZ_SIGNAL_CBC3 (0x4U)
882 #define EPWM_TZ_SIGNAL_CBC4 (0x8U)
884 #define EPWM_TZ_SIGNAL_CBC5 (0x10U)
886 #define EPWM_TZ_SIGNAL_CBC6 (0x20U)
888 #define EPWM_TZ_SIGNAL_DCAEVT2 (0x40U)
890 #define EPWM_TZ_SIGNAL_DCBEVT2 (0x80U)
892 #define EPWM_TZ_SIGNAL_OSHT1 (0x100U)
894 #define EPWM_TZ_SIGNAL_OSHT2 (0x200U)
896 #define EPWM_TZ_SIGNAL_OSHT3 (0x400U)
898 #define EPWM_TZ_SIGNAL_OSHT4 (0x800U)
900 #define EPWM_TZ_SIGNAL_OSHT5 (0x1000U)
902 #define EPWM_TZ_SIGNAL_OSHT6 (0x2000U)
904 #define EPWM_TZ_SIGNAL_DCAEVT1 (0x4000U)
906 #define EPWM_TZ_SIGNAL_DCBEVT1 (0x8000U)
920 #define EPWM_TZ_SIGNAL_CAPEVT_CBC (0x1U)
921 #define EPWM_TZ_SIGNAL_CAPEVT_OST (0x100U)
1044 #define EPWM_TZ_INTERRUPT_CBC (0x2U)
1045 #define EPWM_TZ_INTERRUPT_OST (0x4U)
1047 #define EPWM_TZ_INTERRUPT_DCAEVT1 (0x8U)
1049 #define EPWM_TZ_INTERRUPT_DCAEVT2 (0x10U)
1051 #define EPWM_TZ_INTERRUPT_DCBEVT1 (0x20U)
1053 #define EPWM_TZ_INTERRUPT_DCBEVT2 (0x40U)
1055 #define EPWM_TZ_INTERRUPT_CAPEVT (0x80U)
1064 #define EPWM_TZ_FLAG_CBC (0x2U)
1065 #define EPWM_TZ_FLAG_OST (0x4U)
1067 #define EPWM_TZ_FLAG_DCAEVT1 (0x8U)
1069 #define EPWM_TZ_FLAG_DCAEVT2 (0x10U)
1071 #define EPWM_TZ_FLAG_DCBEVT1 (0x20U)
1073 #define EPWM_TZ_FLAG_DCBEVT2 (0x40U)
1075 #define EPWM_TZ_FLAG_CAPEVT (0x80U)
1085 #define EPWM_TZ_INTERRUPT (0x1U)
1095 #define EPWM_TZ_CBC_FLAG_1 (0x1U)
1096 #define EPWM_TZ_CBC_FLAG_2 (0x2U)
1098 #define EPWM_TZ_CBC_FLAG_3 (0x4U)
1100 #define EPWM_TZ_CBC_FLAG_4 (0x8U)
1102 #define EPWM_TZ_CBC_FLAG_5 (0x10U)
1104 #define EPWM_TZ_CBC_FLAG_6 (0x20U)
1106 #define EPWM_TZ_CBC_FLAG_DCAEVT2 (0x40U)
1108 #define EPWM_TZ_CBC_FLAG_DCBEVT2 (0x80U)
1110 #define EPWM_TZ_CBC_FLAG_CAPEVT (0x100U)
1121 #define EPWM_TZ_OST_FLAG_OST1 (0x1U)
1122 #define EPWM_TZ_OST_FLAG_OST2 (0x2U)
1124 #define EPWM_TZ_OST_FLAG_OST3 (0x4U)
1126 #define EPWM_TZ_OST_FLAG_OST4 (0x8U)
1128 #define EPWM_TZ_OST_FLAG_OST5 (0x10U)
1130 #define EPWM_TZ_OST_FLAG_OST6 (0x20U)
1132 #define EPWM_TZ_OST_FLAG_DCAEVT1 (0x40U)
1134 #define EPWM_TZ_OST_FLAG_DCBEVT1 (0x80U)
1136 #define EPWM_TZ_OST_FLAG_CAPEVT (0x100U)
1162 #define EPWM_TZ_FORCE_EVENT_CBC (0x2U)
1163 #define EPWM_TZ_FORCE_EVENT_OST (0x4U)
1165 #define EPWM_TZ_FORCE_EVENT_DCAEVT1 (0x8U)
1167 #define EPWM_TZ_FORCE_EVENT_DCAEVT2 (0x10U)
1169 #define EPWM_TZ_FORCE_EVENT_DCBEVT1 (0x20U)
1171 #define EPWM_TZ_FORCE_EVENT_DCBEVT2 (0x40U)
1173 #define EPWM_TZ_FORCE_EVENT_CAPEVT (0x80U)
1183 #define EPWM_TZ_SELECT_TRIPOUT_OST (0x1)
1184 #define EPWM_TZ_SELECT_TRIPOUT_CBC (0x2)
1186 #define EPWM_TZ_SELECT_TRIPOUT_TZ1 (0x4)
1188 #define EPWM_TZ_SELECT_TRIPOUT_TZ2 (0x8)
1190 #define EPWM_TZ_SELECT_TRIPOUT_TZ3 (0x10)
1192 #define EPWM_TZ_SELECT_TRIPOUT_TZ4 (0x20)
1194 #define EPWM_TZ_SELECT_TRIPOUT_TZ5 (0x40)
1196 #define EPWM_TZ_SELECT_TRIPOUT_TZ6 (0x80)
1198 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT1 (0x100)
1200 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT2 (0x200)
1202 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT1 (0x400)
1204 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT2 (0x800)
1206 #define EPWM_TZ_SELECT_TRIPOUT_CAPEVT (0x1000)
1216 #define EPWM_INT_TBCTR_ZERO (1U)
1217 #define EPWM_INT_TBCTR_PERIOD (2U)
1219 #define EPWM_INT_TBCTR_ETINTMIX (3U)
1221 #define EPWM_INT_TBCTR_U_CMPA (4U)
1223 #define EPWM_INT_TBCTR_U_CMPC (8U)
1225 #define EPWM_INT_TBCTR_D_CMPA (5U)
1227 #define EPWM_INT_TBCTR_D_CMPC (10U)
1229 #define EPWM_INT_TBCTR_U_CMPB (6U)
1231 #define EPWM_INT_TBCTR_U_CMPD (12U)
1233 #define EPWM_INT_TBCTR_D_CMPB (7U)
1235 #define EPWM_INT_TBCTR_D_CMPD (14U)
1245 #define EPWM_INT_MIX_TBCTR_ZERO (0x1)
1246 #define EPWM_INT_MIX_TBCTR_PERIOD (0x2)
1248 #define EPWM_INT_MIX_TBCTR_U_CMPA (0x4)
1250 #define EPWM_INT_MIX_TBCTR_D_CMPA (0x8)
1252 #define EPWM_INT_MIX_TBCTR_U_CMPB (0x10)
1254 #define EPWM_INT_MIX_TBCTR_D_CMPB (0x20)
1256 #define EPWM_INT_MIX_TBCTR_U_CMPC (0x40)
1258 #define EPWM_INT_MIX_TBCTR_D_CMPC (0x80)
1260 #define EPWM_INT_MIX_TBCTR_U_CMPD (0x100)
1262 #define EPWM_INT_MIX_TBCTR_D_CMPD (0x200)
1264 #define EPWM_INT_MIX_DCAEVT1 (0x400)
1375 #define EPWM_DC_COMBINATIONAL_TRIPIN1 (0x1U)
1376 #define EPWM_DC_COMBINATIONAL_TRIPIN2 (0x2U)
1378 #define EPWM_DC_COMBINATIONAL_TRIPIN3 (0x4U)
1380 #define EPWM_DC_COMBINATIONAL_TRIPIN4 (0x8U)
1382 #define EPWM_DC_COMBINATIONAL_TRIPIN5 (0x10U)
1384 #define EPWM_DC_COMBINATIONAL_TRIPIN6 (0x20U)
1386 #define EPWM_DC_COMBINATIONAL_TRIPIN7 (0x40U)
1388 #define EPWM_DC_COMBINATIONAL_TRIPIN8 (0x80U)
1390 #define EPWM_DC_COMBINATIONAL_TRIPIN9 (0x100U)
1392 #define EPWM_DC_COMBINATIONAL_TRIPIN10 (0x200U)
1394 #define EPWM_DC_COMBINATIONAL_TRIPIN11 (0x400U)
1396 #define EPWM_DC_COMBINATIONAL_TRIPIN12 (0x800U)
1398 #define EPWM_DC_COMBINATIONAL_TRIPIN13 (0x1000U)
1400 #define EPWM_DC_COMBINATIONAL_TRIPIN14 (0x2000U)
1402 #define EPWM_DC_COMBINATIONAL_TRIPIN15 (0x4000U)
1430 #define EPWM_DC_TBCTR_ZERO (0x1)
1431 #define EPWM_DC_TBCTR_PERIOD (0x2)
1433 #define EPWM_DC_TBCTR_U_CMPA (0x4)
1435 #define EPWM_DC_TBCTR_D_CMPA (0x8)
1437 #define EPWM_DC_TBCTR_U_CMPB (0x10)
1439 #define EPWM_DC_TBCTR_D_CMPB (0x20)
1441 #define EPWM_DC_TBCTR_U_CMPC (0x40)
1443 #define EPWM_DC_TBCTR_D_CMPC (0x80)
1445 #define EPWM_DC_TBCTR_U_CMPD (0x100)
1447 #define EPWM_DC_TBCTR_D_CMPD (0x200)
1594 #define EPWM_GL_REGISTER_TBPRD_TBPRDHR (0x1U)
1595 #define EPWM_GL_REGISTER_CMPA_CMPAHR (0x2U)
1597 #define EPWM_GL_REGISTER_CMPB_CMPBHR (0x4U)
1599 #define EPWM_GL_REGISTER_CMPC (0x8U)
1601 #define EPWM_GL_REGISTER_CMPD (0x10U)
1603 #define EPWM_GL_REGISTER_DBRED_DBREDHR (0x20U)
1605 #define EPWM_GL_REGISTER_DBFED_DBFEDHR (0x40U)
1607 #define EPWM_GL_REGISTER_DBCTL (0x80U)
1609 #define EPWM_GL_REGISTER_AQCTLA_AQCTLA2 (0x100U)
1611 #define EPWM_GL_REGISTER_AQCTLB_AQCTLB2 (0x200U)
1613 #define EPWM_GL_REGISTER_AQCSFRC (0x400U)
1747 #define EPWM_MINDB_BLOCK_A (0x0U)
1748 #define EPWM_MINDB_BLOCK_B (0x1U)
1757 #define EPWM_MINDB_NO_INVERT (0x0)
1758 #define EPWM_MINDB_INVERT (0x1)
1767 #define EPWM_MINDB_INVERT_LOGICAL_AND (0x0)
1768 #define EPWM_MINDB_LOGICAL_OR (0x1)
1777 #define EPWM_MINDB_PWMB (0x0)
1778 #define EPWM_MINDB_PWM_OUTXBAR_OUT1 (0x1)
1780 #define EPWM_MINDB_PWM_OUTXBAR_OUT2 (0x2)
1782 #define EPWM_MINDB_PWM_OUTXBAR_OUT3 (0x3)
1784 #define EPWM_MINDB_PWM_OUTXBAR_OUT4 (0x4)
1786 #define EPWM_MINDB_PWM_OUTXBAR_OUT5 (0x5)
1788 #define EPWM_MINDB_PWM_OUTXBAR_OUT6 (0x6)
1790 #define EPWM_MINDB_PWM_OUTXBAR_OUT7 (0x7)
1792 #define EPWM_MINDB_PWM_OUTXBAR_OUT8 (0x8)
1794 #define EPWM_MINDB_PWM_OUTXBAR_OUT9 (0x9)
1796 #define EPWM_MINDB_PWM_OUTXBAR_OUT10 (0xA)
1798 #define EPWM_MINDB_PWM_OUTXBAR_OUT11 (0xB)
1800 #define EPWM_MINDB_PWM_OUTXBAR_OUT12 (0xC)
1802 #define EPWM_MINDB_PWM_OUTXBAR_OUT13 (0xD)
1804 #define EPWM_MINDB_PWM_OUTXBAR_OUT14 (0xE)
1806 #define EPWM_MINDB_PWM_OUTXBAR_OUT15 (0xF)
1815 #define EPWM_MINDB_BLOCKING_SIGNAL_SAME (0x0)
1816 #define EPWM_MINDB_BLOCKING_SIGNAL_DIFF (0x1)
1825 #define EPWM_MINDB_ICSS_XBAR_OUT0 (0x0)
1826 #define EPWM_MINDB_ICSS_XBAR_OUT1 (0x1)
1828 #define EPWM_MINDB_ICSS_XBAR_OUT2 (0x2)
1830 #define EPWM_MINDB_ICSS_XBAR_OUT3 (0x3)
1832 #define EPWM_MINDB_ICSS_XBAR_OUT4 (0x4)
1834 #define EPWM_MINDB_ICSS_XBAR_OUT5 (0x5)
1836 #define EPWM_MINDB_ICSS_XBAR_OUT6 (0x6)
1838 #define EPWM_MINDB_ICSS_XBAR_OUT7 (0x7)
1840 #define EPWM_MINDB_ICSS_XBAR_OUT8 (0x8)
1842 #define EPWM_MINDB_ICSS_XBAR_OUT9 (0x9)
1844 #define EPWM_MINDB_ICSS_XBAR_OUT10 (0xA)
1846 #define EPWM_MINDB_ICSS_XBAR_OUT11 (0xB)
1848 #define EPWM_MINDB_ICSS_XBAR_OUT12 (0xC)
1850 #define EPWM_MINDB_ICSS_XBAR_OUT13 (0xD)
1852 #define EPWM_MINDB_ICSS_XBAR_OUT14 (0xE)
1854 #define EPWM_MINDB_ICSS_XBAR_OUT15 (0xF)
2076 #define EPWM_XCMP_ACTIVE (0x0U)
2077 #define EPWM_XCMP_SHADOW1 (0x1U)
2079 #define EPWM_XCMP_SHADOW2 (0x2U)
2081 #define EPWM_XCMP_SHADOW3 (0x3U)
2492 #define EPWM_DE_CHANNEL_A (0x0U)
2493 #define EPWM_DE_CHANNEL_B (0x1U)
2503 #define EPWM_DE_COUNT_UP (0x0U)
2504 #define EPWM_DE_COUNT_DOWN (0x1U)
2514 #define EPWM_DE_TRIPL (0x1U)
2515 #define EPWM_DE_TRIPH (0x0U)
2525 #define EPWM_CAPGATE_INPUT_ALWAYS_ON (0U)
2526 #define EPWM_CAPGATE_INPUT_ALWAYS_OFF (1U)
2528 #define EPWM_CAPGATE_INPUT_SYNC (2U)
2530 #define EPWM_CAPGATE_INPUT_SYNC_INVERT (3U)
2540 #define EPWM_CAPTURE_INPUT_CAPIN_SYNC (0U)
2541 #define EPWM_CAPTURE_INPUT_CAPIN_SYNC_INVERT (1U)
2553 #define EPWM_CAPTURE_GATE (1U)
2554 #define EPWM_CAPTURE_INPUT (0U)
2564 #define EPWM_AQ_A_SW_DISABLED_B_SW_DISABLED (0x0U)
2565 #define EPWM_AQ_A_SW_OUTPUT_LOW_B_SW_DISABLED (0x1U)
2567 #define EPWM_AQ_A_SW_OUTPUT_HIGH_B_SW_DISABLED (0x2U)
2569 #define EPWM_AQ_A_SW_DISABLED_B_SW_OUTPUT_LOW (0x4U)
2571 #define EPWM_AQ_A_SW_OUTPUT_LOW_B_SW_OUTPUT_LOW (0x5U)
2573 #define EPWM_AQ_A_SW_OUTPUT_HIGH_B_SW_OUTPUT_LOW (0x6U)
2575 #define EPWM_AQ_A_SW_DISABLED_B_SW_OUTPUT_HIGH (0x8U)
2577 #define EPWM_AQ_A_SW_OUTPUT_LOW_B_SW_OUTPUT_HIGH (0x9U)
2579 #define EPWM_AQ_A_SW_OUTPUT_HIGH_B_SW_OUTPUT_HIGH (0xAU)
2588 #define EPWM_DCxCTL_STEP (CSL_EPWM_DCBCTL - CSL_EPWM_DCACTL)
2589 #define EPWM_DCxxTRIPSEL (CSL_EPWM_DCALTRIPSEL - CSL_EPWM_DCAHTRIPSEL)
2590 #define EPWM_XREGSHDWxSTS_STEP (CSL_EPWM_XREGSHDW2STS-CSL_EPWM_XREGSHDW1STS)
2591 #define EPWM_XCMPx_ACTIVE_STEP (CSL_EPWM_XCMP2_ACTIVE-CSL_EPWM_XCMP1_ACTIVE)
2592 #define EPWM_XCMPx_STEP (CSL_EPWM_XCMP1_SHDW2-CSL_EPWM_XCMP1_SHDW1)
2593 #define EPWM_XCMPx_SHDWx_STEP (CSL_EPWM_XCMP2_SHDW1-CSL_EPWM_XCMP1_SHDW1)
2594 #define EPWM_LOCK_KEY (0xA5A50000U)
2635 HW_WR_REG16(base + CSL_EPWM_TBCTR, count);
2662 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2663 (HW_RD_REG16(base + CSL_EPWM_TBCTL) |
2664 CSL_EPWM_TBCTL_PHSDIR_MASK));
2671 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2672 (HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2673 ~CSL_EPWM_TBCTL_PHSDIR_MASK));
2707 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2708 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2709 ~(CSL_EPWM_TBCTL_CLKDIV_MASK | CSL_EPWM_TBCTL_HSPCLKDIV_MASK)) |
2710 (uint16_t)(((uint16_t)prescaler << CSL_EPWM_TBCTL_CLKDIV_SHIFT) |
2711 (uint16_t)((uint16_t)highSpeedPrescaler << CSL_EPWM_TBCTL_HSPCLKDIV_SHIFT))));
2733 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2734 HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_SWFSYNC_MASK);
2773 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCINSEL,
2774 ((HW_RD_REG16(base + CSL_EPWM_EPWMSYNCINSEL) &
2775 (~(uint16_t)CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)) |
2776 (uint16_t)((uint16_t)source & CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)));
2825 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2826 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) |
2870 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2871 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) &
2872 ~((uint16_t)source)));
2899 HW_WR_REG16(base + CSL_EPWM_TBCTL3,
2900 ((HW_RD_REG16(base + CSL_EPWM_TBCTL3) &
2901 ~(CSL_EPWM_TBCTL3_OSSFRCEN_MASK)) |
2902 (uint16_t)trigger));
2929 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2930 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PRDLD_MASK));
2937 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2938 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PRDLD_MASK));
2960 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2961 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PHSEN_MASK));
2981 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2982 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PHSEN_MASK));
3008 HW_WR_REG16(base + CSL_EPWM_TBCTL,
3009 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
3010 ~(CSL_EPWM_TBCTL_CTRMODE_MASK)) | ((uint16_t)counterMode)));
3040 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3041 ((HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
3042 ~(uint16_t)(CSL_EPWM_TBCTL2_PRDLDSYNC_MASK)) |
3043 (uint16_t)((uint16_t)shadowLoadMode << CSL_EPWM_TBCTL2_PRDLDSYNC_SHIFT)));
3062 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3063 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) |
3064 CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
3084 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3085 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
3086 ~CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
3106 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3107 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) | CSL_EPWM_TBCTL2_OSHTSYNC_MASK));
3121 static inline uint16_t
3127 return(HW_RD_REG16(base + CSL_EPWM_TBCTR));
3148 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) &
3149 CSL_EPWM_TBSTS_CTRMAX_MASK) ==
3150 CSL_EPWM_TBSTS_CTRMAX_MASK) ?
true :
false);
3171 HW_WR_REG16(base + CSL_EPWM_TBSTS,
3172 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_CTRMAX_MASK));
3193 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_SYNCI_MASK) ==
3194 CSL_EPWM_TBSTS_SYNCI_MASK) ?
true :
false);
3214 HW_WR_REG16(base + CSL_EPWM_TBSTS,
3215 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_SYNCI_MASK));
3231 static inline uint16_t
3237 return(HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_CTRDIR_MASK);
3261 HW_WR_REG32(base + CSL_EPWM_TBPHS,
3262 ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
3263 ~((uint32_t)CSL_EPWM_TBPHS_TBPHS_MASK)) |
3264 ((uint32_t)phaseCount << CSL_EPWM_TBPHS_TBPHS_SHIFT)));
3290 HW_WR_REG16(base + CSL_EPWM_TBPRD, periodCount);
3304 static inline uint16_t
3310 return(HW_RD_REG16(base + CSL_EPWM_TBPRD));
3381 uint32_t registerOffset;
3382 uint32_t linkComponent = (uint32_t)linkComp;
3386 registerOffset = base + CSL_EPWM_EPWMXLINK2;
3387 linkComponent = (uint32_t)linkComponent - 1U;
3391 registerOffset = base + CSL_EPWM_EPWMXLINKXLOAD;
3392 linkComponent = (uint32_t)linkComponent - 2U;
3396 registerOffset = base + CSL_EPWM_EPWMXLINK;
3402 HW_WR_REG32(registerOffset,
3403 ((uint32_t)(HW_RD_REG32(registerOffset) &
3404 ~((uint32_t)CSL_EPWM_EPWMXLINK_TBPRDLINK_MASK << linkComponent)) |
3405 ((uint32_t)epwmLink << linkComponent)));
3443 uint16_t syncModeOffset;
3444 uint16_t loadModeOffset;
3445 uint16_t shadowModeOffset;
3446 uint32_t registerOffset;
3451 syncModeOffset = CSL_EPWM_CMPCTL_LOADASYNC_SHIFT;
3452 loadModeOffset = CSL_EPWM_CMPCTL_LOADAMODE_SHIFT;
3453 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
3457 syncModeOffset = CSL_EPWM_CMPCTL_LOADBSYNC_SHIFT;
3458 loadModeOffset = CSL_EPWM_CMPCTL_LOADBMODE_SHIFT;
3459 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
3469 registerOffset = base + CSL_EPWM_CMPCTL;
3473 registerOffset = base + CSL_EPWM_CMPCTL2;
3480 HW_WR_REG16(registerOffset,
3481 ((HW_RD_REG16(registerOffset) &
3482 ~((CSL_EPWM_CMPCTL_LOADASYNC_MAX << syncModeOffset) |
3483 (CSL_EPWM_CMPCTL_LOADAMODE_MAX << loadModeOffset) |
3484 (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset))) |
3485 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3486 (((uint16_t)loadMode & CSL_EPWM_CMPCTL_LOADASYNC_MAX) <<
3512 uint16_t shadowModeOffset;
3513 uint32_t registerOffset;
3518 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
3522 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
3532 registerOffset = base + CSL_EPWM_CMPCTL;
3536 registerOffset = base + CSL_EPWM_CMPCTL2;
3542 HW_WR_REG16(registerOffset,
3543 (HW_RD_REG16(registerOffset) |
3544 ((uint32_t)CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset)));
3570 uint32_t registerOffset;
3575 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3586 HW_WR_REG16(registerOffset + 0x2U, compCount);
3593 HW_WR_REG16(registerOffset, compCount);
3612 HW_WR_REG16(base + CSL_EPWM_CMPA + 0x2U, compCount);
3631 HW_WR_REG16(base + CSL_EPWM_CMPB + 0x2U, compCount);
3650 HW_WR_REG16(base + CSL_EPWM_CMPC, compCount);
3669 HW_WR_REG16(base + CSL_EPWM_CMPD, compCount);
3689 static inline uint16_t
3692 uint32_t registerOffset;
3698 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3709 compCount = (uint16_t)((HW_RD_REG32(registerOffset) &
3710 (uint32_t)CSL_EPWM_CMPA_CMPA_MASK) >>
3711 CSL_EPWM_CMPA_CMPA_SHIFT);
3718 compCount = HW_RD_REG16(registerOffset);
3752 return((((HW_RD_REG32(base + CSL_EPWM_CMPCTL) >>
3753 ((((uint16_t)compModule >> 1U) & 0x2U) +
3754 CSL_EPWM_CMPCTL_SHDWAFULL_SHIFT)) &
3755 0x1U) == 0x1U) ?
true:
false);
3796 uint16_t syncModeOffset;
3797 uint16_t shadowModeOffset;
3799 syncModeOffset = CSL_EPWM_AQCTL_LDAQASYNC_SHIFT + (uint16_t)aqModule;
3800 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3806 HW_WR_REG16((base + CSL_EPWM_AQCTL),
3807 ((HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3808 ((~((CSL_EPWM_AQCTL_LDAQAMODE_MASK << (uint16_t)aqModule) |
3809 (CSL_EPWM_AQCTL_LDAQASYNC_MAX << (uint16_t)syncModeOffset))) |
3810 (CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset))) |
3811 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3812 (((uint16_t)loadMode & CSL_EPWM_AQCTL_LDAQAMODE_MASK) <<
3813 (uint16_t)aqModule))));
3836 uint16_t shadowModeOffset;
3838 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3844 HW_WR_REG16(base + CSL_EPWM_AQCTL,
3845 (HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3846 ~(CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)));
3878 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3879 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3880 (~CSL_EPWM_AQTSRCSEL_T1SEL_MASK)) |
3881 ((uint16_t)trigger)));
3913 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3914 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3915 (~(uint16_t)CSL_EPWM_AQTSRCSEL_T2SEL_MASK)) |
3916 (uint16_t)((uint16_t)trigger << CSL_EPWM_AQTSRCSEL_T2SEL_SHIFT)));
3967 uint32_t registerOffset;
3968 uint32_t registerTOffset;
3973 registerOffset = (uint32_t)CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
3974 registerTOffset = (uint32_t)CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
3979 if(((uint16_t)
event & 0x1U) == 1U)
3984 HW_WR_REG16(base + registerTOffset,
3985 ((HW_RD_REG16(base + registerTOffset) &
3986 ~(CSL_EPWM_AQCTLA_ZRO_MAX << ((uint16_t)event - 1U))) |
3987 ((uint16_t)output << ((uint16_t)event - 1U))));
3994 HW_WR_REG16(base + registerOffset,
3995 ((HW_RD_REG16(base + registerOffset) &
3996 ~(CSL_EPWM_AQCTLA_ZRO_MAX << (uint16_t)event)) |
3997 ((uint16_t)output << (uint16_t)event)));
4090 uint32_t registerOffset;
4095 registerOffset = (uint32_t)CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
4100 HW_WR_REG16(base + registerOffset, action);
4169 uint32_t registerTOffset;
4174 registerTOffset = (uint32_t)CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
4179 HW_WR_REG16(base + registerTOffset, action);
4212 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4213 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4214 ~(uint16_t)CSL_EPWM_AQSFRC_RLDCSF_MASK) |
4215 (uint16_t)((uint16_t)mode << CSL_EPWM_AQSFRC_RLDCSF_SHIFT)));
4250 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
4251 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
4252 ~CSL_EPWM_AQCSFRC_CSFA_MASK) |
4253 ((uint16_t)output)));
4257 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
4258 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
4259 ~(uint16_t)CSL_EPWM_AQCSFRC_CSFB_MASK) |
4260 (uint16_t)((uint16_t)output << CSL_EPWM_AQCSFRC_CSFB_SHIFT)));
4299 HW_WR_REG16(base + CSL_EPWM_AQCSFRC, outputAB);
4336 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4337 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4338 ~CSL_EPWM_AQSFRC_ACTSFA_MASK) |
4339 ((uint16_t)output)));
4343 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4344 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4345 ~(uint16_t)CSL_EPWM_AQSFRC_ACTSFB_MASK) |
4346 (uint16_t)((uint16_t)output << CSL_EPWM_AQSFRC_ACTSFB_SHIFT)));
4375 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4376 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
4377 CSL_EPWM_AQSFRC_OTSFA_MASK));
4381 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4382 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
4383 CSL_EPWM_AQSFRC_OTSFB_MASK));
4414 bool enableSwapMode)
4418 mask = (uint16_t)1U << ((uint16_t)output + CSL_EPWM_DBCTL_OUTSWAP_SHIFT);
4425 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4426 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
4433 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4434 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
4462 bool enableDelayMode)
4466 mask = (uint16_t)1U << ((uint16_t)((uint16_t)delayMode + (uint16_t)CSL_EPWM_DBCTL_OUT_MODE_SHIFT));
4473 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4474 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
4481 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4482 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
4514 shift = (((uint16_t)delayMode ^ 0x1U) + CSL_EPWM_DBCTL_POLSEL_SHIFT);
4519 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4520 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~ (1U << shift)) |
4521 ((uint16_t)polarity << shift)));
4553 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4554 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4555 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT))) |
4556 ((uint32_t)input << CSL_EPWM_DBCTL_IN_MODE_SHIFT)));
4594 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4595 (HW_RD_REG16(base + CSL_EPWM_DBCTL) |
4596 CSL_EPWM_DBCTL_DEDB_MODE_MASK));
4603 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4604 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4605 ~CSL_EPWM_DBCTL_DEDB_MODE_MASK));
4610 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4611 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4612 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))) |
4613 ((uint32_t)input << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))));
4643 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
4644 ((HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
4645 ~(uint16_t)CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK) |
4646 (uint16_t)(CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK | (uint16_t)loadMode)));
4667 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
4668 (HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
4669 ~CSL_EPWM_DBCTL2_SHDWDBCTLMODE_MASK));
4697 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4698 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4699 ~(uint16_t)CSL_EPWM_DBCTL_LOADREDMODE_MASK) |
4700 (uint16_t)(CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK |
4701 (uint16_t)((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADREDMODE_SHIFT))));
4722 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4723 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4724 ~CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK));
4752 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4753 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4754 ~(uint16_t)CSL_EPWM_DBCTL_LOADFEDMODE_MASK) |
4755 (uint16_t)(CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK |
4756 (uint16_t)((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADFEDMODE_SHIFT))));
4777 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4778 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4779 ~CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK));
4807 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4808 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4809 ~(uint16_t)CSL_EPWM_DBCTL_HALFCYCLE_MASK) |
4810 (uint16_t)((uint16_t)clockMode << CSL_EPWM_DBCTL_HALFCYCLE_SHIFT)));
4837 HW_WR_REG16(base + CSL_EPWM_DBRED, redCount);
4864 HW_WR_REG16(base + CSL_EPWM_DBFED, fedCount);
4887 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4888 (HW_RD_REG16(base + CSL_EPWM_PCCTL) | CSL_EPWM_PCCTL_CHPEN_MASK));
4908 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4909 (HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPEN_MASK));
4938 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4939 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPDUTY_MASK) |
4940 ((uint32_t)dutyCycleCount << CSL_EPWM_PCCTL_CHPDUTY_SHIFT)));
4970 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4971 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
4972 ~(uint16_t)CSL_EPWM_PCCTL_CHPFREQ_MASK) |
4973 ((uint32_t)freqDiv << CSL_EPWM_PCCTL_CHPFREQ_SHIFT)));
4997 DebugP_assert(firstPulseWidth <= CSL_EPWM_PCCTL_OSHTWTH_MAX);
5002 HW_WR_REG16(base + CSL_EPWM_PCCTL,
5003 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
5004 ~(uint16_t)CSL_EPWM_PCCTL_OSHTWTH_MASK) |
5005 ((uint32_t)firstPulseWidth << CSL_EPWM_PCCTL_OSHTWTH_SHIFT)));
5050 HW_WR_REG32(base + CSL_EPWM_TZSEL,
5051 (HW_RD_REG32(base + CSL_EPWM_TZSEL) | tzSignal));
5093 HW_WR_REG32(base + CSL_EPWM_TZSEL,
5094 (HW_RD_REG32(base + CSL_EPWM_TZSEL) & ~tzSignal));
5122 HW_WR_REG16(base + CSL_EPWM_TZSEL2,
5123 (HW_RD_REG16(base + CSL_EPWM_TZSEL2) | tzSignal));
5151 HW_WR_REG16(base + CSL_EPWM_TZSEL2,
5152 (HW_RD_REG16(base + CSL_EPWM_TZSEL2) & ~tzSignal));
5195 HW_WR_REG16(base + CSL_EPWM_TZDCSEL,
5196 ((HW_RD_REG16(base + CSL_EPWM_TZDCSEL) &
5197 ~(CSL_EPWM_TZDCSEL_DCAEVT1_MASK << (uint16_t)dcType)) |
5198 ((uint16_t)dcEvent << (uint16_t)dcType)));
5220 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5221 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5241 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5242 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) & ~CSL_EPWM_TZCTL2_ETZE_MASK));
5284 HW_WR_REG16(base + CSL_EPWM_TZCTL,
5285 ((HW_RD_REG16(base + CSL_EPWM_TZCTL) &
5286 ~(CSL_EPWM_TZCTL_TZA_MASK << (uint16_t)tzEvent)) |
5287 ((uint16_t)tzAction << (uint16_t)tzEvent)));
5335 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5336 ((HW_RD_REG16(base + CSL_EPWM_TZCTL2) &
5337 ~(CSL_EPWM_TZCTL2_TZAU_MASK << (uint16_t)tzAdvEvent)) |
5338 ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)));
5340 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5341 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5387 HW_WR_REG16(base + CSL_EPWM_TZCTLDCA,
5388 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCA) &
5389 ~(CSL_EPWM_TZCTLDCA_DCAEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
5390 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
5392 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5393 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5438 HW_WR_REG16(base + CSL_EPWM_TZCTLDCB,
5439 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCB) &
5440 ~(CSL_EPWM_TZCTLDCB_DCBEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
5441 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
5443 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5444 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5481 HW_WR_REG16(base + CSL_EPWM_TZEINT,
5482 (HW_RD_REG16(base + CSL_EPWM_TZEINT) | tzInterrupt));
5514 DebugP_assert((tzInterrupt > 0U) && (tzInterrupt <= 0x80U));
5519 HW_WR_REG16(base + CSL_EPWM_TZEINT,
5520 (HW_RD_REG16(base + CSL_EPWM_TZEINT) & ~tzInterrupt));
5544 static inline uint16_t
5550 return(HW_RD_REG16(base + CSL_EPWM_TZFLG) & 0xFFU);
5576 static inline uint16_t
5582 return(HW_RD_REG16(base + CSL_EPWM_TZCBCFLG) & 0x1FFU);
5606 static inline uint16_t
5612 return(HW_RD_REG16(base + CSL_EPWM_TZOSTFLG) & 0x1FFU);
5642 HW_WR_REG16(base + CSL_EPWM_TZCLR,
5643 ((HW_RD_REG16(base + CSL_EPWM_TZCLR) &
5644 ~(uint16_t)CSL_EPWM_TZCLR_CBCPULSE_MASK) |
5645 (uint16_t)((uint16_t)clearEvent << CSL_EPWM_TZCLR_CBCPULSE_SHIFT)));
5683 HW_WR_REG16(base + CSL_EPWM_TZCLR,
5684 (HW_RD_REG16(base + CSL_EPWM_TZCLR) | tzFlags));
5721 HW_WR_REG16(base + CSL_EPWM_TZCBCCLR,
5722 (HW_RD_REG16(base + CSL_EPWM_TZCBCCLR) | tzCBCFlags));
5758 HW_WR_REG16(base + CSL_EPWM_TZOSTCLR,
5759 (HW_RD_REG16(base + CSL_EPWM_TZOSTCLR) | tzOSTFlags));
5793 HW_WR_REG16(base + CSL_EPWM_TZFRC,
5794 (HW_RD_REG16(base + CSL_EPWM_TZFRC) | tzForceEvent));
5820 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5821 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) | tzOutput));
5847 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5848 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) & ~tzOutput));
5871 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5872 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_INTEN_MASK));
5892 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5893 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_INTEN_MASK));
5924 uint16_t mixedSource)
5931 DebugP_assert(((interruptSource > 0U) && (interruptSource < 9U)) ||
5932 (interruptSource == 10U) || (interruptSource == 12U) ||
5933 (interruptSource == 14U));
5943 intSource = interruptSource >> 1U;
5948 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5949 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
5950 CSL_EPWM_ETSEL_INTSELCMP_MASK));
5957 intSource = interruptSource;
5962 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5963 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5964 ~CSL_EPWM_ETSEL_INTSELCMP_MASK));
5968 intSource = interruptSource;
5973 HW_WR_REG16(base + CSL_EPWM_ETINTMIXEN, mixedSource);
5977 intSource = interruptSource;
5983 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5984 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5985 ~CSL_EPWM_ETSEL_INTSEL_MASK) | intSource));
6013 HW_WR_REG16(base + CSL_EPWM_ETPS,
6014 (HW_RD_REG16(base + CSL_EPWM_ETPS) | CSL_EPWM_ETPS_INTPSSEL_MASK));
6016 HW_WR_REG16(base + CSL_EPWM_ETINTPS,
6017 ((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
6018 ~CSL_EPWM_ETINTPS_INTPRD2_MASK) | eventCount));
6040 return(((HW_RD_REG16(base + CSL_EPWM_ETFLG) & 0x1U) ==
6041 0x1U) ?
true :
false);
6061 HW_WR_REG16(base + CSL_EPWM_ETCLR, (CSL_EPWM_ETCLR_INT_MASK));
6084 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6085 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6086 CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
6107 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6108 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
6109 ~CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
6133 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6134 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6135 CSL_EPWM_ETCNTINITCTL_INTINITFRC_MASK));
6158 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_INTINIT_MAX);
6163 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6164 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6165 ~CSL_EPWM_ETCNTINIT_INTINIT_MASK) |
6166 (uint16_t)(eventCount & CSL_EPWM_ETCNTINIT_INTINIT_MASK)));
6180 static inline uint16_t
6186 return(((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
6187 CSL_EPWM_ETINTPS_INTCNT2_MASK) >>
6188 CSL_EPWM_ETINTPS_INTCNT2_SHIFT));
6208 HW_WR_REG16(base + CSL_EPWM_ETFRC,
6209 (HW_RD_REG16(base + CSL_EPWM_ETFRC) | CSL_EPWM_ETFRC_INT_MASK));
6238 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6239 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCAEN_MASK));
6243 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6244 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCBEN_MASK));
6271 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6272 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCAEN_MASK));
6276 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6277 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCBEN_MASK));
6317 uint16_t mixedSource)
6326 source = (uint16_t)socSource >> 1U;
6330 source = (uint16_t)socSource;
6338 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6339 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6340 ~CSL_EPWM_ETSEL_SOCASEL_MASK) |
6341 ((uint32_t)source << CSL_EPWM_ETSEL_SOCASEL_SHIFT)));
6354 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6355 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6356 ~CSL_EPWM_ETSEL_SOCASELCMP_MASK));
6366 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6367 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
6368 CSL_EPWM_ETSEL_SOCASELCMP_MASK));
6375 HW_WR_REG16(base + CSL_EPWM_ETSOCAMIXEN, mixedSource);
6389 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6390 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6391 ~CSL_EPWM_ETSEL_SOCBSEL_MASK) |
6392 ((uint32_t)source << CSL_EPWM_ETSEL_SOCBSEL_SHIFT)));
6405 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6406 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6407 ~CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
6417 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6418 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
6419 CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
6426 HW_WR_REG16(base + CSL_EPWM_ETSOCBMIXEN, mixedSource);
6463 uint16_t preScaleCount)
6468 DebugP_assert(preScaleCount <= CSL_EPWM_ETSOCPS_SOCAPRD2_MAX);
6473 HW_WR_REG16(base + CSL_EPWM_ETPS,
6474 (HW_RD_REG16(base + CSL_EPWM_ETPS) |
6475 CSL_EPWM_ETPS_SOCPSSEL_MASK));
6482 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
6483 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
6484 ~CSL_EPWM_ETSOCPS_SOCAPRD2_MASK) |
6492 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
6493 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
6494 ~CSL_EPWM_ETSOCPS_SOCBPRD2_MASK) |
6495 ((uint32_t)preScaleCount << CSL_EPWM_ETSOCPS_SOCBPRD2_SHIFT)));
6522 return((((HW_RD_REG16(base + CSL_EPWM_ETFLG) >>
6523 ((uint16_t)adcSOCType + CSL_EPWM_ETFLG_SOCA_SHIFT)) &
6524 0x1U) == 0x1U) ?
true :
false);
6549 HW_WR_REG16(base + CSL_EPWM_ETCLR,
6550 (HW_RD_REG16(base + CSL_EPWM_ETCLR) |
6551 ((uint16_t)1U << ((uint16_t)adcSOCType + CSL_EPWM_ETCLR_SOCA_SHIFT))));
6580 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6581 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) | ((uint16_t)1U <<
6582 ((uint16_t)adcSOCType + CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT))));
6610 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6611 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
6612 ~(1U << ((uint16_t)adcSOCType +
6613 CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT))));
6639 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6640 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6641 ((uint16_t)1U << ((uint16_t)adcSOCType +
6642 CSL_EPWM_ETCNTINITCTL_SOCAINITFRC_SHIFT))));
6665 uint16_t eventCount)
6670 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_SOCAINIT_MAX);
6677 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6678 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6679 ~CSL_EPWM_ETCNTINIT_SOCAINIT_MASK) |
6680 (uint16_t)(eventCount << CSL_EPWM_ETCNTINIT_SOCAINIT_SHIFT)));
6684 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6685 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6686 ~CSL_EPWM_ETCNTINIT_SOCBINIT_MASK) |
6687 ((uint32_t)eventCount << CSL_EPWM_ETCNTINIT_SOCBINIT_SHIFT)));
6706 static inline uint16_t
6710 uint16_t eventCount;
6717 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
6718 CSL_EPWM_ETSOCPS_SOCACNT2_SHIFT) &
6719 CSL_EPWM_ETSOCPS_SOCACNT2_MAX;
6723 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
6724 CSL_EPWM_ETSOCPS_SOCBCNT2_SHIFT) &
6725 CSL_EPWM_ETSOCPS_SOCBCNT2_MAX;
6752 HW_WR_REG16(base + CSL_EPWM_ETFRC,
6753 (HW_RD_REG16(base + CSL_EPWM_ETFRC) |
6754 ((uint16_t)1U << ((uint16_t)adcSOCType + CSL_EPWM_ETFRC_SOCA_SHIFT))));
6793 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
6794 ((HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) &
6795 ~(CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK <<
6796 ((uint16_t)dcType << 2U))) |
6797 ((uint16_t)tripSource << ((uint16_t)dcType << 2U))));
6820 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6821 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKE_MASK));
6841 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6842 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_BLANKE_MASK));
6863 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6864 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKINV_MASK));
6884 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6885 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6886 ~CSL_EPWM_DCFCTL_BLANKINV_MASK));
6911 uint16_t mixedSource)
6918 HW_WR_REG16(base + CSL_EPWM_BLANKPULSEMIXSEL, mixedSource);
6924 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6925 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6926 ~CSL_EPWM_DCFCTL_PULSESEL_MASK) |
6927 ((uint16_t)((uint32_t)blankingPulse <<
6928 CSL_EPWM_DCFCTL_PULSESEL_SHIFT))));
6956 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6957 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_SRCSEL_MASK) |
6958 ((uint16_t)filterInput)));
6982 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6983 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) |
6984 CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
7004 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
7005 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7006 ~CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
7032 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
7033 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7034 ~CSL_EPWM_DCFCTL_EDGEMODE_MASK) |
7035 ((uint32_t)edgeMode << CSL_EPWM_DCFCTL_EDGEMODE_SHIFT));
7066 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
7067 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7068 ~CSL_EPWM_DCFCTL_EDGECOUNT_MASK) |
7069 ((uint32_t)edgeCount << CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT));
7084 static inline uint16_t
7090 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7091 CSL_EPWM_DCFCTL_EDGECOUNT_MASK) >>
7092 CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT);
7107 static inline uint16_t
7113 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7114 CSL_EPWM_DCFCTL_EDGESTATUS_MASK) >>
7115 CSL_EPWM_DCFCTL_EDGESTATUS_SHIFT);
7138 HW_WR_REG16(base + CSL_EPWM_DCFOFFSET, windowOffsetCount);
7160 HW_WR_REG16(base + CSL_EPWM_DCFWINDOW, windowLengthCount);
7174 static inline uint16_t
7180 return(HW_RD_REG16(base + CSL_EPWM_DCFOFFSETCNT));
7194 static inline uint16_t
7200 return(HW_RD_REG16(base + CSL_EPWM_DCFWINDOWCNT));
7238 uint32_t registerOffset;
7240 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)
EPWM_DCxCTL_STEP);
7247 HW_WR_REG16(base + registerOffset,
7248 ((HW_RD_REG16(base + registerOffset) &
7249 ~CSL_EPWM_DCACTL_EVT1SRCSEL_MASK) |
7250 (uint16_t)dcEventSource));
7254 HW_WR_REG16(base + registerOffset,
7255 ((HW_RD_REG16(base + registerOffset) &
7256 ~(uint16_t)CSL_EPWM_DCACTL_EVT2SRCSEL_MASK) |
7257 (uint16_t)((uint16_t)dcEventSource << CSL_EPWM_DCACTL_EVT2SRCSEL_SHIFT)));
7293 uint32_t registerOffset;
7295 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)
EPWM_DCxCTL_STEP);
7302 HW_WR_REG16(base + registerOffset,
7303 ((HW_RD_REG16(base + registerOffset) &
7304 ~(uint16_t)CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_MASK) |
7305 (uint16_t)((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_SHIFT)));
7309 HW_WR_REG16(base + registerOffset,
7310 ((HW_RD_REG16(base + registerOffset) &
7311 ~(uint16_t)CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_MASK) |
7312 (uint16_t)((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_SHIFT)));
7336 uint32_t registerOffset;
7338 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)
EPWM_DCxCTL_STEP);
7343 HW_WR_REG16(base + registerOffset,
7344 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SOCE_MASK));
7367 uint32_t registerOffset;
7369 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)
EPWM_DCxCTL_STEP);
7374 HW_WR_REG16(base + registerOffset,
7375 (HW_RD_REG16(base + registerOffset) & ~CSL_EPWM_DCACTL_EVT1SOCE_MASK));
7398 uint32_t registerOffset;
7400 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)
EPWM_DCxCTL_STEP);
7405 HW_WR_REG16(base + registerOffset,
7406 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
7429 uint32_t registerOffset;
7431 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)
EPWM_DCxCTL_STEP);
7436 HW_WR_REG16(base + registerOffset,
7437 (HW_RD_REG16(base + registerOffset) &
7438 ~CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
7471 uint32_t registerOffset;
7473 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)
EPWM_DCxCTL_STEP);
7480 HW_WR_REG16(base + registerOffset,
7481 ((HW_RD_REG16(base + registerOffset) &
7482 ~(uint16_t)CSL_EPWM_DCACTL_EVT1LATSEL_MASK) |
7483 (uint16_t)((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT1LATSEL_SHIFT)));
7487 HW_WR_REG16(base + registerOffset,
7488 ((HW_RD_REG16(base + registerOffset) &
7489 ~(uint16_t)CSL_EPWM_DCACTL_EVT2LATSEL_MASK) |
7490 (uint16_t)((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT2LATSEL_SHIFT)));
7529 uint32_t registerOffset;
7531 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)
EPWM_DCxCTL_STEP);
7538 HW_WR_REG16(base + registerOffset,
7539 ((HW_RD_REG16(base + registerOffset) &
7540 ~(uint16_t)CSL_EPWM_DCACTL_EVT1LATCLRSEL_MASK) |
7541 (uint16_t)((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT1LATCLRSEL_SHIFT)));
7545 HW_WR_REG16(base + registerOffset,
7546 ((HW_RD_REG16(base + registerOffset) &
7547 ~(uint16_t)CSL_EPWM_DCACTL_EVT2LATCLRSEL_MASK) |
7548 (uint16_t)((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT2LATCLRSEL_SHIFT)));
7580 uint32_t registerOffset;
7583 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)
EPWM_DCxCTL_STEP);
7590 status = HW_RD_REG16(base + registerOffset) &
7591 CSL_EPWM_DCACTL_EVT1LAT_MASK;
7595 status = HW_RD_REG16(base + registerOffset) &
7596 CSL_EPWM_DCACTL_EVT2LAT_MASK;
7599 return(status != 0U);
7622 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7623 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) | CSL_EPWM_DCCAPCTL_CAPE_MASK));
7643 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7644 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7645 ~CSL_EPWM_DCCAPCTL_CAPE_MASK));
7666 if(enableShadowMode)
7671 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7672 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7673 ~CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
7680 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7681 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) |
7682 CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
7706 return((HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7707 CSL_EPWM_DCCAPCTL_CAPSTS_MASK) == CSL_EPWM_DCCAPCTL_CAPSTS_MASK);
7723 static inline uint16_t
7729 return(HW_RD_REG16(base + CSL_EPWM_DCCAP));
7758 uint32_t registerOffset;
7764 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7770 HW_WR_REG16(base + registerOffset,
7771 (HW_RD_REG16(base + registerOffset) | tripInput));
7776 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
7777 (HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) |
7778 ((uint16_t)CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK << ((uint16_t)dcType << 2U))));
7807 uint32_t registerOffset;
7813 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7819 HW_WR_REG16(base + registerOffset,
7820 (HW_RD_REG16(base + registerOffset) & ~tripInput));
7846 base + CSL_EPWM_CAPCTL,
7847 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) | CSL_EPWM_CAPCTL_SRCSEL_MASK)
7870 base + CSL_EPWM_CAPCTL,
7871 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_SRCSEL_MASK))
7900 base + CSL_EPWM_CAPCTL,
7901 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_CAPGATEPOL_MASK)) |
7902 ((uint16_t)polSel << CSL_EPWM_CAPCTL_CAPGATEPOL_SHIFT));
7928 base + CSL_EPWM_CAPCTL,
7929 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_CAPINPOL_MASK)) |
7930 ((uint16_t)polSel << CSL_EPWM_CAPCTL_CAPINPOL_SHIFT));
7951 base + CSL_EPWM_CAPCTL,
7952 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_PULSECTL_MASK)) |
7953 (((uint16_t)1U) << CSL_EPWM_CAPCTL_PULSECTL_SHIFT));
7975 base + CSL_EPWM_CAPCTL,
7976 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) | (CSL_EPWM_CAPCTL_PULSECTL_MASK)) &
7977 (~(((uint16_t)1U) << CSL_EPWM_CAPCTL_PULSECTL_SHIFT)));
7998 base + CSL_EPWM_CAPCTL,
7999 HW_RD_REG16(base + CSL_EPWM_CAPCTL) | (CSL_EPWM_CAPCTL_FRCLOAD_MASK));
8036 base + CSL_EPWM_CAPTRIPSEL,
8037 (HW_RD_REG16(base + CSL_EPWM_CAPTRIPSEL) & (~CSL_EPWM_CAPTRIPSEL_CAPGATECOMPSEL_MASK)) |
8038 (((uint16_t)tripSource) << CSL_EPWM_CAPTRIPSEL_CAPGATECOMPSEL_SHIFT));
8043 base + CSL_EPWM_CAPTRIPSEL,
8044 (HW_RD_REG16(base + CSL_EPWM_CAPTRIPSEL) & (~CSL_EPWM_CAPTRIPSEL_CAPINCOMPSEL_MASK)) |
8045 (((uint16_t)tripSource) << CSL_EPWM_CAPTRIPSEL_CAPINCOMPSEL_SHIFT));
8081 base + CSL_EPWM_CAPGATETRIPSEL, tripInput);
8090 base + CSL_EPWM_CAPINTRIPSEL, tripInput);
8132 base + CSL_EPWM_CAPGATETRIPSEL,
8133 HW_RD_REG16(base + CSL_EPWM_CAPGATETRIPSEL) & (~tripInput));
8142 base + CSL_EPWM_CAPINTRIPSEL,
8143 HW_RD_REG16(base + CSL_EPWM_CAPGATETRIPSEL) & (~tripInput));
8167 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8168 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) | CSL_EPWM_VCAPCTL_VCAPE_MASK));
8188 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8189 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) & ~CSL_EPWM_VCAPCTL_VCAPE_MASK));
8213 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8214 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
8215 CSL_EPWM_VCAPCTL_VCAPSTART_MASK));
8239 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8240 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
8241 ~(uint16_t)CSL_EPWM_VCAPCTL_TRIGSEL_MASK) |
8242 (uint16_t)((uint16_t)trigger << CSL_EPWM_VCAPCTL_TRIGSEL_SHIFT)));
8277 HW_WR_REG16(base + CSL_EPWM_VCNTCFG,
8278 ((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
8279 ~(CSL_EPWM_VCNTCFG_STARTEDGE_MASK | CSL_EPWM_VCNTCFG_STOPEDGE_MASK)) |
8280 ((uint32_t)startCount | ((uint32_t)stopCount << CSL_EPWM_VCNTCFG_STOPEDGE_SHIFT))));
8300 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8301 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
8302 CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
8322 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8323 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
8324 ~CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
8345 HW_WR_REG16(base + CSL_EPWM_SWVDELVAL, delayOffsetValue);
8366 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8367 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
8368 ~(uint16_t)CSL_EPWM_VCAPCTL_VDELAYDIV_MASK) |
8369 (uint16_t)((uint16_t)delayMode << CSL_EPWM_VCAPCTL_VDELAYDIV_SHIFT)));
8394 if((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) & CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK)
8395 == CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK)
8406 if((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
8407 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ==
8408 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK)
8434 static inline uint16_t
8440 return(HW_RD_REG16(base + CSL_EPWM_VCNTVAL));
8454 static inline uint16_t
8460 return(HW_RD_REG16(base + CSL_EPWM_HWVDELVAL));
8482 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8483 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_GLD_MASK));
8504 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8505 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLD_MASK));
8543 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8544 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
8545 ~(uint16_t)CSL_EPWM_GLDCTL_GLDMODE_MASK) |
8546 (uint16_t)((uint16_t)loadTrigger << CSL_EPWM_GLDCTL_GLDMODE_SHIFT)));
8576 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8577 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLDPRD_MASK) |
8578 ((uint32_t)prescalePulseCount << CSL_EPWM_GLDCTL_GLDPRD_SHIFT)));
8594 static inline uint16_t
8600 return((HW_RD_REG16(base + CSL_EPWM_GLDCTL) >>
8601 CSL_EPWM_GLDCTL_GLDCNT_SHIFT) & CSL_EPWM_GLDCTL_GLDCNT_MAX);
8623 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8624 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
8625 ~CSL_EPWM_GLDCTL_OSHTMODE_MASK));
8647 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8648 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_OSHTMODE_MASK));
8670 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
8671 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_OSHTLD_MASK));
8692 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
8693 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_GFRCLD_MASK));
8727 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
8732 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
8733 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) | loadRegister));
8768 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
8774 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
8775 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) & ~loadRegister));
8797 HW_WR_REG32(base + CSL_EPWM_EPWMLOCK,
8821 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8822 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
8823 CSL_EPWM_MINDBCFG_ENABLEA_MASK));
8827 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8828 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
8829 CSL_EPWM_MINDBCFG_ENABLEB_MASK));
8850 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8851 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8852 ~CSL_EPWM_MINDBCFG_ENABLEA_MASK));
8856 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8857 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8858 ~CSL_EPWM_MINDBCFG_ENABLEB_MASK));
8882 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8883 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8884 ~CSL_EPWM_MINDBCFG_INVERTA_MASK) |
8885 (invert<<CSL_EPWM_MINDBCFG_INVERTA_SHIFT)));
8889 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8890 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8891 ~CSL_EPWM_MINDBCFG_INVERTB_MASK) |
8892 (invert<<CSL_EPWM_MINDBCFG_INVERTB_SHIFT)));
8913 uint32_t referenceSignal)
8917 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8918 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8919 ~CSL_EPWM_MINDBCFG_POLSELA_MASK) |
8920 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELA_SHIFT)));
8924 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8925 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8926 ~CSL_EPWM_MINDBCFG_POLSELB_MASK) |
8927 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELB_SHIFT)));
8947 uint32_t blockingSignal)
8951 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8952 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8953 ~CSL_EPWM_MINDBCFG_SELBLOCKA_MASK) |
8954 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKA_SHIFT)));
8958 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8959 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8960 ~CSL_EPWM_MINDBCFG_SELBLOCKB_MASK) |
8961 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKB_SHIFT)));
8980 uint32_t referenceSignal)
8984 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8985 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8986 ~CSL_EPWM_MINDBCFG_SELA_MASK) |
8987 (referenceSignal<<CSL_EPWM_MINDBCFG_SELA_SHIFT)));
8991 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8992 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8993 ~CSL_EPWM_MINDBCFG_SELB_MASK) |
8994 (referenceSignal<<CSL_EPWM_MINDBCFG_SELB_SHIFT)));
9010 static inline uint32_t
9017 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
9018 CSL_EPWM_MINDBDLY_DELAYA_MASK);
9022 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
9023 CSL_EPWM_MINDBDLY_DELAYB_MASK);
9048 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
9049 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
9050 ~CSL_EPWM_MINDBDLY_DELAYA_MASK) |
9051 (delay<<CSL_EPWM_MINDBDLY_DELAYA_SHIFT)));
9055 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
9056 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
9057 ~CSL_EPWM_MINDBDLY_DELAYB_MASK) |
9058 (delay<<CSL_EPWM_MINDBDLY_DELAYB_SHIFT)));
9082 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9083 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
9084 ~CSL_EPWM_LUTCTLA_BYPASS_MASK));
9088 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9089 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
9090 ~CSL_EPWM_LUTCTLB_BYPASS_MASK));
9111 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9112 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) |
9113 CSL_EPWM_LUTCTLA_BYPASS_MASK));
9117 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9118 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) |
9119 CSL_EPWM_LUTCTLB_BYPASS_MASK));
9141 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9142 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
9143 ~CSL_EPWM_LUTCTLA_SELXBAR_MASK) |
9144 (xbarInput<<CSL_EPWM_LUTCTLA_SELXBAR_SHIFT)));
9148 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9149 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
9150 ~CSL_EPWM_LUTCTLB_SELXBAR_MASK) |
9151 (xbarInput<<CSL_EPWM_LUTCTLB_SELXBAR_SHIFT)));
9175 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9176 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
9177 ~(CSL_EPWM_LUTCTLA_LUTDEC0_MAX <<
9178 (CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))) |
9179 (force<<(CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))));
9183 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9184 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
9185 ~(CSL_EPWM_LUTCTLB_LUTDEC0_MAX <<
9186 (CSL_EPWM_LUTCTLB_LUTDEC0_SHIFT+decx))) |
9187 (force<<(CSL_EPWM_LUTCTLB_LUTDEC0_SHIFT+decx))));
9226 HW_WR_REG32(base + CSL_EPWM_TBPHS, phaseCount<<8U);
9256 HW_WR_REG32(base + CSL_EPWM_TBPHS,
9257 ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
9258 ~((uint32_t)CSL_EPWM_TBPHS_TBPHSHR_MASK)) |
9259 ((uint32_t)hrPhaseCount << (CSL_EPWM_TBPHS_TBPHSHR_SHIFT + 8U))));
9286 DebugP_assert(hrPeriodCount <= CSL_EPWM_TBPRDHR_TBPRDHR_MAX);
9291 HW_WR_REG16(base + CSL_EPWM_TBPRDHR, hrPeriodCount << 8);
9305 static inline uint16_t
9311 return(HW_RD_REG16(base + CSL_EPWM_TBPRDHR) >> 8U);
9347 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9348 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
9349 ~(CSL_EPWM_HRCNFG_EDGMODE_MAX << (uint16_t)channel)) |
9350 ((uint16_t)mepEdgeMode << (uint16_t)channel)));
9384 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9385 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
9386 ~(CSL_EPWM_HRCNFG_CTLMODE_MAX << ((uint16_t)channel + 2U))) |
9387 ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))));
9422 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9423 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
9424 ~(CSL_EPWM_HRCNFG_HRLOAD_MAX << ((uint16_t)channel + 3U))) |
9425 ((uint16_t)loadEvent << ((uint16_t)channel + 3U))));
9448 if(enableOutputSwap)
9450 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9451 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_SWAPAB_MASK);
9455 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9456 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_SWAPAB_MASK);
9481 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9482 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~(uint16_t)(CSL_EPWM_HRCNFG_SELOUTB_MASK)) |
9483 (uint16_t)((uint16_t)outputOnB << CSL_EPWM_HRCNFG_SELOUTB_SHIFT)));
9504 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9505 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_AUTOCONV_MASK);
9526 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9527 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_AUTOCONV_MASK);
9547 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9548 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_HRPE_MASK);
9568 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9569 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_HRPE_MASK);
9590 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9591 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
9611 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9612 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
9651 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9652 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) &
9653 ~(CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK | CSL_EPWM_HRPCTL_PWMSYNCSEL_MASK)) |
9654 (uint16_t)((uint16_t)syncPulseSource << 1U)));
9658 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9659 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~(uint16_t)CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK) |
9660 (uint16_t)((uint16_t)syncPulseSource << CSL_EPWM_HRPCTL_PWMSYNCSELX_SHIFT)));
9687 HW_WR_REG16(base + CSL_EPWM_TRREM, trremVal & CSL_EPWM_TRREM_TRREM_MASK);
9729 HW_WR_REG32(base + CSL_EPWM_CMPA, compCount << 8);
9736 HW_WR_REG32(base + CSL_EPWM_CMPB, compCount << 8);
9757 static inline uint32_t
9771 compCount = HW_RD_REG32(base + CSL_EPWM_CMPA);
9778 compCount = HW_RD_REG32(base + CSL_EPWM_CMPB);
9781 return(compCount>>8U);
9806 uint16_t hrCompCount)
9821 HW_WR_REG32(base + CSL_EPWM_CMPA,
9822 HW_RD_REG32(base + CSL_EPWM_CMPA) | (((uint32_t)hrCompCount & CSL_EPWM_CMPA_CMPAHR_MASK) << 8U));
9829 HW_WR_REG32(base + CSL_EPWM_CMPB,
9830 HW_RD_REG32(base + CSL_EPWM_CMPB) | (((uint32_t)hrCompCount & CSL_EPWM_CMPB_CMPBHR_MASK) << (uint32_t)8U));
9850 static inline uint16_t
9854 uint16_t hrCompCount;
9864 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPA) & CSL_EPWM_CMPA_CMPAHR_MASK);
9871 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPB) & CSL_EPWM_CMPB_CMPBHR_MASK);
9874 return(hrCompCount >> 8U);
9904 HW_WR_REG16(base + CSL_EPWM_DBREDHR,
9905 (HW_RD_REG16(base + CSL_EPWM_DBREDHR) & ~CSL_EPWM_DBREDHR_DBREDHR_MASK ) |
9906 ((uint32_t)hrRedCount << CSL_EPWM_DBREDHR_DBREDHR_SHIFT));
9935 HW_WR_REG16(base + CSL_EPWM_DBFEDHR,
9936 (HW_RD_REG16(base + CSL_EPWM_DBFEDHR) &
9937 ~CSL_EPWM_DBFEDHR_DBFEDHR_MASK) |
9938 ((uint32_t)hrFedCount << CSL_EPWM_DBFEDHR_DBFEDHR_SHIFT));
9966 HW_WR_REG16(base + CSL_OTTOCAL_HRMSTEP,
9967 ((HW_RD_REG16(base + CSL_OTTOCAL_HRMSTEP) & ~CSL_OTTOCAL_HRMSTEP_HRMSTEP_MASK) |
9968 ((uint32_t)mepCount << CSL_OTTOCAL_HRMSTEP_HRMSTEP_SHIFT)));
9999 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
10000 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~(uint16_t)CSL_EPWM_HRCNFG2_EDGMODEDB_MASK) |
10001 (uint16_t)((uint16_t)mepDBEdge << CSL_EPWM_HRCNFG2_EDGMODEDB_SHIFT)));
10029 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
10030 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~(uint16_t)CSL_EPWM_HRCNFG2_CTLMODEDBRED_MASK) |
10031 (uint16_t)((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBRED_SHIFT)));
10058 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
10059 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~(uint16_t)CSL_EPWM_HRCNFG2_CTLMODEDBFED_MASK) |
10060 (uint16_t)((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBFED_SHIFT)));
10082 uint16_t xcmpvalue)
10084 uint32_t registerOffset;
10089 registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
10094 HW_WR_REG16(registerOffset, xcmpvalue);
10114 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10116 HW_WR_REG32(registerOffset,
10117 (HW_RD_REG32(registerOffset) | CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
10134 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10136 HW_WR_REG32(registerOffset,
10137 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
10156 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10157 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
10159 HW_WR_REG32(registerOffset,
10160 (HW_RD_REG32(registerOffset) | ((uint32_t) CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
10178 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10179 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
10181 HW_WR_REG32(registerOffset,
10182 (HW_RD_REG32(registerOffset) & ~( CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
10211 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10212 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_SHIFT;
10214 HW_WR_REG32(registerOffset,
10215 ( (HW_RD_REG32(registerOffset) & ~(uint32_t)CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_MASK) | ( (uint32_t)alloctype << offset )));
10238 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10239 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_SHIFT;
10241 HW_WR_REG32(registerOffset,
10242 ( (HW_RD_REG32(registerOffset) & ~(uint32_t)CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_MASK) | ( (uint32_t)alloctype << offset )));
10265 uint16_t xcmpvalue)
10267 uint32_t registerOffset;
10272 registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
10277 HW_WR_REG16(registerOffset + 0x2U, xcmpvalue);
10304 uint32_t registerOffset;
10305 registerOffset = base + CSL_EPWM_CMPC_SHDW1 + (uint32_t)cmpReg;
10310 HW_WR_REG16(registerOffset, cmpvalue);
10335 uint16_t xcmpvalue)
10340 uint32_t registerOffset;
10341 registerOffset = base + CSL_EPWM_XMINMAX_ACTIVE + (uint16_t)xminmaxReg;
10346 HW_WR_REG16(registerOffset, xcmpvalue);
10393 uint32_t registerOffset;
10401 registerOffset = (uint32_t)CSL_EPWM_XAQCTLA_ACTIVE + (uint16_t)((uint16_t)epwmOutput/(uint32_t)2);
10403 HW_WR_REG16(base + registerOffset,
10404 ((HW_RD_REG16(base + registerOffset) &
10405 ~(CSL_EPWM_XAQCTLA_ACTIVE_XCMP1_MAX << (uint16_t)event)) |
10406 ((uint16_t)output << (uint16_t)event)));
10410 registerOffset = (uint32_t)CSL_EPWM_XAQCTLA_SHDW1 + (uint16_t)((uint16_t)epwmOutput/(uint32_t)2);
10412 HW_WR_REG16(base + registerOffset,
10413 ((HW_RD_REG16(base + registerOffset) &
10414 ~(CSL_EPWM_XAQCTLA_SHDW1_XCMP1_MAX << (uint16_t)event)) |
10415 ((uint16_t)output << (uint16_t)event)));
10419 registerOffset = (uint32_t)CSL_EPWM_XAQCTLA_SHDW2 + (uint16_t)((uint16_t)epwmOutput/(uint32_t)2);
10421 HW_WR_REG16(base + registerOffset,
10422 ((HW_RD_REG16(base + registerOffset) &
10423 ~(CSL_EPWM_XAQCTLA_SHDW2_XCMP1_MAX << (uint16_t)event)) |
10424 ((uint16_t)output << (uint16_t)event)));
10428 registerOffset = (uint32_t)CSL_EPWM_XAQCTLA_SHDW3 + (uint32_t)((uint16_t)epwmOutput/(uint32_t)2);
10430 HW_WR_REG16(base + registerOffset,
10431 ((HW_RD_REG16(base + registerOffset) &
10432 ~(CSL_EPWM_XAQCTLA_SHDW3_XCMP1_MAX << (uint16_t)event)) |
10433 ((uint16_t)output << (uint16_t)event)));
10457 uint32_t registerOffset = base + CSL_EPWM_XLOAD;
10459 HW_WR_REG32(registerOffset,
10460 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOAD_STARTLD_MASK ));
10477 uint32_t registerOffset = base + CSL_EPWM_XLOAD;
10479 HW_WR_REG32(registerOffset,
10480 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOAD_STARTLD_MASK ));
10500 uint32_t registerOffset;
10501 registerOffset = base + CSL_EPWM_XLOAD;
10503 HW_WR_REG32(registerOffset,
10504 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOAD_FRCLD_MASK ));
10524 uint32_t registerOffset;
10529 registerOffset = base + CSL_EPWM_XLOADCTL;
10533 HW_WR_REG32(registerOffset,
10534 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_LOADMODE_MASK));
10538 HW_WR_REG32(registerOffset,
10539 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOADCTL_LOADMODE_MASK));
10566 uint32_t registerOffset;
10571 registerOffset = base + CSL_EPWM_XLOADCTL;
10573 HW_WR_REG32(registerOffset,
10574 ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWLEVEL_MASK) |
10575 (uint32_t)((uint16_t)level << CSL_EPWM_XLOADCTL_SHDWLEVEL_SHIFT)));
10597 uint32_t registerOffset;
10602 registerOffset = base + CSL_EPWM_XLOADCTL;
10604 HW_WR_REG32(registerOffset,
10605 ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_MASK) |
10606 (uint32_t)((uint16_t)ptr << CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_SHIFT)));
10630 uint32_t registerOffset;
10634 registerOffset = base + CSL_EPWM_XLOADCTL;
10638 HW_WR_REG32(registerOffset,
10639 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF2PRD_MASK))
10640 | ((uint32_t)count<<CSL_EPWM_XLOADCTL_RPTBUF2PRD_SHIFT)) );
10644 HW_WR_REG32(registerOffset,
10645 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF3PRD_MASK))
10646 | ((uint32_t)count<<CSL_EPWM_XLOADCTL_RPTBUF3PRD_SHIFT)) );
10674 uint32_t registerOffset;
10678 registerOffset = base + CSL_EPWM_DECTL;
10680 HW_WR_REG32(registerOffset,
10681 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_ENABLE_MAX ));
10700 uint32_t registerOffset;
10704 registerOffset = base + CSL_EPWM_DECTL;
10706 HW_WR_REG32(registerOffset,
10707 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_ENABLE_MAX ));
10732 uint32_t registerOffset;
10737 registerOffset = base + CSL_EPWM_DECTL;
10741 HW_WR_REG32(registerOffset,
10742 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_MODE_MASK));
10746 HW_WR_REG32(registerOffset,
10747 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_MODE_MASK));
10772 uint32_t registerOffset;
10776 registerOffset = base + CSL_EPWM_DECTL;
10778 HW_WR_REG32(registerOffset,
10779 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DECTL_REENTRYDLY_MASK))
10780 | ((uint32_t)delay<<CSL_EPWM_DECTL_REENTRYDLY_SHIFT)) );
10806 uint32_t registerOffset;
10810 registerOffset = base + CSL_EPWM_DECOMPSEL;
10814 HW_WR_REG32(registerOffset,
10815 ((HW_RD_REG32(registerOffset) &
10816 ~CSL_EPWM_DECOMPSEL_TRIPL_MASK) |
10817 ((uint32_t)source<<CSL_EPWM_DECOMPSEL_TRIPL_SHIFT)));
10821 HW_WR_REG32(registerOffset,
10822 ((HW_RD_REG32(registerOffset) &
10823 ~CSL_EPWM_DECOMPSEL_TRIPH_MASK) |
10824 ((uint32_t)source<<CSL_EPWM_DECOMPSEL_TRIPH_SHIFT)));
10857 uint32_t registerOffset;
10861 registerOffset = base + CSL_EPWM_DEACTCTL;
10865 HW_WR_REG32(registerOffset,
10866 ((HW_RD_REG32(registerOffset) &
10867 ~CSL_EPWM_DEACTCTL_PWMA_MASK) |
10868 ((uint32_t)signal<<CSL_EPWM_DEACTCTL_PWMA_SHIFT)));
10872 HW_WR_REG32(registerOffset,
10873 ((HW_RD_REG32(registerOffset) &
10874 ~CSL_EPWM_DEACTCTL_PWMB_MASK) |
10875 ((uint32_t)signal<<CSL_EPWM_DEACTCTL_PWMB_SHIFT)));
10901 uint32_t registerOffset;
10905 registerOffset = base + CSL_EPWM_DEACTCTL;
10909 HW_WR_REG32(registerOffset,
10910 ((HW_RD_REG32(registerOffset) &
10911 ~CSL_EPWM_DEACTCTL_TRIPSELA_MASK) |
10912 (signal<<CSL_EPWM_DEACTCTL_TRIPSELA_SHIFT)));
10916 HW_WR_REG32(registerOffset,
10917 ((HW_RD_REG32(registerOffset) &
10918 ~CSL_EPWM_DEACTCTL_TRIPSELB_MASK) |
10919 (signal<<CSL_EPWM_DEACTCTL_TRIPSELB_SHIFT)));
10935 uint32_t registerOffset;
10939 registerOffset = base + CSL_EPWM_DEACTCTL;
10941 HW_WR_REG32(registerOffset,
10942 (HW_RD_REG32(registerOffset) &
10943 ~(CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
10959 uint32_t registerOffset;
10963 registerOffset = base + CSL_EPWM_DEACTCTL;
10965 HW_WR_REG32(registerOffset,
10966 (HW_RD_REG32(registerOffset) |
10967 (CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
10983 uint32_t registerOffset;
10987 registerOffset = base + CSL_EPWM_DEFRC;
10989 HW_WR_REG32(registerOffset,
10990 (HW_RD_REG32(registerOffset) | CSL_EPWM_DEFRC_DEACTIVE_MASK));
11006 uint32_t registerOffset;
11010 registerOffset = base + CSL_EPWM_DECLR;
11012 HW_WR_REG32(registerOffset,
11013 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECLR_DEACTIVE_MASK));
11029 uint32_t registerOffset;
11033 registerOffset = base + CSL_EPWM_DEMONCTL;
11035 HW_WR_REG32(registerOffset,
11036 (HW_RD_REG32(registerOffset) |
11037 (CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
11052 uint32_t registerOffset;
11056 registerOffset = base + CSL_EPWM_DEMONCTL;
11058 HW_WR_REG32(registerOffset,
11059 (HW_RD_REG32(registerOffset) &
11060 ~(CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
11082 uint32_t registerOffset;
11086 registerOffset = base + CSL_EPWM_DEMONSTEP;
11090 HW_WR_REG32(registerOffset,
11091 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DEMONSTEP_INCSTEP_MASK)
11092 | ((uint32_t)stepsize<<CSL_EPWM_DEMONSTEP_INCSTEP_SHIFT));
11096 HW_WR_REG32(registerOffset,
11097 ((HW_RD_REG32(registerOffset) &
11098 ~CSL_EPWM_DEMONSTEP_DECSTEP_MASK) |
11099 ((uint32_t)stepsize<<CSL_EPWM_DEMONSTEP_DECSTEP_SHIFT)));
11120 uint32_t registerOffset;
11124 registerOffset = base + CSL_EPWM_DEMONTHRES;
11126 HW_WR_REG32(registerOffset,
11127 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DEMONTHRES_THRESHOLD_MASK))
11128 | ((uint32_t)threshold<<CSL_EPWM_DEMONTHRES_THRESHOLD_SHIFT)) );
11183 #endif // EPWM_V1_H_
@ EPWM_TZ_ACTION_HIGH
high voltage state
Definition: etpwm.h:979
@ HRPWM_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:1916
static void EPWM_disableInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:6102
static void EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output, bool enableSwapMode)
Definition: etpwm.h:4413
@ HRPWM_XCMP6_SHADOW3
XCMP6_SHADOW3.
Definition: etpwm.h:2062
static void EPWM_enableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6574
@ EPWM_AQ_OUTPUT_HIGH_UP_T1
T1 event on count up and set output pins to high.
Definition: etpwm.h:688
static uint16_t EPWM_getValleyHWDelay(uint32_t base)
Definition: etpwm.h:8455
static uint16_t EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base)
Definition: etpwm.h:7108
EPWM_TimeBaseCountMode
Definition: etpwm.h:359
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT22
Trip source is INPUTXBAR out22 signal.
Definition: etpwm.h:2412
@ HRPWM_XCMP1_SHADOW2
XCMP1_SHADOW2.
Definition: etpwm.h:2033
@ EPWM_TZ_ACTION_LOW
low voltage state
Definition: etpwm.h:980
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8
Sync-in source is EPWM8 sync-out signal.
Definition: etpwm.h:205
static uint16_t EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5577
EPWM_ActionQualifierLoadMode
Definition: etpwm.h:521
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP10
Sync-in source is ECAP10 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:273
@ EPWM_LINK_WITH_EPWM_5
link current ePWM with ePWM5
Definition: etpwm.h:406
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP13
Sync-in source is ECAP13 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:279
@ HRPWM_XTBPRD_ACTIVE
XTBPRD_ACTIVE.
Definition: etpwm.h:2011
static void EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_FallingEdgeDelayLoadMode loadMode)
Definition: etpwm.h:4746
static void EPWM_selectPeriodLoadEvent(uint32_t base, EPWM_PeriodShadowLoadMode shadowLoadMode)
Definition: etpwm.h:3034
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD
Clear CBC pulse when counter equals zero or period.
Definition: etpwm.h:1152
static void EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink, EPWM_LinkComponent linkComp)
Definition: etpwm.h:3378
EPWM_XCMP_XLOADCTL_SHDWLEVEL
Definition: etpwm.h:2313
static void HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel, HRPWM_MEPEdgeMode mepEdgeMode)
Definition: etpwm.h:9341
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG2
Sync-in source is FSI-RX2 RX Trigger 2 signal.
Definition: etpwm.h:313
@ EPWM_SOC_A
SOC A.
Definition: etpwm.h:1281
@ EPWM_DC_EVENT_1
Digital Compare Event number 1.
Definition: etpwm.h:1491
@ EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:527
@ EPWM_AQ_SW_OUTPUT_HIGH
Set output pins to High.
Definition: etpwm.h:613
@ EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD
Time base counter equals zero or period.
Definition: etpwm.h:1418
@ EPWM_DE_TRIP_SRC_CMPSSB1
Trip source is CMPSSB1 signal.
Definition: etpwm.h:2454
@ EPWM_HSCLOCK_DIVIDER_2
Divide clock by 2.
Definition: etpwm.h:168
@ EPWM_LINK_WITH_EPWM_9
link current ePWM with ePWM9
Definition: etpwm.h:410
static void HRPWM_setMEPStep(uint32_t base, uint16_t mepCount)
Definition: etpwm.h:9956
@ HRPWM_XTBPRD_SHADOW1
XTBPRD_SHADOW1.
Definition: etpwm.h:2030
static void EPWM_startValleyCapture(uint32_t base)
Definition: etpwm.h:8208
static void EPWM_setXCMPShadowRepeatBufxCount(uint32_t base, uint32_t bufferset, uint8_t count)
Definition: etpwm.h:10628
static void EPWM_disableOneShotSync(uint32_t base)
Definition: etpwm.h:3079
@ EPWM_XCMP2_SHADOW3
XCMP2_SHADOW3.
Definition: etpwm.h:2152
@ EPWM_GL_LOAD_PULSE_CNTR_CMPC_U
load when counter is equal to cmpc and cmpc is incrementing
Definition: etpwm.h:1576
static void EPWM_enableValleyHWDelay(uint32_t base)
Definition: etpwm.h:8295
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT18
Trip source is INPUTXBAR out18 signal.
Definition: etpwm.h:2404
static void EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base, EPWM_CycleByCycleTripZoneClearMode clearEvent)
Definition: etpwm.h:5636
static void EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv)
Definition: etpwm.h:4960
@ EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT1
Sync-in source is C2K Timesync xbar sync pwm out1 signal.
Definition: etpwm.h:291
static void EPWM_enableTripZoneOutput(uint32_t base, uint16_t tzOutput)
Definition: etpwm.h:5815
@ EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO
shadow to active load occurs when time base counter reaches 0.
Definition: etpwm.h:375
@ EPWM_DE_TRIP_SRC_CMPSSB0
Trip source is CMPSSB0 signal.
Definition: etpwm.h:2452
@ EPWM_REGISTER_GROUP_TRIP_ZONE
Trip zone register group.
Definition: etpwm.h:1733
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM24
Sync-in source is EPWM24 sync-out signal.
Definition: etpwm.h:237
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U
Digital Compare event A/B 1 while counting up.
Definition: etpwm.h:1028
static void EPWM_forceDiodeEmulationActive(uint32_t base)
Definition: etpwm.h:10981
@ EPWM_COMP_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:482
EPWM_ActionQualifierContForce
Definition: etpwm.h:739
@ EPWM_DE_SYNC_INV_TRIPHorL
synchronized and inverted version of TRIPH or TRIPL signal
Definition: etpwm.h:2479
static uint16_t EPWM_getTimeBaseCounterValue(uint32_t base)
Definition: etpwm.h:3122
static uint16_t EPWM_getADCTriggerEventCount(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6707
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT16
Trip source is INPUTXBAR out16 signal.
Definition: etpwm.h:2400
@ EPWM_DE_HIGH
a constant high signal
Definition: etpwm.h:2483
static void EPWM_enableTripZoneAdvAction(uint32_t base)
Definition: etpwm.h:5215
static void EPWM_setCounterCompareValue_opt_cmpA(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3610
@ HRPWM_PWMSYNC_SOURCE_ZERO
Counter equals zero.
Definition: etpwm.h:1946
@ HRPWM_PWMSYNC_SOURCE_COMPD_UP
Counter equals COMPD when counting up.
Definition: etpwm.h:1952
static void HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount)
Definition: etpwm.h:9925
static void EPWM_setActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierEventAction action)
Definition: etpwm.h:4086
@ EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD
Clear CBC latch when counter equals zero or period.
Definition: etpwm.h:1550
@ EPWM_CLOCK_DIVIDER_32
Divide clock by 32.
Definition: etpwm.h:154
static void EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount)
Definition: etpwm.h:4854
@ EPWM_XCMP_4_CMPA
Allocate XCMP1 - XCMP4 registers to CMPA.
Definition: etpwm.h:2262
#define EPWM_XCMP_SHADOW1
XCMP set = Shadow 2.
Definition: etpwm.h:2078
@ EPWM_XMIN_SHADOW1
XMIN_SHADOW1.
Definition: etpwm.h:2208
static void EPWM_setCounterCompareValue_opt_cmpD(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3667
@ EPWM_COMP_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:488
@ EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT0
Sync-in source is C2K Timesync xbar sync pwm out0 signal.
Definition: etpwm.h:289
@ EPWM_DE_TRIP_SRC_CMPSSB2
Trip source is CMPSSB2 signal.
Definition: etpwm.h:2456
@ EPWM_DC_EDGEFILT_EDGECNT_6
Digital Compare Edge filter edge count = 7.
Definition: etpwm.h:1718
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP12
Sync-in source is ECAP12 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:277
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT12
Trip source is INPUTXBAR out12 signal.
Definition: etpwm.h:2392
Float32 dutyValA
Desired ePWMxA Signal Duty.
Definition: etpwm.h:2605
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO
load on sync or when counter equals zero
Definition: etpwm.h:531
HRPWM_XCMPReg
Definition: etpwm.h:1993
static void EPWM_forceActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput)
Definition: etpwm.h:4367
@ EPWM_XCMP2_ACTIVE
XCMP2_ACTIVE.
Definition: etpwm.h:2095
@ EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO
Clear CBC latch when counter equals zero.
Definition: etpwm.h:1546
@ EPWM_LINK_WITH_EPWM_22
link current ePWM with ePWM22
Definition: etpwm.h:423
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1
T1 event on count down and no change in the output pins.
Definition: etpwm.h:692
void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode)
@ HRPWM_XCMP6_SHADOW1
XCMP6_SHADOW1.
Definition: etpwm.h:2024
@ EPWM_LINK_WITH_EPWM_16
link current ePWM with ePWM16
Definition: etpwm.h:417
EPWM_DigitalCompareEdgeFilterEdgeCount
Definition: etpwm.h:1704
@ EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA
Time base counter down equals COMPA and set output pins to high.
Definition: etpwm.h:653
static void EPWM_selectDigitalCompareTripInput(uint32_t base, EPWM_DigitalCompareTripInput tripSource, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:6786
EPWM_TripZoneDigitalCompareOutput
Definition: etpwm.h:931
EPWM_TripZoneAdvancedEvent
Definition: etpwm.h:991
@ EPWM_XCMP5_SHADOW3
XCMP5_SHADOW3.
Definition: etpwm.h:2158
@ EPWM_FED_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:846
static void EPWM_clearADCTriggerFlag(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6543
@ EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:486
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP9
Sync-in source is ECAP9 sync-out signal.
Definition: etpwm.h:271
@ EPWM_XCMP1_SHADOW1
XCMP1_SHADOW1.
Definition: etpwm.h:2112
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP0
Sync-in source is ECAP0 sync-out signal.
Definition: etpwm.h:253
#define EPWM_XCMP_ACTIVE
< XCMP set = Active
Definition: etpwm.h:2076
static void HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel, HRPWM_MEPCtrlMode mepCtrlMode)
Definition: etpwm.h:9378
static void EPWM_setDigitalCompareEventSyncMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareSyncMode syncMode)
Definition: etpwm.h:7288
@ EPWM_DB_POLARITY_ACTIVE_HIGH
DB polarity is not inverted.
Definition: etpwm.h:782
static void EPWM_setActionQualifierContSWForceShadowMode(uint32_t base, EPWM_ActionQualifierContForce mode)
Definition: etpwm.h:4205
@ EPWM_DB_RED
DB RED (Rising Edge Delay) mode.
Definition: etpwm.h:770
EPWM_XCompareReg
Definition: etpwm.h:2177
@ EPWM_LINK_WITH_EPWM_24
link current ePWM with ePWM24
Definition: etpwm.h:425
EPWM_ActionQualifierTriggerSource
Definition: etpwm.h:547
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1
Time base counter equals XCMP1.
Definition: etpwm.h:2228
@ HRPWM_MEP_PHASE_CTRL
TBPHSHR controls MEP edge.
Definition: etpwm.h:1899
#define EPWM_SYNC_OUT_SOURCE_M
Definition: etpwm.h:79
@ EPWM_COUNTER_COMPARE_D
counter compare D
Definition: etpwm.h:470
@ EPWM_CMPD_SHADOW1
CMPD_SHADOW1.
Definition: etpwm.h:2181
@ EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW
Event when DCxL high DCxH low.
Definition: etpwm.h:951
EPWM_XMinMaxReg
Definition: etpwm.h:2200
@ EPWM_LINK_TBPRD
link TBPRD:TBPRDHR registers
Definition: etpwm.h:443
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT29
Trip source is INPUTXBAR out29 signal.
Definition: etpwm.h:2426
#define EPWM_INT_TBCTR_D_CMPD
time-base counter equal to CMPD when the timer is decrementing
Definition: etpwm.h:1236
@ EPWM_TZ_ADV_ACTION_EVENT_TZA_U
TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up.
Definition: etpwm.h:999
@ EPWM_SOC_TBCTR_PERIOD
Time-base counter equal to period.
Definition: etpwm.h:1298
static uint16_t EPWM_getGlobalLoadEventCount(uint32_t base)
Definition: etpwm.h:8595
@ HRPWM_XCMP5_SHADOW1
XCMP5_SHADOW1.
Definition: etpwm.h:2022
static void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction)
Definition: etpwm.h:5431
@ HRPWM_XCMP3_SHADOW3
XCMP3_SHADOW3.
Definition: etpwm.h:2056
@ EPWM_AQ_OUTPUT_TOGGLE_ZERO
Time base counter equals zero and toggle the output pins.
Definition: etpwm.h:631
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM18
Sync-in source is EPWM18 sync-out signal.
Definition: etpwm.h:225
static void HRPWM_setDeadbandMEPEdgeSelect(uint32_t base, HRPWM_MEPDeadBandEdgeMode mepDBEdge)
Definition: etpwm.h:9993
@ EPWM_DE_TRIP_SRC_CMPSSB4
Trip source is CMPSSB4 signal.
Definition: etpwm.h:2460
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT
Digital compare filter event.
Definition: etpwm.h:556
@ HRPWM_DB_MEP_CTRL_RED
MEP controls Rising Edge Delay.
Definition: etpwm.h:1980
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM0
Sync-in source is EPWM0 sync-out signal.
Definition: etpwm.h:189
@ EPWM_SOC_TBCTR_D_CMPC
time-base counter equal to CMPC when the timer is decrementing
Definition: etpwm.h:1308
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT14
Trip source is INPUTXBAR out14 signal.
Definition: etpwm.h:2396
static void EPWM_setOneShotSyncOutTrigger(uint32_t base, EPWM_OneShotSyncOutTrigger trigger)
Definition: etpwm.h:2893
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA
Time base counter down equals COMPA.
Definition: etpwm.h:574
EPWM_ActionQualifierEventAction
Definition: etpwm.h:623
static void EPWM_disableXCMPMode(uint32_t base)
Definition: etpwm.h:10132
static void EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount)
Definition: etpwm.h:7133
@ EPWM_XCMP_6_CMPA
Allocate XCMP1 - XCMP6 registers to CMPA.
Definition: etpwm.h:2266
@ EPWM_CMPD_SHADOW3
CMPD_SHADOW3.
Definition: etpwm.h:2189
EPWM_ClockDivider tbClkDiv
Time Base Counter Clock Divider.
Definition: etpwm.h:2610
@ EPWM_AQ_OUTPUT_NO_CHANGE
No change in the output pins.
Definition: etpwm.h:597
@ EPWM_DE_TRIP_SRC_CMPSSA0
Trip source is CMPSSA0 signal.
Definition: etpwm.h:2432
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1
Digital compare event B 1.
Definition: etpwm.h:550
static void HRPWM_setHiResRisingEdgeDelay(uint32_t base, uint16_t hrRedCount)
Definition: etpwm.h:9894
@ EPWM_XTBPRD_SHADOW3
XTBPRD_SHADOW3.
Definition: etpwm.h:2166
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG1
Sync-in source is FSI-RX1 RX Trigger 1 signal.
Definition: etpwm.h:303
@ HRPWM_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:1912
static void EPWM_setMinDeadBandDelay(uint32_t base, uint32_t block, uint32_t delay)
Definition: etpwm.h:9044
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM27
Sync-in source is EPWM27 sync-out signal.
Definition: etpwm.h:243
@ EPWM_XCMP3_SHADOW3
XCMP3_SHADOW3.
Definition: etpwm.h:2154
@ EPWM_LINK_WITH_EPWM_12
link current ePWM with ePWM12
Definition: etpwm.h:413
static void HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB)
Definition: etpwm.h:9476
static void EPWM_enableInterrupt(uint32_t base)
Definition: etpwm.h:5866
static void EPWM_setCMPShadowRegValue(uint32_t base, EPWM_XCompareReg cmpReg, uint16_t cmpvalue)
Definition: etpwm.h:10298
static void EPWM_disableTripZoneAdvAction(uint32_t base)
Definition: etpwm.h:5236
static void EPWM_clearDiodeEmulationActive(uint32_t base)
Definition: etpwm.h:11004
#define EPWM_DB_INPUT_EPWMA
Input signal is ePWMA.
Definition: etpwm.h:793
@ HRPWM_XCMP5_ACTIVE
XCMP5_ACTIVE.
Definition: etpwm.h:2003
static void EPWM_setDeadBandCounterClock(uint32_t base, EPWM_DeadBandClockMode clockMode)
Definition: etpwm.h:4801
@ EPWM_OSHT_SYNC_OUT_TRIG_RELOAD
Trigger is OSHT reload.
Definition: etpwm.h:335
@ EPWM_AQ_OUTPUT_HIGH_ZERO
Time base counter equals zero and set output pins to high.
Definition: etpwm.h:629
@ EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD
load on sync event or when counter is equal to period
Definition: etpwm.h:1572
HRPWM_ChannelBOutput
Definition: etpwm.h:1928
@ EPWM_LINK_WITH_EPWM_2
link current ePWM with ePWM2
Definition: etpwm.h:403
static void EPWM_enableIllegalComboLogic(uint32_t base, uint32_t block)
Definition: etpwm.h:9078
static void HRPWM_disablePeriodControl(uint32_t base)
Definition: etpwm.h:9563
@ EPWM_DB_OUTPUT_A
DB output is ePWMA.
Definition: etpwm.h:758
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD
Clear CBC pulse when counter equals period.
Definition: etpwm.h:1150
EPWM_TripZoneDigitalCompareOutputEvent
Definition: etpwm.h:945
@ EPWM_SHADOW_LOAD_MODE_SYNC
shadow to active load occurs only when a SYNC occurs
Definition: etpwm.h:380
static void EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode)
Definition: etpwm.h:3003
EPWM_PeriodLoadMode
Definition: etpwm.h:345
Float32 sysClkInHz
SYSCLK Frequency(in Hz)
Definition: etpwm.h:2608
EPWM_CurrentLink
Definition: etpwm.h:400
static void EPWM_setDeadBandDelayPolarity(uint32_t base, EPWM_DeadBandDelayMode delayMode, EPWM_DeadBandPolarity polarity)
Definition: etpwm.h:4508
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM15
Sync-in source is EPWM15 sync-out signal.
Definition: etpwm.h:219
@ EPWM_HSCLOCK_DIVIDER_1
Divide clock by 1.
Definition: etpwm.h:167
static void EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth)
Definition: etpwm.h:4992
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4
Sync-in source is EPWM4 sync-out signal.
Definition: etpwm.h:197
@ EPWM_HSCLOCK_DIVIDER_14
Divide clock by 14.
Definition: etpwm.h:174
@ EPWM_AQ_OUTPUT_LOW_DOWN_T2
T2 event on count down and set output pins to low.
Definition: etpwm.h:710
#define EPWM_DCxxTRIPSEL
Definition: etpwm.h:2589
HRPWM_MEPCtrlMode
Definition: etpwm.h:1895
EPWM_DiodeEmulationSignal
Definition: etpwm.h:2474
@ EPWM_REGISTER_GROUP_DIGITAL_COMPARE
Digital compare group.
Definition: etpwm.h:1735
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG0
Sync-in source is FSI-RX3 RX Trigger 0 signal.
Definition: etpwm.h:317
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8
Time base counter equals XCMP8.
Definition: etpwm.h:2242
@ EPWM_XCMP_7_CMPA
Allocate XCMP1 - XCMP7 registers to CMPA.
Definition: etpwm.h:2268
static void EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base)
Definition: etpwm.h:4772
static void EPWM_clearEventTriggerInterruptFlag(uint32_t base)
Definition: etpwm.h:6056
EPWM_DigitalCompareTripInput
Definition: etpwm.h:1346
@ HRPWM_XCMP4_ACTIVE
XCMP4_ACTIVE.
Definition: etpwm.h:2001
@ EPWM_AQ_SW_OUTPUT_LOW
Set output pins to low.
Definition: etpwm.h:612
static void EPWM_enableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:7754
EPWM_SyncInPulseSource
Definition: etpwm.h:185
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2
T2 event on count down and toggle the output pins.
Definition: etpwm.h:714
static void EPWM_selectMinimumDeadBandReferenceSignal(uint32_t base, uint32_t block, uint32_t referenceSignal)
Definition: etpwm.h:8979
EPWM_DeadBandControlLoadMode
Definition: etpwm.h:806
EPWM_ActionQualifierSWOutput
Definition: etpwm.h:610
static void EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode)
Definition: etpwm.h:8361
@ EPWM_AQ_OUTPUT_ON_T1_COUNT_UP
T1 event on count up.
Definition: etpwm.h:580
static void EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags)
Definition: etpwm.h:5673
static void HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:10053
EPWM_ADCStartOfConversionType
Definition: etpwm.h:1280
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT28
Trip source is INPUTXBAR out28 signal.
Definition: etpwm.h:2424
@ EPWM_XCMP_2_CMPA
Allocate XCMP1 - XCMP2 registers to CMPA.
Definition: etpwm.h:2258
static void EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger)
Definition: etpwm.h:8234
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY
Definition: etpwm.h:1669
static void EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode)
Definition: etpwm.h:2655
static void EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent, EPWM_TripZoneAdvancedAction tzAdvAction)
Definition: etpwm.h:5329
@ EPWM_GL_LOAD_PULSE_SYNC
load on sync event
Definition: etpwm.h:1568
static void EPWM_disableDigitalCompareWindowInverseMode(uint32_t base)
Definition: etpwm.h:6879
@ EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO
load on sync event or when counter is equal to zero
Definition: etpwm.h:1570
static void EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount)
Definition: etpwm.h:4928
#define EPWM_INT_TBCTR_ETINTMIX
Time-base counter based on mix events.
Definition: etpwm.h:1220
@ EPWM_XCMP5_SHADOW1
XCMP5_SHADOW1.
Definition: etpwm.h:2120
@ EPWM_LINK_WITH_EPWM_18
link current ePWM with ePWM18
Definition: etpwm.h:419
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA
Time base counter down equals COMPA and no change in the output pins.
Definition: etpwm.h:649
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT25
Trip source is INPUTXBAR out25 signal.
Definition: etpwm.h:2418
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_0
Only Active register is available.
Definition: etpwm.h:2315
static void EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount)
Definition: etpwm.h:6003
static void EPWM_nobypassDiodeEmulationLogic(uint32_t base)
Definition: etpwm.h:10933
@ EPWM_CLOCK_DIVIDER_8
Divide clock by 8.
Definition: etpwm.h:152
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT3
Trip source is INPUTXBAR out3 signal.
Definition: etpwm.h:2374
@ EPWM_TZ_ADV_ACTION_EVENT_TZA_D
TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down.
Definition: etpwm.h:997
static bool EPWM_getSyncStatus(uint32_t base)
Definition: etpwm.h:3188
@ HRPWM_XCMP7_SHADOW2
XCMP7_SHADOW2.
Definition: etpwm.h:2045
@ HRPWM_XCMP8_SHADOW1
XCMP8_SHADOW1.
Definition: etpwm.h:2028
@ EPWM_TZ_ADV_ACTION_LOW
low voltage state
Definition: etpwm.h:1013
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:492
@ EPWM_COUNTER_MODE_UP
Up - count mode.
Definition: etpwm.h:360
@ EPWM_SOC_TBCTR_U_CMPD
time-base counter equal to CMPD when the timer is incrementing
Definition: etpwm.h:1312
static void EPWM_setADCTriggerSource(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, EPWM_ADCStartOfConversionSource socSource, uint16_t mixedSource)
Definition: etpwm.h:6314
static void EPWM_disableSplitXCMP(uint32_t base)
Definition: etpwm.h:10176
static void EPWM_enableMinimumDeadBand(uint32_t base, uint32_t block)
Definition: etpwm.h:8817
@ EPWM_HSCLOCK_DIVIDER_6
Divide clock by 6.
Definition: etpwm.h:170
@ EPWM_XCMP_1_CMPA
Allocate XCMP1 register to CMPA.
Definition: etpwm.h:2256
static uint16_t EPWM_getTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5545
@ EPWM_REGISTER_GROUP_GLOBAL_LOAD
Global load register group.
Definition: etpwm.h:1732
@ EPWM_GL_LOAD_PULSE_CNTR_PERIOD
load when counter is equal to period
Definition: etpwm.h:1564
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2
Time base counter equals XCMP2.
Definition: etpwm.h:2230
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2
T2 event on count up and no change in the output pins.
Definition: etpwm.h:700
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG0
Sync-in source is FSI-RX0 RX Trigger 0 signal.
Definition: etpwm.h:293
static uint16_t EPWM_getTimeBasePeriod(uint32_t base)
Definition: etpwm.h:3305
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG2
Sync-in source is FSI-RX0 RX Trigger 2 signal.
Definition: etpwm.h:297
static void EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue)
Definition: etpwm.h:8340
@ EPWM_DC_MODULE_A
Digital Compare Module A.
Definition: etpwm.h:1476
@ EPWM_AQ_OUTPUT_A
ePWMxA output
Definition: etpwm.h:728
EPWM_GlobalLoadTrigger
Definition: etpwm.h:1560
@ EPWM_HSCLOCK_DIVIDER_10
Divide clock by 10.
Definition: etpwm.h:172
@ EPWM_LINK_WITH_EPWM_0
link current ePWM with ePWM0
Definition: etpwm.h:401
@ EPWM_COUNT_MODE_DOWN_AFTER_SYNC
Count down after sync event.
Definition: etpwm.h:137
@ EPWM_DC_WINDOW_START_TBCTR_ZERO
Time base counter equals zero.
Definition: etpwm.h:1416
@ EPWM_AQ_OUTPUT_TOGGLE
Toggle the output pins.
Definition: etpwm.h:600
EPWM_DigitalCompareCBCLatchClearEvent
Definition: etpwm.h:1544
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1
Digital compare event A 1.
Definition: etpwm.h:548
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP14
Sync-in source is ECAP14 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:281
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_TWO
Shadow buffer 2 is in use.
Definition: etpwm.h:2338
static void EPWM_disableDiodeEmulationMonitorModeControl(uint32_t base)
Definition: etpwm.h:11050
@ EPWM_AQ_OUTPUT_HIGH_DOWN_T1
T1 event on count down and set output pins to high.
Definition: etpwm.h:696
@ EPWM_XCMP3_SHADOW1
XCMP3_SHADOW1.
Definition: etpwm.h:2116
static bool EPWM_getDigitalCompareCaptureStatus(uint32_t base)
Definition: etpwm.h:7701
@ EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE
Valley capture trigged by software.
Definition: etpwm.h:1625
static void EPWM_setGlobalLoadOneShotLatch(uint32_t base)
Definition: etpwm.h:8665
@ EPWM_AQ_SW_DISABLED
Software forcing disabled.
Definition: etpwm.h:611
@ HRPWM_XCMP3_SHADOW1
XCMP3_SHADOW1.
Definition: etpwm.h:2018
EPWM_ADCStartOfConversionSource
Definition: etpwm.h:1292
@ HRPWM_XCMP5_SHADOW3
XCMP5_SHADOW3.
Definition: etpwm.h:2060
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT23
Trip source is INPUTXBAR out23 signal.
Definition: etpwm.h:2414
static void EPWM_disableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:7803
@ HRPWM_PWMSYNC_SOURCE_COMPD_DOWN
Counter equals COMPD when counting down.
Definition: etpwm.h:1954
EPWM_EmulationMode
Definition: etpwm.h:120
@ EPWM_XMIN_SHADOW3
XMIN_SHADOW3.
Definition: etpwm.h:2216
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2
Trip zone 2.
Definition: etpwm.h:553
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP11
Sync-in source is ECAP11 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:275
@ EPWM_DC_WINDOW_SOURCE_DCBEVT2
DC filter signal source is DCBEVT2.
Definition: etpwm.h:1461
#define EPWM_INT_TBCTR_U_CMPC
time-base counter equal to CMPC when the timer is incrementing
Definition: etpwm.h:1224
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM25
Sync-in source is EPWM25 sync-out signal.
Definition: etpwm.h:239
@ EPWM_DC_EDGEFILT_EDGECNT_2
Digital Compare Edge filter edge count = 3.
Definition: etpwm.h:1710
#define EPWM_INT_TBCTR_D_CMPB
time-base counter equal to CMPB when the timer is decrementing
Definition: etpwm.h:1234
EPWM_XCMP_ALLOC_CMPA
Values that can be passed to EPWM_allocAXCMP() as the alloctype parameter.
Definition: etpwm.h:2252
@ EPWM_XMIN_ACTIVE
XMIN_ACTIVE.
Definition: etpwm.h:2204
@ EPWM_LINK_WITH_EPWM_20
link current ePWM with ePWM20
Definition: etpwm.h:421
@ EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:830
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2
Digital compare event A 2.
Definition: etpwm.h:549
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6
Time base counter equals XCMP6.
Definition: etpwm.h:2238
@ HRPWM_XCMP3_SHADOW2
XCMP3_SHADOW2.
Definition: etpwm.h:2037
static void HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource)
Definition: etpwm.h:9639
static void HRPWM_setHiResTimeBasePeriod(uint32_t base, uint16_t hrPeriodCount)
Definition: etpwm.h:9281
@ EPWM_LINK_WITH_EPWM_30
link current ePWM with ePWM30
Definition: etpwm.h:431
static void EPWM_enableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7333
@ EPWM_DC_TYPE_DCAL
Digital Compare A Low.
Definition: etpwm.h:1333
EPWM_CounterCompareModule
Definition: etpwm.h:466
EPWM_HSClockDivider tbHSClkDiv
Time Base Counter HS Clock Divider.
Definition: etpwm.h:2611
@ EPWM_XTBPRD_SHADOW1
XTBPRD_SHADOW1.
Definition: etpwm.h:2128
@ EPWM_OSHT_SYNC_OUT_TRIG_SYNC
Trigger is OSHT sync.
Definition: etpwm.h:334
HRPWM_CounterCompareModule
Definition: etpwm.h:1964
@ EPWM_TZ_EVENT_DCXL_LOW
Event when DCxL low.
Definition: etpwm.h:949
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D
Digital Compare event A/B 1 while counting down.
Definition: etpwm.h:1030
static void HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount)
Definition: etpwm.h:9216
EPWM_DigitalCompareSyncMode
Definition: etpwm.h:1516
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT15
Trip source is INPUTXBAR out15 signal.
Definition: etpwm.h:2398
static void EPWM_setTimeBaseCounter(uint32_t base, uint16_t count)
Definition: etpwm.h:2630
@ EPWM_COUNTER_COMPARE_A
counter compare A
Definition: etpwm.h:467
@ EPWM_DC_EDGEFILT_MODE_BOTH
Definition: etpwm.h:1694
@ EPWM_LINK_WITH_EPWM_13
link current ePWM with ePWM13
Definition: etpwm.h:414
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM16
Sync-in source is EPWM16 sync-out signal.
Definition: etpwm.h:221
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB
Time base counter up equals COMPB.
Definition: etpwm.h:576
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP4
Sync-in source is ECAP4 sync-out signal.
Definition: etpwm.h:261
@ EPWM_XCMP1_SHADOW2
XCMP1_SHADOW2.
Definition: etpwm.h:2131
static void EPWM_enableTripZoneSignals(uint32_t base, uint32_t tzSignal)
Definition: etpwm.h:5045
@ EPWM_DC_TRIP_TRIPIN13
Trip 13.
Definition: etpwm.h:1359
@ HRPWM_XCMP7_SHADOW3
XCMP7_SHADOW3.
Definition: etpwm.h:2064
@ EPWM_DC_EDGEFILT_EDGECNT_7
Definition: etpwm.h:1720
@ HRPWM_XCMP2_SHADOW1
XCMP2_SHADOW1.
Definition: etpwm.h:2016
@ EPWM_AQ_OUTPUT_B
ePWMxB output
Definition: etpwm.h:729
@ EPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR
Trip zone clear group.
Definition: etpwm.h:1734
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD
Time base counter equals period.
Definition: etpwm.h:570
static void EPWM_disableDigitalCompareBlankingWindow(uint32_t base)
Definition: etpwm.h:6836
@ EPWM_SOC_TBCTR_ZERO
Time-base counter equal to zero.
Definition: etpwm.h:1296
@ EPWM_LINK_WITH_EPWM_29
link current ePWM with ePWM29
Definition: etpwm.h:430
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY
Definition: etpwm.h:1675
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT31
Trip source is INPUTXBAR out31 signal.
Definition: etpwm.h:2430
static void EPWM_setCounterCompareValue_opt_cmpC(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3648
@ EPWM_LINK_WITH_EPWM_14
link current ePWM with ePWM14
Definition: etpwm.h:415
static void EPWM_setActionQualifierT1TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger)
Definition: etpwm.h:3872
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM17
Sync-in source is EPWM17 sync-out signal.
Definition: etpwm.h:223
#define EPWM_MINDB_BLOCK_A
Values that can be passed to.
Definition: etpwm.h:1747
EPWM_ActionQualifierOutputEvent
Definition: etpwm.h:566
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD
load on sync or when counter equals period
Definition: etpwm.h:533
@ EPWM_XCMP_XLOADCTL_LOADMODE_LOADMULTIPLE
Load mode is LOADMULTIPLE.
Definition: etpwm.h:2302
@ EPWM_DC_EDGEFILT_EDGECNT_0
Digital Compare Edge filter edge count = 0.
Definition: etpwm.h:1706
@ EPWM_AQ_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:523
@ EPWM_DC_TYPE_DCAH
Digital Compare A High.
Definition: etpwm.h:1332
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1
Sync-in source is EPWM1 sync-out signal.
Definition: etpwm.h:191
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM31
Sync-in source is EPWM31 sync-out signal.
Definition: etpwm.h:251
@ EPWM_XCMP8_SHADOW3
XCMP8_SHADOW3.
Definition: etpwm.h:2164
@ HRPWM_OUTPUT_ON_B_INV_A
Definition: etpwm.h:1932
static void EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger)
Definition: etpwm.h:8538
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3
Sync-in source is EPWM3 sync-out signal.
Definition: etpwm.h:195
@ EPWM_TZ_ACTION_EVENT_TZB
TZ1 - TZ6, DCBEVT2, DCBEVT1.
Definition: etpwm.h:963
static bool EPWM_getEventTriggerInterruptStatus(uint32_t base)
Definition: etpwm.h:6035
static void EPWM_setXCMPActionQualifierAction(uint32_t base, uint32_t shadowset, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_XCMPActionQualifierOutputEvent event)
Definition: etpwm.h:10388
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:494
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4
Time base counter equals XCMP4.
Definition: etpwm.h:2234
@ EPWM_CLOCK_DIVIDER_64
Divide clock by 64.
Definition: etpwm.h:155
@ EPWM_AQ_OUTPUT_TOGGLE_UP_T1
T1 event on count up and toggle the output pins.
Definition: etpwm.h:690
static void EPWM_selectDiodeEmulationTripSignal(uint32_t base, uint32_t channel, uint32_t signal)
Definition: etpwm.h:10898
static void EPWM_allocAXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPA alloctype)
Definition: etpwm.h:10209
@ EPWM_LINK_WITH_EPWM_3
link current ePWM with ePWM3
Definition: etpwm.h:404
EPWM_TimeBaseCountMode tbCtrMode
Time Base Counter Mode.
Definition: etpwm.h:2609
static void EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount)
Definition: etpwm.h:3256
static void EPWM_enableDiodeEmulationMode(uint32_t base)
Definition: etpwm.h:10672
EPWM_DigitalCompareType
Definition: etpwm.h:1331
@ EPWM_COMP_LOAD_ON_SYNC_ONLY
load on sync only
Definition: etpwm.h:496
@ EPWM_REGISTER_GROUP_HR
HRPWM register group.
Definition: etpwm.h:1731
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA
Time base counter down equals COMPA and toggle the output pins.
Definition: etpwm.h:655
@ EPWM_LINK_WITH_EPWM_21
link current ePWM with ePWM21
Definition: etpwm.h:422
static void EPWM_forceEventTriggerInterrupt(uint32_t base)
Definition: etpwm.h:6203
static void EPWM_selectXbarInput(uint32_t base, uint32_t block, uint32_t xbarInput)
Definition: etpwm.h:9137
static void EPWM_setDiodeEmulationMode(uint32_t base, EPWM_DiodeEmulationMode mode)
Definition: etpwm.h:10730
EPWM_DeadBandOutput
Definition: etpwm.h:757
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U
Digital Compare event A/B 2 while counting up.
Definition: etpwm.h:1032
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG1
Sync-in source is FSI-RX0 RX Trigger 1 signal.
Definition: etpwm.h:295
@ EPWM_EMULATION_STOP_AFTER_FULL_CYCLE
Stop when counter completes whole cycle.
Definition: etpwm.h:124
@ EPWM_TZ_ADV_ACTION_EVENT_TZB_D
TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down.
Definition: etpwm.h:993
static void EPWM_disableValleyHWDelay(uint32_t base)
Definition: etpwm.h:8317
@ EPWM_SOC_TBCTR_MIXED_EVENT
Time-base counter equal to zero or period.
Definition: etpwm.h:1300
static void EPWM_setXCMPShadowBufPtrLoadOnce(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWBUFPTR ptr)
Definition: etpwm.h:10595
static void EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler, EPWM_HSClockDivider highSpeedPrescaler)
Definition: etpwm.h:2701
@ EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB
Time base counter up equals COMPB and toggle the output pins.
Definition: etpwm.h:663
static uint16_t EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base)
Definition: etpwm.h:7195
@ EPWM_AQ_OUTPUT_LOW_UP_CMPB
Time base counter up equals COMPB and set output pins to low.
Definition: etpwm.h:659
@ EPWM_RED_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:826
@ EPWM_HSCLOCK_DIVIDER_8
Divide clock by 8.
Definition: etpwm.h:171
@ EPWM_TZ_DC_OUTPUT_A2
Digital Compare output 2 A.
Definition: etpwm.h:933
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT13
Trip source is INPUTXBAR out13 signal.
Definition: etpwm.h:2394
Float32 dutyValB
Desired ePWMxB Signal Duty.
Definition: etpwm.h:2606
static void EPWM_lockRegisters(uint32_t base, EPWM_LockRegisterGroup registerGroup)
Definition: etpwm.h:8792
static void HRPWM_disableAutoConversion(uint32_t base)
Definition: etpwm.h:9521
@ EPWM_DE_TRIP_SRC_CMPSSA2
Trip source is CMPSSA2 signal.
Definition: etpwm.h:2436
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM12
Sync-in source is EPWM12 sync-out signal.
Definition: etpwm.h:213
@ HRPWM_XCMP2_ACTIVE
XCMP2_ACTIVE.
Definition: etpwm.h:1997
#define EPWM_INT_TBCTR_D_CMPC
time-base counter equal to CMPC when the timer is decrementing
Definition: etpwm.h:1228
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2
T2 event on count down and no change in the output pins.
Definition: etpwm.h:708
@ EPWM_AQ_OUTPUT_TOGGLE_UP_T2
T2 event on count up and toggle the output pins.
Definition: etpwm.h:706
@ EPWM_XCMP8_ACTIVE
XCMP8_ACTIVE.
Definition: etpwm.h:2107
static void EPWM_enableXLoad(uint32_t base)
Definition: etpwm.h:10455
@ EPWM_TZ_ACTION_DISABLE
disable action
Definition: etpwm.h:981
@ EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN
ePWM sync
Definition: etpwm.h:555
static void EPWM_forceADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6633
static uint32_t EPWM_getMinDeadBandDelay(uint32_t base, uint32_t block)
Definition: etpwm.h:9011
@ HRPWM_XCMP6_ACTIVE
XCMP6_ACTIVE.
Definition: etpwm.h:2005
@ EPWM_XCMP_NONE_CMPA
Allocate 0 XCMP registers to CMPA.
Definition: etpwm.h:2254
static void EPWM_disableIllegalComboLogic(uint32_t base, uint32_t block)
Definition: etpwm.h:9107
@ EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD
load on sync event or when counter is equal to period or zero
Definition: etpwm.h:1574
static void EPWM_disableActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule)
Definition: etpwm.h:3833
static void EPWM_setADCTriggerEventPrescale(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t preScaleCount)
Definition: etpwm.h:6461
static void EPWM_enableInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:6079
EPWM_DiodeEmulationTripSource
Definition: etpwm.h:2366
static void EPWM_enableDigitalCompareCounterCapture(uint32_t base)
Definition: etpwm.h:7617
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_ONE
Shadow buffer 1 is in use.
Definition: etpwm.h:2336
@ EPWM_DC_WINDOW_SOURCE_DCAEVT1
DC filter signal source is DCAEVT1.
Definition: etpwm.h:1458
EPWM_DigitalCompareEvent
Definition: etpwm.h:1490
static void HRPWM_enableAutoConversion(uint32_t base)
Definition: etpwm.h:9499
@ EPWM_LINK_COMP_B
link COMPB registers
Definition: etpwm.h:445
@ EPWM_LINK_WITH_EPWM_6
link current ePWM with ePWM6
Definition: etpwm.h:407
static void EPWM_enableDigitalCompareWindowInverseMode(uint32_t base)
Definition: etpwm.h:6858
@ EPWM_XCMP4_SHADOW3
XCMP4_SHADOW3.
Definition: etpwm.h:2156
@ EPWM_LINK_WITH_EPWM_15
link current ePWM with ePWM15
Definition: etpwm.h:416
@ HRPWM_MEP_DUTY_PERIOD_CTRL
CMPAHR/CMPBHR or TBPRDHR controls MEP edge.
Definition: etpwm.h:1897
static void EPWM_disableDeadBandControlShadowLoadMode(uint32_t base)
Definition: etpwm.h:4662
@ EPWM_DE_TRIP_SRC_CMPSSA5
Trip source is CMPSSA5 signal.
Definition: etpwm.h:2442
@ EPWM_DB_POLARITY_ACTIVE_LOW
DB polarity is inverted.
Definition: etpwm.h:783
static void EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_RisingEdgeDelayLoadMode loadMode)
Definition: etpwm.h:4691
@ EPWM_TZ_ADV_ACTION_DISABLE
disable action
Definition: etpwm.h:1015
@ EPWM_CLOCK_DIVIDER_4
Divide clock by 4.
Definition: etpwm.h:151
@ EPWM_DC_EVENT_INPUT_SYNCED
DC input signal is synced with TBCLK.
Definition: etpwm.h:1518
@ EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD
Time base counter equals period and no change in the output pins.
Definition: etpwm.h:633
@ EPWM_LINK_DBRED
link DBRED registers
Definition: etpwm.h:449
EPWM_ValleyCounterEdge
Definition: etpwm.h:1649
EPWM_LockRegisterGroup
Definition: etpwm.h:1730
@ EPWM_SYNC_IN_PULSE_SRC_DISABLE
Disable Sync-in.
Definition: etpwm.h:187
static void EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
Definition: etpwm.h:4580
void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams)
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_THREE
Shadow buffer 3 is in use.
Definition: etpwm.h:2340
EPWM_SyncCountMode
Definition: etpwm.h:136
@ EPWM_RED_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:832
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG0
Sync-in source is FSI-RX1 RX Trigger 0 signal.
Definition: etpwm.h:301
@ EPWM_HSCLOCK_DIVIDER_12
Divide clock by 12.
Definition: etpwm.h:173
HRPWM_Channel
Definition: etpwm.h:1865
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM21
Sync-in source is EPWM21 sync-out signal.
Definition: etpwm.h:231
static void EPWM_setDeadBandControlShadowLoadMode(uint32_t base, EPWM_DeadBandControlLoadMode loadMode)
Definition: etpwm.h:4637
@ EPWM_DC_TRIP_TRIPIN4
Trip 4.
Definition: etpwm.h:1350
EPWM_HSClockDivider
Definition: etpwm.h:166
@ EPWM_RED_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:828
static void HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap)
Definition: etpwm.h:9443
@ EPWM_AQ_OUTPUT_LOW_DOWN_CMPA
Time base counter down equals COMPA and set output pins to low.
Definition: etpwm.h:651
static void EPWM_disableIndependentPulseLogic(uint32_t base)
Definition: etpwm.h:7969
@ HRPWM_MEP_CTRL_DISABLE
HRPWM is disabled.
Definition: etpwm.h:1879
@ EPWM_AQ_OUTPUT_NO_CHANGE_ZERO
Time base counter equals zero and no change in the output pins.
Definition: etpwm.h:625
@ EPWM_DE_TRIP_SRC_CMPSSA1
Trip source is CMPSSA1 signal.
Definition: etpwm.h:2434
static void EPWM_selectCaptureTripInput(uint32_t base, EPWM_DigitalCompareTripInput tripSource, uint8_t dcType)
Definition: etpwm.h:8026
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT19
Trip source is INPUTXBAR out19 signal.
Definition: etpwm.h:2406
@ EPWM_AQ_OUTPUT_LOW
Set output pins to low.
Definition: etpwm.h:598
@ EPWM_XCMP_1_CMPB
Allocate XCMP5 register to CMPB.
Definition: etpwm.h:2282
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT8
Trip source is INPUTXBAR out8 signal.
Definition: etpwm.h:2384
static uint16_t EPWM_getTimeBaseCounterDirection(uint32_t base)
Definition: etpwm.h:3232
HRPWM_LoadMode
Definition: etpwm.h:1910
@ EPWM_XCMP1_ACTIVE
XCMP1_ACTIVE.
Definition: etpwm.h:2093
static void EPWM_selectMinimumDeadBandAndOrLogic(uint32_t base, uint32_t block, uint32_t referenceSignal)
Definition: etpwm.h:8912
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM19
Sync-in source is EPWM19 sync-out signal.
Definition: etpwm.h:227
static uint16_t EPWM_getDigitalCompareCaptureCount(uint32_t base)
Definition: etpwm.h:7724
static void EPWM_setDigitalCompareBlankingEvent(uint32_t base, EPWM_DigitalCompareBlankingPulse blankingPulse, uint16_t mixedSource)
Definition: etpwm.h:6909
#define EPWM_INT_TBCTR_U_CMPD
time-base counter equal to CMPD when the timer is incrementing
Definition: etpwm.h:1232
@ EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE
Load mode is LOADONCE.
Definition: etpwm.h:2300
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG1
Sync-in source is FSI-RX3 RX Trigger 1 signal.
Definition: etpwm.h:319
@ EPWM_LINK_XLOAD
link XLOAD registers
Definition: etpwm.h:451
@ EPWM_TZ_ADV_ACTION_EVENT_TZB_U
TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up.
Definition: etpwm.h:995
@ EPWM_TZ_EVENT_DC_DISABLED
Event is disabled.
Definition: etpwm.h:946
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_3
SHDW3, SHDW2, SHDW1 and Active registers are available.
Definition: etpwm.h:2321
static uint16_t EPWM_getInterruptEventCount(uint32_t base)
Definition: etpwm.h:6181
@ HRPWM_XCMP8_SHADOW2
XCMP8_SHADOW2.
Definition: etpwm.h:2047
static void EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode)
Definition: etpwm.h:7664
Float32 freqInHz
Desired Signal Frequency(in Hz)
Definition: etpwm.h:2604
@ EPWM_ACTION_QUALIFIER_A
Action Qualifier A.
Definition: etpwm.h:510
#define EPWM_DE_TRIPH
Definition: etpwm.h:2516
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM11
Sync-in source is EPWM11 sync-out signal.
Definition: etpwm.h:211
@ EPWM_DE_TRIP_SRC_CMPSSB5
Trip source is CMPSSB5 signal.
Definition: etpwm.h:2462
@ EPWM_DE_TRIP_SRC_CMPSSA4
Trip source is CMPSSA4 signal.
Definition: etpwm.h:2440
#define EPWM_XCMP_SHADOW3
Definition: etpwm.h:2082
EPWM_TripZoneEvent
Definition: etpwm.h:961
@ HRPWM_XCMP5_SHADOW2
XCMP5_SHADOW2.
Definition: etpwm.h:2041
@ HRPWM_XCMP3_ACTIVE
XCMP3_ACTIVE.
Definition: etpwm.h:1999
@ EPWM_DC_TRIP_COMBINATION
All Trips (Trip1 - Trip 15) are selected.
Definition: etpwm.h:1362
@ EPWM_GL_LOAD_PULSE_GLOBAL_FORCE
load on global force
Definition: etpwm.h:1584
@ EPWM_DC_TRIP_TRIPIN15
Trip 15.
Definition: etpwm.h:1361
static void EPWM_disableGlobalLoadOneShotMode(uint32_t base)
Definition: etpwm.h:8618
#define EPWM_INT_TBCTR_D_CMPA
time-base counter equal to CMPA when the timer is decrementing
Definition: etpwm.h:1226
EPWM_DigitalCompareBlankingPulse
Definition: etpwm.h:1412
static uint16_t HRPWM_getHiResCounterCompareValueOnly(uint32_t base, HRPWM_CounterCompareModule compModule)
Definition: etpwm.h:9851
static void EPWM_forceSyncPulse(uint32_t base)
Definition: etpwm.h:2728
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY
Definition: etpwm.h:1672
EPWM_ValleyDelayMode
Definition: etpwm.h:1661
@ EPWM_LINK_WITH_EPWM_11
link current ePWM with ePWM11
Definition: etpwm.h:412
@ EPWM_CLOCK_DIVIDER_1
Divide clock by 1.
Definition: etpwm.h:149
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA
Time base counter up equals COMPA and no change in the output pins.
Definition: etpwm.h:641
@ EPWM_XCMP_3_CMPA
Allocate XCMP1 - XCMP3 registers to CMPA.
Definition: etpwm.h:2260
#define EPWM_CAPTURE_GATE
Capture Gate.
Definition: etpwm.h:2553
static void EPWM_setSyncInPulseSource(uint32_t base, EPWM_SyncInPulseSource source)
Definition: etpwm.h:2768
@ EPWM_DE_TRIP_SRC_CMPSSB8
Trip source is CMPSSB8 signal.
Definition: etpwm.h:2468
@ EPWM_TZ_ACTION_HIGH_Z
high impedance output
Definition: etpwm.h:978
static void EPWM_allocBXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPB alloctype)
Definition: etpwm.h:10236
@ HRPWM_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:1914
static void EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction)
Definition: etpwm.h:5380
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT6
Trip source is INPUTXBAR out6 signal.
Definition: etpwm.h:2380
static void EPWM_setDigitalCompareEdgeFilterMode(uint32_t base, EPWM_DigitalCompareEdgeFilterMode edgeMode)
Definition: etpwm.h:7026
@ EPWM_LINK_WITH_EPWM_23
link current ePWM with ePWM23
Definition: etpwm.h:424
@ EPWM_EMULATION_STOP_AFTER_NEXT_TB
Stop after next Time Base counter increment or decrement.
Definition: etpwm.h:122
static void EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount)
Definition: etpwm.h:8565
@ EPWM_SOC_TBCTR_D_CMPA
time-base counter equal to CMPA when the timer is decrementing
Definition: etpwm.h:1306
@ EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL
signal source is unfiltered (DCAEVT1/2)
Definition: etpwm.h:1504
bool invertSignalB
Invert ePWMxB Signal if true.
Definition: etpwm.h:2607
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG2
Sync-in source is FSI-RX1 RX Trigger 2 signal.
Definition: etpwm.h:305
@ EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN
T2 event on count down.
Definition: etpwm.h:586
static void EPWM_setActionQualifierAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_ActionQualifierOutputEvent event)
Definition: etpwm.h:3962
@ EPWM_DB_FED
DB FED (Falling Edge Delay) mode.
Definition: etpwm.h:771
static void EPWM_disableMinimumDeadBand(uint32_t base, uint32_t block)
Definition: etpwm.h:8846
@ EPWM_TZ_DC_OUTPUT_B2
Digital Compare output 2 B.
Definition: etpwm.h:935
static void EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule, uint16_t compCount)
Definition: etpwm.h:3567
@ EPWM_TZ_ADV_ACTION_HIGH_Z
high impedance output
Definition: etpwm.h:1011
static uint16_t EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base)
Definition: etpwm.h:7175
static void EPWM_invertMinimumDeadBandSignal(uint32_t base, uint32_t block, uint32_t invert)
Definition: etpwm.h:8877
@ EPWM_DE_TRIP_SRC_CMPSSA8
Trip source is CMPSSA8 signal.
Definition: etpwm.h:2448
@ EPWM_DC_TYPE_DCBL
Digital Compare B Low.
Definition: etpwm.h:1335
@ EPWM_CLOCK_DIVIDER_2
Divide clock by 2.
Definition: etpwm.h:150
EPWM_DeadBandDelayMode
Definition: etpwm.h:769
static void EPWM_invertCaptureInputPolarity(uint32_t base, uint8_t polSel)
Definition: etpwm.h:7921
static void EPWM_enableDigitalCompareEdgeFilter(uint32_t base)
Definition: etpwm.h:6977
@ HRPWM_XCMP4_SHADOW1
XCMP4_SHADOW1.
Definition: etpwm.h:2020
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM26
Sync-in source is EPWM26 sync-out signal.
Definition: etpwm.h:241
@ EPWM_DC_EDGEFILT_EDGECNT_3
Digital Compare Edge filter edge count = 4.
Definition: etpwm.h:1712
@ HRPWM_LOAD_ON_CMPB_EQ
load on translater event CMPB-3
Definition: etpwm.h:1918
#define EPWM_INT_TBCTR_U_CMPA
time-base counter equal to CMPA when the timer is incrementing
Definition: etpwm.h:1222
static void EPWM_setCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule, EPWM_CounterCompareLoadMode loadMode)
Definition: etpwm.h:3439
EPWM_OneShotSyncOutTrigger
Definition: etpwm.h:333
static void EPWM_setXCMPRegValue(uint32_t base, EPWM_XCMPReg xcmpReg, uint16_t xcmpvalue)
Definition: etpwm.h:10264
static void EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount)
Definition: etpwm.h:4827
static void EPWM_enableSplitXCMP(uint32_t base)
Definition: etpwm.h:10154
static void EPWM_configCaptureGateInputPolarity(uint32_t base, uint8_t polSel)
Definition: etpwm.h:7893
@ EPWM_TZ_EVENT_DCXH_HIGH
Event when DCxH high.
Definition: etpwm.h:948
@ EPWM_CLOCK_DIVIDER_16
Divide clock by 16.
Definition: etpwm.h:153
@ EPWM_DC_TRIP_TRIPIN12
Trip 12.
Definition: etpwm.h:1358
@ EPWM_XCMP_2_CMPB
Allocate XCMP5 - XCMP6 registers to CMPB.
Definition: etpwm.h:2284
static void EPWM_disableDiodeEmulationMode(uint32_t base)
Definition: etpwm.h:10698
@ EPWM_XCMP5_SHADOW2
XCMP5_SHADOW2.
Definition: etpwm.h:2139
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT5
Trip source is INPUTXBAR out5 signal.
Definition: etpwm.h:2378
@ EPWM_LINK_WITH_EPWM_10
link current ePWM with ePWM10
Definition: etpwm.h:411
static void EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6231
@ EPWM_DC_TRIP_TRIPIN10
Trip 10.
Definition: etpwm.h:1356
@ EPWM_XMIN_SHADOW2
XMIN_SHADOW2.
Definition: etpwm.h:2212
@ HRPWM_XCMP8_SHADOW3
XCMP8_SHADOW3.
Definition: etpwm.h:2066
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2
Sync-in source is ECAP2 sync-out signal.
Definition: etpwm.h:257
static void EPWM_setADCTriggerEventCountInitValue(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t eventCount)
Definition: etpwm.h:6663
HRPWM_MEPDeadBandEdgeMode
Definition: etpwm.h:1976
@ EPWM_SOC_TBCTR_U_CMPC
time-base counter equal to CMPC when the timer is incrementing
Definition: etpwm.h:1304
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT4
Trip source is INPUTXBAR out4 signal.
Definition: etpwm.h:2376
@ EPWM_VALLEY_COUNT_STOP_EDGE
Valley count stop edge.
Definition: etpwm.h:1651
@ EPWM_COUNTER_MODE_STOP_FREEZE
Stop - Freeze counter.
Definition: etpwm.h:363
static void EPWM_setCounterCompareValue_opt_cmpB(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3629
@ EPWM_LINK_WITH_EPWM_17
link current ePWM with ePWM17
Definition: etpwm.h:418
static void EPWM_setDigitalCompareCBCLatchMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareCBCLatchMode latchMode)
Definition: etpwm.h:7466
static void EPWM_forceGlobalLoadOneShotEvent(uint32_t base)
Definition: etpwm.h:8687
static bool EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge)
Definition: etpwm.h:8389
EPWM_ActionQualifierOutput
Definition: etpwm.h:596
@ EPWM_DC_EDGEFILT_MODE_RISING
Digital Compare Edge filter low to high edge mode.
Definition: etpwm.h:1690
@ EPWM_TZ_ACTION_EVENT_DCBEVT2
DCBEVT2 (Digital Compare B event 2)
Definition: etpwm.h:967
@ EPWM_AQ_OUTPUT_LOW_UP_T1
T1 event on count up and set output pins to low.
Definition: etpwm.h:686
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM14
Sync-in source is EPWM14 sync-out signal.
Definition: etpwm.h:217
@ EPWM_XCMP2_SHADOW1
XCMP2_SHADOW1.
Definition: etpwm.h:2114
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT7
Trip source is INPUTXBAR out7 signal.
Definition: etpwm.h:2382
@ HRPWM_PWMSYNC_SOURCE_COMPC_DOWN
Counter equals COMPC when counting down.
Definition: etpwm.h:1950
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM10
Sync-in source is EPWM10 sync-out signal.
Definition: etpwm.h:209
EPWM_ClockDivider
Definition: etpwm.h:148
#define EPWM_DB_INPUT_DB_RED
Input signal is the output of Rising Edge delay.
Definition: etpwm.h:797
EPWM_LinkComponent
Definition: etpwm.h:442
static void EPWM_disableSyncOutPulseSource(uint32_t base, uint16_t source)
Definition: etpwm.h:2860
static void EPWM_disableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6604
@ EPWM_GL_LOAD_PULSE_CNTR_CMPD_D
load when counter is equal to cmpd and cmpd is decrementing
Definition: etpwm.h:1582
@ EPWM_XMAX_SHADOW1
XMAX_SHADOW1.
Definition: etpwm.h:2206
HRPWM_SyncPulseSource
Definition: etpwm.h:1942
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT17
Trip source is INPUTXBAR out17 signal.
Definition: etpwm.h:2402
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO
Valley capture trigged by when counter is equal to zero.
Definition: etpwm.h:1627
@ EPWM_AQ_OUTPUT_LOW_DOWN_CMPB
Time base counter down equals COMPB and set output pins to low.
Definition: etpwm.h:667
EPWM_DigitalCompareModule
Definition: etpwm.h:1475
static bool EPWM_getADCTriggerFlagStatus(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6516
@ EPWM_FED_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:850
EPWM_DigitalCompareCBCLatchMode
Definition: etpwm.h:1530
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG3
Sync-in source is FSI-RX1 RX Trigger 3 signal.
Definition: etpwm.h:307
@ EPWM_SOC_B
SOC B.
Definition: etpwm.h:1282
@ HRPWM_XCMP7_ACTIVE
XCMP7_ACTIVE.
Definition: etpwm.h:2007
@ EPWM_PERIOD_SHADOW_LOAD
PWM Period register access is through shadow register.
Definition: etpwm.h:347
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D
Digital Compare event A/B 2 while counting down.
Definition: etpwm.h:1034
@ EPWM_DC_EDGEFILT_EDGECNT_1
Digital Compare Edge filter edge count = 2.
Definition: etpwm.h:1708
static void HRPWM_setHiResCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint16_t hrCompCount)
Definition: etpwm.h:9804
@ EPWM_DC_EVENT_SOURCE_FILT_SIGNAL
signal source is filtered (DCEVTFILT)
Definition: etpwm.h:1506
@ EPWM_DE_TRIP_SRC_CMPSSA3
Trip source is CMPSSA3 signal.
Definition: etpwm.h:2438
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM23
Sync-in source is EPWM23 sync-out signal.
Definition: etpwm.h:235
@ EPWM_LINK_WITH_EPWM_8
link current ePWM with ePWM8
Definition: etpwm.h:409
@ EPWM_AQ_OUTPUT_HIGH_UP_CMPB
Time base counter up equals COMPB and set output pins to high.
Definition: etpwm.h:661
static bool EPWM_getTimeBaseCounterOverflowStatus(uint32_t base)
Definition: etpwm.h:3143
@ EPWM_DE_TRIP_SRC_CMPSSA9
Trip source is CMPSSA9 signal.
Definition: etpwm.h:2450
@ EPWM_COUNTER_COMPARE_B
counter compare B
Definition: etpwm.h:468
@ EPWM_SOC_DCxEVT1
Event is based on DCxEVT1.
Definition: etpwm.h:1294
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1
T1 event on count up and no change in the output pins.
Definition: etpwm.h:684
@ EPWM_DC_CBC_LATCH_ENABLED
DC cycle-by-cycle(CBC) latch is enabled.
Definition: etpwm.h:1534
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1
Trip zone 1.
Definition: etpwm.h:552
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM28
Sync-in source is EPWM28 sync-out signal.
Definition: etpwm.h:245
static void EPWM_setXMINMAXRegValue(uint32_t base, EPWM_XMinMaxReg xminmaxReg, uint16_t xcmpvalue)
Definition: etpwm.h:10334
EPWM_ValleyTriggerSource
Definition: etpwm.h:1623
@ EPWM_DC_TRIP_TRIPIN6
Trip 6.
Definition: etpwm.h:1352
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP5
Sync-in source is ECAP5 sync-out signal.
Definition: etpwm.h:263
@ EPWM_TZ_ADV_ACTION_TOGGLE
toggle the output
Definition: etpwm.h:1014
@ EPWM_LINK_COMP_A
link COMPA registers
Definition: etpwm.h:444
static void EPWM_enableGlobalLoad(uint32_t base)
Definition: etpwm.h:8477
static void EPWM_disableValleyCapture(uint32_t base)
Definition: etpwm.h:8183
@ EPWM_TZ_ADV_ACTION_HIGH
high voltage state
Definition: etpwm.h:1012
@ EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1
Valley capture trigged by DCBEVT1 (Digital Compare B event 1)
Definition: etpwm.h:1637
EPWM_AdditionalActionQualifierEventAction
Definition: etpwm.h:682
static void EPWM_configureDiodeEmulationTripSources(uint32_t base, EPWM_DiodeEmulationTripSource source, uint32_t tripLorH)
Definition: etpwm.h:10803
@ EPWM_XCMP7_SHADOW2
XCMP7_SHADOW2.
Definition: etpwm.h:2143
static void EPWM_forceCaptureEventLoad(uint32_t base)
Definition: etpwm.h:7992
static void EPWM_enableChopper(uint32_t base)
Definition: etpwm.h:4882
@ HRPWM_XTBPRD_SHADOW2
XTBPRD_SHADOW2.
Definition: etpwm.h:2049
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO
Time base counter equals zero.
Definition: etpwm.h:568
@ EPWM_DC_TRIP_TRIPIN3
Trip 3.
Definition: etpwm.h:1349
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG1
Sync-in source is FSI-RX2 RX Trigger 1 signal.
Definition: etpwm.h:311
static void EPWM_enablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:2955
static void EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base, EPWM_TripZoneDigitalCompareOutput dcType, EPWM_TripZoneDigitalCompareOutputEvent dcEvent)
Definition: etpwm.h:5188
@ EPWM_AQ_SW_IMMEDIATE_LOAD
No shadow load mode. Immediate mode only.
Definition: etpwm.h:747
@ EPWM_DC_WINDOW_SOURCE_DCBEVT1
DC filter signal source is DCBEVT1.
Definition: etpwm.h:1460
static void EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base)
Definition: etpwm.h:3166
EPWM_DeadBandPolarity
Definition: etpwm.h:781
@ EPWM_DC_TRIP_TRIPIN7
Trip 7.
Definition: etpwm.h:1353
@ EPWM_LINK_WITH_EPWM_28
link current ePWM with ePWM28
Definition: etpwm.h:429
HRPWM_MEPEdgeMode
Definition: etpwm.h:1877
static void EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6264
@ EPWM_DB_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:814
static void HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:9416
static void EPWM_disableCaptureTripCombinationInput(uint32_t base, uint16_t tripInput, uint8_t dcType)
Definition: etpwm.h:8122
@ EPWM_XCMP7_SHADOW3
XCMP7_SHADOW3.
Definition: etpwm.h:2162
static void EPWM_enableDiodeEmulationMonitorModeControl(uint32_t base)
Definition: etpwm.h:11027
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL
No Shadow buffer is in use.
Definition: etpwm.h:2334
static void EPWM_enableDigitalCompareBlankingWindow(uint32_t base)
Definition: etpwm.h:6815
@ EPWM_DC_WINDOW_START_TBCTR_PERIOD
Time base counter equals period.
Definition: etpwm.h:1414
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT11
Trip source is INPUTXBAR out11 signal.
Definition: etpwm.h:2390
EPWM_TripZoneAdvancedAction
Definition: etpwm.h:1010
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY
Definition: etpwm.h:1666
@ EPWM_CMPC_SHADOW2
CMPC_SHADOW2.
Definition: etpwm.h:2183
@ HRPWM_MEP_CTRL_RISING_EDGE
MEP controls rising edge.
Definition: etpwm.h:1881
@ EPWM_DC_TRIP_TRIPIN14
Trip 14.
Definition: etpwm.h:1360
#define EPWM_DE_CHANNEL_A
< Diode emulation channel A
Definition: etpwm.h:2492
static void HRPWM_disablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:9606
static void EPWM_disableTripZoneOutput(uint32_t base, uint16_t tzOutput)
Definition: etpwm.h:5842
@ EPWM_XCMP_8_CMPA
Allocate XCMP1 - XCMP8 registers to CMPA.
Definition: etpwm.h:2270
@ EPWM_XCMP6_SHADOW3
XCMP6_SHADOW3.
Definition: etpwm.h:2160
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT26
Trip source is INPUTXBAR out26 signal.
Definition: etpwm.h:2420
@ EPWM_AQ_OUTPUT_TOGGLE_PERIOD
Time base counter equals period and toggle the output pins.
Definition: etpwm.h:639
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD
Valley capture trigged when counter is equal to zero or period.
Definition: etpwm.h:1631
static void EPWM_setActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output)
Definition: etpwm.h:4327
static void EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
Definition: etpwm.h:8763
@ EPWM_COUNTER_MODE_UP_DOWN
Up - down - count mode.
Definition: etpwm.h:362
@ EPWM_DC_TRIP_TRIPIN11
Trip 11.
Definition: etpwm.h:1357
static void EPWM_enableOneShotSync(uint32_t base)
Definition: etpwm.h:3057
static void EPWM_enableSyncOutPulseSource(uint32_t base, uint16_t source)
Definition: etpwm.h:2815
static void EPWM_setAdditionalActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_AdditionalActionQualifierEventAction action)
Definition: etpwm.h:4165
EPWM_TripZoneAction
Definition: etpwm.h:977
@ HRPWM_DB_MEP_CTRL_RED_FED
MEP controls both Falling and Rising edge delay.
Definition: etpwm.h:1984
@ EPWM_XCMP6_ACTIVE
XCMP6_ACTIVE.
Definition: etpwm.h:2103
#define EPWM_LOCK_KEY
Definition: etpwm.h:2594
@ HRPWM_MEP_CTRL_FALLING_EDGE
MEP controls falling edge.
Definition: etpwm.h:1883
@ EPWM_DE_TRIP_SRC_CMPSSB3
Trip source is CMPSSB3 signal.
Definition: etpwm.h:2458
@ EPWM_DE_TRIP_SRC_CMPSSB6
Trip source is CMPSSB6 signal.
Definition: etpwm.h:2464
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP8
Sync-in source is ECAP8 sync-out signal.
Definition: etpwm.h:269
@ EPWM_DC_CBC_LATCH_DISABLED
DC cycle-by-cycle(CBC) latch is disabled.
Definition: etpwm.h:1532
@ EPWM_LINK_GLDCTL2
link GLDCTL2 registers
Definition: etpwm.h:448
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD
Valley capture trigged by when counter is equal period.
Definition: etpwm.h:1629
EPWM_TripZoneAdvDigitalCompareEvent
Definition: etpwm.h:1026
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT9
Trip source is INPUTXBAR out9 signal.
Definition: etpwm.h:2386
static void EPWM_selectMinimumDeadBandBlockingSignal(uint32_t base, uint32_t block, uint32_t blockingSignal)
Definition: etpwm.h:8946
EPWM_DigitalCompareEventSource
Definition: etpwm.h:1502
@ EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC
Definition: etpwm.h:378
static void EPWM_setDiodeEmulationMonitorCounterThreshold(uint32_t base, uint16_t threshold)
Definition: etpwm.h:11118
static void EPWM_enableCaptureTripCombinationInput(uint32_t base, uint16_t tripInput, uint8_t dcType)
Definition: etpwm.h:8070
EPWM_XCMP_ALLOC_CMPB
Values that can be passed to EPWM_allocBXCMP() as the alloctype parameter.
Definition: etpwm.h:2280
@ EPWM_AQ_OUTPUT_ON_T2_COUNT_UP
T2 event on count up.
Definition: etpwm.h:584
static void EPWM_enableIndependentPulseLogic(uint32_t base)
Definition: etpwm.h:7945
static uint16_t EPWM_getOneShotTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5607
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB
Time base counter down equals COMPB and toggle the output pins.
Definition: etpwm.h:671
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7
Time base counter equals XCMP7.
Definition: etpwm.h:2240
@ HRPWM_OUTPUT_ON_B_NORMAL
ePWMxB output is normal.
Definition: etpwm.h:1930
static void EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent, EPWM_TripZoneAction tzAction)
Definition: etpwm.h:5278
@ EPWM_FED_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:844
EPWM_DigitalCompareEdgeFilterMode
Definition: etpwm.h:1688
static void EPWM_disableCaptureInEvent(uint32_t base)
Definition: etpwm.h:7864
@ HRPWM_XCMP6_SHADOW2
XCMP6_SHADOW2.
Definition: etpwm.h:2043
@ EPWM_LINK_WITH_EPWM_7
link current ePWM with ePWM7
Definition: etpwm.h:408
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB
Time base counter up equals COMPB and no change in the output pins.
Definition: etpwm.h:657
static void EPWM_setDigitalCompareFilterInput(uint32_t base, EPWM_DigitalCompareFilterInput filterInput)
Definition: etpwm.h:6950
@ HRPWM_XCMP1_ACTIVE
XCMP1_ACTIVE.
Definition: etpwm.h:1995
@ EPWM_AQ_OUTPUT_LOW_DOWN_T1
T1 event on count down and set output pins to low.
Definition: etpwm.h:694
#define EPWM_INT_TBCTR_U_CMPB
time-base counter equal to CMPB when the timer is incrementing
Definition: etpwm.h:1230
@ EPWM_DC_EDGEFILT_EDGECNT_5
Digital Compare Edge filter edge count = 6.
Definition: etpwm.h:1716
@ EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:848
@ EPWM_TZ_EVENT_DCXL_HIGH
Event when DCxL high.
Definition: etpwm.h:950
@ EPWM_TZ_ACTION_EVENT_DCAEVT1
DCAEVT1 (Digital Compare A event 1)
Definition: etpwm.h:964
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP15
Sync-in source is ECAP15 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:283
@ EPWM_TZ_EVENT_DCXH_LOW
Event when DCxH low.
Definition: etpwm.h:947
@ EPWM_AQ_OUTPUT_HIGH_UP_CMPA
Time base counter up equals COMPA and set output pins to high.
Definition: etpwm.h:645
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG3
Sync-in source is FSI-RX0 RX Trigger 3 signal.
Definition: etpwm.h:299
static void EPWM_forceInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:6128
static uint16_t EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base)
Definition: etpwm.h:7085
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:490
@ EPWM_AQ_OUTPUT_HIGH
Set output pins to High.
Definition: etpwm.h:599
@ EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD
load when counter is equal to zero or period
Definition: etpwm.h:1566
@ HRPWM_DB_MEP_CTRL_DISABLE
HRPWM is disabled.
Definition: etpwm.h:1978
@ EPWM_DC_TRIP_TRIPIN9
Trip 9.
Definition: etpwm.h:1355
@ EPWM_XCMP3_ACTIVE
XCMP3_ACTIVE.
Definition: etpwm.h:2097
static void EPWM_enableGlobalLoadOneShotMode(uint32_t base)
Definition: etpwm.h:8642
EPWM_RisingEdgeDelayLoadMode
Definition: etpwm.h:824
@ EPWM_SOC_TBCTR_D_CMPB
time-base counter equal to CMPB when the timer is decrementing
Definition: etpwm.h:1314
EPWM_CycleByCycleTripZoneClearMode
Definition: etpwm.h:1146
#define EPWM_DE_COUNT_UP
Values that can be passed to EPWM_setDiodeEmulationMonitorModeStep()
Definition: etpwm.h:2503
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD
shadow mode load when counter equals period
Definition: etpwm.h:743
@ EPWM_VALLEY_COUNT_START_EDGE
Valley count start edge.
Definition: etpwm.h:1650
EPWM_XCMPActionQualifierOutputEvent
Values that can be passed to EPWM_setXCMPActionQualifierAction() as the event parameter.
Definition: etpwm.h:2226
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT2
Trip source is INPUTXBAR out2 signal.
Definition: etpwm.h:2372
@ EPWM_DE_TRIP_SRC_CMPSSA7
Trip source is CMPSSA7 signal.
Definition: etpwm.h:2446
@ EPWM_LINK_WITH_EPWM_27
link current ePWM with ePWM27
Definition: etpwm.h:428
@ EPWM_DC_EDGEFILT_MODE_FALLING
Digital Compare Edge filter both edges mode.
Definition: etpwm.h:1692
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD
shadow mode load when counter equals zero or period
Definition: etpwm.h:745
@ EPWM_XCMP8_SHADOW2
XCMP8_SHADOW2.
Definition: etpwm.h:2145
static void HRPWM_setHiResPhaseShift(uint32_t base, uint16_t hrPhaseCount)
Definition: etpwm.h:9246
@ EPWM_XCMP3_SHADOW2
XCMP3_SHADOW2.
Definition: etpwm.h:2135
@ EPWM_DC_EVENT_2
Digital Compare Event number 2.
Definition: etpwm.h:1492
@ HRPWM_XCMP2_SHADOW2
XCMP2_SHADOW2.
Definition: etpwm.h:2035
@ EPWM_COUNTER_COMPARE_C
counter compare C
Definition: etpwm.h:469
static void EPWM_disableDigitalCompareCounterCapture(uint32_t base)
Definition: etpwm.h:7638
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP6
Sync-in source is ECAP6 sync-out signal.
Definition: etpwm.h:265
static void EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
Definition: etpwm.h:5471
static void EPWM_setLutDecX(uint32_t base, uint32_t block, uint32_t decx, uint32_t force)
Definition: etpwm.h:9171
@ EPWM_LINK_WITH_EPWM_19
link current ePWM with ePWM19
Definition: etpwm.h:420
@ EPWM_AQ_OUTPUT_LOW_PERIOD
Time base counter equals period and set output pins to low.
Definition: etpwm.h:635
EPWM_DiodeEmulationMode
Definition: etpwm.h:2352
@ EPWM_XCMP1_SHADOW3
XCMP1_SHADOW3.
Definition: etpwm.h:2150
@ EPWM_XCMP4_SHADOW1
XCMP4_SHADOW1.
Definition: etpwm.h:2118
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP7
Sync-in source is ECAP7 sync-out signal.
Definition: etpwm.h:267
static void EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount)
Definition: etpwm.h:7155
static void EPWM_setDiodeEmulationReentryDelay(uint32_t base, uint8_t delay)
Definition: etpwm.h:10770
@ EPWM_CMPC_SHADOW1
CMPC_SHADOW1.
Definition: etpwm.h:2179
static void EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base)
Definition: etpwm.h:4717
@ EPWM_DB_COUNTER_CLOCK_HALF_CYCLE
Dead band counter runs at 2*TBCLK rate.
Definition: etpwm.h:864
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5
Sync-in source is EPWM5 sync-out signal.
Definition: etpwm.h:199
@ EPWM_DC_TRIP_TRIPIN2
Trip 2.
Definition: etpwm.h:1348
@ EPWM_XCMP_4_CMPB
Allocate XCMP5 - XCMP8 registers to CMPB.
Definition: etpwm.h:2288
static void EPWM_forceXLoad(uint32_t base)
Definition: etpwm.h:10495
static bool EPWM_getCounterCompareShadowStatus(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3740
@ EPWM_CMPD_SHADOW2
CMPD_SHADOW2.
Definition: etpwm.h:2185
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3
Time base counter equals XCMP3.
Definition: etpwm.h:2232
static void EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode)
Definition: etpwm.h:2922
@ EPWM_AQ_OUTPUT_HIGH_DOWN_T2
T2 event on count down and set output pins to high.
Definition: etpwm.h:712
static void EPWM_setActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule, EPWM_ActionQualifierLoadMode loadMode)
Definition: etpwm.h:3792
static void EPWM_setActionQualifierContSWForceAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierSWOutput output)
Definition: etpwm.h:4241
@ HRPWM_XCMP1_SHADOW1
XCMP1_SHADOW1.
Definition: etpwm.h:2014
@ EPWM_SOC_TBCTR_U_CMPB
time-base counter equal to CMPB when the timer is incrementing
Definition: etpwm.h:1310
static void EPWM_selectDiodeEmulationPWMsignal(uint32_t base, uint32_t channel, EPWM_DiodeEmulationSignal signal)
Definition: etpwm.h:10854
@ HRPWM_XCMP1_SHADOW3
XCMP1_SHADOW3.
Definition: etpwm.h:2052
EPWM_FallingEdgeDelayLoadMode
Definition: etpwm.h:842
static void EPWM_disablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:2976
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB
Time base counter down equals COMPB.
Definition: etpwm.h:578
@ EPWM_DE_LOW
a constant low signal
Definition: etpwm.h:2481
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0
Trip source is INPUTXBAR out0 signal.
Definition: etpwm.h:2368
static void EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags)
Definition: etpwm.h:5748
@ EPWM_DB_OUTPUT_B
DB output is ePWMB.
Definition: etpwm.h:759
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT20
Trip source is INPUTXBAR out20 signal.
Definition: etpwm.h:2408
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO
Clear CBC pulse when counter equals zero.
Definition: etpwm.h:1148
@ EPWM_GL_LOAD_PULSE_CNTR_CMPD_U
load when counter is equal to cmpd and cmpd is incrementing
Definition: etpwm.h:1580
static void EPWM_setXCMPShadowLevel(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWLEVEL level)
Definition: etpwm.h:10564
@ HRPWM_COUNTER_COMPARE_A
counter compare A
Definition: etpwm.h:1965
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO
shadow mode load when counter equals zero
Definition: etpwm.h:741
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1
T1 event on count down and toggle the output pins.
Definition: etpwm.h:698
@ EPWM_AQ_LOAD_ON_SYNC_ONLY
load on sync only
Definition: etpwm.h:537
@ HRPWM_XCMP4_SHADOW3
XCMP4_SHADOW3.
Definition: etpwm.h:2058
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM13
Sync-in source is EPWM13 sync-out signal.
Definition: etpwm.h:215
@ EPWM_LINK_COMP_D
link COMPD registers
Definition: etpwm.h:447
@ EPWM_COUNT_MODE_UP_AFTER_SYNC
Count up after sync event.
Definition: etpwm.h:138
@ EPWM_DC_EDGEFILT_EDGECNT_4
Digital Compare Edge filter edge count = 5.
Definition: etpwm.h:1714
static void EPWM_enableValleyCapture(uint32_t base)
Definition: etpwm.h:8162
static void EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode, bool enableDelayMode)
Definition: etpwm.h:4461
@ EPWM_DE_TRIP_SRC_CMPSSB7
Trip source is CMPSSB7 signal.
Definition: etpwm.h:2466
@ EPWM_CMPC_SHADOW3
CMPC_SHADOW3.
Definition: etpwm.h:2187
@ EPWM_AQ_OUTPUT_HIGH_UP_T2
T2 event on count up and set output pins to high.
Definition: etpwm.h:704
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB
Time base counter down equals COMPB and no change in the output pins.
Definition: etpwm.h:665
static void EPWM_setActionQualifierT2TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger)
Definition: etpwm.h:3907
static void EPWM_disableTripZoneSignals(uint32_t base, uint32_t tzSignal)
Definition: etpwm.h:5088
@ EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA
Time base counter up equals COMPA and toggle the output pins.
Definition: etpwm.h:647
static void HRPWM_setXCMPRegValue(uint32_t base, HRPWM_XCMPReg xcmpReg, uint16_t xcmpvalue)
Definition: etpwm.h:10081
@ EPWM_DC_TRIP_TRIPIN8
Trip 8.
Definition: etpwm.h:1354
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM30
Sync-in source is EPWM30 sync-out signal.
Definition: etpwm.h:249
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG2
Sync-in source is FSI-RX3 RX Trigger 2 signal.
Definition: etpwm.h:321
@ EPWM_XCMP8_SHADOW1
XCMP8_SHADOW1.
Definition: etpwm.h:2126
#define EPWM_DB_INPUT_EPWMB
Input signal is ePWMB.
Definition: etpwm.h:795
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5
Time base counter equals XCMP5.
Definition: etpwm.h:2236
@ EPWM_SOC_TBCTR_U_CMPA
time-base counter equal to CMPA when the timer is incrementing
Definition: etpwm.h:1302
@ EPWM_LINK_WITH_EPWM_26
link current ePWM with ePWM26
Definition: etpwm.h:427
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT1
Trip source is INPUTXBAR out1 signal.
Definition: etpwm.h:2370
@ EPWM_DE_TRIP_SRC_CMPSSA6
Trip source is CMPSSA6 signal.
Definition: etpwm.h:2444
@ EPWM_XCMP_5_CMPA
Allocate XCMP1 - XCMP5 registers to CMPA.
Definition: etpwm.h:2264
static void EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags)
Definition: etpwm.h:5711
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT24
Trip source is INPUTXBAR out24 signal.
Definition: etpwm.h:2416
@ EPWM_ACTION_QUALIFIER_B
Action Qualifier B.
Definition: etpwm.h:511
@ HRPWM_XCMP8_ACTIVE
XCMP8_ACTIVE.
Definition: etpwm.h:2009
@ EPWM_DC_MODULE_B
Digital Compare Module B.
Definition: etpwm.h:1477
@ EPWM_DB_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:810
@ EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1
Valley capture trigged by DCAEVT1 (Digital Compare A event 1)
Definition: etpwm.h:1633
@ EPWM_PERIOD_DIRECT_LOAD
PWM Period register access is directly.
Definition: etpwm.h:349
#define EPWM_DCxCTL_STEP
Defines to be used by the driver.
Definition: etpwm.h:2588
EPWM_XCMPReg
Definition: etpwm.h:2091
@ EPWM_LINK_DBFED
link DBFED registers
Definition: etpwm.h:450
@ EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN
T1 event on count down.
Definition: etpwm.h:582
@ HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE
MEP controls both rising and falling edge.
Definition: etpwm.h:1885
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1
Sync-in source is ECAP1 sync-out signal.
Definition: etpwm.h:255
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:177
EPWM_ActionQualifierModule
Definition: etpwm.h:509
EPWM_ActionQualifierOutputModule
Definition: etpwm.h:727
@ EPWM_LINK_WITH_EPWM_25
link current ePWM with ePWM25
Definition: etpwm.h:426
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT30
Trip source is INPUTXBAR out30 signal.
Definition: etpwm.h:2428
static void EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6747
@ EPWM_DC_EVENT_INPUT_NOT_SYNCED
DC input signal is not synced with TBCLK.
Definition: etpwm.h:1520
static void EPWM_setDiodeEmulationMonitorModeStep(uint32_t base, uint32_t direction, uint8_t stepsize)
Definition: etpwm.h:11079
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2
Digital compare event B 2.
Definition: etpwm.h:551
@ HRPWM_XCMP2_SHADOW3
XCMP2_SHADOW3.
Definition: etpwm.h:2054
EPWM_DigitalCompareFilterInput
Definition: etpwm.h:1457
static void EPWM_setXCMPLoadMode(uint32_t base, EPWM_XCMPXloadCtlLoadMode mode)
Definition: etpwm.h:10522
@ EPWM_TZ_DC_OUTPUT_B1
Digital Compare output 1 B.
Definition: etpwm.h:934
static void EPWM_enableTripZone2Signals(uint32_t base, uint16_t tzSignal)
Definition: etpwm.h:5117
@ EPWM_AQ_OUTPUT_LOW_UP_CMPA
Time base counter up equals COMPA and set output pins to low.
Definition: etpwm.h:643
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
load on sync or when counter equals zero or period
Definition: etpwm.h:535
@ EPWM_LINK_WITH_EPWM_1
link current ePWM with ePWM1
Definition: etpwm.h:402
@ EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2
Valley capture trigged by DCBEVT2 (Digital Compare B event 2)
Definition: etpwm.h:1639
@ EPWM_LINK_WITH_EPWM_4
link current ePWM with ePWM4
Definition: etpwm.h:405
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG0
Sync-in source is FSI-RX2 RX Trigger 0 signal.
Definition: etpwm.h:309
@ EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:812
static void EPWM_disableXLoad(uint32_t base)
Definition: etpwm.h:10475
@ EPWM_AQ_OUTPUT_LOW_UP_T2
T2 event on count up and set output pins to low.
Definition: etpwm.h:702
static uint16_t EPWM_getValleyCount(uint32_t base)
Definition: etpwm.h:8435
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3
Trip zone 3.
Definition: etpwm.h:554
static void EPWM_disableDigitalCompareEdgeFilter(uint32_t base)
Definition: etpwm.h:6999
@ EPWM_COUNTER_MODE_DOWN
Down - count mode.
Definition: etpwm.h:361
static void HRPWM_enablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:9585
@ EPWM_XMAX_SHADOW2
XMAX_SHADOW2.
Definition: etpwm.h:2210
@ EPWM_DE_TRIP_SRC_CMPSSB9
Trip source is CMPSSB9 signal.
Definition: etpwm.h:2470
@ EPWM_SOC_TBCTR_D_CMPD
time-base counter equal to CMPD when the timer is decrementing
Definition: etpwm.h:1316
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM20
Sync-in source is EPWM20 sync-out signal.
Definition: etpwm.h:229
static void EPWM_enableXCMPMode(uint32_t base)
Definition: etpwm.h:10112
static void EPWM_enableCaptureInEvent(uint32_t base)
Definition: etpwm.h:7839
@ EPWM_DIODE_EMULATION_OST
Diode Emulation mode is One Shot.
Definition: etpwm.h:2356
@ HRPWM_CHANNEL_B
HRPWM B.
Definition: etpwm.h:1867
static void EPWM_disableCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3509
static void HRPWM_enablePeriodControl(uint32_t base)
Definition: etpwm.h:9542
@ EPWM_XCMP4_SHADOW2
XCMP4_SHADOW2.
Definition: etpwm.h:2137
@ EPWM_DE_SYNC_TRIPHorL
synchronized version of TRIPH or TRIPL signal
Definition: etpwm.h:2477
@ EPWM_TZ_ACTION_EVENT_DCBEVT1
DCBEVT1 (Digital Compare B event 1)
Definition: etpwm.h:966
@ EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD
Clear CBC latch when counter equals period.
Definition: etpwm.h:1548
@ EPWM_GL_LOAD_PULSE_CNTR_ZERO
load when counter is equal to zero
Definition: etpwm.h:1562
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM9
Sync-in source is EPWM9 sync-out signal.
Definition: etpwm.h:207
@ EPWM_DIODE_EMULATION_CBC
Diode Emulation mode is Cycle by Cycle.
Definition: etpwm.h:2354
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT21
Trip source is INPUTXBAR out21 signal.
Definition: etpwm.h:2410
static void EPWM_disableInterrupt(uint32_t base)
Definition: etpwm.h:5887
static void EPWM_disableGlobalLoad(uint32_t base)
Definition: etpwm.h:8499
static void EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
Definition: etpwm.h:4542
@ EPWM_XMAX_ACTIVE
XMAX_ACTIVE.
Definition: etpwm.h:2202
#define EPWM_XCMP_SHADOW2
XCMP set = Shadow 3.
Definition: etpwm.h:2080
static void EPWM_selectDigitalCompareCBCLatchClearEvent(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareCBCLatchClearEvent clearEvent)
Definition: etpwm.h:7524
@ HRPWM_COUNTER_COMPARE_B
counter compare B
Definition: etpwm.h:1966
static void HRPWM_setCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint32_t compCount)
Definition: etpwm.h:9712
static void EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount, uint16_t stopCount)
Definition: etpwm.h:8266
@ EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT4
Sync-in source is Input XBAR out4 signal.
Definition: etpwm.h:285
@ EPWM_XCMP6_SHADOW2
XCMP6_SHADOW2.
Definition: etpwm.h:2141
static void EPWM_disableChopper(uint32_t base)
Definition: etpwm.h:4903
static void EPWM_setActionQualifierContSWForceAction_opt_outputs(uint32_t base, uint8_t outputAB)
Definition: etpwm.h:4297
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG3
Sync-in source is FSI-RX2 RX Trigger 3 signal.
Definition: etpwm.h:315
static void EPWM_disableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7426
@ EPWM_LINK_COMP_C
link COMPC registers
Definition: etpwm.h:446
static void EPWM_disableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7364
@ HRPWM_XCMP7_SHADOW1
XCMP7_SHADOW1.
Definition: etpwm.h:2026
@ EPWM_COMP_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:484
@ EPWM_HSCLOCK_DIVIDER_4
Divide clock by 4.
Definition: etpwm.h:169
@ EPWM_XCMP_3_CMPB
Allocate XCMP5 - XCMP7 registers to CMPB.
Definition: etpwm.h:2286
@ HRPWM_DB_MEP_CTRL_FED
MEP controls Falling Edge Delay.
Definition: etpwm.h:1982
static uint16_t EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3690
static void EPWM_bypassDiodeEmulationLogic(uint32_t base)
Definition: etpwm.h:10957
static void EPWM_startOneShotSync(uint32_t base)
Definition: etpwm.h:3101
@ EPWM_AQ_OUTPUT_LOW_ZERO
Time base counter equals zero and set output pins to low.
Definition: etpwm.h:627
#define EPWM_MINDB_BLOCK_B
Definition: etpwm.h:1749
static void HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal)
Definition: etpwm.h:9677
@ HRPWM_XCMP4_SHADOW2
XCMP4_SHADOW2.
Definition: etpwm.h:2039
@ EPWM_XTBPRD_ACTIVE
XTBPRD_ACTIVE.
Definition: etpwm.h:2109
EPWM_PeriodShadowLoadMode
Definition: etpwm.h:373
#define EPWM_DE_TRIPL
Values that can be passed to EPWM_configureDiodeEmulationTripSources()
Definition: etpwm.h:2514
static void EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
Definition: etpwm.h:8722
@ EPWM_AQ_OUTPUT_HIGH_PERIOD
Time base counter equals period and set output pins to high.
Definition: etpwm.h:637
static void EPWM_disableTripZone2Signals(uint32_t base, uint16_t tzSignal)
Definition: etpwm.h:5146
@ EPWM_CLOCK_DIVIDER_128
Divide clock by 128.
Definition: etpwm.h:156
EPWM_CounterCompareLoadMode
Definition: etpwm.h:480
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6
Sync-in source is EPWM6 sync-out signal.
Definition: etpwm.h:201
@ EPWM_TZ_ACTION_EVENT_TZA
TZ1 - TZ6, DCAEVT2, DCAEVT1.
Definition: etpwm.h:962
static void HRPWM_setRisingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:10023
static void EPWM_setDigitalCompareEventSource(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareEventSource dcEventSource)
Definition: etpwm.h:7233
@ HRPWM_XTBPRD_SHADOW3
XTBPRD_SHADOW3.
Definition: etpwm.h:2068
@ EPWM_XCMP6_SHADOW1
XCMP6_SHADOW1.
Definition: etpwm.h:2122
@ EPWM_AQ_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:525
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7
Sync-in source is EPWM7 sync-out signal.
Definition: etpwm.h:203
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3
Sync-in source is ECAP3 sync-out signal.
Definition: etpwm.h:259
static void EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
Definition: etpwm.h:5509
@ EPWM_DC_WINDOW_START_TBCTR_BLANK_PULSE_MIX
Time base counter blank pulse mix.
Definition: etpwm.h:1420
EPWM_DeadBandClockMode
Definition: etpwm.h:860
@ EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2
Valley capture trigged by DCAEVT2 (Digital Compare A event 2)
Definition: etpwm.h:1635
EPWM_XCMPXloadCtlLoadMode
Definition: etpwm.h:2298
@ EPWM_XCMP4_ACTIVE
XCMP4_ACTIVE.
Definition: etpwm.h:2099
static void EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent)
Definition: etpwm.h:5783
static void EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount)
Definition: etpwm.h:6153
@ HRPWM_PWMSYNC_SOURCE_PERIOD
Counter equals Period.
Definition: etpwm.h:1944
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG3
Sync-in source is FSI-RX3 RX Trigger 3 signal.
Definition: etpwm.h:323
static uint16_t HRPWM_getHiResTimeBasePeriod(uint32_t base)
Definition: etpwm.h:9306
@ EPWM_GL_LOAD_PULSE_CNTR_CMPC_D
load when counter is equal to cmpc and cmpc is decrementing
Definition: etpwm.h:1578
#define EPWM_DE_COUNT_DOWN
Definition: etpwm.h:2505
@ EPWM_XMAX_SHADOW3
XMAX_SHADOW3.
Definition: etpwm.h:2214
@ EPWM_TZ_ACTION_EVENT_DCAEVT2
DCAEVT2 (Digital Compare A event 2)
Definition: etpwm.h:965
static void EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource, uint16_t mixedSource)
Definition: etpwm.h:5923
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2
Sync-in source is EPWM2 sync-out signal.
Definition: etpwm.h:193
@ EPWM_DC_TYPE_DCBH
Digital Compare B High.
Definition: etpwm.h:1334
static void EPWM_enableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7395
static void EPWM_clearSyncEvent(uint32_t base)
Definition: etpwm.h:3209
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_2
SHDW2, SHDW1 and Active registers are available.
Definition: etpwm.h:2319
@ EPWM_EMULATION_FREE_RUN
Free run.
Definition: etpwm.h:126
static bool EPWM_getDigitalCompareCBCLatchStatus(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent)
Definition: etpwm.h:7576
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM22
Sync-in source is EPWM22 sync-out signal.
Definition: etpwm.h:233
static void EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, EPWM_DigitalCompareEdgeFilterEdgeCount edgeCount)
Definition: etpwm.h:7060
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_1
SHDW1 and Active registers are available.
Definition: etpwm.h:2317
@ EPWM_AQ_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:529
@ EPWM_XCMP7_ACTIVE
XCMP7_ACTIVE.
Definition: etpwm.h:2105
@ EPWM_DC_TRIP_TRIPIN5
Trip 5.
Definition: etpwm.h:1351
@ HRPWM_PWMSYNC_SOURCE_COMPC_UP
Counter equals COMPC when counting up.
Definition: etpwm.h:1948
@ EPWM_VALLEY_DELAY_MODE_SW_DELAY
Delay value equals the offset value defines by software.
Definition: etpwm.h:1663
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT10
Trip source is INPUTXBAR out10 signal.
Definition: etpwm.h:2388
@ EPWM_XTBPRD_SHADOW2
XTBPRD_SHADOW2.
Definition: etpwm.h:2147
@ EPWM_XCMP2_SHADOW2
XCMP2_SHADOW2.
Definition: etpwm.h:2133
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT27
Trip source is INPUTXBAR out27 signal.
Definition: etpwm.h:2422
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA
Time base counter up equals COMPA.
Definition: etpwm.h:572
@ EPWM_XCMP7_SHADOW1
XCMP7_SHADOW1.
Definition: etpwm.h:2124
@ EPWM_XCMP5_ACTIVE
XCMP5_ACTIVE.
Definition: etpwm.h:2101
static void EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount)
Definition: etpwm.h:3285
@ HRPWM_CHANNEL_A
HRPWM A.
Definition: etpwm.h:1866
@ EPWM_DB_COUNTER_CLOCK_FULL_CYCLE
Dead band counter runs at TBCLK rate.
Definition: etpwm.h:862
@ EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT20
Sync-in source is Input XBAR out20 signal.
Definition: etpwm.h:287
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM29
Sync-in source is EPWM29 sync-out signal.
Definition: etpwm.h:247
EPWM_XCMP_XLOADCTL_SHDWBUFPTR
Definition: etpwm.h:2332
@ EPWM_DC_WINDOW_SOURCE_DCAEVT2
DC filter signal source is DCAEVT2.
Definition: etpwm.h:1459
@ EPWM_LINK_WITH_EPWM_31
link current ePWM with ePWM31
Definition: etpwm.h:432
static uint32_t HRPWM_getCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule)
Definition: etpwm.h:9758
@ EPWM_DC_TRIP_TRIPIN1
Trip 1.
Definition: etpwm.h:1347
@ EPWM_DB_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:808
@ EPWM_TZ_DC_OUTPUT_A1
Digital Compare output 1 A.
Definition: etpwm.h:932
@ EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB
Time base counter down equals COMPB and set output pins to high.
Definition: etpwm.h:669