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AM263x MCU+ SDK
09.02.00
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Go to the documentation of this file.
62 #include <sdl/include/hw_types.h>
63 #include <sdl/include/sdl_types.h>
66 #include <sdl/dcc/v1/soc/sdl_dcc_soc.h>
108 #define DCC_SRC0_COUNT_MAX (0xFFFFFU)
112 #define DCC_SRC0_VALID_MAX (0x0FFFFU)
116 #define DCC_SRC1_COUNT_MAX (0xFFFFFU)
118 #define MIN_CLK0_VLD_SEED (4u)
143 #define SDL_DCC_MODE_SINGLE_SHOT (DCC_DCCGCTRL_SINGLESHOT_MODE)
147 #define SDL_DCC_MODE_CONTINUOUS (DCC_DCCGCTRL_SINGLESHOT_DISABLE)
161 #define SDL_DCC_CLK0_SRC_CLOCK0_0 (DCC_DCCCLKSRC0_CLKSRC0_0)
163 #define SDL_DCC_CLK0_SRC_CLOCK0_1 (DCC_DCCCLKSRC0_CLKSRC0_1)
165 #define SDL_DCC_CLK0_SRC_CLOCK0_2 (DCC_DCCCLKSRC0_CLKSRC0_2)
179 #define SDL_DCC_CLK1_SRC_CLOCKSRC0 (DCC_DCCCLKSRC1_CLKSRC_0)
181 #define SDL_DCC_CLK1_SRC_CLOCKSRC1 (DCC_DCCCLKSRC1_CLKSRC_1)
183 #define SDL_DCC_CLK1_SRC_CLOCKSRC2 (DCC_DCCCLKSRC1_CLKSRC_2)
185 #define SDL_DCC_CLK1_SRC_CLOCKSRC3 (DCC_DCCCLKSRC1_CLKSRC_3)
187 #define SDL_DCC_CLK1_SRC_CLOCKSRC4 (DCC_DCCCLKSRC1_CLKSRC_4)
189 #define SDL_DCC_CLK1_SRC_CLOCKSRC5 (DCC_DCCCLKSRC1_CLKSRC_5)
191 #define SDL_DCC_CLK1_SRC_CLOCKSRC6 (DCC_DCCCLKSRC1_CLKSRC_6)
193 #define SDL_DCC_CLK1_SRC_CLOCKSRC7 (DCC_DCCCLKSRC1_CLKSRC_7)
195 #define SDL_DCC_CLK1_SRC_FICLK (SDL_DCC2_DCCCLKSRC1_CLKSRC_OTHER)
210 #define SDL_DCC_INTERRUPT_ERR (0x0U)
212 #define SDL_DCC_INTERRUPT_DONE (0x1U)
231 typedef struct SDL_DCC_config_st
271 typedef struct SDL_DCC_staticRegs_st
379 #define DCC_DCCGCTRL (0x0U)
380 #define DCC_DCCREV (0x4U)
381 #define DCC_DCCCNTSEED0 (0x8U)
382 #define DCC_DCCVALIDSEED0 (0xcU)
383 #define DCC_DCCCNTSEED1 (0x10U)
384 #define DCC_DCCSTAT (0x14U)
385 #define DCC_DCCCNT0 (0x18U)
386 #define DCC_DCCVALID0 (0x1cU)
387 #define DCC_DCCCNT1 (0x20U)
388 #define DCC_DCCCLKSRC1 (0x24U)
389 #define DCC_DCCCLKSRC0 (0x28U)
395 #define DCC_DCCGCTRL_DCCENA_SHIFT (0U)
396 #define DCC_DCCGCTRL_DCCENA_MASK (0x0000000fU)
397 #define DCC_DCCGCTRL_DCCENA_ENABLE (0xAU)
398 #define DCC_DCCGCTRL_DCCENA_DISABLE (0x5U)
400 #define DCC_DCCGCTRL_ERRENA_SHIFT (4U)
401 #define DCC_DCCGCTRL_ERRENA_MASK (0x000000f0U)
402 #define DCC_DCCGCTRL_ERRENA_ENABLE (0xAU)
403 #define DCC_DCCGCTRL_ERRENA_DISABLE (0x5U)
405 #define DCC_DCCGCTRL_SINGLESHOT_SHIFT (8U)
406 #define DCC_DCCGCTRL_SINGLESHOT_MASK (0x00000f00U)
407 #define DCC_DCCGCTRL_SINGLESHOT_MODE (0xAU)
409 #define DCC_DCCGCTRL_SINGLESHOT_DISABLE (0x5U)
411 #define DCC_DCCGCTRL_DONEENA_SHIFT (12U)
412 #define DCC_DCCGCTRL_DONEENA_MASK (0x0000f000U)
413 #define DCC_DCCGCTRL_DONEENA_ENABLE (0xAU)
414 #define DCC_DCCGCTRL_DONEENA_DISABLE (0x5U)
416 #define DCC_DCCGCTRL_RES_SHIFT (16U)
417 #define DCC_DCCGCTRL_RES_MASK (0xffff0000U)
419 #define DCC_DCCREV_MINOR_SHIFT (0U)
420 #define DCC_DCCREV_MINOR_MASK (0x0000003fU)
422 #define DCC_DCCREV_CUSTOM_SHIFT (6U)
423 #define DCC_DCCREV_CUSTOM_MASK (0x000000c0U)
425 #define DCC_DCCREV_MAJOR_SHIFT (8U)
426 #define DCC_DCCREV_MAJOR_MASK (0x00000700U)
428 #define DCC_DCCREV_RTL_SHIFT (11U)
429 #define DCC_DCCREV_RTL_MASK (0x0000f800U)
431 #define DCC_DCCREV_FUNC_SHIFT (16U)
432 #define DCC_DCCREV_FUNC_MASK (0x0fff0000U)
434 #define DCC_DCCREV_RES_SHIFT (28U)
435 #define DCC_DCCREV_RES_MASK (0x30000000U)
437 #define DCC_DCCREV_SCHEME_SHIFT (30U)
438 #define DCC_DCCREV_SCHEME_MASK (0xc0000000U)
440 #define DCC_DCCCNTSEED0_COUNTSEED0_SHIFT (0U)
441 #define DCC_DCCCNTSEED0_COUNTSEED0_MASK (0x000fffffU)
443 #define DCC_DCCCNTSEED0_RES_SHIFT (20U)
444 #define DCC_DCCCNTSEED0_RES_MASK (0xfff00000U)
446 #define DCC_DCCVALIDSEED0_VALIDSEED0_SHIFT (0U)
447 #define DCC_DCCVALIDSEED0_VALIDSEED0_MASK (0x0000ffffU)
449 #define DCC_DCCVALIDSEED0_RES_SHIFT (16U)
450 #define DCC_DCCVALIDSEED0_RES_MASK (0xffff0000U)
452 #define DCC_DCCCNTSEED1_COUNTSEED1_SHIFT (0U)
453 #define DCC_DCCCNTSEED1_COUNTSEED1_MASK (0x000fffffU)
455 #define DCC_DCCCNTSEED1_RES_SHIFT (20U)
456 #define DCC_DCCCNTSEED1_RES_MASK (0xfff00000U)
458 #define DCC_DCCSTAT_ERRFLG_SHIFT (0U)
459 #define DCC_DCCSTAT_ERRFLG_MASK (0x00000001U)
460 #define DCC_DCCSTAT_ERRFLG_DISABLE (1U)
462 #define DCC_DCCSTAT_DONEFLG_SHIFT (1U)
463 #define DCC_DCCSTAT_DONEFLG_MASK (0x00000002U)
464 #define DCC_DCCSTAT_DONEFLG_DISABLE (1U)
466 #define DCC_DCCSTAT_RES_SHIFT (2U)
467 #define DCC_DCCSTAT_RES_MASK (0xfffffffcU)
469 #define DCC_DCCCNT0_COUNT0_SHIFT (0U)
470 #define DCC_DCCCNT0_COUNT0_MASK (0x000fffffU)
472 #define DCC_DCCCNT0_RES_SHIFT (20U)
473 #define DCC_DCCCNT0_RES_MASK (0xfff00000U)
475 #define DCC_DCCVALID0_VALID0_SHIFT (0U)
476 #define DCC_DCCVALID0_VALID0_MASK (0x0000ffffU)
478 #define DCC_DCCVALID0_RES_SHIFT (16U)
479 #define DCC_DCCVALID0_RES_MASK (0xffff0000U)
481 #define DCC_DCCCNT1_COUNT1_SHIFT (0U)
482 #define DCC_DCCCNT1_COUNT1_MASK (0x000fffffU)
484 #define DCC_DCCCNT1_RES_SHIFT (20U)
485 #define DCC_DCCCNT1_RES_MASK (0xfff00000U)
487 #define DCC_DCCCLKSRC1_CLKSRC_SHIFT (0U)
488 #define DCC_DCCCLKSRC1_CLKSRC_MASK (0x0000000fU)
489 #define DCC_DCCCLKSRC1_CLKSRC_0 (0x0U)
490 #define DCC_DCCCLKSRC1_CLKSRC_1 (0x1U)
491 #define DCC_DCCCLKSRC1_CLKSRC_2 (0x2U)
492 #define DCC_DCCCLKSRC1_CLKSRC_3 (0x3U)
493 #define DCC_DCCCLKSRC1_CLKSRC_4 (0x4U)
494 #define DCC_DCCCLKSRC1_CLKSRC_5 (0x5U)
495 #define DCC_DCCCLKSRC1_CLKSRC_6 (0x6U)
496 #define DCC_DCCCLKSRC1_CLKSRC_7 (0x7U)
497 #define SDL_DCC2_DCCCLKSRC1_CLKSRC_OTHER (0xFU)
499 #define DCC_DCCCLKSRC1_RES1_SHIFT (4U)
500 #define DCC_DCCCLKSRC1_RES1_MASK (0x00000ff0U)
502 #define DCC_DCCCLKSRC1_KEY_SHIFT (12U)
503 #define DCC_DCCCLKSRC1_KEY_MASK (0x0000f000U)
504 #define DCC_DCCCLKSRC1_KEY_ENABLE (0xAU)
505 #define DCC_DCCCLKSRC1_KEY_DISABLE (0x0U)
507 #define DCC_DCCCLKSRC1_RES0_SHIFT (16U)
508 #define DCC_DCCCLKSRC1_RES0_MASK (0xffff0000U)
510 #define DCC_DCCCLKSRC0_CLKSRC0_SHIFT (0U)
511 #define DCC_DCCCLKSRC0_CLKSRC0_MASK (0x0000000fU)
512 #define DCC_DCCCLKSRC0_CLKSRC0_0 (0x0U)
513 #define DCC_DCCCLKSRC0_CLKSRC0_1 (0x1U)
514 #define DCC_DCCCLKSRC0_CLKSRC0_2 (0x2U)
516 #define DCC_DCCCLKSRC0_RES1_SHIFT (4U)
517 #define DCC_DCCCLKSRC0_RES1_MASK (0xfffffff0)
519 #define DCC_DCCCLKSRC0_KEY_SHIFT (12U)
520 #define DCC_DCCCLKSRC0_KEY_MASK (0x0000f000U)
521 #define DCC_DCCCLKSRC0_KEY_ENABLE (0xAU)
522 #define DCC_DCCCLKSRC0_KEY_DISABLE (0x0U)
524 #define DCC_DCCCLKSRC0_RES0_SHIFT (16U)
525 #define DCC_DCCCLKSRC0_RES0_MASK (0xffff0000U)
uint32_t SDL_DCC_mode
Enum to select the DCC Operation Mode.
Definition: dcc/v1/sdl_dcc.h:141
int32_t SDL_DCC_getStaticRegs(SDL_DCC_Inst instance, SDL_DCC_staticRegs *pStaticRegs)
This API is used to get the value of static registers for DCC module.
uint32_t clk0Valid
Definition: dcc/v1/sdl_dcc.h:264
int32_t SDL_DCC_configure(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig)
This API is used to configure DCC module.
uint32_t SDL_DCC_clkSrc1
Enum to select the COUNT1 clock source.
Definition: dcc/v1/sdl_dcc.h:177
int32_t SDL_DCC_getStatus(SDL_DCC_Inst instance, SDL_DCC_Status *pStatus)
This API is used to get the stauts of DCC module.
SDL_DCC_Inst
Definition: sdl_soc_dcc.h:72
int32_t SDL_DCC_disable(SDL_DCC_Inst instance)
This API is used to disable the DCC module.
uint32_t clk1Cnt
Definition: dcc/v1/sdl_dcc.h:266
bool errIntr
Definition: dcc/v1/sdl_dcc.h:258
uint32_t DCC_CNTSEED0
Definition: dcc/v1/sdl_dcc.h:275
bool doneIntr
Definition: dcc/v1/sdl_dcc.h:256
SDL_DCC_clkSrc0 clk0Src
Definition: dcc/v1/sdl_dcc.h:237
int32_t SDL_DCC_enableIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr)
This API is used to Enable the interrupts.
uint32_t SDL_DCC_intrType
Enum for DCC interrupts.
Definition: dcc/v1/sdl_dcc.h:208
uint32_t DCC_REV
Definition: dcc/v1/sdl_dcc.h:273
uint32_t clk1Src
Definition: dcc/v1/sdl_dcc.h:241
Definition: dcc/v1/sdl_dcc.h:272
uint32_t DCC_CNTSEED1
Definition: dcc/v1/sdl_dcc.h:279
SDL_DCC_config config
Definition: dcc/v1/sdl_dcc.h:260
SDL_DCC_mode mode
Definition: dcc/v1/sdl_dcc.h:233
int32_t SDL_DCC_verifyConfig(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig)
This API is used to verify the configuration for DCC module.
uint32_t clk0Cnt
Definition: dcc/v1/sdl_dcc.h:262
uint32_t clk1Seed
Definition: dcc/v1/sdl_dcc.h:249
uint32_t DCC_CLKSRC0
Definition: dcc/v1/sdl_dcc.h:283
This file contains the prototypes of the APIs present in the device abstraction layer file of DCC....
uint32_t clk0ValidSeed
Definition: dcc/v1/sdl_dcc.h:247
int32_t SDL_DCC_enable(SDL_DCC_Inst instance)
This API is used to enable the DCC module.
uint32_t clk0Seed
Definition: dcc/v1/sdl_dcc.h:245
Structure containing parameters for DCC module configuration.
Definition: dcc/v1/sdl_dcc.h:232
uint32_t DCC_VALIDSEED0
Definition: dcc/v1/sdl_dcc.h:277
int32_t SDL_DCC_clearIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr)
This API is used to clear the interrupts.
uint32_t SDL_DCC_clkSrc0
Enum to select the COUNT0 clock source.
Definition: dcc/v1/sdl_dcc.h:159
Definition: dcc/v1/sdl_dcc.h:255
uint32_t DCC_CLKSRC1
Definition: dcc/v1/sdl_dcc.h:281