AM263Px INDUSTRIAL COMMUNICATIONS SDK  2026.00.00
HSR_PRP(High-availability seamless Redundancy/Parallel Redundancy Protocol) FWHAL

Introduction

This software is designed for the TI SoCs with PRU-ICSS IP to enable customers add HSR/PRP(High-availability seamless Redundancy and Parallel Redundancy Protocol) Dual Attached Node support to their system. It implements HSR/PRP functionality and provides HSR/PRP FPGA like functionality integrated into TI SoCs.

HSR and PRP are Ethernet based communication technology commonly deployed in smart grid substation for low cost, easy to maintain and interoperable common network infrastructure with built-in redundancy. They exist as a LRE(Link Redundancy Entity) between the MAC and Network layer above providing a transparent view of the MAC below to the application. Every packet is duplicated by the HSR/PRP FWHAL on it's way out and only a single copy of the duplicates arriving is forwarded to Host.

Software Architecture

HSR/PRP firmware for PRU-ICSS is a black box product maintained by TI. HSR/PRP FWHAL(Firmware and Hardware Abstraction Layer) allows loading and running HSR/PRP firmware and acts as an interface with the firmware. Firmware is based on 200 MHz clock frequency for PRU-ICSS Core Clock and IEP Clock.

Data Sheet

Features Supported

Feature Description Implementation
High-Availability Seamless (HSR as per clause 5 of IEC 62439) Redundancy Operates as a DANH, Support for modes – H, T, U and N as per standard, Two ports as per standard(Port A & Port B), Modes can be changed at runtime Yes
Parallel Redundancy Protocol (PRP as per clause 4 of IEC 62439) Operates as DANP, Two ports as per standard(Port A & Port B) Yes
Quality of Service (QoS) Two priority receive queues on host port(6 KB), Four priority transmit queues on each physical port(3 KB). Yes
Node Table 256 entries, Hash Table for faster lookup(Complexity : O(1)), Node forget time : 60s, Node Table statistics Yes
Multicast Filtering Support for Multicast Packet Filtering, Hash Table for faster lookup(Complexity : O(1)) Yes
VLAN Filtering Support for VLAN Filtering for host port, Hash Table for faster lookup(Complexity : O(1)) Yes
Duplicate Discard Table Duplicate discard on Port to Host path (PRP), Data integrity (CRC) check during port to port forwarding Yes
Duplex Full Yes
Half No
Speed Auto Yes
10Mbps No
100Mbps Yes
Statistics Supports all MIB statistics as per standard, Node Table statistics for debugging, Self-configuring Yes
PTP/1588 – Time Synchronization PTP, Supports P2P clock, PTP over 802.3 (Annex F), Transparent Clock supported, Ordinary Clock supported, Single and Two step clock supported, Peer delay Response is always sent as two-step Yes
Port Buffering 1 ms buffering per port Yes
Storm Prevention Multicast and Broadcast storm prevention per port Yes
Interrupt for Link loss detection Link loss detection, Callback APIs to perform tasks related to change in network topology Yes

PTP Statistics

PTP (Precision Time Protocol) statistics show the synchronization performance between the timeTransmitter and timeReceiver device:

  • Topology: HSR PTP timeTransmitter <-> AM263Px (PTP timeReceiver - HSR Mode H) with both the ports connected:
    Peer Delay on P1 : 91 ns
    Peer Delay on P2 : 92 ns
    --------DUT configured as Slave---------
    *********PTP/1588 Params********
    Clock Drift : 4 ns
    Curr offset : 1 ns
    Min offset : -24 ns
    Max offset : 19 ns
    Num Sync Missed : 0
    UTC Offset (Seconds field) : 1762857578 seconds
    Master connected on Port : 2
    *******************************
    IP Address : 192.168.1.10
    Device config : HSR MODE H
  • Topology: PRP PTP timeTransmitter <-> AM263Px (PTP timeReceiver - PRP) with both the ports connected:
    Peer Delay on P1 : 4 ns
    Peer Delay on P2 : 0 ns
    --------DUT configured as Slave---------
    *********PTP/1588 Params********
    Clock Drift : 3 ns
    Curr offset : 4 ns
    Min offset : -26 ns
    Max offset : 18 ns
    Num Sync Missed : 0
    UTC Offset (Seconds field) : 1762857905 seconds
    Master connected on Port : 2
    *******************************
    IP Address : 192.168.1.10
    Device config : PRP

Known Issues

Record ID Details Workaround
PINDSW-5290 Frame drops due to LWIP pool reduction

MCUSDK-4379 Low Tx side throughput seen when tested using iperf application

MCUSDK-8234 HSR/PRP - PTP Device is unable to keep offset under 1000 ns

Hardware Requirements

  • Sitara Processor with PRU-ICSS IP and HSR-PRP support
  • HW signals required to implement HSR-PRP functionality is shown below, this info needs to be used in conjunction with SYSCONFIG.
    Signal Name Requirement

    Description

    PRU-ICSS MDIO
    PR0_MDIO0_MDC Mandatory MDIO clock
    PR0_MDIO0_MDIO Mandatory MDIO Data
    PRU-ICSS Distributed Clocks (Network Clock synchronization)
    PRGx_IEP0_EDC_SYNC_OUT0 Mandatory (for PTP support) SYNC0 out - Time synchronized OUT0
    PRGx_IEP0_EDC_SYNC_OUT1 Optional

    SYNC1 out

    PRU-ICSS MII Port0 (IN Port) & PRU-ICSS MII Port1 (OUT Port)
    MII0_RXD0 Mandatory MII0 and MII1 Receive Data0
    MII1_RXD0
    MII0_RXD1 Mandatory MII0 and MII1 Receive Data1
    MII1_RXD1
    MII0_RXD2 Mandatory MII0 and MII1 Receive Data2
    MII1_RXD2
    MII0_RXD3 Mandatory MII0 and MII1 Receive Data3
    MII1_RXD3
    MII0_RXDV Mandatory MII0 and MII1 RX Data Valid
    MII1_RXDV
    MII0_RXER Optional MII0 and MII1 RXERR
    MII1_RXER
    MII0_TXD0 Mandatory MII0 and MII1 Transmit Data0
    MII1_TXD0
    MII0_TXD1 Mandatory MII0 and MII1 Transmit Data1
    MII1_TXD1
    MII0_TXD2 Mandatory MII0 and MII1 Transmit Data2
    MII1_TXD2
    MII0_TXD3 Mandatory MII0 and MII1 Transmit Data3
    MII1_TXD3
    MII0_TXEN Mandatory MII0 and MII1 TX enable
    MII1_TXEN
    MII0_RXCLK Mandatory MII0 and MII1 Receive clock
    MII1_RXCLK
    MII0_TXCLK Mandatory MII0 and MII1 Transmit clock

    MII1_TXCLK

Important Files and Directory Structure

Folder/Files Description
${SDK_INSTALL_PATH}/examples/industrial_comms
hsr_prp_demo HSR/PRP Examples (based on pre-integrated stack)
${SDK_INSTALL_PATH}/source/industrial_comms/hsr_prp
icss_fwhal/firmware Firmware for the PRU cores in PRU-ICSS. Firmware Version : 2.21.48
icss_fwhal/lib/ FWHAL library for HSR/PRP
icss_fwhal/*.c FWHAL source files
icss_fwhal/*.h FWHAL interface files

Terms and Abbreviations

Abbreviation Expansion
PRU-ICSS Programmable Real-Time Unit Industrial Communication Subsystem
HSR High-availability seamless Redundancy Protocol (A redundancy protocol)
DANH Dual Attached Node (HSR)
PRP Parallel Redundancy Protocol (A redundancy protocol)
DANP Dual Attached Node (PRP)
LRE Link Redundancy Entity
MII Media Independent Interface
DL Datalink Layer
PTP-1588 Precision Time Protocol (IEEE time synchronization protocol)

API Documentation

Please see APIs for HSR/PRP FWHAL for API documentation.

Procedure to kick-off the PRP

  • Initialize ICSS-EMAC to work as a switch
  • Initialize the required tasks and interrupts
  • Initialize the HSR/PRP FWHAL and PRU-ICSS INTC
  • Load HSR/PRP firmware into PRUs of PRU-ICSS
  • Start firmware
  • Handle the events as needed.

Integration with ICSS-EMAC

TI HSR/PRP solution uses the ICSS-EMAC as it's base switch layer. The PRU Firmware is customized for HSR/PRP functionalities, and is not same as a standard switch firmware. All the traffic to Host is handled by HSR/PRP LRE (Link redundancy entity). The NRT(non-real time) traffic is passed to the LwIP stack while the Real time traffic goes to the registered callback.

Interface with ICSS-EMAC

HSR/PRP packets are standard ethernet frames and all protocol specific data is embedded in TCP/IP payload. On a standard ICSS-EMAC Switch driver, of the 4 queues, two queues are dedicated to each receiving port, that is packet from ICSS_EMAC_QUEUE1, ICSS_EMAC_QUEUE3 go to RT callback and packets from ICSS_EMAC_QUEUE2, ICSS_EMAC_QUEUE4 go to NRT callback. We need to set "RT/NRT Priority Separation Queue" to (QUEUE 2) in SysConfig for ICSS-EMAC. More info on ICSS-EMAC can be found in ICSS_EMAC section.

The packets are forwarded to based on the priority of the packet which is decided by the queue number (refer to ICSS_EMAC_DESIGN_QOS). The driver decides to forward high priority packets to the rxRTCallBack and the rest are forwarded to LwIP stack, done by rxNRTCallBack.

Callbacks from ICSS EMAC

HSR/PRP FWHAL provides custom Rx and Tx functions to be used for HSR/PRP application. This needs to be configured while initializing ICSS EMAC driver. The custom Rx and Tx functions override the default Rx and Tx functions (ICSS_EMAC_rxPktGet and ICSS_EMAC_txPacket respectively) provided by ICSS-EMAC driver. Refer to ICSS_EMAC section in MCU+ SDK.

Callback Name Description Function used for callback registration
Custom Rx The callback handles the PRP trailer present it in the message and removes it for the upper layers, presenting a transparent interface. RedRxPktGet
Custom Tx The callback inserts the redundancy tags in the frame, duplicates packets on both ports and attempts to send them out at the same time. RedTxPacket
Rx RT This callback is used for processing high priority packets like PTP. It is implemented in the application itself as an example. hsrprp_processHighPrioFrames
Rx NRT This callback is used to send all the non real-time packets to lwIP stack. Lwip2Emac_serviceRx

Interrupts

HSR/PRP firmware generates the following interrupts.

HSR/PRP implementation uses following interrupts mapped to Host Interrupt Controller. 8 Host Interrupts (Host Interrupts 2 through 9) are exported from the PRU_ICSSG internal INTC for signaling the device level interrupt controllers. PRU_EVTOUT0 to PRU_EVTOUT7 correspond to these eight interrupts in the following table. Please check PRUICSS Interrupt Controller section for more details.

Name Host Interrupt Description
Frame Receive PRU_ICSS_EVTOUT0 Notifies host when firmware has stored a frame in host receive queue
Tx Callback Interrupt PRU_ICSS_EVTOUT3 Raised when a PTP/1588 frame which requires Tx Timestamping is sent out
Link Status PRU_ICSS_EVTOUT6 Interrupt is raised when the Link on MII0/MII1 port comes up or goes down

Tasks

The HSR/PRP FWHAL uses following tasks

  • RedLifeCheckTask : Check for Link up, prepare a supervision frame and then send them periodically. This is done by waiting on a semaphore redLifeCheckSemaphore which is in turn posted by a Timer. The task initialization is done inside RedLifeCheckTaskCreate.
  • RedNodetableRefresh : Increments the timeLastSeenX values by 1 every 10 ms and delete a node table entry if it reaches NODE_FORGET_TIME. The task initialization is done inside RedLifeCheckTaskCreate.

Semaphores

The HSR/PRP FWHAL uses following semaphores

  • redLifeCheckSemaphore : redLifeCheckSemaphore to gate the sending of supervision frames. A timer interrupt upon expiry posts the semaphore thus enabling periodic transmission of supervision frames.Semaphore created in RedLifeCheckTaskCreate.
  • nodesTableSemaphore : nodesTableSemaphore to gate the increments of timeLastSeenX values by 1 every 10 ms and delete a node table entry if it reaches NODE_FORGET_TIME. Semaphore created in RedLifeCheckTaskCreate.

Clocks

The HSR/PRP FWHAL uses following clocks

  • redPruCheckTimer : This timer is used to periodically check and clear bits in Firmware implementation. ISR is RedPruCheckTimerHandler. Period is specified by RED_PRU_CHECK_TIMER_PERIOD (microseconds).
  • redLifeCheckTimer : This timer is used to send supervision frames periodically. ISR is RedLifeCheckTimerHandler where it posts a semaphore redLifeCheckSemaphore to indicate to a waiting task to send supervision frames. Period is specified by RED_LIFE_CHECK_TIMER_PERIOD (microseconds).

See also