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EtherNet/IP™ Adapter3.09.01 |
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EtherNet/IP™ Adapter3.09.01 |
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| Feature | Description | Standard | Premium |
|---|---|---|---|
| EtherNet/IP Device Class | Adapter | Yes | Yes |
| Scanner | No | No | |
| Device Profile Examples | Generic Device (0x2B) General Purpose Discrete I/O Device (0x07) | Yes | Yes |
| Device Configuration | EDS File | Yes | Yes |
| Connection Types | Exclusive Owner | Yes | Yes |
| Input Only | Yes | Yes | |
| Listen Only | Yes | Yes | |
| Connection Trigger Types | Cyclic | Yes | Yes |
| Application Triggered | No | No | |
| Change of State | Yes | Yes | |
| Maximum Connections | Class 1 | 8 | 8 |
| Class 3 | 32 | 32 | |
| Explicit Messaging | Connected | Yes | Yes |
| Unconnected | Yes | Yes | |
| Standard Objects | Identity Object (0x01) | Yes | Yes |
| Message Router Object (0x02) | Yes | Yes | |
| Assembly Object (0x04) | Yes | Yes | |
| Connection Manager Object (0x06) | Yes | Yes | |
| Time Sync Object (0x43) | Yes | Yes | |
| Device Level Ring Object (0x47) | Yes | Yes | |
| QoS Object (0x48) | Yes | Yes | |
| TCP/IP Interface Object (0xF5) | Yes | Yes | |
| Ethernet Link Object (0xF6) | Yes | Yes | |
| LLDP Management Object (0x109) | Yes | Yes | |
| LLDP Data Table Object (0x10A) | Yes | Yes | |
| Supported Elementary Data Types | BOOL | Yes | Yes |
| SINT | Yes | Yes | |
| INT | Yes | Yes | |
| DINT | Yes | Yes | |
| LINT | Yes | Yes | |
| USINT | Yes | Yes | |
| UINT | Yes | Yes | |
| UDINT | Yes | Yes | |
| ULINT | Yes | Yes | |
| REAL | Yes | Yes | |
| LREAL | Yes | Yes | |
| STRING | Planned | Planned | |
| BYTE | Yes | Yes | |
| WORD | Yes | Yes | |
| DWORD | Yes | Yes | |
| LWORD | Yes | Yes | |
| STRING2 | Planned | Planned | |
| SHORT_STRING | Yes | Yes | |
| EPATH | Yes | Yes | |
| Supported Constructed Data Types | Formal Array | Yes | Yes |
| IP Addressing Modes | DHCP | Yes | Yes |
| BOOTP | Yes | Yes | |
| Static | Yes | Yes | |
| VLAN tagging | IEEE802.1Q, 3 bit PCP (8 levels) | Yes | Yes |
| Switch queues | 4 | 4 | |
| Statistics | Media counters supported per interface (dual port switch) | Yes | Yes |
| Interface counters supported per interface | Yes | Yes | |
| CIP Sync (PTP/IEEE1588) | Supports Drives Profile : E2E clock | Yes | Yes |
| PTP over UDP | Yes | Yes | |
| Transparent Clock supported | Yes | Yes | |
| Ordinary Clock supported | Yes | Yes | |
| Single and Two Step Clock supported | Yes | Yes | |
| Supported Network Features | Link Layer Discovery Protocol (LLDP) | Yes | Yes |
| Device Level Ring (DLR) | Yes | Yes | |
| Device Level Ring Supervisor (DLR Supervisor) ℹ️ | No | Yes | |
| Address Conflict Detection (ACD) | Yes | Yes | |
| Quality of Service (QoS) | Yes | Yes | |
| CIP Reset Services | Identity Object Reset Services of Typ 0, 1, and 2 | Identity Object Reset Services of Typ 0, 1, and 2 | |
| Device Level Ring (DLR) | Beacon based | Yes | Yes |
| Self configuring | Yes | Yes | |
| Min. beacon interval | 200 µs | 200 µs | |
| Min. beacon timeout | 400 µs | 400 µs | |
| Baud Rate | 100 Mbit/s | Yes | Yes |
| 10 Mbit/s | Yes | Yes | |
| Duplex Mode | Half | Yes | Yes |
| Full | Yes | Yes | |
| Auto Negotiation | Yes | Yes | |
| Conformance | ODVA CT21 | ODVA CT21 |
ℹ️ This feature is part of premium SDK. In case you are using standard and need premium, please contact your regional TI sales representative for additional details.
| Feature | Description | Setting |
|---|---|---|
| Process Data Image | max. I/O assembly (size) | 1480 Bytes |
| Connection Trigger Types and Cycle Times | Cyclic (Class 1) | 1 ms |
| Change of State | 1 ms | |
| Bridge Delay | Min Bridge Delay | 2.71 μs |
| Max Bridge Delay | 3.19 μs |
| Task | Prio | Changeable | Description |
|---|---|---|---|
| uart_task | 2 | yes | UART printing |
| cmn_app_task | 8 | yes | User application |
| lldpRcv | 8 | yes | Stack LLDP |
| WriteEeprom | 8 | yes | Write thread for non volatile data |
| WriteFlash | 8 | yes | Write thread for non volatile data |
| phymdix task | 12 | yes | Stack MDIX Configuration |
| statistic | 14 | yes | Stack statistics |
| tcpip_thread | 14 | yes | LWIP thread |
| TimeSync_Background | 14 | yes | TimeSync Driver |
| TimeSync_NRT | 16 | yes | TimeSync Driver |
| cyclicio | 20 | yes | Stack cyclic communication |
| packet | 20 | yes | Stack explicit messages |
| RxTask | 20 | yes | FWHAL RX Task |
| TimeSync_DelayReqTx | 20 | yes | TimeSync Driver |
| TimeSync_TxTimestamp_P1 | 20 | yes | TimeSync Driver |
| TimeSync_TxTimestamp_P2 | 20 | yes | TimeSync Driver |
| linkTask | 24 | yes | FWHAL Link Task |
All priorities are changeable, but it is highly recommended to not change the order.
The table below lists resource requirement for the Generic Device (0x2B) and Discrete I/O Device (0x07) examples. Please note that this application has only a limited functional scope that does not contain the basic web server that is include with the example code. More complex application code will result in higher ROM and RAM requirements.
| Generic Device | Discrete I/O | |
|---|---|---|
| Code | 264.61 kB | 272.02 kB |
| RO Data | 71.39 kB | 72.97 kB |
| RW Data | 584.64 kB | 584.77 kB |
1.9.8