This software is designed for the TI SoCs with PRU-ICSS IP to enable customers add EtherNet/IP Adapter protocol support to their system. It implements EtherNet/IP + PTP + DLR functionality and provides EtherNet/IP ASIC like functionality integrated into TI SoCs.
EtherNet/IP firmware for PRU-ICSS is a black box product maintained by TI. EtherNet/IP Adapter FWHAL(Firmware and Hardware Abstraction Layer) allows loading and running EtherNet/IP firmware and acts as an interface with the firmware. FWHAL implements the key interface between EtherNet/IP Adapter firmware and EtherNet/IP Adapter stack.
Record ID | Details | Workaround |
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PINDSW-4982 | SQE and Carrier Sense Errors counters not supported in EtherNet/IP | - |
Folder/Files | Description |
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${SDK_INSTALL_PATH}/examples/industrial_comms | |
ethernetip_adapter_demo | EtherNet/IP Adapter Examples (based on pre-integrated stack) |
${SDK_INSTALL_PATH}/source/industrial_comms/ethernetip_adapter | |
icss_fwhal/firmware | Firmware for the PRU cores in PRU-ICSS. Firmware Version : 5.2.9 |
icss_fwhal/lib/ | FWHAL library for EtherNet/IP Adapter |
icss_fwhal/*.c | FWHAL source files |
icss_fwhal/*.h | FWHAL interface files |
stack | Stack header files and stack library |
Abbreviation | Expansion |
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PRU-ICSS | Programmable Real-Time Unit Industrial Communication Subsystem |
DLR | Device Level Ring (A redundancy protocol) |
PTP | Precision Time Protocol |
OC | Ordinary Clock |
TC | Transparent Clock |
E2E | End to End |
Please see APIs for EtherNet/IP Adapter FWHAL for API documentation. It is recommended to use these FWHAL APIs in the stack adaptation files.
Ethernet/IP Adapter examples uses the ICSS-EMAC as its base switch layer. The PRU Firmware provides switch functionality and additional PTP and DLR functionalities. The NRT(non-real time) traffic is handled by ICSS-EMAC, wherein the packets are forwarded either to the TCP stack or a custom callback (configurable in ICSS-EMAC).
Ethernet/IP packets are standard ethernet frames and all protocol specific data is embedded in TCP/IP payload. Hence the standard switch model applies. Packets are segregated based on VLAN PCP field. The 8 priorities which map to 4 queues, with highest and next highest priorities going to Queue 0 and Queue 1 and so on. If PCP field does not exist, then frames go to Queue 3. All queues except the highest priority queue forward the frames to TCP/IP stack. Further if packet type does not match PTP or DLR then that frame goes to TCP/IP stack. The highest priority queues are used for PTP and DLR. These packets are directly forwarded to the registered callback in ICSS-EMAC (using rxRTCallBack).
EtherNet/IP firmware generates the following interrupts.
8 Host Interrupts (Host Interrupts 2 through 9) are exported from the PRU_ICSSG internal INTC for signaling the device level interrupt controllers. PRU_EVTOUT0 to PRU_EVTOUT7 correspond to these eight interrupts in the following table. Please check PRUICSS Interrupt Controller section for more details.
Name | Host Interrupt | Description |
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Frame Receive | PRU_EVTOUT0 | Notifies host when firmware has stored a frame in host receive queue |
DLR Port 0 Interrupt | PRU_EVTOUT1 | Raised when there is a state change in DLR on Port 0 |
DLR Port 1 Interrupt | PRU_EVTOUT2 | Raised when there is a state change in DLR on Port 1 |
Tx Callback Interrupt | PRU_EVTOUT3 | Raised when a PTP/1588 frame which requires Tx Timestamping is sent out |
DLR Beacon Timeout Interrupt for Port 0 | PRU_EVTOUT4 | Raised when the beacon timeout timer on Port 0 expires |
DLR Beacon Timeout Interrupt for Port 1 | PRU_EVTOUT7 | Raised when the beacon timeout timer on Port 1 expires |
Link Change | PRU_EVTOUT6 | Interrupt is raised when the link on Ethernet PHY comes up or goes down |
Device Level Ring on EtherNet/IP firmware provides redundancy to the switch implementation. It is a beacon based implementation with support for a minimum beacon of 200us and timeout of 400us. More information is available in ICSS DLR Design.
PTP/1588 on EtherNet/IP provides time synchronization support. The implementation is driven by CIP Sync requirements which require End to End clock support over UDP (Annex D). EtherNet/IP adapter application supports both OC and TC implementations along with syntonization.
Please refer to below documents to understand more about EtherNet/IP Adapter on TI platforms and EtherNet/IP Adapter protocol specifications.
Document | Description |
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EtherNet/IP on TI's Sitara processors | Application note by TI on the EtherNet/IP Adapter implementation on TI's Sitara Processors. |