TI ESC is fully register compatible with ET1100 ASIC, for any exceptions to this please search for "Not available in TI ESC" and "PDI access is exception here for TI ESC" in below table. Please see TI EtherCAT SubDevice Controller Exceptions for additional details.
Register name | Register offset | Bit/s | Permissions-ECAT | Permissions-PDI | Reset value | Description |
---|---|---|---|---|---|---|
Type | 0x0000 | |||||
0-7 | R/- | R/- | 0x90 | Type of SubDevice controller | ||
Revision | 0x0001 | |||||
0-7 | R/- | R/- | 5/6 | AM263x : 5 AM64x, AM243x : 6 | ||
Build | 0x0002-0x0003 | |||||
0-15 | R/- | R/- | 0x50C | Firmware build version | ||
FMMUs supported | 0x0004 | |||||
0-7 | R/- | R/- | 8 | Number of FMMUs supported. | ||
SyncManagers supported | 0x0005 | |||||
0-7 | R/- | R/- | 8 | Number of SMs supported. | ||
RAM Size | 0x0006 | |||||
0-7 | R/- | R/- | 59 | Size of Process Data RAM (in KB) | ||
Port Descriptor | 0x0007 | 0x0f | ||||
0-1 | R/- | R/- | 11b | Port 0 description. 00 - not implemented 01 - not configured (SII EEPROM) 10 - EBUS 11 - MII / RMII | ||
2-3 | R/- | R/- | 11b | Port 1 description | ||
4-5 | R/- | R/- | 00b | Port 2 description - Not available in TI ESC | ||
6-7 | R/- | R/- | 00b | Port 3 description - Not available in TI ESC | ||
ESC Features supported | 0x0008-0x0009 | 0x008c | Features supported | |||
0 | R/- | R/- | 0b | FMMU Operation. 0: byte oriented, 1: bit oriented. TI-ESC supports read-only bit oriented FMMUs (LRD command) | ||
1 | R/- | R/- | Reserved. Reads 0 | |||
2 | R/- | R/- | 1b | Distributed clocks - 0: not available 1: available. | ||
3 | R/- | R/- | 1b | Distributed clocks - 0: 32-bit 1: 64-bit | ||
4 | R/- | R/- | 0b | Low jitter EBUS: 0 - not available (standard jitter) 1 - available (jitter minimised) | ||
5 | R/- | R/- | 0b | Enhanced link detection EBUS: 0 - not available 1 - available | ||
6 | R/- | R/- | 0b | Enhanced link detection MII 0 - not available 1 - available | ||
7 | R/- | R/- | 1b | Separate handling of FCS errors 0 - not supported 1 - supported: frames with wrong FCS and additional nibble will be counted separately in Forwarded RX Error Counter | ||
8 | R/- | R/- | 0b | Enhanced DC SYNC Activation 0 - not available 1 - available | ||
9 | R/- | R/- | 0b | LRW Command support 0 - supported 1 - not supported | ||
10 | R/- | R/- | 0b | BRW/APRW/FPRW Command support 0 - supported 1 - not supported | ||
11 | R/- | R/- | 0b | Fixed SM/FMMU configuration 0 - variable configuration 1 - fixed configuration | ||
12-15 | R/- | R/- | Reserved | |||
Configured Station Address | 0x0010-0x0011 | |||||
0-15 | R/W | R/- | 0 | Node address: used in FPRD/FPWR/FPRW commands | ||
Configured Station Alias | 0x0012-0x0013 | |||||
0-15 | R/- | R/W | 0 | Alias addressed used in FPxx commands. Reset to EEPROM 0x0004. Activated by setting bit 0x100:24 / 0x103:0 | ||
0x0020-0x0021 | Not available in TI ESC | |||||
0x0030-0x0031 | Not available in TI ESC | |||||
0x0040-0x0041 | Not available in TI ESC | |||||
ESC DL Control | 0x0100-0x0103 | 1 | ||||
0 | R/W | R/- | 1b | 0: Non-ECAT packets are forwarded 1: non-ECAT packets are destroyed | ||
1 | R/W | R/- | 0b | 0: Settings written in 0x101 are for permanent use 1: New 0x101 settings are used for 1 s, then reverted | ||
2-7 | R/- | R/- | 0 | Reserved | ||
8-9 | R/W | R/- | 00b | Loop port 0 00 auto 01 auto-close / manual open 10 always open 11 always closed | ||
10-11 | R/W | R/- | 00b | Loop port 1 | ||
12-13 | R/W | R/- | 00b | Loop port 2 - Not available in TI ESC | ||
14-15 | R/W | R/- | 00b | Loop port 3 - Not available in TI ESC | ||
16-23 | Not available in TI ESC | |||||
24 | R/W | R/- | 0b | 0: Ignore station alias, 1: alias used for FPxx | ||
25-31 | R/- | R/- | Reserved | |||
Physical Read/Write Offset | 0x0108-0x0109 | 0 | ||||
0-15 | R/W | R/- | 0 | Offset between Read and Write address for R/W Commands (FPRW, APRW). RD_ADR = ADR, WR_ADR = ADR + Offset | ||
ESC DL Status | 0x0110-0x0111 | |||||
0 | R/- | R/- | 0: EEPROM not loaded, PDI not operational (no access to PD RAM) 1: EEPROM loaded correctly, PDI operational (access to PD RAM) | |||
1 | R/- | R/- | 0: PDI watchdog expired 1: PDI watchdog reloaded | |||
2 | R/- | R/- | Enhanced link detection 0: deactivated on all ports 1: activated on at least one port | |||
3 | R/- | R/- | Reserved | |||
4 | R/- | R/- | Physical link on port 0 0: no link 1: link detected | |||
5 | R/- | R/- | Physical link on port 1 | |||
6 | R/- | R/- | Physical link on port 2 - Not available in TI ESC | |||
7 | R/- | R/- | Physical link on port 3 - Not available in TI ESC | |||
8 | R/- | R/- | Loop port 0 0: opened 1: closed | |||
9 | R/- | R/- | Communication on port 0 0: no stable communication 1: communication established | |||
10 | R/- | R/- | Loop port 1 | |||
11 | R/- | R/- | Communication on port 1 | |||
12 | R/- | R/- | Loop port 2 - Not available in TI ESC | |||
13 | R/- | R/- | Communication on port 2 - Not available in TI ESC | |||
14 | R/- | R/- | Loop port 3 - Not available in TI ESC | |||
15 | R/- | R/- | Communication on port 3 - Not available in TI ESC | |||
AL Control | 0x120-0x121 | 0 | ||||
0-3 | R/W | R/- | 0001: Request INIT state 0011: Request BOOTSTRAP state 0010: Request PREOP state 0100: Request SAFEOP state 1000: Request OP state | |||
4 | R/W | R/- | 0: no acknowledge of error in 0x130 1: acknowledge error ind in 0x130 | |||
5-15 | R/- | R/- | Reserved | |||
AL Status | 0x0130-0x0131 | 0 | ||||
0-3 | R/- | R/W | Current state - 1: INIT, 3: BOOTSTRAP, 2: PREOP 4: SAFEOP, 8: OP | |||
4 | R/- | R/W | 0: Device in requested state or bit cleared by command 1: Device has not entered requested state or changed state as a result of a local action | |||
5-15 | R/- | R/- | Reserved | |||
AL Status Code | 0x0134 | 0 | ||||
0-15 | R/- | R/W | AL status code | |||
PDI Control | 0x0140 | PDI access is exception here for TI ESC | ||||
0-7 | R/- | RW- | 0x80 | PDI type / EEPROM 0x0000 On-chip bus | ||
ESC Configuration | 0x0141 | 0x0c | PDI access is exception here for TI ESC | |||
0 | R/- | RW- | 0b | Control of AL Status 0 - AL Status has to be set by PDI 1 - AL Status will be set to value written to AL Control register | ||
1 | R/- | RW- | 0b | Enhanced link detection at all ports 0 - disabled 1 - enabled at all ports | ||
2 | R/- | RW- | 1b | DC Sync Out unit 0 - disabled (power saving) 1 - enabled | ||
3 | R/- | RW- | 1b | DC Latch In unit | ||
4 | R/- | RW- | 0b | Enhanced link detection, port 0 | ||
5 | R/- | RW- | 0b | Enhanced link detection, port 1 | ||
6 | R/- | RW- | Enhanced link detection, port 2 - Not available in TI ESC | |||
7 | R/- | RW- | Enhanced link detection, port 3 - Not available in TI ESC | |||
PDI Configuration | 0x0150 | 0xe0 | ||||
0-4 | R/- | RW- | 0 | Reserved | ||
5-7 | R/- | RW- | 111b | On chip bus 111: TI ESC | ||
Sync/Latch PDI Configuration | 0x0151 | 0x00 | ||||
0-2 | R/- | R/- | 00b | Not available in TI ESC | ||
3 | R/- | R/- | 0b | SYNC0 mapped to AL Event Request register 0x0220.2: 0 - Disabled 1 - Enabled | ||
4-6 | R/- | R/- | 00b | Not available in TI ESC | ||
7 | R/- | R/- | 0b | SYNC1 mapped to AL Event Request register 0x0220.3: 0 - Disabled 1 - Enabled | ||
On-chip bus extended configuration | 0x0152-0x0153 | Not available in TI ESC | ||||
ECAT Event Mask | 0x0200-0x0201 | |||||
0-15 | R/W | R/- | 0 | For each bit 0 - Corresponding bit in 0x210-0x211 will not appear in ECAT IRQ (the IRQ bit is filled with 0 instead) 1 - Corresponding bit appears in IRQ | ||
AL Event Mask | 0x0204-0x0207 | |||||
0-31 | R/- | R/W | 0 | For each bit 0 - Corresponding bit in 0x220-0x223 will not appear in PDI IRQ (the IRQ bit is filled with 0 instead) 1 - Corresponding bit appears in IRQ | ||
ECAT Event Request | 0x0210-0x0211 | 0 | ||||
0 | R/- | R/- | 0 - No change on DC latch inputs 1 - At least one change on DC latch inputs Cleared by reading DC latch times (0x9AE) from ECAT | |||
1 | R/- | R/- | Reserved | |||
2 | R/- | R/- | 0 - No change in DL status 1 - DL status changed Cleared by reading DL status (0x110) from ECAT | |||
3 | R/- | R/- | 0 - No change in AL status 1 - AL status changed Cleared by reading AL status (0x130) from ECAT | |||
4 | R/- | R/- | SyncManager Channel 0 event: 0 - no pending event 1 - event pending | |||
5 | R/- | R/- | SyncManager Channel 1 event (Cleared reading 0x806) | |||
6 | R/- | R/- | SyncManager Channel 2 event | |||
7 | R/- | R/- | SyncManager Channel 3 event | |||
8 | R/- | R/- | SyncManager Channel 4 event | |||
9 | R/- | R/- | SyncManager Channel 5 event | |||
10 | R/- | R/- | SyncManager Channel 6 event | |||
11 | R/- | R/- | SyncManager Channel 7 event | |||
12-15 | R/- | R/- | Reserved | |||
AL Event Request | 0x0220-0x0223 | 0 | ||||
0 | R/- | R/- | 0 - no request for change in AL state (0x120) 1 - request for change in AL state | |||
1 | R/- | R/- | 0 - no change in DC latch inputs 1 - at least one change in DC latch inputs | |||
2 | R/- | R/- | State of DC SYNC0 (if register 0x0151.3=1): Bit is cleared by reading SYNC0 status 0x098E from PDI) | |||
3 | R/- | R/- | State of DC SYNC1 | |||
4 | R/- | R/- | SyncManager activation register (SyncManager register offset 0x6) changed: 0 - No change in any SyncManager 1 - At least one SyncManager changed (Bit is cleared by reading SyncManager Activation registers 0x0806 etc. from PDI) | |||
5 | R/- | R/- | 0 - no EEPROM command pending 1 - EEPROM command pending | |||
6 | R/- | R/- | Watchdog process data 0 - has not expired 1 - has expired (Bit is cleared by reading Watchdog Status Process Data 0x0440 from PDI) | |||
7 | R/- | R/- | Reserved | |||
8-23 | R/- | R/- | 0 - No SM (bit number - 8) interrupt pending 1 - SM interrupt pending | |||
24-31 | R/- | R/- | Reserved | |||
RX Error Counter | 0x0300-0x0307 | 0 | ||||
0-7 | R/W | R/- | 0 | Invalid frame counter port 0. Counting is stopped when 0xFF is reached. Cleared if any of the counters (0x300-0x30b) is written.The invalid frame counters are incremented if there is an error in the frame format (Preamble, SFD – Start of Frame Delimiter, FCS – Checksum, invalid length) | ||
8-15 | R/W | R/- | 0 | RX Error counter port 0. Counting is stopped when 0xFF is reached. Cleared if any of the counters (0x300-0x30b) is written. | ||
16-23 | R/W | R/- | 0 | Invalid frame counter port 1. Counting is stopped when 0xFF is reached. Cleared if any of the counters (0x300-0x30b) is written.The invalid frame counters are incremented if there is an error in the frame format (Preamble, SFD – Start of Frame Delimiter, FCS – Checksum, invalid length) | ||
24-31 | R/W | R/- | 0 | RX Error counter port 1.Counting is stopped when 0xFF is reached. Cleared if any of the counters (0x300-0x30b) is written. | ||
32-39 | R/- | R/- | 0 | Invalid frame counter port 2 - Not available in TI ESC | ||
40-47 | R/- | R/- | 0 | RX Error counter port 2 - Not available in TI ESC | ||
48-55 | R/- | R/- | 0 | Invalid frame counter port 3 - Not available in TI ESC | ||
56-63 | R/- | R/- | 0 | RX Error counter port 3 - Not available in TI ESC | ||
Forwarded RX Error Counter | 0x0308-0x030B | 0 | ||||
0-7 | R/W | R/- | 0 | Forwarded error counter of Port 0 (counting is stopped when 0xFF is reached). Cleared if one of the RX Error counters 0x0300-0x030B is written. | ||
8-15 | R/W | R/- | 0 | Forwarded error counter of Port 1 (counting is stopped when 0xFF is reached). Cleared if one of the RX Error counters 0x0300-0x030B is written. | ||
16-23 | R/- | R/- | 0 | Forwarded error counter of Port 2 - Not available in TI ESC | ||
24-31 | R/- | R/- | 0 | Forwarded error counter of Port 3 - Not available in TI ESC | ||
ECAT Processing Unit Error Counter | 0x030C | |||||
0-7 | R/W | R/- | 0 | ECAT Processing Unit error counter (counting is stopped when 0xFF is reached). Counts errors of frames passing the Processing Unit (e.g., FCS is wrong or datagram structure is wrong). Cleared if register is written. | ||
PDI Error Counter | 0x030D | Not available in TI ESC | ||||
Lost Link Counter | 0x0310-0x0313 | 0 | ||||
0-7 | R/W | R/- | 0 | Lost Link counter of Port 0 (counting is stopped when 0xff is reached). Counts only if port loop is Auto or Auto-Close. Cleared if one of the Lost Link counter registers is written. | ||
8-15 | R/W | R/- | 0 | Lost Link counter of Port 1 | ||
16-23 | R/- | R/- | 0 | Lost Link counter of Port 2 - Not available in TI ESC | ||
24-31 | R/- | R/- | 0 | Lost Link counter of Port 3 - Not available in TI ESC | ||
Watchdog Divider | 0x0400-0x0401 | |||||
0-12 | R/W | R/- | 0x9c2 | (Number of 25 MHz ticks representing basic clock increment for watchdog) - 2. Default value is 0x9c2 = 2498 i.e. 100 us per WD cycle. NOTE: For TI ESC max value is:
| ||
Watchdog Time PDI | 0x0410-0x0411 | |||||
0-15 | R/W | R/- | 0x3e8 | Watchdog time PDI in cycles. Cycle defined by 0x400-0x401. Default value is 1000 for 100ms | ||
Watchdog Time Process Data | 0x0420-0x0421 | |||||
0-15 | R/W | R/- | 0x3e8 | Watchdog time PD in cycles. Default value is 1000 for 100ms | ||
Watchdog Status Process Data | 0x0440-0x0441 | |||||
0-15 | R/- | R/- | 0 | Process Data watchdog 0 - Expired 1 - Active or Disabled Reading this from PDI clears 0x220.6 | ||
Watchdog Counter Process Data | 0x0442 | |||||
0-7 | R/W | R/- | 0 | Write from ECAT clears the register. Number of times PD watchdog expired. Counting stopped at 0xff. (Counter also increases by 1 every time PD watchdog is disabled.) | ||
Watchdog Counter PDI | 0x0443 | |||||
0-7 | R/W | R/- | 0 | Write from ECAT clears the register. Number of times PDI watchdog expired. Counting stopped at 0xff. (Counter also increases by 1 every time PDI watchdog is disabled.) | ||
EEPROM Configuration | 0x0500 | 0 | ||||
0 | R/W | R/- | 0b | 0 - EEPROM control is not offerred to PDI 1 - EEPROM control is offerred to PDI | ||
1 | R/W | R/- | 0b | Force EEPROM access for ECAT 0 - Do not change bit 0x501.0 1 - Reset 0x501.0 to 0 | ||
2-7 | R/- | R/- | Reserved | |||
EEPROM PDI Access State | 0x0501 | 0 | ||||
0 | R/- | R/(W) | 0b | 0 - PDI releases EEPROM access 1 - PDI takes EEPROM access PDI write access possible only when 0x500.0 = 1 and 0x500.1 = 0 | ||
EEPROM Control/Status | 0x0502-0x0503 | 0x0060 | ||||
0 | R/W | R/- | 0b | ECAT write enable - to be set whenever WRITE instruction is given from 0x502.8-10 | ||
1-4 | R/- | R/- | Reserved | |||
5 | R/- | R/- | 1b | EEPROM emulation 0 - normal operation. I2C is used 1 (TI) - PDI emulates EEPROM, I2C is not used | ||
6 | R/- | R/- | 1b | Supported number of EEPROM bytes: 0 - 4 bytes 1 - 8 bytes | ||
7 | R/- | R/- | 0b | EEPROM addressing: 0 - 1 address byte (1KBit – 16KBit EEPROMs) 1 - 2 address bytes (32KBit – 4 MBit EEPROMs) | ||
8-10 | R/(W) | R/(W) | 000b | Write access depends on 0x500-0x501 EEPROM command 000 - no command (write clears EEPROM error bits) 001 - READ (causes 'EEPROM address' (0x504-0x507) to be read and data placed in EEPROM data (0x508-5x50f) 010 - WRITE 100 - RELOAD. Verify checksum, if valid, data in EEPROM to be written in configuration registers (except Station Alias, which needs reset for reload) | ||
11 | R/- | R/- | 0b | Checksum error. Set when RELOAD is instructed with incorrect checksum. Reset when another EEPROM command is issued. | ||
12 | R/- | R/- | 0b | EEPROM loading status 0 - completed successfully. EEPROM configuration available in registers. 1 - in progress or finished with failure | ||
13 | R/- | R/(W) | 0b | W available for PDIs emulating EEPROM. 0 - Last EEPROM command carried out successfully 1 - Invalid EEPROM command or previous command not completed by emulator | ||
14 | R/- | R/- | 0b | Set when WRITE is issued without 0x502.0 set. Reset when NO COMMAND is issued | ||
15 | R/- | R/- | 0b | EEPROM interface is busy | ||
EEPROM Address | 0x0504-0x0507 | |||||
0-32 | R/(W) | R/(W) | 0 | Write access depends on 0x500-0x501 EEPROM address on which EEPROM READ or WRITE is to be carried out | ||
EEPROM Data | 0x0508-0x050f | |||||
0-64 | R/(W) | R/(W) | 0 | Write access depends on 0x500-0x501. Data read from / to write in EEPROM Address (0x504-0x507) | ||
MII Management | 0x0510-0x0511 | 0 | MII Settings | |||
Control/Status | 0 | |||||
0 | R/W | R/- | Write enable. Analogous to 0x502.0 | |||
1 | R/W | R/- | 0: Only ECAT controls MII via these registers 1: PDI can also use these registers to modify MII settings. Note: For TI SubDevices, PDI can modify MII settings using FWHAL API. See FWHAL API guide for details. | |||
2 | R/W | R/- | MI link detection (link configuration, link detection, registers 0x0518-0x051B): 0 - Not available 1 - MI link detection active | |||
3-7 | R/W | R/- | PHY address offset | |||
8-9 | R/W | R/- | Command register: 00 - no command 01 - read 10 - write | |||
10-12 | R/W | R/- | Reserved | |||
13 | R/W | R/- | Read error: bit set when error during MII read (PHY/register not available). Cleared by writing to this register. | |||
14 | R/W | R/- | Command error: 0 - last command was successful 1 - invalid command or Write without Write enable | |||
15 | R/W | R/- | 0 - MII control state machine is idle 1 - MII control state machine is busy | |||
PHY Address | 0x0512 | 0 | ||||
0-4 | R/W | R/- | 0 | PHY address: Address PHY whose settings should be modified / read by next MII command | ||
5-7 | R/W | R/- | Reserved | |||
PHY Register Address | 0x0513 | |||||
0-4 | R/W | R/- | 0 | Address of the register within the PHY | ||
5-7 | R/W | R/- | Reserved | |||
PHY Data | 0x0514-0x0515 | |||||
0-15 | R/W | R/- | 0 | PHY read/write data | ||
Logical Start Address FMMU 0 | 0x0600-0x0603 | |||||
0-31 | R/W | R/- | 0 | FMMU 0: Logical address | ||
Length FMMU 0 | 0x0604-0x0605 | |||||
0-15 | R/W | R/- | 0 | FMMU 0: Length | ||
Logical Start bit FMMU 0 | 0x0606 | 0 | ||||
0-2 | R/W | R/- | FMMU 0 start bit. Logical starting bit that shall be mapped (bits are counted from least significant bit (=0) to most significant bit(=7) | |||
3-7 | R/W | R/- | Reserved | |||
Logical Stop bit FMMU 0 | 0x0607 | 0 | ||||
0-2 | R/W | R/- | FMMU 0 ending bit. Last logical bit that shall be mapped (bits are counted from least significant bit (=0) to most significant bit(=7) | |||
3-7 | R/W | R/- | Reserved | |||
Physical Start Address FMMU 0 | 0x0608-0x0x609 | 0 | ||||
0-15 | R/W | R/- | FMMU 0 physical start address | |||
Physical Start bit FMMU 0 | 0x060A | 0 | ||||
0-2 | R/W | R/- | FMMU 0 physical start bit. | |||
3-7 | R/W | R/- | Reserved | |||
Type FMMU 0 | 0x060B | 0 | ||||
0 | R/W | R/- | 0 - Ignore FMMU 0 mapping for read accesses 1 - Use mapping for read accesses | |||
1 | R/W | R/- | 0 - Ignore FMMU 0 mapping for write accesses 1 - Use mapping for write accesses | |||
2-7 | R/W | R/- | Reserved | |||
Activate FMMU 0 | 0x60C | 0 | ||||
0 | R/W | R/- | Deactivate FMMU 0 | |||
1-7 | R/W | R/- | Reserved | |||
Reserved FMMU 0 | 0x060D-0x060F | |||||
0-23 | R/- | R/- | Reserved | |||
0x0610-0x061F | 0-127 | R/(W) | R/- | Configuration for FMMU 1 | ||
0x0620-0x062F | 0-127 | R/(W) | R/- | Configuration for FMMU 2 | ||
0x0630-0x063F | 0-127 | R/(W) | R/- | Configuration for FMMU 3 | ||
0x0640-0x064F | 0-127 | R/(W) | R/- | Configuration for FMMU 4 | ||
0x0650-0x065F | 0-127 | R/(W) | R/- | Configuration for FMMU 5 | ||
0x0660-0x066F | 0-127 | R/(W) | R/- | Configuration for FMMU 6 | ||
0x0670-0x067F | 0-127 | R/(W) | R/- | Configuration for FMMU 7 | ||
Physical Start Address SyncManager 0 | 0x0800-0x0801 | |||||
0-15 | R/W | R/- | 0 | SM 0 starting physical address | ||
Length SyncManager 0 | 0x0802-0x0803 | |||||
0-15 | R/W | R/- | 0 | SM 0 Length: SM is disabled if length is equal to zero | ||
Control Register SyncManager 0 | 0x0804 | 0 | Note: Write access only when SM 0 is disabled | |||
0-1 | R/(W) | R/- | SM 0 mode: 00 - 3-buffer 10 - 1-buffer (mailbox) 01, 11 - reserved | |||
2-3 | R/(W) | R/- | SM 0 direction: 00 - ECAT read, PDI write 01 - ECAT write, PDI read 10, 11 - reserved | |||
4 | R/(W) | R/- | SM 0 interrupt in ECAT request register (0x210-0x211) 0 - no 1 - yes | |||
5 | R/(W) | R/- | SM 0 interrupt in PDI request register (0x220) | |||
6 | R/(W) | R/- | Watchdog trigger 0 - disabled 1 - enabled | |||
7 | R/- | R/- | Reserved | |||
Status Register SyncManager 0 | 0x0805 | 0 | ||||
0 | R/- | R/- | Interrupt Write: 1: Interrupt after buffer was completely and successfully written 0: Interrupt cleared after first byte of buffer was read | |||
1 | R/- | R/- | Interrupt Read: 1: Interrupt after buffer was completely and successful read 0: Interrupt cleared after first byte of buffer was written | |||
2 | R/- | R/- | Reserved | |||
3 | R/- | R/- | Mailbox mode: mailbox status: 0: Mailbox empty 1: Mailbox full Buffered mode: reserved | |||
4-5 | R/- | R/- | Buffered mode: buffer status (last written buffer): Not available in TI ESC 00: 1. buffer 01: 2. buffer 10: 3. buffer 11: (no buffer written) Mailbox mode: reserved | |||
6 | R/- | R/- | Read buffer in use (opened) Not available in TI ESC | |||
7 | R/- | R/- | Write buffer in use (opened) Not available in TI ESC | |||
Activate SyncManager 0 | 0x0806 | 0 | ||||
0 | R/W | R/- | SyncManager Enable/Disable: 0: Disable: Access to Memory without SyncManager control 1: Enable: SyncManager is active and controls Memory area set in configuration | |||
1 | R/W | R/- | Repeat Request: A toggle of Repeat Request means that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox) | |||
2-5 | R/W | R/- | Reserved | |||
6 | R/W | R/- | Latch Event ECAT: Not available in TI ESC | |||
7 | R/W | R/- | Latch Event PDI: Not available in TI ESC | |||
PDI Activate SyncManager 0 | 0x0807 | 0 | ||||
0 | R/- | R/W | Deactivate SyncManager: Read: 0: Normal operation, SyncManager activated. 1: SyncManager deactivated and reset SyncManager locks access to Memory area. Write: 0: Activate SyncManager 1: Request SyncManager deactivation NOTE: Writing 1 is delayed until the end of a frame which is currently processed. | |||
1 | R/- | R/W | Repeat Ack: If this is set to the same value as set by Repeat Request, the PDI acknowledges the execution of a previous set Repeat request. | |||
2-7 | R/- | R/W | Reserved | |||
0x0808-0x080F | 0-63 | Configuration for SM 1 | ||||
0x0810-0x0817 | 0-63 | Configuration for SM 2 | ||||
0x0818-0x081F | 0-63 | Configuration for SM 3 | ||||
0x0820-0x0827 | 0-63 | Configuration for SM 4 | ||||
0x0828-0x082F | 0-63 | Configuration for SM 5 | ||||
0x0830-0x0837 | 0-63 | Configuration for SM 6 | ||||
0x0838-0x083F | 0-63 | Configuration for SM 7 | ||||
Receive Time Port 0 | 0x0900-0x0903 | |||||
0-31 | R/W* | R/- | 0 | Receive time port 0 : Write: A write access to register 0x0900 with BWR, APWR (any address) or FPWR (configured address) latches the local time of the beginning of the receive frame (start first bit of preamble) at respective port. Read: Local time of the beginning of the last receive frame containing a write access to this register. NOTE: The time stamps cannot be read in the same frame in which this register was written. | ||
0x0904-0x0907 | ||||||
0-31 | R/- | R/- | 0 | Receive time port 1 | ||
0x0908-0x090B | ||||||
0-31 | R/- | R/- | 0 | Receive time port 2 - Not available in TI ESC | ||
0x090C-0x090F | ||||||
0-31 | R/- | R/- | 0 | Receive time port 3 - Not available in TI ESC | ||
System Time | 0x0910-0x0917 | 0 | ||||
0-63 | R/- | R/- | ECAT read access: Local copy of the System Time when the frame passed the reference clock (i.e., including System Time Delay). Time latched at beginning of the frame (Ethernet SOF delimiter). PDI read access: Local copy of the System Time. Time latched when reading first byte (0x0910) | |||
0-31 | W | R/- | Write access: Written value will be compared with the local copy of the System time. The result is an input to the time control loop. | |||
Receive Time ECAT Processing Unit | 0x0918-0x0919 | |||||
0-63 | R/- | R/- | 0 | Local time of the beginning of a frame (start first bit of preamble) received at the ECAT Processing Unit containing a write access to Register 0x0900. NOTE: Example, if port 0 is open, this register reflects the Receive Time Port 0 as a 64 bit value. | ||
System Time Offset | 0x0920-0x0927 | |||||
0-63 | R/W | R/- | 0 | Difference between local time and System Time. Offset is added to the local time. | ||
System Time Delay | 0x0928-0x092B | |||||
0-31 | R/W | R/- | 0 | Delay between Reference Clock and the ESC | ||
System Time Difference | 0x092C-0x092F | 0 | ||||
0-30 | R/- | R/- | 0 | Mean difference between local copy of System Time and received System Time values | ||
31 | R/- | R/- | 0 | 0: Local copy of System Time greater than or equal received System Time 1: Local copy of System Time smaller than received System Time | ||
Speed Counter Start | 0x0930-0x0931 | |||||
0-14 | R/W | R/- | 0 | |||
15 | R/W | R/- | Reserved | |||
Speed Counter Diff | 0x0932-0x0933 | |||||
0-15 | R/- | R/- | Representation of the deviation between local clock period and Reference Clock's clock period (representation: two's complement) Range: ±(Speed Counter Start – 0x7F) | |||
System Time Difference Filter Depth | 0x0934 | |||||
0-3 | R/W | R/- | 0x4 | Filter depth for averaging the received System Time deviation - TI ESC supports 0, 2, 4, 8, 16 only. Rounded to next larger power of 2. 0xc selects 16 | ||
4-7 | R/W | R/- | Reserved | |||
Speed Counter Filter Depth | 0x0935 | |||||
0-3 | R/W | R/- | 0xc | TI ESC supports 0, 2, 4, 8, 16 only. Rounded to next larger power of 2. 0xc selects 16 | ||
4-7 | R/W | R/- | Reserved | |||
Cyclic Unit Control | 0x0980 | 0 | ||||
0 | R/- | R/- | 0b | SYNC out unit control: 0: ECAT controlled 1: PDI controlled | ||
1-3 | R/- | R/- | Reserved | |||
4 | R/- | R/- | 0b | Latch In unit 0: 0: ECAT controlled 1: PDI controlled NOTE: Always 1 (PDI controlled) if System Time is PDI controlled. Latch interrupt is routed to ECAT/PDI depending on this setting. | ||
5 | R/- | R/- | 0b | Latch In unit 1 | ||
6-7 | R/- | R/- | Reserved | |||
Activation register | 0x0981 | 0 | ||||
0 | R/W | R/- | 0b | Sync Out Unit activation: 0: Deactivated 1: Activated NOTE: Write 1 after Start Time was written to generate SYNC signal | ||
1 | R/W | R/- | 0b | SYNC0 generation: 0: Deactivated 1: SYNC0 pulse is generated | ||
2 | R/W | R/- | 0b | SYNC1 generation: 0: Deactivated 1: SYNC1 pulse is generated | ||
3-7 | R/W | R/- | 00000b | |||
Pulse Length of SyncSignals | 0x0982-0x0983 | EEPROM reload operation updates this field (like ET1100,unlike IP Core) | ||||
0-15 | R/- | RW- | 0 | Pulse length of SyncSignals (in Units of 10ns) 0: Acknowledge mode: SyncSignal will be cleared by reading SYNC0/SYNC1 Status register Loaded from EEPROM ADR: 0x2 (During reset/ reload command) | ||
Activation Status | 0x0984 | 0 | ||||
0 | R/- | R/- | 0b | SYNC0 activation state: 0: First SYNC0 pulse is not pending 1: First SYNC0 pulse is pending | ||
1 | R/- | R/- | 0b | SYNC1 activation state: 0: First SYNC1 pulse is not pending 1: First SYNC1 pulse is pending | ||
2-7 | R/- | R/- | Reserved | |||
SYNC0 Status | 0x098E | 0 | ||||
0 | R/- | R/- | 0b | SYNC0 state for Acknowledge mode. SYNC0 in Acknowledge mode is cleared by reading this register from PDI, use only in Acknowledge mode | ||
1-7 | R/- | R/- | Reserved | |||
SYNC1 Status | 0x098F | 0 | ||||
0 | R/- | R/- | 0b | SYNC1 state for Acknowledge mode. SYNC1 in Acknowledge mode is cleared by reading this register from PDI, use only in Acknowledge mode | ||
1-7 | R/- | R/- | Reserved | |||
Start Time Cyclic Operation | 0x0990-0x0997 | |||||
0-63 | R/W | R/- | 0 | Write: Start time (System time) of cyclic operation Read: System time of next SYNC0 pulse | ||
Next SYNC1 Pulse | 0x0998-0x099F | |||||
0-63 | R/- | R/- | 0 | System time of next SYNC1 pulse | ||
SYNC0 Cycle Time | 0x09A0-0x09A3 | |||||
0-31 | R/W | R/- | 0 | Time between two consecutive SYNC0 pulses in ns 0: Single shot mode, generate only one SYNC0 pulse. | ||
SYNC1 Cycle Time | 0x09A4-0x09A7 | |||||
0-31 | R/W | R/- | 0 | Time between SYNC1 pulses and SYNC0 pulse in ns | ||
Latch0 Control | 0x09A8 | 0 | ||||
0 | R/W | R/- | 0b | Latch0 positive edge: 0: Continuous Latch active 1: Single event (only first event active) | ||
1 | R/W | R/- | 0b | Latch0 negative edge | ||
2-7 | R/W | R/- | Reserved | |||
Latch1 Control | 0x09A9 | 0 | ||||
0 | R/W | R/- | 0b | Latch1 positive edge | ||
1 | R/W | R/- | 0b | Latch1 negative edge | ||
2-7 | R/W | R/- | Reserved | |||
Latch0 Status | 0x09AE | 0 | ||||
0 | R/- | R/- | 0b | Event Latch0 positive edge. 0: Positive edge not detected or continuous mode 1: Positive edge detected in single event mode only. Flag cleared by reading out Latch0 Time Positive Edge. | ||
1 | R/- | R/- | 0b | Event Latch0 negative edge. | ||
2 | R/- | R/- | 0b | Latch0 pin state Not available in TI ESC | ||
3-7 | R/- | R/- | Reserved | |||
Latch1 Status | 0x09AF | 0 | ||||
0 | R/- | R/- | 0b | Event Latch1 positive edge. | ||
1 | R/- | R/- | 0b | Event Latch1 negative edge | ||
2 | R/- | R/- | 0b | Latch1 pin state Not available in TI ESC | ||
3 | R/- | R/- | Reserved | |||
Latch0 Time Positive Edge | 0x09B0-0x09B7 | |||||
0-63 | R/- | R/- | 0 | Register captures System time at the positive edge of the Latch0 signal. Reading clears Latch0 Status 0x09AE[0] | ||
Latch0 Time Negative Edge | 0x09B8-0x09BF | |||||
0-63 | R/- | R/- | 0 | System time at the negative edge of the Latch0 signal. | ||
Latch1 Time Positive Edge | 0x09C0-0x09C7 | |||||
0-63 | R/- | R/- | 0 | System time at the positive edge of the Latch1 signal. | ||
Latch1 Time Negative Edge | 0x9C8-0x9CF | |||||
0-63 | R/- | R/- | 0 | System time at the negative edge of the Latch1 signal. | ||
EtherCAT Buffer Change Event Time | 0x09F0-0x09F3 | Not available in TI ESC | ||||
PDI Buffer Start Event Time | 0x09F8-0x9FB | Not available in TI ESC | ||||
PDI Buffer Change Event Time | 0x09FC-0x09FF | Not available in TI ESC | ||||
TI ESC Vendor Specific Registers | ||||||
RX Port0 frame counter | 0x0E00-0x0E03 | |||||
0-31 | R/- | R/- | 0 | Number of valid frames seen at port 0. Change in this register can be used to control the ACT LED. | ||
RX Port1 frame counter | 0x0E04-0x0E07 | |||||
0-31 | R/- | R/- | 0 | Number of valid frames seen at port 1. Change in this register can be used to control the ACT LED. | ||
Port0 PHY address | 0x0E08 | |||||
0-7 | R/- | R/W | 0 | To specify PHY address of PHY connected to physical port0 to PRU firmware | ||
Port1 PHY address | 0x0E09 | |||||
0-7 | R/- | R/W | 0 | To specify PHY address of PHY connected to physical port1 to PRU firmware | ||
PDI ISR DIGIO pin selection register | 0x0E0A | |||||
0-7 | R/W | R/W | 0 | PDI ISR DIGIO pin selection register, selects one of pr1_edio_data_out(24+N), N=0-7 pins as PDI ISR hw pin, configure 255 to disable. Set corresponding bitmask to enable. Application needs to configure pinmux correctly for this to work. | ||
PRU MII RX LINK Polarity | 0x0E0C | |||||
0-31 | R/- | R/W | 0b | Link LED signal polarity PHY address N (Bit N): 0 - Active high 1 - Active low | ||
Port0 TX Start Delay | 0x0E10 | |||||
0-15 | R/W | R/W | 0x50 | TX_START_DELAY for port 0. Change from default values is not recommended. | ||
Port1 TX Start Delay | 0x0E12 | |||||
0-15 | R/W | R/W | 0x50 | TX_START_DELAY for port 1. Change from default values is not recommended. | ||
ESC Reset | 0x0E14-0x0E17 | |||||
0-31 | R/W | R/W | 0 | Vendor specific ESC WARM RESET register. Write "RST"(0x545352) or "rst"(0x747372) to force WARM RESET | ||
NOTE: Normally one need not program any of these following registers(0x0E18-0x0E1F) and even access can be disabled via ECAT if not desired. This may be used to tweak DC drift compensation algorithm for PC based MainDevices (using higher ppm timer) as network clock reference instead of first DC enabled SubDevice in the network. | ||||||
Aggressive DC drift compensation step register | 0x0E18 | |||||
0-7 | R/W | R/W | 1 | Vendor specific aggressive DC drift compensation step register 1 by default, if System Difference exceeds 0xE1D:0xE1C, compensate by additional steps specified here. | ||
Speed counter scale factor register | 0x0E19 | |||||
0-7 | R/W | R/W | 2 | Speed counter is computed by default in 5ns units (this register is to scale this) | ||
Drift compensation fast convergence | 0x0E1A | |||||
0-7 | R/W | R/W | 0 | Vendor specific DC drift compensation fast convergence register takes into account System time diff sign if enabled. 0 : Enabled (default) Otherwise : Disabled | ||
Vendor specific DC drift compensation adjust max limit. 32 (default) | 0x0E1B | |||||
0-7 | R/W | R/W | 32 | Vendor specific DC drift compensation adjust max limit. 32 (default) | ||
Aggressive Drift compensation Trigger | 0x0E1C-0x0E1D | |||||
0-15 | R/W | R/W | 255 | Vendor specific aggressive DC drift compensation trigger register. 255 ns by default | ||
NOTE: Normally one need not program the following register and even access can be disabled via ECAT if not desired. This register is used to enable/disable Enhanced Process Data access latency feature (must be enabled in the application as well). | ||||||
Enhanced Process Data buffer access latency mode control Register | 0x0E24-0x0E25 | |||||
0-15 | R/W | R/W | 0 | Vendor specific Enhanced Process Data buffer access latency mode control Register. 0 by default. If set to 1 then firmware assumes that application has the Enhanced mode enabled and works accordingly. (Will not work correctly if not enabled from application side). | ||
PHY RX Error Counter Register | 0x0E28-0x0E29 | |||||
0-15 | - | R/W | 0 | Address of PHY register maintaining RX Error (RX_ERR) count during frame (when RX_DV is asserted). 0 by default. If set to 0, no PHY register is read for updating 0x0301/0x0303 registers in TI ESC. For TI DP83869/DP83867/DP82826E/DP83822 PHYs, 0x15 should be configured. NOTE: This register should be programmed before PRU cores start running | ||
PDI ISR Time Register | 0x0E2C-0x0E33 | |||||
0-63 | - | R/W | 0 | Register captures the System time when PDI ISR is triggered. | ||
PRU Clock Frequency Selection Register | 0x0E34-0x0E35 | |||||
0-7 | - | R/W | 0 | Selection of 200 MHz or 333 MHz clock frequency for PRU-ICSS Core Clock and IEP Clock used by EtherCAT SubDevice Firmware. | ||
MDIO Link Register for MDIO Manual Mode | 0x0E4C-0x0E4F | |||||
0-31 | R/- | R/- | 0 | MDIO Link State register when the MDIO Manual Mode is enabled (Enabled by default in SoCs with PRU-ICSSG version 1.3 (AM243x, AM64x)) This register is updated after a read of the Generic Status Register of a PHY. The corresponding bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is cleared to zero if the PHY indicates it does not have link or fails to acknowledge the read transaction. This feature is not available in SoCs with PRU-ICSSM (AM263x) | ||
MDIO User Access 0 Register for MDIO Manual Mode | 0x0EC0-0x0EC3 | MDIO User Access 0 Register when the MDIO Manual Mode is enabled (Enabled by default in SoCs with PRU-ICSSG version 1.3 (AM243x, AM64x)) This feature is not available in SoCs with PRU-ICSSM (AM263x) | ||||
0-15 | R/W | R/W | 0 | The data value read from or to be written to the specified PHY register. NOTE: This register should be programmed with PHY address for Port 0, if MDIO Manual Mode is being used (Mandatory for AM243x and AM64x) | ||
16-20 | R/W | R/W | 0 | This field specifies the PHY to be accessed for this transaction. | ||
21-25 | R/W | R/W | 0 | This field specifies the PHY register to be accessed for this transaction. | ||
26-28 | R/W | R/W | 0 | Reserved | ||
29 | R/W | R/W | 0 | This bit is set if the PHY acknowledged the read transaction. | ||
30 | R/W | R/W | 0 | Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read. | ||
31 | R/W | R/W | 0 | Go bit Writing a 1h to this bit triggers an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0h to this bit has no effect. This bit will self clear when the requested access has been completed. NOTE: Any writes to this register should be avoided when the go bit is 1h. If byte access is being used, the go bit should be written last. | ||
MDIO User PHY Select 0 Register for MDIO Manual Mode | 0x0EC4-0x0EC7 | MDIO User PHY Select 0 Register when the MDIO Manual Mode is enabled (Enabled by default in SoCs with PRU-ICSSG version 1.3 (AM243x, AM64x)) This feature is not available in SoCs with PRU-ICSSM (AM263x) | ||||
0-4 | R/W | R/W | 0 | PHY address whose link status is to be monitored NOTE: This register should be programmed with PHY address for Port 0, if MDIO Manual Mode is being used (Mandatory for AM243x and AM64x) | ||
5 | R/W | R/W | 0 | Reserved | ||
6 | R/W | R/W | 0 | Link change interrupt enable | ||
7 | R/W | R/W | 0 | Link status determination select Set to 1h to enable link change status interrupts for PHY address specified in bits 0-4. Link change interrupts are disabled if this bit is set to 0h. NOTE: This field should be set to 1, if MDIO Manual Mode is being used (Mandatory for AM243x and AM64x) | ||
8-31 | R/W | R/W | 0 | Reserved | ||
MDIO User Access 1 Register for MDIO Manual Mode | 0x0EC8-0x0ECB | MDIO User Access 1 Register when the MDIO Manual Mode is enabled (Enabled by default in SoCs with PRU-ICSSG version 1.3 (AM243x, AM64x)) This feature is not available in SoCs with PRU-ICSSM (AM263x) | ||||
0-15 | R/W | R/W | 0 | The data value read from or to be written to the specified PHY register. NOTE: This register should be programmed with PHY address for Port 0, if MDIO Manual Mode is being used (Mandatory for AM243x and AM64x) | ||
16-20 | R/W | R/W | 0 | This field specifies the PHY to be accessed for this transaction. | ||
21-25 | R/W | R/W | 0 | This field specifies the PHY register to be accessed for this transaction. | ||
26-28 | R/W | R/W | 0 | Reserved | ||
29 | R/W | R/W | 0 | This bit is set if the PHY acknowledged the read transaction. | ||
30 | R/W | R/W | 0 | Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read. | ||
31 | R/W | R/W | 0 | Go bit Writing a 1h to this bit triggers an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0h to this bit has no effect. This bit will self clear when the requested access has been completed. NOTE: Any writes to this register should be avoided when the go bit is 1h. If byte access is being used, the go bit should be written last. | ||
MDIO User PHY Select 1 Register for MDIO Manual Mode | 0x0ECC-0x0ECF | MDIO User PHY Select 1 Register when the MDIO Manual Mode is enabled (Enabled by default in SoCs with PRU-ICSSG version 1.3 (AM243x, AM64x)) This feature is not available in SoCs with PRU-ICSSM (AM263x) | ||||
0-4 | R/W | R/W | 0 | PHY address whose link status is to be monitored NOTE: This register should be programmed with PHY address for Port 1, if MDIO Manual Mode is being used (Mandatory for AM243x and AM64x) | ||
5 | R/W | R/W | 0 | Reserved | ||
6 | R/W | R/W | 0 | Link change interrupt enable | ||
7 | R/W | R/W | 0 | Link status determination select Set to 1h to enable link change status interrupts for PHY address specified in bits 0-4. Link change interrupts are disabled if this bit is set to 0h. NOTE: This field should be set to 1, if MDIO Manual Mode is being used (Mandatory for AM243x and AM64x) | ||
8-31 | R/W | R/W | 0 | Reserved |