AM243x INDUSTRIAL COMMUNICATIONS SDK  2026.00.00
EtherCAT SubDevice Beckhoff SSC Demo

Introduction

This example is a EtherCAT SubDevice application based on EtherCAT SubDevice Stack Code (SSC) version 5.13 from Beckhoff.

The example does the following:

  • Initializes the EtherCAT SubDevice stack
  • Initializes the FWHAL, which kicks off the ESC
  • SubDevice is taken to INIT state. It can be move to OP (operational) state by connecting it to a EtherCAT MainDevice, and process data communication is possible after that.
  • Allows user to control 8 LEDs for AM243X-EVM and 4 LEDs for AM243X-LP using an EtherCAT MainDevice
  • Allows Online Application Upgrade, if loaded using SBL OSPI
Note

In the E1/E2 revision of am243x-lp board, there are following issues which impact enhanced link detection and RX_ER monitor by ICSSG. Therefore EtherCAT cable redundancy can not be supported in E1/E2 revision.

  • "PRG1_PRU0_GPO8" is not connected to "PRG1_CPSW_ETH1_LED_LINK" from Ethernet PHY
  • "PRG1_PRU1_GPO8" is not connected to "PRG1_CPSW_ETH2_LED_LINK" from Ethernet PHY
  • "PRG1_PRU0_GPO5" is not connected to "PRG1_CPSW_ETH1_LED_1000/RX_ER" from Ethernet PHY
  • "PRG1_PRU1_GPO5" is not connected to "PRG1_CPSW_ETH2_LED_1000/RX_ER" from Ethernet PHY

In E3 and above revisions, the following connections are available. SDK example enables cable redundancy and will work on E3 and above revisions only. For running it on E1/E2 revision, few changes are required. For more details, see Supported Combinations.

ESI EEPROM over SPI Flash

Overview

This example supports ESI (EtherCAT SubDevice Information) EEPROM emulation over OSPI/QSPI SPI Flash, eliminating the need for a dedicated I2C EEPROM. The ESI data is stored in a dedicated 2KB region of the SPI Flash and accessed via a memory-mapped interface.

Note
By default, I2C EEPROM is configured. The SPI Flash-based ESI storage is an optional enhancement. To use SPI Flash instead of I2C EEPROM, configure the ESI EEPROM Storage option in SysConfig as described below.

SPI Flash Memory Layout

The ESI region is placed beyond the maximum FoE firmware boundary to prevent any overlap during firmware updates:

Region Offset (AM64x / AM243x / AM263x) Offset (AM261x / AM263Px) Size Purpose
SBL 0x00000 0x00000 ≤512KB Second-stage bootloader
FoE Application 0x80000 0x81000 ≤1MB Firmware via FoE download
ESI EEPROM 0x180000 0x181000 2KB EtherCAT SubDevice config
Note
The FoE region is protected by a 1MB (FOE_APPL_MAX_SIZE) compile-time guard in tiesceoefoe.h. Any FoE download that exceeds this limit is rejected before it can reach the ESI region.

SysConfig Linker Configuration

The ESI EEPROM region is carved out as a dedicated section in the generated linker.cmd via the SysConfig Memory Configurator. This ensures the flash programmer does not overwrite ESI data when reflashing the application.

Step 1 — Add FLASH_ESI Memory Region

In Memory Configurator → Memory Region → ADD:

Field AM64x / AM243x / AM263x AM261x / AM263Px
Name FLASH_ESI FLASH_ESI
Type FLASH FLASH
Start Address 0x60180000 0x60181000
Region Size 0x800 0x800

Step 2 — Add ESI EEPROM Section

In Memory Configurator → Section → ADD:

Field Value
Name ESI EEPROM over SPI Flash
Type NOLOAD
Group Section Unchecked
Load Memory FLASH_ESI
Run Memory FLASH_ESI
Output Section Name .esieeprom
Start Section __esieeprom_start
End Section __esieeprom_end

Generated linker.cmd Output

The SysConfig tool generates the following entries:

/* Memory Regions */
FLASH_ESI (IRW) : ORIGIN = 0x60180000, LENGTH = 0x800 /* AM64x/AM243x/AM263x */
/* FLASH_ESI (IRW) : ORIGIN = 0x60181000, LENGTH = 0x800 -- AM261x/AM263Px */
/* Sections */
.esieeprom (NOLOAD) : {
} align(8)
RUN_START(__esieeprom_start)
RUN_END(__esieeprom_end)
} > FLASH_ESI
Note
NOLOAD means the linker reserves the address space but places no data there in the output binary (.appimage). The flash programmer skips this region entirely when programming the application. ESI content is managed at runtime by tiesc_ospiEepromWrite() / tiesc_ospiEepromRead().

Step 3 — Enable ESI EEPROM over SPI Flash in SysConfig

In the EtherCAT SysConfig module, set the ESI EEPROM Storage option to OSPI/QSPI Flash. This generates #define TIESC_ESI_EEPROM_OSPI_ENABLE into ti_drivers_config.h, which routes the BSP EEPROM callbacks to the SPI Flash implementation.

Linker Symbol Usage in Code

OSPI_ESI_DATA_OFFSET (the physical flash offset used by Flash_read/Flash_write) is derived from the __esieeprom_start linker symbol in tiescsoc.h:

/* OSPI XIP hardware base — maps physical flash offset 0x0 to CPU address 0x60000000 */
#define OSPI_FLASH_XIP_BASE (0x60000000U)
/* Physical flash offset derived from linker symbol — single-sourced from SysConfig */
extern uint32_t __esieeprom_start;
#define OSPI_ESI_DATA_OFFSET ((uint32_t)(&__esieeprom_start) - OSPI_FLASH_XIP_BASE)

This means the ESI flash address is single-sourced from SysConfig — if the FLASH_ESI memory region origin is changed in SysConfig, OSPI_ESI_DATA_OFFSET picks up the new value automatically without any code change.

Flash Operation

Write Flow:

  1. EtherCAT master writes to ESI address range — data is cached in RAM (eeprom_cache)
  2. On flush event, tiesc_ospiEepromWrite() is called:
    • Erases the 64KB block at the ESI offset
    • Writes full 2KB ESI data to SPI Flash
  3. On first boot with blank flash: default ESI from compiled-in array is written automatically

Read Flow:

  1. On boot, bsp_eeprom_emulation_init() reads ESI from Flash into RAM cache
  2. Stack accesses ESI via RAM pointer — no further Flash reads during operation
  3. ESI data is preserved across application firmware updates (NOLOAD region)

Debug Support

Enable debug logging by defining TIESC_ESI_EEPROM_OSPI_DEBUG:

  • Full 2048-byte dump of ESI EEPROM region at each call site (labelled)
  • Write call counter and verified physical address

Example output:

ESI EEPROM: OSPI_ESI_DATA_OFFSET = 0x00180000 (__esieeprom_start XIP = 0x60180000)
ESI flash dump (After Write):
[0000]: 6D 04 08 29 01 10 00 10
[0008]: 20 03 03 10 02 00 03 00
...

Performance Considerations

  • First Boot: One write to persist default ESI to Flash
  • FOE Download: One write per download completion (full 2KB block erase + write)
  • Application Exit: One final write to ensure data persistence
  • Flash Wear: Block erase is 64KB (covers ESI + extra space), but only 2KB is written

Supported Combinations

Parameter Value
CPU + OS r5fss0-0 freertos
ICSSG ICSSG1
Toolchain ti-arm-clang
Boards am243x-evm, am243x-lp (E3 and A Revision)
Example folder examples/industrial_comms/ethercat_subdevice_beckhoff_ssc_demo
Parameter Value
CPU + OS r5fss1-0 freertos
ICSSG ICSSG0
Toolchain ti-arm-clang
Boards am243x-evm, am243x-lp (E3 and A Revision)
Example folder examples/industrial_comms/ethercat_subdevice_beckhoff_ssc_demo

As mentioned above, SDK example will work on E3 and above revisions of am243x-lp only. For running it on E1/E2 revision, following changes are needed.

  • Disable enhanced link detection
    • In tiesc_socParamsInit() function present in "${SDK_INSTALL_PATH}/examples/industrial_comms/ethercat_subdevice_beckhoff_ssc_demo/am243x-lp/tiescsoc.c", set bspInitParams->enhancedlink_enable to TIESC_MDIO_RX_LINK_DISABLE.
    • For newer versions of SDK, Enhanced Link can be disabled from the EtherCAT module in SysConfig:
      Disable Enhanced Link in SysConfig
  • Disable the pinmux configuration for pins not available in E1/E2 revision
    • In "EtherCAT" module in SysConfig, uncheck following pins from PRU_ICSSG1_MII_G_RT.
      • MII0_RXER(PR1_MII0_RXER)
      • MII0_RXLINK(PR1_MII0_RXLINK)
      • MII1_RXER(PR1_MII1_RXER)
      • MII1_RXLINK(PR1_MII1_RXLINK)

PRU ICSSG0 Instance

This example, configured to run on r5fss_1_0_freertos uses PRU_ICSSG0 instance in PRU_ICSSG peripheral. On EVMs supported by TI (AM64X-EVM, AM243X-EVM), it is not possible to use PRU_ICSSG0, as the PRG0_RGMII1 and PRG0_RGMII0 pins are not connected to Ethernet PHYs. This example would require a dedicated custom board to use the PRU_ICSSG0 instance of ICSSG peripheral. This example, with the custom board, is compatible for PRU_ICSSG0 and it provides full support out of the box.

See ICSSG0 Usage Guide for more details

Performance Benchmarking

TwinCAT MainDevice was used as the EtherCAT MainDevice for these tests.

Cycle Time

Lowest cycle time tested is 31.25 us (microseconds) with Distributed Clock (DC) Synchronization mode.

Interrupt Processing Time

Following is the interrupt processing time for PDI and Sync ISRs with 50 us cycle time. The RxPDO size is 5 bytes and TxPDO size is 7 bytes in this example.

Scenario PDI ISR Processing Time (microseconds) SYNC0 ISR Processing Time (microseconds) SYNC1 ISR Processing Time (microseconds)
DC mode with SYNC0 enabled 2.7 3.2 0
DC mode with SYNC0 and SYNC1 enabled 2.7 0.8 2.6

Steps to Run the Example

  • To build this example, it is necessary to get the EtherCAT SubDevice Stack Code (SSC). Download EtherCAT stack version 5.13 from ETG website and extract it to a local folder. Please refer to "Application Note ET9300 (EtherCAT SubDevice Stack Code)" for more details on SSC.
  • Generate the patched EtherCAT SubDevice stack code source files using any one of the below mentioned methods:
    • Using the patch file
      • Copy the EtherCAT SubDevice Stack files to {SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/stack_sources/ folder.
      • Download Windows Patch Utility from gnuwin32 sourceforge. (Note that this is not a TI tool. See licensing information page for more details)
      • Download Dos2Unix/Unix2Dos-Text file format converters from gnuwin32 sourceforge. (Note that this is not a TI tool. See licensing information page for more details)
      • Patch file utility(Patch.exe) and unix2dos.exe utility can be found in their bin folders.
      • Launch DOS Command prompt
      • CD to the folder ${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/patch which contains TI_ECAT.patch.
      • Execute unix2dos.exe as given below:
        $(Dos2Unix/Unix2Dos-DIR)/bin/unix2dos.exe TI_ECAT.patch
      • CD to patch file utility bin folder.
      • Execute patch.exe as given below:
        patch.exe -i ${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/patch/TI_ECAT.patch -d ${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/stack_sources/
- **Using Beckhoff SSC Tool**
    - Install SSC tool version 1.5.3.0. This configuration tool facilitates working with the EtherCAT SubDevice Stack Code (SSC), as it allows reducing the size of the EtherCAT SubDevice stack code by removing unused code parts depending on the desired configuration. Objects should be defined in a .xlsx file. Please refer to [EtherCAT SubDevice Design - Quick Guide](https://download.beckhoff.com/download/document/io/ethercat-development-products/ethercat_slave_design_quick_guide.pdf) for details.
    - Each SoC has its own configuration folder under `${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/patch/<soc>/` (e.g., `am64x`, `am243x`, `am263x`, `am263px`, `am261x`). Each folder contains two XML configuration files:
        - `TI_ESC_8i3.xml` — Standard EtherCAT sample demo. Use this for the default SDK example.
        - `TI_ESC_CiA402_8i3.xml` — CiA402 drive profile. Use this when building the CiA402 demo.
    - Click on "Import" button and select the desired XML file from the SoC-specific folder inside `${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/patch` folder.
    - Make sure "Custom" is selected in the dialog box and select the matching TI configuration from the list.
    - Set DC_SUPPORTED to 1 if not set.
    - Save the project.
    - Click "Project->Create new SubDevice Files". This will generate the EtherCAT Source files specific to the the selected TI device.
    - Copy all the generated files except tiescappl.c, tiescappl.h and tiescapplObjects.h to `${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/stack_sources/`.

    \note
    - For the SDK example, tiescappl.c and tiescappl.h files are used from "${SDK_INSTALL_PATH}/examples/industrial_comms/ethercat_subdevice_beckhoff_ssc_demo/" folder, and not from the SSC Tool generated files.
    - If you want to modify the object dictionary for the standard demo, you can update `${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/patch/<soc>/tiescappl.xlsx` and then the SSC tool will generate the application code accordingly.
    - `TI_ESC_CiA402_8i3.xml` intentionally omits the `ApplicationFile` xlsx reference. This is required so that the SSC Tool respects the `CiA402_SAMPLE_APPLICATION=1` setting and generates `cia402appl.c` / `cia402appl.h`. If `tiescappl.xlsx` is referenced, the tool overrides this setting to 0 and skips CiA402 file generation.
  • Change macro definitions in {SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/stack_sources/ecat_def.h, if required for your application. Please ensure that TIESC_HW is set to 1, and TIESC_APPLICATION is set to 1.
Note
Fast link detection using RX_LINK pins (MLINK mode) is required to support complete EtherCAT functionality, and certain conformance tests will fail if fast link detection is not used. Link Polling is not suggested, use it only for debugging if required.
Attention
If you need to reload and run the example again, EVM power-cycle is MUST.

Sample Output

Shown below is a sample output when the application is run:

EtherCAT Device
EtherCAT Sample application
Revision/Type : x0690 Build : x054F
Firmware Version : 6.5.79
SYNC0 task started
SYNC1 task started

See Also

EtherCAT SubDevice FWHAL