EtherCAT Debug Guide

Table of Contents

• Assumptions
• Scope
• Ethernet PHY Configuration App Note
• Common Debugging Tasks
  • Make sure all Mandatory EtherCAT signals are connected
  • Loading and running on CCS
  • Checking Link Status
    • Make sure the HW connections are working fine
  • Additional Debug Support
  • PHY Identification Issues
    • PHY Register Access Issues
  • Custom PHY Configuration Requirements
    • Mandatory PHY Configurations
    • LED Configuration for Enhanced Link Detection
    • PHY Configuration Implementation Checklist
• References
• EtherCAT Related E2E Queries

It is highly recommended to go through EtherCAT SubDevice FWHAL page before proceeding with this page.

Assumptions

• A basic understanding of ICSS Architecture and SoC
• In addition to this a basic familiarity with the following tools
  • EtherCAT basics and functionality
  • EtherCAT specific PHY support/integration
  • Code Composer Studio
  • Wireshark or any other packet sniffing tool
  • Basic TwinCAT configuration or any other EtherCAT MainDevice

Scope

This page is meant to help the developer in

• Familiarizing with common debugging tools and techniques
• Identifying and resolving frequently faced issues

Ethernet PHY Configuration App Note

You can refer to Ethernet PHY Configuration Using MDIO for Industrial Applications for details on the required PHY configuration to the MDIO module.

Common Debugging Tasks

Make sure all Mandatory EtherCAT signals are connected

Refer to Hardware Requirements for the hardware requirements required to run EtherCAT.

Loading and running on CCS

See CCS Launch, Load and Run page for details on how to load and run binaries on EVM or LP using CCS.

Checking Link Status

Most common issue observed is in cases where different PHYs (compared to those on EVM/LP) and the PHY status registers may be read incorrectly and that might lead to some issues.

The presence and responsiveness of the connected PHY on the MDIO bus is indicated by the MDIO_ALIVE_REG (offset 0x2408). The link detection is observed in MDIO_LINK_REG (at offset 0x240C). On the connection of an active network to the EtherCAT SubDevice using an ethernet cable, the bits corresponding to the PHY Address will be set/cleared based on the PHY link polarity. The polarity is to be followed when EnhancedLink feature is enabled.
Make sure that PHY Address is configured in such a way where if you see the bit getting set/reset when you connect the in/out port to an active network using Ethernet cable, then you should configure that particular bit address as the PHY Address of the corresponding port. This is important to configure the correct PHY Address for the IN port or the OUT port.

Do note that the PHY Address Configuration should be as per the corresponding board schematics, where the strap pin configuration can be referred to. The MDIOALIVE Register probes for a valid PHY.

Note

In AM243x/AM64x devices, The MDIO_ALIVE_REG (MDIO Alive Register), MDIO_LINK_REG (MDIO Link Register), MDIO_USER_ACCESS_REG_0 (MDIO User Access 0 Register), MDIO_USER_PHY_SEL_REG_0 (MDIO User PHY Select 0 Register), MDIO_USER_ACCESS_REG_1 (MDIO User Access 1 Register) and MDIO_USER_PHY_SEL_REG_1 (MDIO User PHY Select 1 Register) are emulated at the following register spaces:

MDIO Emulated Register Space for EtherCAT SubDevice

This is done due to silicon errata i2329 — MDIO interface corruption. Please refer to PRU-ICSS Firmware for MDIO Manual Mode for more details.

Make sure the HW connections are working fine

• In order to confirm the basic HW connection and communication is working, the user can disable MDIO Manual Mode. In most cases, the errata will not be seen, and hence disabling the MDIO Manual mode (MDIO emulation firmware) should be fine. Do note that disabling MDIO Manual Mode is only for testing purposes. We recommend Enabling MDIO Manual Mode at all times during validation of the application.

Once this is disabled, the MDIO Registers should show the details and configurations for the connected PHY at the MDIO Register space (From 0x30032400 for ICSSG0 instance and 0x300B2400 for ICSSG1 instance).

Additional Debug Support

Following are some of the issues that were supported in order to bring-up the EtherCAT SubDevice on a custom HW or a different PHY:

Issue	Probable Cause	Probable Fix (Couple of things to look on)
PHY is not able to detect the EtherCAT link.	MDIO is not able to access the PHY Registers.	Make sure the HW connections are correct and intact.
	MII0_RXLINK and MII1_RXLINK signals are not connected properly.	Disable EnhancedLink and make sure MDIO Manual Mode Link Status Update is configured to PHY Polling Based.
	LED is not configured correctly to detect a stable LINK.	LED configuration has to be a stable LINK (LED_SPEED or LED_LINK (without activity blink))
	Polarity of Link is not configured properly via the API.	Refer to Enhanced Link Detection Procedure on the procedure to configure the link polarity. Make sure IN and OUT ports are configured correctly based on the PHY Link status.
	PHY may not be getting the link status update.	Make sure the PHY is detecting by reading the BMSR Register of the PHY.
	MDIO Manual Mode is enabled and Enhanced Link detection is disabled but still MLINK mode is configured.	Make sure "MDIO Manual Mode Link Status Update" field is set to PHY Polling Based in SysConfig. The current SDK will pick the correct option based on the EnhancedLink status, but in previous SDK versions, this needs to be done manually.
	External PHYs sometimes aren't correctly reset or initialized, leading to link problems.	Make sure PHY reset sequence is implemented correctly for the external PHY. Additionally, refer to tiesc_ethphyInit API for the EtherCAT specific configurations to be done for the PHY.
The ESC Reg 0x110 DL Status shows the out port is still connected even if the cable is disconnected, which would cause the SubDevice to no longer return the frames sent by the MainDevice.	MDIO_USER_PHY_SEL_REG (offset 0x2484) register is not configured correctly.	MDIO_USER_PHY_SEL_REG (offset 0x2484) needs to be configured to enable the link change interrupt (bit6). Additionally, the corresponding link status determination (bit7) is to be programmed for MLINK/MDIO based determination (MLINK for EnhancedLink and MDIO for otherwise). For the Beckhoff Demo, this configuration is done within tiesc_ethphyInit() API.
Link and the auto-negotiation is complete from PHY Register Status but not able to scan using MainDevice. No link detection on ESC DL Status Register.	TI ESC is not receiving the EtherCAT frames.	Make sure RX Frame counter (ESC Register 0x0E00 and 0x0E04) is getting incremented to make sure frames are being received by the TI ESC (Firmware)
	Incorrect MDIO API (MDIO_phyRegWrite) used to write to the extended PHY Registers.	This function is intended to be used with the IEEE standard PHY registers only. Use the MDIO_phyExtRegWrite API to write into registers above the standard PHY registers (above offset 32h)
The EtherCAT Error counters (ESC Register 0x0300 to 0x0303) are incrementing from time to time.	EtherCAT MainDevice may be sending out Error frames.	Monitor the wireshark logs for any error frames from the EtherCAT MainDevice. Additionally, try with another MainDevice and observe the behavior.
	MainDevice PC NIC may be sending out error frames and the ESC may be processing it	Make sure DL Control (ESC Register 0x0100) is configured correctly. If Bit0 is set then non-EtherCAT frames will be destroyed. Otherwise the frames are forwarded without processing.
EtherCAT SubDevice configured correctly but TwinCAT not able to scan for the Device.	TwinCAT is not configured correctly to detect for the TI EtherCAT SubDevice.	Follow Creating TwinCAT Project to add the ESI file and install the EtherCAT driver for the TwinCAT port.
TwinCAT reports "received invalid DC timings!" warning for a SubDevice when operating in DC mode	Incorrect cable connection between SubDevices — the OUT port of one device is connected to the OUT port of the next device instead of its IN port	Verify cable topology: the OUT port of the upstream SubDevice must be connected to the IN port of the downstream SubDevice To diagnose, capture a Wireshark trace and apply the filter ecat.dc.dif.ba. If DC RecvTime_0 (ESC register 0x0900) reads 0x00000000 for the affected SubDevice, this confirms the incorrect connection

PHY Identification Issues

A common issue when implementing EtherCAT on custom hardware is the inability to get proper identification from the Ethernet PHY. This section provides guidance on troubleshooting PHY identification problems.

PHY Register Access Issues

If you're having trouble accessing the PHY registers or getting incorrect values:

Issue	Probable Cause	Troubleshooting Steps
Cannot read PHY ID registers (0x02, 0x03)	Incorrect PHY address configuration	Verify the PHY address used matches the hardware configuration (check strap pins) Try scanning all possible PHY addresses (0-31) to find responsive PHY Check MDIO_ALIVE_REG to see which PHY addresses respond
Reading all zeros or 0xFFFF from PHY registers	MDIO hardware connection issues	Verify MDIO and MDC pins are properly connected Check for pull-up resistors on MDIO line Verify the PHY has power and reset sequence completed Verify clock frequency to PHY is within specification Make sure MDIO Manual Mode is enabled from SysConfig
Inconsistent PHY register readings	Signal integrity or timing issues	Use proper termination on MDIO lines Reduce MDIO clock frequency Ensure proper grounding between MCU and PHY Check for potential interference sources
PHY ID doesn't match expected value	PHY model mismatch or incorrect initialization	Double-check PHY part number against datasheet Ensure PHY has completed power-on reset sequence
Link Up not coming up	PHY is not configured in MII mode	Check PHY strapping pins for interface mode selection Ensure PHY is configured for MII mode, not RMII or RGMII EtherCAT requires MII mode operation Verify interface mode register settings in PHY configuration

Custom PHY Configuration Requirements

When integrating a custom PHY (different from the DP83869/DP83826 used in TI EVMs/LPs), the following configurations must be implemented to ensure proper EtherCAT operation. These requirements are derived from the tiesc_ethphyInit() API implementation.

Mandatory PHY Configurations

Configuration	Purpose	Implementation Details	Priority
MII Mode Selection	EtherCAT requires MII interface mode for proper frame handling	Configure PHY to operate in MII mode (not RMII or RGMII) Check PHY datasheet for interface mode selection registers May require hardware strapping pin configuration Example: ETHPHY_CMD_ENABLE_MII command	Critical
Auto-MDIX Enable	Allows automatic detection and configuration of straight-through or crossover cables	Enable Auto-MDIX in PHY control registers Improves cable compatibility and reduces installation errors Example: ETHPHY_CMD_ENABLE_AUTO_MDIX command	Recommended
Extended Full-Duplex Ability	Enables full-duplex operation required for EtherCAT communication	Configure PHY for full-duplex mode Disable half-duplex advertisement if supported Example: ETHPHY_CMD_ENABLE_EXTENDED_FD_ABILITY command	Critical
Odd Nibble Detection	EtherCAT uses odd nibble (alignment error) frames as markers to detect error sources in the network topology	PHY must transparently forward and receive odd nibble error frames Disable PHY's automatic alignment to byte boundary feature This allows EtherCAT to use alignment errors for diagnostic purposes Implementation: Set bit to disable nibble alignment (counterintuitive naming in some PHYs) Example: ETHPHY_CMD_ENABLE_ODD_NIBBLE_DETECTION command Note: Command name may say "enable detection" but actually disables PHY correction	Critical
Enhanced IPG Detection	Detects RXERR during inter-packet gap (IDLE state)	Enable detection of receive errors during idle periods Improves error detection and network diagnostics Example: ETHPHY_CMD_ENABLE_ENHANCED_IPG_DETECTION command	Recommended
Fast Link Down Detection	Rapidly detects link loss for quick EtherCAT topology changes	Enable fast link drop based on RX error count Configure to drop link when 32 RX errors occur in 10μs interval Optional: Enable energy loss detection for ~10μs reaction time Critical for EtherCAT's fast fault detection requirements Example: ETHPHY_CMD_ENABLE_FAST_LINK_DOWN_DETECTION command	Critical
Disable 1000M Advertisement	EtherCAT SubDevice operates at 100Mbps only	Disable gigabit advertisement in PHY capability registers Forces 100BASE-TX operation Prevents unnecessary auto-negotiation delays Example: ETHPHY_CMD_DISABLE_1000M_ADVERTISEMENT command	Critical
MDIO Link Interrupt Enable	Enables link status change interrupts for the ESC	Configure MDIO_LINKSEL mode based on Enhanced Link setting:   • MDIO_LINKSEL_MLINK_MODE when Enhanced Link is enabled   • MDIO_LINKSEL_MDIO_MODE when Enhanced Link is disabled Enable for both PHY addresses (IN port and OUT port) Example: MDIO_enableLinkInterrupt() API calls	Critical
PHY Soft Reset	Applies all configuration changes after setup	Perform soft reset after all configurations are complete Ensures all register changes take effect Wait for reset completion before proceeding Example: ETHPHY_CMD_SOFT_RESTART command	Critical

LED Configuration for Enhanced Link Detection

When Enhanced Link Detection is enabled (using MII_RXLINK signals), proper LED configuration is essential:

LED Pin	Configuration	Purpose	Required for Enhanced Link
LED_0	Link OK (without activity blink)	Provides stable link indication to MII_RXLINK signal Must be steady state (not blinking) for proper link detection Used by ESC hardware for fast link status monitoring	Yes (Critical)
LED_1	RX_ER (Receive Error)	Indicates receive errors during frame reception Helps detect frame corruption and signal integrity issues Used for diagnostics and fast link drop detection	Recommended
LED_2	Link OK with RX/TX Activity Blink	Visual indication of link status and data activity Useful for debugging and status monitoring Configure blink rate (typical: 200ms)	Optional
LED_3	10/100M Link Established	Indicates speed of established link Helps verify correct speed negotiation (100Mbps for EtherCAT) Useful for diagnostics	Optional

Note

Critical: For Enhanced Link Detection, LED_0 must be configured as a stable LINK indicator (LED_LINK or LED_SPEED), not as LINK_ACTIVITY. A blinking LED will cause intermittent link detection failures as the MII_RXLINK signal requires a steady state.

PHY Configuration Implementation Checklist

When porting to a custom PHY, use this checklist to ensure all required configurations are implemented:

• [ ] Hardware Verification
  • [ ] PHY is configured for MII mode (check strapping pins)
  • [ ] MDIO and MDC connections are verified
  • [ ] MII signals (TXD, RXD, TX_EN, RX_DV, RX_ER, etc.) are connected
  • [ ] MII_RXLINK signals are connected (if using Enhanced Link Detection)
  • [ ] PHY reset signal is properly controlled
  • [ ] PHY power supply is stable and within specification
• [ ] Basic PHY Configuration
  • [ ] PHY address matches hardware configuration
  • [ ] PHY can be accessed via MDIO (verify PHY ID registers)
  • [ ] MII mode is enabled in PHY registers
  • [ ] Auto-MDIX is enabled
  • [ ] 1000M advertisement is disabled
  • [ ] Full-duplex mode is enabled
• [ ] EtherCAT-Specific Configuration
  • [ ] Odd nibble detection is disabled from PHY
  • [ ] Enhanced IPG detection is enabled
  • [ ] Fast link down detection is enabled (RX error based)
  • [ ] LED_0 is configured for stable link indication (if using Enhanced Link)
  • [ ] LED_1 is configured for RX_ER indication (recommended)
  • [ ] MDIO link interrupts are enabled with correct mode
• [ ] Testing and Verification
  • [ ] PHY achieves link with EtherCAT MainDevice
  • [ ] Link status is correctly reported in ESC DL Status register
  • [ ] Link drop is detected within required time (10µs)
  • [ ] No excessive error counters in ESC registers (0x0300-0x030D)
  • [ ] EtherCAT communication is stable under load

References

Module	Location		TRM Reference/Register Description	Description
	ICSSG0 Instance	ICSSG1 Instance
PRU_ICSSG_CFG	0x30026000 to 0x30026198	0x300A6000 to 0x300A6198	Section 6.4.14.9	PRU_ICSSG_CFG is the main configuration interface for the subsystem
PRU_IEP_IEP0	0x3002E000 to 0x3002E318	0x300AE000 to 0x300AE318	Section 6.4.14.9	PRU_IEP_IEP handles precise timing needed for industrial protocols
PRU_MII_RT_MII_RT	0x30032000 to 0x3003206C	0x300B2000 to 0x300B206C	Section 6.4.14.11	PRU_MII_RT_MII_RT manages the actual Ethernet frame handling
PRU_MDIO_MDIO	0x30032400 to 0x3003248C	0x300B2400 to 0x300B248C	Section 6.4.14.10	PRU_MDIO_MDIO deals with PHY layer configuration
EtherCAT ESC Register Space	0x30010000 to 0x30010ED1	0x30090000 to 0x30090ED1	TI EtherCAT SubDevice Controller Register List	EtherCAT ESC Register Space contains all EtherCAT-specific functionality

EtherCAT Related E2E Queries

Refer to EtherCAT related E2E posts for previously answered queries on EtherCAT.