Assumption

A basic understanding of ICSS Architecture and SoC
In addition to this a basic familiarity with the following tools
- EtherCAT basics and functionality
- EtherCAT specific PHY support/integration
- Code Composer Studio
- Wireshark or any other packet sniffing tool
- Basic TwinCAT configuration or any other EtherCAT MainDevice

Scope

This page is meant to help the developer in

Familiarizing with common debugging tools and techniques
Identifying and resolving frequently faced issues

Ethernet PHY Configuration App Note

You can refer to Ethernet PHY Configuration Using MDIO for Industrial Applications for details on the required PHY configuration to the MDIO module.

Common Debugging Tasks

Make sure all Mandatory EtherCAT signales are connected

Refer to Hardware Requirements for the hardware requirements required to run EtherCAT.

Loading and running on CCS

See CCS Launch, Load and Run page for details on how to load and run binaries on EVM or LP using CCS.

Checking Link Status

Most common issue observed is in cases where different PHYs (compared to those on EVM/LP) and the PHY status registers may be read incorrectly and that might lead to some issues.

The presence and responsiveness of the connected PHY on the MDIO bus is indicated by the MDIO_ALIVE_REG (offset 0x2408). The link detection is observed in MDIO_LINK_REG (at offset 0x240C). On the connection of an active network to the EtherCAT SubDevice using an ethernet cable, the bits corresponding to the PHY Address will be set/cleared based on the PHY link polarity. The polarity is to be followed when EnhancedLink feature is enabled.
Make sure that PHY Address is configured in such a way where if you see the bit getting set/reset when you connect the in/out port to an active network using Ethernet cable, then you should configure that particular bit address as the PHY Address of the corresponding port. This is important to configure the correct PHY Address for the IN port or the OUT port.

Do note that the PHY Adderss Configuration should be as per teh correspondinng board schematics, where the strap pin configuration can be referred to. The MDIOALIVE Register probes for a valid PHY.

Note

In AM243x/AM64x devices, The MDIO_ALIVE_REG (MDIO Alive Register), MDIO_LINK_REG (MDIO Link Register), MDIO_USER_ACCESS_REG_0 (MDIO User Access 0 Register), MDIO_USER_PHY_SEL_REG_0 (MDIO User PHY Select 0 Register), MDIO_USER_ACCESS_REG_1 (MDIO User Access 1 Register) and MDIO_USER_PHY_SEL_REG_1 (MDIO User PHY Select 1 Register) are emulated at the following register spaces:

MDIO Emulated Register Space for EtherCAT SubDevice

This is done due to the i2329— MDIO interface corruption silicon errata. Please refer to PRU-ICSS Firmware for MDIO Manual Mode for more details.

Make sure the HW connections are working fine

In order to confirm the basic HW connection and communication is working, the user can disable MDIO Manual Mode. In most cases, the errata will not be seen, and hence disabling the MDIO Manual mode (MDIO emulation firmware) should be fine. Do note that disabling MDIO Manual Mode is only for testing purpose. We recommend Enabling MDIO Manual Mode at all times during validation of the application.

Once this is disabled, the MDIO Registers should show the details and configurations for the connected PHY at the MDIO Register space (From 0x30032400 for ICSSG0 instance and 0x300B2400 for ICSSG1 instance).

Additional Debug Support

Following are some of the issues that were supported in order to bring-up the EtherCAT SubDevice on a custom HW or a different PHY:

Issue	Probable Cause	Probable Fix (Couple of things to look on)
PHY is not able to detect the EtherCAT link.	MDIO is not able to access the PHY Registers.	Make sure the HW connections are correct and intact.
	MII0_RXLINK and MII1_RXLINK signals are not connected properly.	Disable EnhancedLink and make sure `MDIO Manual Mode Link Status Update` is configured to PHY Polling Based.
	LED is not configured correctly to detect a stable LINK.	LED configuration has to be a stable LINK (LED_SPEED or LED_LINK (without activity blink))
	Polarity of Link is not configured properly via the API.	Refer to Enhanced Link Detection Procedure on the procedure to configure the link polarity. Make sure IN and OUT ports are configured correctly based on the PHY Link status.
	PHY may not be getting the link status update.	Make sure the PHY is detecting by reading the BMSR Register of the PHY.
	MDIO Manual Mode is enabled and Enhanced Link detection is disabled but still MLINK mode is configured.	Make sure "MDIO Manual Mode Link Status Update" field is set to PHY Polling Based in SysConfig. The current SDK will pick the correct opetion based on the EnhancedLink status, but in previous SDK versions, this needs to be done manually.
	External PHYs sometimes aren't correctly reset or initialized, leading to link problems.	Make sure PHY reset sequence is implemented correctly for the external PHY. Additionally, refer to `tiesc_ethphyInit` API for the EtherCAT specific configurations to be done for the PHY.
The ESC Reg 0x110 DL Status shows the out port is still connected even if the cable is disconnected, which would cause the SubDevice to no longer return the frames sent by the MainDevice.	MDIO_USER_PHY_SEL_REG (offset 0x2484) register is not configured correctly.	MDIO_USER_PHY_SEL_REG (offset 0x2484) needs to be configured to enable the link change interrupt (bit6). Additionally, the corresponding link status determination (bit7) is to be programmed for MLINK/MDIO based determination (MLINK for EnhancedLink and MDIO for otherwise). For the Beckhoff Demo, this configuration is done within tiesc_ethphyInit() API.
Link and the auto-negotiation is complete from PHY Register Status but not able to scan using MainDevice. No link detection on ESC DL Status Register.	TI ESC is not receiving the EtherCAT frames.	Make sure RX Frame counter (ESC Register 0x0E00 and 0x0E04) is getting incremented to make sure frames are being received by the TI ESC (Firmware)
	Incorrect MDIO API (MDIO_phyRegWrite) used to write to the etended PHY Registers.	This function is intended to be used with the IEEE standard PHY registers only. Use the MDIO_phyExtRegWrite API to write into registers above the standard PHY registers (above offset 32h)
The EtherCAT Error counters (ESC Register 0x0300 to 0x0303) are incrementing from time to time.	EtherCAT MainDevice may be sending out Error frames.	Monitor the wireshark logs for any error frames from the EtherCAT MainDevice. Additionally, try with another MainDevice and observe the behavior.
	MainDevice PC NIC may be sending out error frames and the ESC may be processing it	Make sure DL Control (ESC Register 0x0100) is configured correctly. If Bit0 is set then non-EtherCAT frames will be destroyed. Otherwise the frames are forwarded without processing.
EtherCAT SubDevice configured correctly but TwinCAt not able to scan for the Device.	TwinCAT is not configured correctly to detect for the TI EtherCAT SubDevice.	Follow Creating TwinCAT Project to add ESI file and installing EtherCAt driver for the TwinCAT port.

References

Module	Location		TRM Reference/Register Description	Description
Module	ICSSG0 Instance	ICSSG1 Instance	TRM Reference/Register Description	Description
PRU_ICSSG_CFG	0x30026000	0x300A6000	Section 6.4.14.9	PRU_ICSSG_CFG is the main configuration interface for the subsystem
PRU_IEP_IEP	0x3002E000	0x300AE000	Section 6.4.14.9	PRU_IEP_IEP handles precise timing needed for industrial protocols
PRU_MII_RT_MII_RT	0x30032000	0x300B2000	Section 6.4.14.11	PRU_MII_RT_MII_RT manages the actual Ethernet frame handling
PRU_MDIO_MDIO	0x30032400	0x300B2400	Section 6.4.14.10	PRU_MDIO_MDIO deals with PHY layer configuration
EtherCAT ESC Register Space	0x30010000	0x30090000	TI EtherCAT SubDevice Controller Register List	EtherCAT ESC Register Space contains all EtherCAT-specific functionality

EtherCAT Related E2E Queries

Refer to EtherCAT related E2E posts for previously answered queries on EtherCAT.

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