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AM243x MCU+ SDK
09.02.00
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72 #define DDR_ECC_1B_ERROR (0U)
73 #define DDR_ECC_2B_ERROR (1U)
74 #define DDR_ECC_ERR_ALL (2U)
uint32_t ddrEccEnd1
Definition: ddr/v0/ddr.h:91
uint32_t ddrEccStart2
Definition: ddr/v0/ddr.h:93
uint16_t ddrssCtlRegCount
Definition: ddr/v0/ddr.h:118
uintptr_t doublebitErrorAddress
Definition: ddr/v0/ddr.h:137
Emif ECC Error Information structure.
Definition: ddr/v0/ddr.h:135
uint16_t * ddrssPhyRegNum
Definition: ddr/v0/ddr.h:116
uint32_t ddrEccStart0
Definition: ddr/v0/ddr.h:87
uint32_t * ddrssPhyReg
Definition: ddr/v0/ddr.h:112
uint16_t ddrssPhyRegCount
Definition: ddr/v0/ddr.h:120
void DDR_Params_init(DDR_Params *prms)
Set default values to DDR_Params.
void DDR_enableInlineECC(uint8_t enableFlag)
Enable/Disable DDR inline ECC.
uintptr_t singlebitErrorAddress
Definition: ddr/v0/ddr.h:136
DDR Inline ECC region The structure specifies the DDR inline ECC region start and End address.
Definition: ddr/v0/ddr.h:86
uint64_t clk2Freq
Definition: ddr/v0/ddr.h:108
uint32_t * ddrssPhyIndepReg
Definition: ddr/v0/ddr.h:111
uint8_t enableEccFlag
Definition: ddr/v0/ddr.h:124
uint16_t ddrssPhyIndepRegCount
Definition: ddr/v0/ddr.h:119
uint8_t fshcount
Definition: ddr/v0/ddr.h:122
int32_t DDR_getECCErrorInfo(DDR_ECCErrorInfo *ECCErrorInfo)
Get ECC error status.
uint16_t * ddrssPhyIndepRegNum
Definition: ddr/v0/ddr.h:115
int32_t DDR_clearECCError(uint8_t errorType)
Clear ECC errors for DDR.
int32_t DDR_init(DDR_Params *prms)
DDR4 Initialization function.
uint64_t clk1Freq
Definition: ddr/v0/ddr.h:107
DDR config structure.
Definition: ddr/v0/ddr.h:106
uint32_t ddrEccEnd2
Definition: ddr/v0/ddr.h:94
uint16_t * ddrssCtlRegNum
Definition: ddr/v0/ddr.h:114
DDR_EccRegion * eccRegion
Definition: ddr/v0/ddr.h:125
uint32_t singlebitErrorCount
Definition: ddr/v0/ddr.h:138
uint32_t ddrEccStart1
Definition: ddr/v0/ddr.h:90
uint32_t ddrEccEnd0
Definition: ddr/v0/ddr.h:88
uint32_t * ddrssCtlReg
Definition: ddr/v0/ddr.h:110