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AM263x MCU+ SDK
09.01.00
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Go to the documentation of this file.
64 #include <drivers/hw_include/hw_types.h>
65 #include <drivers/hw_include/cslr_soc.h>
67 #include <drivers/hw_include/cslr_eqep.h>
80 #define EQEP_CONFIG_QUADRATURE (0x0000U)
81 #define EQEP_CONFIG_CLOCK_DIR (0x4000U)
83 #define EQEP_CONFIG_UP_COUNT (0x8000U)
85 #define EQEP_CONFIG_DOWN_COUNT (0xC000U)
92 #define EQEP_CONFIG_2X_RESOLUTION (0x0000U)
93 #define EQEP_CONFIG_1X_RESOLUTION (0x0800U)
100 #define EQEP_CONFIG_NO_SWAP (0x0000U)
101 #define EQEP_CONFIG_SWAP (0x0400U)
116 #define EQEP_COMPARE_NO_SYNC_OUT (0x0000U)
117 #define EQEP_COMPARE_IDX_SYNC_OUT (0x2000U)
119 #define EQEP_COMPARE_STROBE_SYNC_OUT (0x3000U)
126 #define EQEP_COMPARE_NO_SHADOW (0x0000U)
127 #define EQEP_COMPARE_LOAD_ON_ZERO (0x8000U)
129 #define EQEP_COMPARE_LOAD_ON_MATCH (0xC000U)
139 #define EQEP_INT_GLOBAL (0x0001U)
140 #define EQEP_INT_POS_CNT_ERROR (0x0002U)
141 #define EQEP_INT_PHASE_ERROR (0x0004U)
142 #define EQEP_INT_DIR_CHANGE (0x0008U)
143 #define EQEP_INT_WATCHDOG (0x0010U)
144 #define EQEP_INT_UNDERFLOW (0x0020U)
145 #define EQEP_INT_OVERFLOW (0x0040U)
146 #define EQEP_INT_POS_COMP_READY (0x0080U)
147 #define EQEP_INT_POS_COMP_MATCH (0x0100U)
148 #define EQEP_INT_STROBE_EVNT_LATCH (0x0200U)
149 #define EQEP_INT_INDEX_EVNT_LATCH (0x0400U)
150 #define EQEP_INT_UNIT_TIME_OUT (0x0800U)
151 #define EQEP_INT_QMA_ERROR (0x1000U)
159 #define EQEP_STS_UNIT_POS_EVNT (0x0080U)
160 #define EQEP_STS_DIR_ON_1ST_IDX (0x0040U)
162 #define EQEP_STS_DIR_FLAG (0x0020U)
164 #define EQEP_STS_DIR_LATCH (0x0010U)
166 #define EQEP_STS_CAP_OVRFLW_ERROR (0x0008U)
168 #define EQEP_STS_CAP_DIR_ERROR (0x0004U)
170 #define EQEP_STS_1ST_IDX_FLAG (0x0002U)
172 #define EQEP_STS_POS_CNT_ERROR (0x0001U)
184 #define EQEP_LATCH_CNT_READ_BY_CPU (0x0000U)
185 #define EQEP_LATCH_UNIT_TIME_OUT (0x0004U)
191 #define EQEP_LATCH_RISING_STROBE (0x0000U)
192 #define EQEP_LATCH_EDGE_DIR_STROBE (0x0040U)
198 #define EQEP_LATCH_RISING_INDEX (0x0010U)
199 #define EQEP_LATCH_FALLING_INDEX (0x0020U)
200 #define EQEP_LATCH_SW_INDEX_MARKER (0x0030U)
208 #define EQEP_INIT_DO_NOTHING (0x0000U)
214 #define EQEP_INIT_RISING_STROBE (0x0800U)
215 #define EQEP_INIT_EDGE_DIR_STROBE (0x0C00U)
221 #define EQEP_INIT_RISING_INDEX (0x0200U)
222 #define EQEP_INIT_FALLING_INDEX (0x0300U)
394 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
395 (HW_RD_REG16(base + CSL_EQEP_QEPCTL) | CSL_EQEP_QEPCTL_QPEN_MASK));
416 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
417 (HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~CSL_EQEP_QEPCTL_QPEN_MASK));
451 HW_WR_REG16(base + CSL_EQEP_QDECCTL,
452 ((HW_RD_REG16(base + CSL_EQEP_QDECCTL) & ~(CSL_EQEP_QDECCTL_SWAP_MASK |
453 CSL_EQEP_QDECCTL_XCR_MASK | CSL_EQEP_QDECCTL_QSRC_MASK)) | config));
479 uint32_t maxPosition)
484 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
485 ((HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~CSL_EQEP_QEPCTL_PCRM_MASK) |
491 HW_WR_REG32(base + CSL_EQEP_QPOSMAX, maxPosition);
509 static inline uint32_t
515 return(HW_RD_REG32(base + CSL_EQEP_QPOSCNT));
537 HW_WR_REG32(base + CSL_EQEP_QPOSCNT, position);
555 static inline int16_t
563 if((HW_RD_REG16(base + CSL_EQEP_QEPSTS) & CSL_EQEP_QEPSTS_QDF_MASK) != 0U)
605 HW_WR_REG16(base + CSL_EQEP_QEINT,
606 (HW_RD_REG16(base + CSL_EQEP_QEINT) | intFlags));
639 HW_WR_REG16(base + CSL_EQEP_QEINT,
640 (HW_RD_REG16(base + CSL_EQEP_QEINT) & ~intFlags));
668 static inline uint16_t
674 return(HW_RD_REG16(base + CSL_EQEP_QFLG));
711 HW_WR_REG16(base + CSL_EQEP_QCLR, intFlags);
744 HW_WR_REG16(base + CSL_EQEP_QFRC,
745 (HW_RD_REG16(base + CSL_EQEP_QFRC) | intFlags));
767 return((HW_RD_REG16(base + CSL_EQEP_QFLG) & CSL_EQEP_QFLG_PHE_MASK) != 0U);
795 static inline uint16_t
801 return(HW_RD_REG16(base + CSL_EQEP_QEPSTS) & 0x00FFU);
834 HW_WR_REG16(base + CSL_EQEP_QEPSTS, statusFlags);
871 HW_WR_REG16(base + CSL_EQEP_QCAPCTL,
872 ((HW_RD_REG16(base + CSL_EQEP_QCAPCTL) & ~(CSL_EQEP_QCAPCTL_UPPS_MASK |
873 CSL_EQEP_QCAPCTL_CCPS_MASK)) | ((uint16_t)evntPrescale |
874 (uint16_t)capPrescale)));
894 HW_WR_REG16(base + CSL_EQEP_QCAPCTL,
895 (HW_RD_REG16(base + CSL_EQEP_QCAPCTL) | CSL_EQEP_QCAPCTL_CEN_MASK));
915 HW_WR_REG16(base + CSL_EQEP_QCAPCTL,
916 (HW_RD_REG16(base + CSL_EQEP_QCAPCTL) & ~CSL_EQEP_QCAPCTL_CEN_MASK));
931 static inline uint16_t
937 return(HW_RD_REG16(base + CSL_EQEP_QCPRD));
951 static inline uint16_t
957 return(HW_RD_REG16(base + CSL_EQEP_QCTMR));
977 HW_WR_REG16(base + CSL_EQEP_QPOSCTL,
978 (HW_RD_REG16(base + CSL_EQEP_QPOSCTL) | CSL_EQEP_QPOSCTL_PCE_MASK));
999 HW_WR_REG16(base + CSL_EQEP_QPOSCTL,
1000 (HW_RD_REG16(base + CSL_EQEP_QPOSCTL) & ~CSL_EQEP_QPOSCTL_PCE_MASK));
1024 DebugP_assert(cycles <= (CSL_EQEP_QPOSCTL_PCSPW_MASK + 1U));
1029 HW_WR_REG16(base + CSL_EQEP_QPOSCTL,
1030 ((HW_RD_REG16(base + CSL_EQEP_QPOSCTL) &
1031 ~(uint16_t)CSL_EQEP_QPOSCTL_PCSPW_MASK) | (cycles - 1U)));
1054 HW_WR_REG32(base + CSL_EQEP_QUPRD, period);
1077 HW_WR_REG32(base + CSL_EQEP_QUPRD, period);
1082 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
1083 (HW_RD_REG16(base + CSL_EQEP_QEPCTL) | CSL_EQEP_QEPCTL_UTE_MASK));
1104 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
1105 (HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~CSL_EQEP_QEPCTL_UTE_MASK));
1131 HW_WR_REG16(base + CSL_EQEP_QWDPRD, period);
1136 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
1137 (HW_RD_REG16(base + CSL_EQEP_QEPCTL) | CSL_EQEP_QEPCTL_WDE_MASK));
1158 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
1159 (HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~CSL_EQEP_QEPCTL_WDE_MASK));
1180 HW_WR_REG16(base + CSL_EQEP_QWDTMR, value);
1192 static inline uint16_t
1198 return(HW_RD_REG16(base + CSL_EQEP_QWDTMR));
1233 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
1234 ((HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~(CSL_EQEP_QEPCTL_IEI_MASK |
1235 CSL_EQEP_QEPCTL_SEI_MASK)) | initMode));
1265 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
1266 (HW_RD_REG16(base + CSL_EQEP_QEPCTL) | CSL_EQEP_QEPCTL_SWI_MASK));
1270 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
1271 (HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~CSL_EQEP_QEPCTL_SWI_MASK));
1296 HW_WR_REG32(base + CSL_EQEP_QPOSINIT, position);
1335 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
1336 ((HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~(CSL_EQEP_QEPCTL_QCLM_MASK |
1337 CSL_EQEP_QEPCTL_IEL_MASK | CSL_EQEP_QEPCTL_SEL_MASK)) | latchMode));
1354 static inline uint32_t
1360 return(HW_RD_REG32(base + CSL_EQEP_QPOSILAT));
1378 static inline uint32_t
1384 return(HW_RD_REG32(base + CSL_EQEP_QPOSSLAT));
1400 static inline uint32_t
1406 return(HW_RD_REG32(base + CSL_EQEP_QPOSLAT));
1423 static inline uint16_t
1429 return(HW_RD_REG16(base + CSL_EQEP_QCTMRLAT));
1446 static inline uint16_t
1452 return(HW_RD_REG16(base + CSL_EQEP_QCPRDLAT));
1479 HW_WR_REG16(base + CSL_EQEP_QMACTRL,
1480 ((HW_RD_REG16(base + CSL_EQEP_QMACTRL) & ~CSL_EQEP_QMACTRL_MODE_MASK) |
1481 (uint16_t)qmaMode));
1509 HW_WR_REG16(base + CSL_EQEP_QEPSTROBESEL,
1510 ((HW_RD_REG16(base + CSL_EQEP_QEPSTROBESEL) &
1511 ~CSL_EQEP_QEPSTROBESEL_STROBESEL_MASK) | (uint16_t)strobeSrc));
1532 HW_WR_REG16(base + CSL_EQEP_QDECCTL,
1533 (HW_RD_REG16(base + CSL_EQEP_QDECCTL) | CSL_EQEP_QDECCTL_QIDIRE_MASK));
1554 HW_WR_REG16(base + CSL_EQEP_QDECCTL,
1555 (HW_RD_REG16(base + CSL_EQEP_QDECCTL) & ~CSL_EQEP_QDECCTL_QIDIRE_MASK));
1577 HW_WR_REG32(base + CSL_EQEP_QEPSRCSEL,
1578 ((HW_RD_REG32(base + CSL_EQEP_QEPSRCSEL) &
1579 ~(CSL_EQEP_QEPSRCSEL_QEPASEL_MASK | CSL_EQEP_QEPSRCSEL_QEPBSEL_MASK |
1580 CSL_EQEP_QEPSRCSEL_QEPISEL_MASK)) |
1581 ((uint32_t)((uint32_t)(sourceConfig.
sourceA) <<
1582 CSL_EQEP_QEPSRCSEL_QEPASEL_SHIFT) |
1583 (uint32_t)((uint32_t)(sourceConfig.
sourceB) <<
1584 CSL_EQEP_QEPSRCSEL_QEPBSEL_SHIFT) |
1585 (uint32_t)((uint32_t)(sourceConfig.
sourceIndex) <<
1586 CSL_EQEP_QEPSRCSEL_QEPISEL_SHIFT))));
1617 HW_WR_REG16(base + CSL_EQEP_QEPCTL,
1618 ((HW_RD_REG16(base + CSL_EQEP_QEPCTL) &
1619 ~CSL_EQEP_QEPSRCSEL_QEPISEL_SHIFT) |
1620 ((uint16_t)emuMode << CSL_EQEP_QEPCTL_FREE_SOFT_SHIFT)));
1679 bool invertIndex,
bool invertStrobe);
1697 #endif // EQEP_V1_H_
static void EQEP_enableDirectionChangeDuringIndex(uint32_t base)
Definition: eqep/v1/eqep.h:1527
@ EQEP_SOURCE_PWMXBAROUT11
Signal comes from PWM Xbar out 11.
Definition: eqep/v1/eqep.h:327
static uint16_t EQEP_getCapturePeriodLatch(uint32_t base)
Definition: eqep/v1/eqep.h:1447
@ EQEP_CAPTURE_CLK_DIV_32
CAPCLK = SYSCLKOUT/32.
Definition: eqep/v1/eqep.h:255
@ EQEP_SOURCE_PWMXBAROUT23
Signal comes from PWM Xbar out 23.
Definition: eqep/v1/eqep.h:339
@ EQEP_UNIT_POS_EVNT_DIV_2
UPEVNT = QCLK/2.
Definition: eqep/v1/eqep.h:269
@ EQEP_POSITION_RESET_MAX_POS
Reset position on maximum position.
Definition: eqep/v1/eqep.h:235
void EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB, bool invertIndex, bool invertStrobe)
@ EQEP_UNIT_POS_EVNT_DIV_2048
UPEVNT = QCLK/2048.
Definition: eqep/v1/eqep.h:279
static void EQEP_enableModule(uint32_t base)
Definition: eqep/v1/eqep.h:389
static uint32_t EQEP_getPosition(uint32_t base)
Definition: eqep/v1/eqep.h:510
@ EQEP_SOURCE_PWMXBAROUT29
Signal comes from PWM Xbar out 29.
Definition: eqep/v1/eqep.h:345
@ EQEP_SOURCE_PWMXBAROUT8
Signal comes from PWM Xbar out 8.
Definition: eqep/v1/eqep.h:324
static void EQEP_disableCapture(uint32_t base)
Definition: eqep/v1/eqep.h:910
@ EQEP_POSITION_RESET_1ST_IDX
Reset position on the first index pulse.
Definition: eqep/v1/eqep.h:237
static void EQEP_setDecoderConfig(uint32_t base, uint16_t config)
Definition: eqep/v1/eqep.h:446
static void EQEP_setCaptureConfig(uint32_t base, EQEP_CAPCLKPrescale capPrescale, EQEP_UPEVNTPrescale evntPrescale)
Definition: eqep/v1/eqep.h:865
@ EQEP_SOURCE_PWMXBAROUT21
Signal comes from PWM Xbar out 21.
Definition: eqep/v1/eqep.h:337
static void EQEP_setLatchMode(uint32_t base, uint32_t latchMode)
Definition: eqep/v1/eqep.h:1330
static void EQEP_disableCompare(uint32_t base)
Definition: eqep/v1/eqep.h:994
EQEP_StrobeSource
Definition: eqep/v1/eqep.h:289
@ EQEP_CAPTURE_CLK_DIV_2
CAPCLK = SYSCLKOUT/2.
Definition: eqep/v1/eqep.h:251
@ EQEP_SOURCE_PWMXBAROUT9
Signal comes from PWM Xbar out 9.
Definition: eqep/v1/eqep.h:325
static void EQEP_disableInterrupt(uint32_t base, uint16_t intFlags)
Definition: eqep/v1/eqep.h:634
@ EQEP_CAPTURE_CLK_DIV_8
CAPCLK = SYSCLKOUT/8.
Definition: eqep/v1/eqep.h:253
@ EQEP_SOURCE_PWMXBAROUT2
Signal comes from PWM Xbar out 2.
Definition: eqep/v1/eqep.h:318
static void EQEP_setInitialPosition(uint32_t base, uint32_t position)
Definition: eqep/v1/eqep.h:1291
static uint16_t EQEP_getWatchdogTimerValue(uint32_t base)
Definition: eqep/v1/eqep.h:1193
static void EQEP_selectSource(uint32_t base, EQEP_SourceSelect sourceConfig)
Definition: eqep/v1/eqep.h:1572
static void EQEP_disableDirectionChangeDuringIndex(uint32_t base)
Definition: eqep/v1/eqep.h:1549
static void EQEP_loadUnitTimer(uint32_t base, uint32_t period)
Definition: eqep/v1/eqep.h:1049
@ EQEP_SOURCE_PWMXBAROUT16
Signal comes from PWM Xbar out 16.
Definition: eqep/v1/eqep.h:332
static uint16_t EQEP_getCaptureTimerLatch(uint32_t base)
Definition: eqep/v1/eqep.h:1424
@ EQEP_QMA_MODE_BYPASS
QMA module is bypassed.
Definition: eqep/v1/eqep.h:301
EQEP_UPEVNTPrescale
Definition: eqep/v1/eqep.h:267
static void EQEP_setPosition(uint32_t base, uint32_t position)
Definition: eqep/v1/eqep.h:532
EQEP_PositionResetMode
Definition: eqep/v1/eqep.h:231
static void EQEP_enableUnitTimer(uint32_t base, uint32_t period)
Definition: eqep/v1/eqep.h:1072
static void EQEP_enableInterrupt(uint32_t base, uint16_t intFlags)
Definition: eqep/v1/eqep.h:600
static void EQEP_disableUnitTimer(uint32_t base)
Definition: eqep/v1/eqep.h:1099
static void EQEP_disableModule(uint32_t base)
Definition: eqep/v1/eqep.h:411
@ EQEP_SOURCE_PWMXBAROUT4
Signal comes from PWM Xbar out 4.
Definition: eqep/v1/eqep.h:320
EQEP_Source sourceA
Definition: eqep/v1/eqep.h:356
static uint32_t EQEP_getPositionLatch(uint32_t base)
Definition: eqep/v1/eqep.h:1401
EQEP_CAPCLKPrescale
Definition: eqep/v1/eqep.h:249
@ EQEP_STROBE_FROM_GPIO
Strobe signal comes from GPIO.
Definition: eqep/v1/eqep.h:290
@ EQEP_CAPTURE_CLK_DIV_16
CAPCLK = SYSCLKOUT/16.
Definition: eqep/v1/eqep.h:254
@ EQEP_SOURCE_PWMXBAROUT26
Signal comes from PWM Xbar out 26.
Definition: eqep/v1/eqep.h:342
@ EQEP_SOURCE_PWMXBAROUT18
Signal comes from PWM Xbar out 18.
Definition: eqep/v1/eqep.h:334
static uint16_t EQEP_getCapturePeriod(uint32_t base)
Definition: eqep/v1/eqep.h:932
static uint32_t EQEP_getStrobePositionLatch(uint32_t base)
Definition: eqep/v1/eqep.h:1379
@ EQEP_POSITION_RESET_IDX
Reset position on index pulse.
Definition: eqep/v1/eqep.h:233
@ EQEP_UNIT_POS_EVNT_DIV_32
UPEVNT = QCLK/32.
Definition: eqep/v1/eqep.h:273
@ EQEP_CAPTURE_CLK_DIV_128
CAPCLK = SYSCLKOUT/128.
Definition: eqep/v1/eqep.h:257
static void EQEP_forceInterrupt(uint32_t base, uint16_t intFlags)
Definition: eqep/v1/eqep.h:739
@ EQEP_SOURCE_PWMXBAROUT24
Signal comes from PWM Xbar out 24.
Definition: eqep/v1/eqep.h:340
@ EQEP_SOURCE_PWMXBAROUT0
Signal comes from PWM Xbar out 0.
Definition: eqep/v1/eqep.h:316
EQEP_Source sourceB
Definition: eqep/v1/eqep.h:357
static void EQEP_enableCompare(uint32_t base)
Definition: eqep/v1/eqep.h:972
EQEP_Source sourceIndex
Definition: eqep/v1/eqep.h:358
static uint16_t EQEP_getInterruptStatus(uint32_t base)
Definition: eqep/v1/eqep.h:669
@ EQEP_SOURCE_PWMXBAROUT3
Signal comes from PWM Xbar out 3.
Definition: eqep/v1/eqep.h:319
@ EQEP_SOURCE_PWMXBAROUT5
Signal comes from PWM Xbar out 5.
Definition: eqep/v1/eqep.h:321
@ EQEP_SOURCE_PWMXBAROUT15
Signal comes from PWM Xbar out 15.
Definition: eqep/v1/eqep.h:331
static uint16_t EQEP_getCaptureTimer(uint32_t base)
Definition: eqep/v1/eqep.h:952
@ EQEP_CAPTURE_CLK_DIV_1
CAPCLK = SYSCLKOUT/1.
Definition: eqep/v1/eqep.h:250
static void EQEP_clearInterruptStatus(uint32_t base, uint16_t intFlags)
Definition: eqep/v1/eqep.h:706
EQEP_Source
Definition: eqep/v1/eqep.h:313
static void EQEP_disableWatchdog(uint32_t base)
Definition: eqep/v1/eqep.h:1153
@ EQEP_SOURCE_PWMXBAROUT6
Signal comes from PWM Xbar out 6.
Definition: eqep/v1/eqep.h:322
static void EQEP_setStrobeSource(uint32_t base, EQEP_StrobeSource strobeSrc)
Definition: eqep/v1/eqep.h:1504
static void EQEP_setPositionCounterConfig(uint32_t base, EQEP_PositionResetMode mode, uint32_t maxPosition)
Definition: eqep/v1/eqep.h:478
@ EQEP_UNIT_POS_EVNT_DIV_8
UPEVNT = QCLK/8.
Definition: eqep/v1/eqep.h:271
@ EQEP_SOURCE_PWMXBAROUT12
Signal comes from PWM Xbar out 12.
Definition: eqep/v1/eqep.h:328
@ EQEP_SOURCE_ZERO
Signal is 0.
Definition: eqep/v1/eqep.h:314
@ EQEP_UNIT_POS_EVNT_DIV_4
UPEVNT = QCLK/4.
Definition: eqep/v1/eqep.h:270
static void EQEP_clearStatus(uint32_t base, uint16_t statusFlags)
Definition: eqep/v1/eqep.h:829
static uint16_t EQEP_getStatus(uint32_t base)
Definition: eqep/v1/eqep.h:796
@ EQEP_SOURCE_PWMXBAROUT27
Signal comes from PWM Xbar out 27.
Definition: eqep/v1/eqep.h:343
@ EQEP_SOURCE_DEVICE_PIN
Signal comes from Device Pin.
Definition: eqep/v1/eqep.h:315
@ EQEP_SOURCE_PWMXBAROUT10
Signal comes from PWM Xbar out 10.
Definition: eqep/v1/eqep.h:326
static uint32_t EQEP_getIndexPositionLatch(uint32_t base)
Definition: eqep/v1/eqep.h:1355
@ EQEP_SOURCE_PWMXBAROUT22
Signal comes from PWM Xbar out 22.
Definition: eqep/v1/eqep.h:338
EQEP_EmulationMode
Definition: eqep/v1/eqep.h:368
static void EQEP_enableWatchdog(uint32_t base, uint16_t period)
Definition: eqep/v1/eqep.h:1126
static void EQEP_setSWPositionInit(uint32_t base, bool initialize)
Definition: eqep/v1/eqep.h:1258
@ EQEP_QMA_MODE_2
QMA mode-2 operation is selected.
Definition: eqep/v1/eqep.h:303
static int16_t EQEP_getDirection(uint32_t base)
Definition: eqep/v1/eqep.h:556
@ EQEP_UNIT_POS_EVNT_DIV_512
UPEVNT = QCLK/512.
Definition: eqep/v1/eqep.h:277
static void EQEP_setEmulationMode(uint32_t base, EQEP_EmulationMode emuMode)
Definition: eqep/v1/eqep.h:1612
static void EQEP_setQMAModuleMode(uint32_t base, EQEP_QMAMode qmaMode)
Definition: eqep/v1/eqep.h:1474
@ EQEP_UNIT_POS_EVNT_DIV_1024
UPEVNT = QCLK/1024.
Definition: eqep/v1/eqep.h:278
Definition: eqep/v1/eqep.h:355
static void EQEP_enableCapture(uint32_t base)
Definition: eqep/v1/eqep.h:889
static bool EQEP_getError(uint32_t base)
Definition: eqep/v1/eqep.h:762
@ EQEP_EMULATIONMODE_STOPATROLLOVER
Counters stop at period rollover.
Definition: eqep/v1/eqep.h:370
@ EQEP_SOURCE_PWMXBAROUT14
Signal comes from PWM Xbar out 14.
Definition: eqep/v1/eqep.h:330
EQEP_QMAMode
Definition: eqep/v1/eqep.h:300
@ EQEP_UNIT_POS_EVNT_DIV_64
UPEVNT = QCLK/64.
Definition: eqep/v1/eqep.h:274
@ EQEP_SOURCE_PWMXBAROUT19
Signal comes from PWM Xbar out 19.
Definition: eqep/v1/eqep.h:335
@ EQEP_SOURCE_PWMXBAROUT25
Signal comes from PWM Xbar out 25.
Definition: eqep/v1/eqep.h:341
void EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue, uint16_t cycles)
@ EQEP_EMULATIONMODE_STOPIMMEDIATELY
Counters stop immediately.
Definition: eqep/v1/eqep.h:369
@ EQEP_SOURCE_PWMXBAROUT28
Signal comes from PWM Xbar out 28.
Definition: eqep/v1/eqep.h:344
@ EQEP_SOURCE_PWMXBAROUT13
Signal comes from PWM Xbar out 13.
Definition: eqep/v1/eqep.h:329
static void EQEP_setWatchdogTimerValue(uint32_t base, uint16_t value)
Definition: eqep/v1/eqep.h:1175
@ EQEP_SOURCE_PWMXBAROUT7
Signal comes from PWM Xbar out 7.
Definition: eqep/v1/eqep.h:323
@ EQEP_CAPTURE_CLK_DIV_4
CAPCLK = SYSCLKOUT/4.
Definition: eqep/v1/eqep.h:252
static void EQEP_setPositionInitMode(uint32_t base, uint16_t initMode)
Definition: eqep/v1/eqep.h:1228
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:177
@ EQEP_QMA_MODE_1
QMA mode-1 operation is selected.
Definition: eqep/v1/eqep.h:302
@ EQEP_UNIT_POS_EVNT_DIV_16
UPEVNT = QCLK/16.
Definition: eqep/v1/eqep.h:272
static void EQEP_setComparePulseWidth(uint32_t base, uint16_t cycles)
Definition: eqep/v1/eqep.h:1019
@ EQEP_CAPTURE_CLK_DIV_64
CAPCLK = SYSCLKOUT/64.
Definition: eqep/v1/eqep.h:256
@ EQEP_SOURCE_PWMXBAROUT1
Signal comes from PWM Xbar out 1.
Definition: eqep/v1/eqep.h:317
@ EQEP_UNIT_POS_EVNT_DIV_128
UPEVNT = QCLK/128.
Definition: eqep/v1/eqep.h:275
@ EQEP_SOURCE_PWMXBAROUT17
Signal comes from PWM Xbar out 17.
Definition: eqep/v1/eqep.h:333
@ EQEP_UNIT_POS_EVNT_DIV_256
UPEVNT = QCLK/256.
Definition: eqep/v1/eqep.h:276
@ EQEP_EMULATIONMODE_RUNFREE
Counter unaffected by suspend.
Definition: eqep/v1/eqep.h:371
@ EQEP_UNIT_POS_EVNT_DIV_1
UPEVNT = QCLK/1.
Definition: eqep/v1/eqep.h:268
@ EQEP_POSITION_RESET_UNIT_TIME_OUT
Reset position on a unit time event.
Definition: eqep/v1/eqep.h:239
@ EQEP_SOURCE_PWMXBAROUT20
Signal comes from PWM Xbar out 20.
Definition: eqep/v1/eqep.h:336