64 #include <drivers/hw_include/cslr_cmpss.h>
65 #include <drivers/hw_include/cslr_soc.h>
66 #include <drivers/hw_include/hw_types.h>
75 #define CMPSS_HICMP_CTL_M (CSL_CMPSSA_COMPCTL_COMPHSOURCE_MASK | \
76 CSL_CMPSSA_COMPCTL_COMPHINV_MASK | \
77 CSL_CMPSSA_COMPCTL_ASYNCHEN_MASK)
79 #define CMPSS_LOCMP_CTL_M (CSL_CMPSSA_COMPCTL_COMPLSOURCE_MASK | \
80 CSL_CMPSSA_COMPCTL_COMPLINV_MASK | \
81 CSL_CMPSSA_COMPCTL_ASYNCLEN_MASK)
93 #define CMPSS_INSRC_DAC (0x0000U)
94 #define CMPSS_INSRC_PIN (0x0001U)
101 #define CMPSS_INSRC_PIN_INL (0x0000U)
102 #define CMPSS_INSRC_PIN_INH (0x0001U)
109 #define CMPSS_INV_INVERTED (0x0002U)
110 #define CMPSS_OR_ASYNC_OUT_W_FILT (0x0040U)
123 #define CMPSS_TRIPOUT_ASYNC_COMP (0x0000U)
124 #define CMPSS_TRIPOUT_SYNC_COMP (0x0010U)
126 #define CMPSS_TRIPOUT_FILTER (0x0020U)
128 #define CMPSS_TRIPOUT_LATCH (0x0030U)
135 #define CMPSS_TRIP_ASYNC_COMP (0x0000U)
136 #define CMPSS_TRIP_SYNC_COMP (0x0004U)
138 #define CMPSS_TRIP_FILTER (0x0008U)
140 #define CMPSS_TRIP_LATCH (0x000CU)
149 #define CMPSS_STS_HI_FILTOUT (0x0001U)
150 #define CMPSS_STS_HI_LATCHFILTOUT (0x0002U)
152 #define CMPSS_STS_LO_FILTOUT (0x0100U)
154 #define CMPSS_STS_LO_LATCHFILTOUT (0x0200U)
166 #define CMPSS_DACVAL_SYSCLK (0x0000U)
167 #define CMPSS_DACVAL_PWMSYNC (0x0080U)
174 #define CMPSS_DACREF_VDDA (0x0000U)
175 #define CMPSS_DACREF_VDAC (0x0020U)
182 #define CMPSS_DACSRC_SHDW (0x0000U)
183 #define CMPSS_DACSRC_RAMP (0x0001U)
208 HW_WR_REG16((base + CSL_CMPSSA_COMPCTL),
209 HW_RD_REG16(base + CSL_CMPSSA_COMPCTL) |
210 CSL_CMPSSA_COMPCTL_COMPDACE_MASK);
230 HW_WR_REG16((base + CSL_CMPSSA_COMPCTL),
231 HW_RD_REG16(base + CSL_CMPSSA_COMPCTL) &
232 ~CSL_CMPSSA_COMPCTL_COMPDACE_MASK);
270 HW_WR_REG16((base + CSL_CMPSSA_COMPCTL),
309 HW_WR_REG16((base + CSL_CMPSSA_COMPCTL),
348 HW_WR_REG16((base + CSL_CMPSSA_COMPCTL),
349 (HW_RD_REG16(base + CSL_CMPSSA_COMPCTL) &
350 ~(CSL_CMPSSA_COMPCTL_CTRIPOUTHSEL_MASK |
351 CSL_CMPSSA_COMPCTL_CTRIPHSEL_MASK)) | config);
388 HW_WR_REG16((base + CSL_CMPSSA_COMPCTL),
389 (HW_RD_REG16(base + CSL_CMPSSA_COMPCTL) &
390 ~(CSL_CMPSSA_COMPCTL_CTRIPOUTLSEL_MASK |
391 CSL_CMPSSA_COMPCTL_CTRIPLSEL_MASK)) | (config << 8U));
412 static inline uint16_t
418 return(HW_RD_REG16(base + CSL_CMPSSA_COMPSTS));
460 HW_WR_REG16((base + CSL_CMPSSA_COMPDACCTL),
461 (HW_RD_REG16(base + CSL_CMPSSA_COMPDACCTL) &
462 ~(CSL_CMPSSA_COMPDACCTL_SWLOADSEL_MASK |
463 CSL_CMPSSA_COMPDACCTL_SELREF_MASK |
464 CSL_CMPSSA_COMPDACCTL_DACSOURCE_MASK)) | config);
490 HW_WR_REG16((base + CSL_CMPSSA_DACHVALS), value);
516 HW_WR_REG16((base + CSL_CMPSSA_DACLVALS), value);
540 HW_WR_REG16((base + CSL_CMPSSA_CTRIPHFILCTL),
541 HW_RD_REG16(base + CSL_CMPSSA_CTRIPHFILCTL) |
542 CSL_CMPSSA_CTRIPHFILCTL_FILINIT_MASK);
566 HW_WR_REG16((base + CSL_CMPSSA_CTRIPLFILCTL),
567 HW_RD_REG16(base + CSL_CMPSSA_CTRIPLFILCTL) |
568 CSL_CMPSSA_CTRIPLFILCTL_FILINIT_MASK);
584 static inline uint16_t
590 return(HW_RD_REG16(base + CSL_CMPSSA_DACHVALA));
606 static inline uint16_t
612 return(HW_RD_REG16(base + CSL_CMPSSA_DACLVALA));
633 HW_WR_REG16((base + CSL_CMPSSA_COMPSTSCLR),
634 HW_RD_REG16(base + CSL_CMPSSA_COMPSTSCLR) |
635 CSL_CMPSSA_COMPSTSCLR_HLATCHCLR_MASK);
656 HW_WR_REG16((base + CSL_CMPSSA_COMPSTSCLR),
657 HW_RD_REG16(base + CSL_CMPSSA_COMPSTSCLR) |
658 CSL_CMPSSA_COMPSTSCLR_LLATCHCLR_MASK);
680 HW_WR_REG16((base + CSL_CMPSSA_RAMPMAXREFS), value);
693 static inline uint16_t
699 return(HW_RD_REG16(base + CSL_CMPSSA_RAMPMAXREFA));
721 HW_WR_REG16((base + CSL_CMPSSA_RAMPDECVALS), value);
734 static inline uint16_t
740 return(HW_RD_REG16(base + CSL_CMPSSA_RAMPDECVALA));
765 HW_WR_REG16((base + CSL_CMPSSA_RAMPDLYS), value);
778 static inline uint16_t
784 return(HW_RD_REG16(base + CSL_CMPSSA_RAMPDLYA));
814 HW_WR_REG16((base + CSL_CMPSSA_COMPDACCTL),
815 (HW_RD_REG16(base + CSL_CMPSSA_COMPDACCTL) &
816 ~CSL_CMPSSA_COMPDACCTL_BLANKSOURCE_MASK) | (((pwmBlankSrc - 1U)&0xFU) <<
817 CSL_CMPSSA_COMPDACCTL_BLANKSOURCE_SHIFT));
820 HW_WR_REG16((base + CSL_CMPSSA_COMPDACCTL2),
821 (HW_RD_REG16(base + CSL_CMPSSA_COMPDACCTL2) &
822 ~CSL_CMPSSA_COMPDACCTL2_BLANKSOURCEUSEL_MASK) | ((((pwmBlankSrc-1U)>>4U) <<
823 CSL_CMPSSA_COMPDACCTL2_BLANKSOURCEUSEL_SHIFT) &
824 CSL_CMPSSA_COMPDACCTL2_BLANKSOURCEUSEL_MASK));
845 HW_WR_REG16((base + CSL_CMPSSA_COMPDACCTL),
846 HW_RD_REG16(base + CSL_CMPSSA_COMPDACCTL) |
847 CSL_CMPSSA_COMPDACCTL_BLANKEN_MASK);
868 HW_WR_REG16((base + CSL_CMPSSA_COMPDACCTL),
869 HW_RD_REG16(base + CSL_CMPSSA_COMPDACCTL) &
870 ~CSL_CMPSSA_COMPDACCTL_BLANKEN_MASK);
887 HW_WR_REG16((base + CSL_CMPSSA_COMPDACCTL2),
888 HW_RD_REG16(base + CSL_CMPSSA_COMPDACCTL2) |
889 ((0x1U<<CSL_CMPSSA_COMPDACCTL2_DEENABLE_SHIFT) &
890 CSL_CMPSSA_COMPDACCTL2_DEENABLE_MASK));
908 HW_WR_REG16((base + CSL_CMPSSA_COMPDACCTL2),
909 HW_RD_REG16(base + CSL_CMPSSA_COMPDACCTL2) &
910 ~((0x1U<<CSL_CMPSSA_COMPDACCTL2_DEENABLE_SHIFT) &
911 CSL_CMPSSA_COMPDACCTL2_DEENABLE_MASK));
929 HW_WR_REG16((base + CSL_CMPSSA_COMPDACCTL2),
930 (HW_RD_REG16(base + CSL_CMPSSA_COMPDACCTL2) &
931 ~CSL_CMPSSA_COMPDACCTL2_DEACTIVESEL_MASK) |
932 ((deactivesel << CSL_CMPSSA_COMPDACCTL2_DEACTIVESEL_SHIFT) &
933 CSL_CMPSSA_COMPDACCTL2_DEACTIVESEL_MASK));
953 HW_WR_REG16((base + CSL_CMPSSA_DACHVALS2),
954 dacval & CSL_CMPSSA_DACHVALS2_DACVAL_MASK);
974 HW_WR_REG16((base + CSL_CMPSSA_DACLVALS2),
975 dacval & CSL_CMPSSA_DACLVALS2_DACVAL_MASK);
1003 HW_WR_REG16((base + CSL_CMPSSA_CONFIG1),
1004 (HW_RD_REG16(base + CSL_CMPSSA_CONFIG1) &
1005 (~CSL_CMPSSA_CONFIG1_COMPHHYS_MASK)) |
1006 (CSL_CMPSSA_CONFIG1_COMPHHYS_MASK &
1007 (value << CSL_CMPSSA_CONFIG1_COMPHHYS_SHIFT))
1036 HW_WR_REG16((base + CSL_CMPSSA_CONFIG1),
1037 (HW_RD_REG16(base + CSL_CMPSSA_CONFIG1) &
1038 (~CSL_CMPSSA_CONFIG1_COMPLHYS_MASK)) |
1039 (CSL_CMPSSA_CONFIG1_COMPLHYS_MASK &
1040 (value << CSL_CMPSSA_CONFIG1_COMPLHYS_SHIFT))
1091 uint16_t sampleWindow, uint16_t threshold);
1139 uint16_t sampleWindow, uint16_t threshold);
1202 uint16_t delayVal, uint16_t pwmSyncSrc,
bool useRampValShdw);
1220 #endif // CMPSS_V0_H_