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AM263x MCU+ SDK
09.01.00
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Go to the documentation of this file.
63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
66 #include <drivers/hw_include/cslr_adc.h>
76 #define ADC_EVT_TRIPHI (0x0001U)
77 #define ADC_EVT_TRIPLO (0x0002U)
78 #define ADC_EVT_ZERO (0x0004U)
86 #define ADC_FORCE_SOC0 (0x0001U)
87 #define ADC_FORCE_SOC1 (0x0002U)
88 #define ADC_FORCE_SOC2 (0x0004U)
89 #define ADC_FORCE_SOC3 (0x0008U)
90 #define ADC_FORCE_SOC4 (0x0010U)
91 #define ADC_FORCE_SOC5 (0x0020U)
92 #define ADC_FORCE_SOC6 (0x0040U)
93 #define ADC_FORCE_SOC7 (0x0080U)
94 #define ADC_FORCE_SOC8 (0x0100U)
95 #define ADC_FORCE_SOC9 (0x0200U)
96 #define ADC_FORCE_SOC10 (0x0400U)
97 #define ADC_FORCE_SOC11 (0x0800U)
98 #define ADC_FORCE_SOC12 (0x1000U)
99 #define ADC_FORCE_SOC13 (0x2000U)
100 #define ADC_FORCE_SOC14 (0x4000U)
101 #define ADC_FORCE_SOC15 (0x8000U)
388 #define ADC_ADCSOCxCTL_STEP (CSL_ADC_ADCSOC1CTL - CSL_ADC_ADCSOC0CTL)
389 #define ADC_ADCINTSELxNy_STEP (CSL_ADC_ADCINTSEL3N4 - CSL_ADC_ADCINTSEL1N2)
391 #define ADC_ADCPPBx_STEP (CSL_ADC_ADCPPB2CONFIG - CSL_ADC_ADCPPB1CONFIG)
393 #define ADC_ADCPPBTRIP_MASK ((uint32_t)CSL_ADC_ADCPPB1TRIPHI_LIMITHI_MASK \
395 | (uint32_t)CSL_ADC_ADCPPB1TRIPHI_HSIGN_MASK)
396 #define ADC_RESULT_ADCPPBxRESULT_STEP (CSL_ADC_RESULT_ADCPPB2RESULT -\
398 CSL_ADC_RESULT_ADCPPB1RESULT)
399 #define ADC_RESULT_ADCRESULTx_STEP (CSL_ADC_RESULT_ADCRESULT1 - \
401 CSL_ADC_RESULT_ADCRESULT0)
432 HW_WR_REG16(base + CSL_ADC_ADCCTL2,
433 ((HW_RD_REG16(base + CSL_ADC_ADCCTL2) &
434 ~CSL_ADC_ADCCTL2_PRESCALE_MASK) | (uint16_t)clkPrescale));
483 DebugP_assert((sampleWindow >= 16U) && (sampleWindow <= 512U));
488 ctlRegAddr = base + CSL_ADC_ADCSOC0CTL +
494 HW_WR_REG32(ctlRegAddr,
495 (((uint32_t)channel << CSL_ADC_ADCSOC0CTL_CHSEL_SHIFT) |
496 ((uint32_t)trigger << CSL_ADC_ADCSOC0CTL_TRIGSEL_SHIFT) |
497 (sampleWindow - 1U)));
536 shiftVal = (uint16_t)socNumber << 1U;
542 HW_WR_REG32(base + CSL_ADC_ADCINTSOCSEL1,
543 ((HW_RD_REG32(base + CSL_ADC_ADCINTSOCSEL1) &
544 ~((uint32_t)CSL_ADC_ADCINTSOCSEL1_SOC0_MASK << shiftVal)) |
545 ((uint32_t)trigger << shiftVal)));
571 HW_WR_REG16(base + CSL_ADC_ADCCTL1,
572 ((HW_RD_REG16(base + CSL_ADC_ADCCTL1) &
573 ~CSL_ADC_ADCCTL1_INTPULSEPOS_MASK) |
574 ((uint16_t)pulseMode<<CSL_ADC_ADCCTL1_INTPULSEPOS_SHIFT)));
602 HW_WR_REG16(base + CSL_ADC_ADCINTCYCLE, cycleOffset);
626 HW_WR_REG16(base + CSL_ADC_ADCCTL1,
627 (HW_RD_REG16(base + CSL_ADC_ADCCTL1) | CSL_ADC_ADCCTL1_ADCPWDNZ_MASK));
647 HW_WR_REG16(base + CSL_ADC_ADCCTL1,
648 (HW_RD_REG16(base + CSL_ADC_ADCCTL1) &
649 ~CSL_ADC_ADCCTL1_ADCPWDNZ_MASK));
673 HW_WR_REG16(base + CSL_ADC_ADCSOCFRC1, ((uint16_t)1U << (uint16_t)socNumber));
703 HW_WR_REG16(base + CSL_ADC_ADCSOCFRC1, socMask);
730 return((HW_RD_REG16(base + CSL_ADC_ADCINTFLG) &
731 (1U << (uint16_t)adcIntNum)) != 0U);
758 HW_WR_REG16(base + CSL_ADC_ADCINTFLGCLR, ((uint16_t)1U << (uint16_t)adcIntNum));
786 return((HW_RD_REG16(base + CSL_ADC_ADCINTOVF) &
787 (1U << (uint16_t)adcIntNum)) != 0U);
814 HW_WR_REG16(base + CSL_ADC_ADCINTOVFCLR, ((uint16_t)1U << (uint16_t)adcIntNum));
836 static inline uint16_t
842 return(HW_RD_REG16(resultBase + CSL_ADC_RESULT_ADCRESULT0 +
865 return((HW_RD_REG16(base + CSL_ADC_ADCCTL1) &
866 CSL_ADC_ADCCTL1_ADCBSY_MASK) != 0U);
904 regValue = (uint16_t)trigger |
905 ((burstSize - 1U) << CSL_ADC_ADCBURSTCTL_BURSTSIZE_SHIFT);
907 HW_WR_REG16(base + CSL_ADC_ADCBURSTCTL,
908 ((HW_RD_REG16(base + CSL_ADC_ADCBURSTCTL) &
909 ~((uint16_t)CSL_ADC_ADCBURSTCTL_BURSTTRIGSEL_MASK |
910 CSL_ADC_ADCBURSTCTL_BURSTSIZE_MASK)) | regValue));
934 HW_WR_REG16(base + CSL_ADC_ADCBURSTCTL,
935 (HW_RD_REG16(base + CSL_ADC_ADCBURSTCTL) |
936 CSL_ADC_ADCBURSTCTL_BURSTEN_MASK));
958 HW_WR_REG16(base + CSL_ADC_ADCBURSTCTL,
959 (HW_RD_REG16(base + CSL_ADC_ADCBURSTCTL) &
960 ~CSL_ADC_ADCBURSTCTL_BURSTEN_MASK));
996 HW_WR_REG16(base + CSL_ADC_ADCSOCPRICTL,
997 ((HW_RD_REG16(base + CSL_ADC_ADCSOCPRICTL) &
998 ~CSL_ADC_ADCSOCPRICTL_SOCPRIORITY_MASK) | (uint16_t)priMode));
1036 CSL_ADC_ADCPPB1CONFIG;
1041 HW_WR_REG16(base + ppbOffset,
1042 ((HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1CONFIG_CONFIG_MASK) |
1043 ((uint16_t)socNumber & CSL_ADC_ADCPPB1CONFIG_CONFIG_MASK)));
1072 HW_WR_REG16(base + CSL_ADC_ADCEVTSEL,
1073 (HW_RD_REG16(base + CSL_ADC_ADCEVTSEL) |
1074 (evtFlags << ((uint16_t)ppbNumber * 4U))));
1102 HW_WR_REG16(base + CSL_ADC_ADCEVTSEL,
1103 (HW_RD_REG16(base + CSL_ADC_ADCEVTSEL) &
1104 ~(evtFlags << ((uint16_t)ppbNumber * 4U))));
1134 HW_WR_REG16(base + CSL_ADC_ADCEVTINTSEL,
1135 (HW_RD_REG16(base + CSL_ADC_ADCEVTINTSEL) |
1136 (intFlags << ((uint16_t)ppbNumber * 4U))));
1166 HW_WR_REG16(base + CSL_ADC_ADCEVTINTSEL,
1167 (HW_RD_REG16(base + CSL_ADC_ADCEVTINTSEL) &
1168 ~(intFlags << ((uint16_t)ppbNumber * 4U))));
1183 static inline uint16_t
1189 return((HW_RD_REG16(base + CSL_ADC_ADCEVTSTAT) >>
1190 ((uint16_t)ppbNumber * 4U)) & 0x7U);
1220 HW_WR_REG16(base + CSL_ADC_ADCEVTCLR,
1221 (HW_RD_REG16(base + CSL_ADC_ADCEVTCLR) |
1222 (evtFlags << ((uint16_t)ppbNumber * 4U))));
1242 static inline int32_t
1248 return((int32_t)HW_RD_REG32(resultBase + CSL_ADC_RESULT_ADCPPB1RESULT +
1266 static inline uint16_t
1275 CSL_ADC_ADCPPB1STAMP;
1280 return(HW_RD_REG16(base + ppbOffset) & CSL_ADC_ADCPPB1STAMP_DLYSTAMP_MASK);
1319 CSL_ADC_ADCPPB1OFFCAL;
1324 HW_WR_REG16(base + ppbOffset,
1325 ((HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1OFFCAL_OFFCAL_MASK) |
1326 ((uint16_t)offset & CSL_ADC_ADCPPB1OFFCAL_OFFCAL_MASK)));
1362 CSL_ADC_ADCPPB1OFFREF;
1367 HW_WR_REG16(base + ppbOffset, offset);
1396 CSL_ADC_ADCPPB1CONFIG;
1401 HW_WR_REG16(base + ppbOffset,
1402 (HW_RD_REG16(base + ppbOffset) |
1403 CSL_ADC_ADCPPB1CONFIG_TWOSCOMPEN_MASK));
1432 CSL_ADC_ADCPPB1CONFIG;
1437 HW_WR_REG16(base + ppbOffset,
1438 (HW_RD_REG16(base + ppbOffset) &
1439 ~CSL_ADC_ADCPPB1CONFIG_TWOSCOMPEN_MASK));
1466 CSL_ADC_ADCPPB1CONFIG;
1471 HW_WR_REG16(base + ppbOffset,
1472 (HW_RD_REG16(base + ppbOffset) | CSL_ADC_ADCPPB1CONFIG_CBCEN_MASK));
1498 CSL_ADC_ADCPPB1CONFIG;
1503 HW_WR_REG16(base + ppbOffset,
1504 (HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1CONFIG_CBCEN_MASK));
1528 uint32_t intRegAddr;
1535 intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
1537 shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
1542 HW_WR_REG16(intRegAddr,
1543 HW_RD_REG16(intRegAddr) |
1544 (CSL_ADC_ADCINTSEL1N2_INT1E_MASK << shiftVal));
1568 uint32_t intRegAddr;
1575 intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
1577 shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
1582 HW_WR_REG16(intRegAddr,
1583 HW_RD_REG16(intRegAddr) &
1584 ~(CSL_ADC_ADCINTSEL1N2_INT1E_MASK << shiftVal));
1612 uint32_t intRegAddr;
1619 intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
1621 shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
1626 HW_WR_REG16(intRegAddr,
1627 ((HW_RD_REG16(intRegAddr) &
1628 ~(CSL_ADC_ADCINTSEL1N2_INT1SEL_MASK << shiftVal)) |
1629 ((uint16_t)socNumber << shiftVal)));
1654 uint32_t intRegAddr;
1661 intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
1663 shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
1668 HW_WR_REG16(intRegAddr,
1669 HW_RD_REG16(intRegAddr) |
1670 (CSL_ADC_ADCINTSEL1N2_INT1CONT_MASK << shiftVal));
1696 uint32_t intRegAddr;
1703 intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
1705 shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
1710 HW_WR_REG16(intRegAddr,
1711 HW_RD_REG16(intRegAddr) &
1712 ~(CSL_ADC_ADCINTSEL1N2_INT1CONT_MASK << shiftVal));
1765 int32_t tripHiLimit, int32_t tripLoLimit);
@ ADC_SOC_NUMBER7
SOC/EOC number 7.
Definition: adc/v1/adc.h:331
ADC_Resolution
Definition: adc/v1/adc.h:135
@ ADC_SOC_NUMBER15
SOC/EOC number 15.
Definition: adc/v1/adc.h:339
@ ADC_SOC_NUMBER9
SOC/EOC number 9.
Definition: adc/v1/adc.h:333
@ ADC_CH_ADCIN3_ADCIN2
differential, ADCIN3 and ADCIN2
Definition: adc/v1/adc.h:262
@ ADC_TRIGGER_EPWM26_SOCA
ePWM26, ADCSOCA
Definition: adc/v1/adc.h:218
@ ADC_TRIGGER_EPWM3_SOCA
ePWM3, ADCSOCA
Definition: adc/v1/adc.h:172
#define ADC_RESULT_ADCPPBxRESULT_STEP
Register offset difference between 2 ADCPPBxRESULT registers.
Definition: adc/v1/adc.h:397
@ ADC_CLK_DIV_2_0
ADCCLK = (input clock) / 2.0.
Definition: adc/v1/adc.h:112
static void ADC_disablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t intFlags)
Definition: adc/v1/adc.h:1155
@ ADC_TRIGGER_EPWM14_SOCB
ePWM14, ADCSOCB
Definition: adc/v1/adc.h:195
static void ADC_disablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v1/adc.h:1424
ADC_ClkPrescale
Definition: adc/v1/adc.h:110
@ ADC_INT_NUMBER3
ADCINT3 Interrupt.
Definition: adc/v1/adc.h:295
@ ADC_TRIGGER_ECAP8_SOCEVT
eCAP8, SOCEVT
Definition: adc/v1/adc.h:238
@ ADC_TRIGGER_EPWM24_SOCA
ePWM24, ADCSOCA
Definition: adc/v1/adc.h:214
@ ADC_CH_ADCIN2
single-ended, ADCIN2
Definition: adc/v1/adc.h:253
@ ADC_TRIGGER_EPWM23_SOCA
ePWM23, ADCSOCA
Definition: adc/v1/adc.h:212
@ ADC_TRIGGER_EPWM11_SOCB
ePWM11, ADCSOCB
Definition: adc/v1/adc.h:189
static uint16_t ADC_getPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v1/adc.h:1184
@ ADC_PULSE_END_OF_CONV
Occurs at the end of the conversion.
Definition: adc/v1/adc.h:279
static void ADC_clearInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v1/adc.h:809
static void ADC_enableBurstMode(uint32_t base)
Definition: adc/v1/adc.h:929
@ ADC_CH_ADCIN0
single-ended, ADCIN0
Definition: adc/v1/adc.h:251
@ ADC_SOC_NUMBER8
SOC/EOC number 8.
Definition: adc/v1/adc.h:332
@ ADC_TRIGGER_EPWM9_SOCB
ePWM9, ADCSOCB
Definition: adc/v1/adc.h:185
@ ADC_TRIGGER_EPWM16_SOCA
ePWM16, ADCSOCA
Definition: adc/v1/adc.h:198
@ ADC_SOC_NUMBER1
SOC/EOC number 1.
Definition: adc/v1/adc.h:325
@ ADC_PRI_THRU_SOC5_HIPRI
SOC 0-5 hi pri, others in round robin.
Definition: adc/v1/adc.h:369
static void ADC_disablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
Definition: adc/v1/adc.h:1092
@ ADC_INT_SOC_TRIGGER_ADCINT1
ADCINT1 will trigger the SOC.
Definition: adc/v1/adc.h:351
@ ADC_TRIGGER_EPWM2_SOCB
ePWM2, ADCSOCB
Definition: adc/v1/adc.h:171
@ ADC_INT_NUMBER4
ADCINT4 Interrupt.
Definition: adc/v1/adc.h:296
@ ADC_TRIGGER_EPWM27_SOCA
ePWM27, ADCSOCA
Definition: adc/v1/adc.h:220
@ ADC_SOC_NUMBER11
SOC/EOC number 11.
Definition: adc/v1/adc.h:335
#define ADC_ADCINTSELxNy_STEP
Register offset difference between 2 ADCINTSELxNy registers.
Definition: adc/v1/adc.h:390
@ ADC_INT_SOC_TRIGGER_NONE
No ADCINT will trigger the SOC.
Definition: adc/v1/adc.h:350
@ ADC_PRI_THRU_SOC14_HIPRI
SOC 0-14 hi pri, SOC15 in round robin.
Definition: adc/v1/adc.h:378
@ ADC_MODE_SINGLE_ENDED
Sample on single pin with VREFLO.
Definition: adc/v1/adc.h:147
@ ADC_TRIGGER_EPWM28_SOCA
ePWM28, ADCSOCA
Definition: adc/v1/adc.h:222
@ ADC_TRIGGER_EPWM6_SOCB
ePWM6, ADCSOCB
Definition: adc/v1/adc.h:179
@ ADC_TRIGGER_EPWM12_SOCB
ePWM12, ADCSOCB
Definition: adc/v1/adc.h:191
@ ADC_TRIGGER_EPWM4_SOCA
ePWM4, ADCSOCA
Definition: adc/v1/adc.h:174
static void ADC_enablePPBEventCBCClear(uint32_t base, uint32_t ppbNumber)
Definition: adc/v1/adc.h:1458
static void ADC_forceMultipleSOC(uint32_t base, uint16_t socMask)
Definition: adc/v1/adc.h:698
@ ADC_CLK_DIV_4_0
ADCCLK = (input clock) / 4.0.
Definition: adc/v1/adc.h:116
static void ADC_disablePPBEventCBCClear(uint32_t base, uint32_t ppbNumber)
Definition: adc/v1/adc.h:1490
ADC_PulseMode
Definition: adc/v1/adc.h:275
@ ADC_TRIGGER_EPWM29_SOCB
ePWM29, ADCSOCB
Definition: adc/v1/adc.h:225
@ ADC_TRIGGER_ECAP3_SOCEVT
eCAP3, SOCEVT
Definition: adc/v1/adc.h:233
#define ADC_ADCSOCxCTL_STEP
Defines used by the driver.
Definition: adc/v1/adc.h:388
@ ADC_TRIGGER_EPWM27_SOCB
ePWM27, ADCSOCB
Definition: adc/v1/adc.h:221
static void ADC_setInterruptPulseMode(uint32_t base, ADC_PulseMode pulseMode)
Definition: adc/v1/adc.h:566
static void ADC_setInterruptSource(uint32_t base, ADC_IntNumber adcIntNum, ADC_SOCNumber socNumber)
Definition: adc/v1/adc.h:1609
@ ADC_PRI_THRU_SOC10_HIPRI
SOC 0-10 hi pri, others in round robin.
Definition: adc/v1/adc.h:374
@ ADC_TRIGGER_ECAP1_SOCEVT
eCAP1, SOCEVT
Definition: adc/v1/adc.h:231
@ ADC_TRIGGER_EPWM30_SOCB
ePWM30, ADCSOCB
Definition: adc/v1/adc.h:227
@ ADC_PRI_THRU_SOC11_HIPRI
SOC 0-11 hi pri, others in round robin.
Definition: adc/v1/adc.h:375
@ ADC_PRI_THRU_SOC3_HIPRI
SOC 0-3 hi pri, others in round robin.
Definition: adc/v1/adc.h:367
ADC_Trigger
Definition: adc/v1/adc.h:159
@ ADC_CLK_DIV_5_0
ADCCLK = (input clock) / 5.0.
Definition: adc/v1/adc.h:118
@ ADC_PRI_THRU_SOC4_HIPRI
SOC 0-4 hi pri, others in round robin.
Definition: adc/v1/adc.h:368
@ ADC_TRIGGER_EPWM2_SOCA
ePWM2, ADCSOCA
Definition: adc/v1/adc.h:170
@ ADC_PRI_THRU_SOC7_HIPRI
SOC 0-7 hi pri, others in round robin.
Definition: adc/v1/adc.h:371
@ ADC_TRIGGER_EPWM31_SOCA
ePWM31, ADCSOCA
Definition: adc/v1/adc.h:228
ADC_SOCNumber
Definition: adc/v1/adc.h:323
@ ADC_CH_ADCIN1
single-ended, ADCIN1
Definition: adc/v1/adc.h:252
static void ADC_setBurstModeConfig(uint32_t base, ADC_Trigger trigger, uint16_t burstSize)
Definition: adc/v1/adc.h:891
static void ADC_enableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v1/adc.h:1652
@ ADC_INT_NUMBER1
ADCINT1 Interrupt.
Definition: adc/v1/adc.h:293
@ ADC_TRIGGER_EPWM7_SOCB
ePWM7, ADCSOCB
Definition: adc/v1/adc.h:181
static void ADC_setInterruptSOCTrigger(uint32_t base, ADC_SOCNumber socNumber, ADC_IntSOCTrigger trigger)
Definition: adc/v1/adc.h:528
@ ADC_CH_CAL0
single-ended, CAL0
Definition: adc/v1/adc.h:257
@ ADC_TRIGGER_RTI1
RTI Timer 1.
Definition: adc/v1/adc.h:162
@ ADC_SOC_NUMBER3
SOC/EOC number 3.
Definition: adc/v1/adc.h:327
static bool ADC_getInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v1/adc.h:725
static uint16_t ADC_getPPBDelayTimeStamp(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v1/adc.h:1267
@ ADC_SOC_NUMBER10
SOC/EOC number 10.
Definition: adc/v1/adc.h:334
@ ADC_TRIGGER_EPWM12_SOCA
ePWM12, ADCSOCA
Definition: adc/v1/adc.h:190
@ ADC_TRIGGER_EPWM9_SOCA
ePWM9, ADCSOCA
Definition: adc/v1/adc.h:184
@ ADC_TRIGGER_EPWM15_SOCB
ePWM15, ADCSOCB
Definition: adc/v1/adc.h:197
static void ADC_enablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
Definition: adc/v1/adc.h:1062
@ ADC_TRIGGER_EPWM17_SOCB
ePWM17, ADCSOCB
Definition: adc/v1/adc.h:201
@ ADC_PRI_THRU_SOC13_HIPRI
SOC 0-13 hi pri, others in round robin.
Definition: adc/v1/adc.h:377
@ ADC_CLK_DIV_7_5
ADCCLK = (input clock) / 7.5.
Definition: adc/v1/adc.h:123
@ ADC_TRIGGER_EPWM29_SOCA
ePWM29, ADCSOCA
Definition: adc/v1/adc.h:224
@ ADC_PRI_THRU_SOC6_HIPRI
SOC 0-6 hi pri, others in round robin.
Definition: adc/v1/adc.h:370
@ ADC_TRIGGER_ECAP7_SOCEVT
eCAP7, SOCEVT
Definition: adc/v1/adc.h:237
static void ADC_setInterruptCycleOffset(uint32_t base, uint16_t cycleOffset)
Definition: adc/v1/adc.h:597
static void ADC_setPPBCalibrationOffset(uint32_t base, ADC_PPBNumber ppbNumber, int16_t offset)
Definition: adc/v1/adc.h:1310
@ ADC_TRIGGER_EPWM5_SOCB
ePWM5, ADCSOCB
Definition: adc/v1/adc.h:177
@ ADC_CLK_DIV_6_0
ADCCLK = (input clock) / 6.0.
Definition: adc/v1/adc.h:120
@ ADC_TRIGGER_EPWM25_SOCA
ePWM25, ADCSOCA
Definition: adc/v1/adc.h:216
ADC_PPBNumber
Definition: adc/v1/adc.h:306
@ ADC_CLK_DIV_8_5
ADCCLK = (input clock) / 8.5.
Definition: adc/v1/adc.h:125
@ ADC_TRIGGER_EPWM22_SOCB
ePWM22, ADCSOCB
Definition: adc/v1/adc.h:211
@ ADC_PRI_ALL_ROUND_ROBIN
Round robin mode is used for all.
Definition: adc/v1/adc.h:363
@ ADC_TRIGGER_EPWM17_SOCA
ePWM17, ADCSOCA
Definition: adc/v1/adc.h:200
@ ADC_TRIGGER_ECAP9_SOCEVT
eCAP9, SOCEVT
Definition: adc/v1/adc.h:239
@ ADC_SOC_NUMBER0
SOC/EOC number 0.
Definition: adc/v1/adc.h:324
ADC_IntSOCTrigger
Definition: adc/v1/adc.h:349
void ADC_setMode(uint32_t base, ADC_Resolution resolution, ADC_SignalMode signalMode)
@ ADC_TRIGGER_EPWM28_SOCB
ePWM28, ADCSOCB
Definition: adc/v1/adc.h:223
@ ADC_PPB_NUMBER3
Post-processing block 3.
Definition: adc/v1/adc.h:309
static void ADC_clearInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v1/adc.h:753
ADC_PriorityMode
Definition: adc/v1/adc.h:362
@ ADC_CLK_DIV_8_0
ADCCLK = (input clock) / 8.0.
Definition: adc/v1/adc.h:124
@ ADC_PRI_THRU_SOC8_HIPRI
SOC 0-8 hi pri, others in round robin.
Definition: adc/v1/adc.h:372
@ ADC_TRIGGER_EPWM1_SOCB
ePWM1, ADCSOCB
Definition: adc/v1/adc.h:169
@ ADC_SOC_NUMBER5
SOC/EOC number 5.
Definition: adc/v1/adc.h:329
@ ADC_CLK_DIV_6_5
ADCCLK = (input clock) / 6.5.
Definition: adc/v1/adc.h:121
@ ADC_INT_SOC_TRIGGER_ADCINT2
ADCINT2 will trigger the SOC.
Definition: adc/v1/adc.h:352
@ ADC_TRIGGER_EPWM6_SOCA
ePWM6, ADCSOCA
Definition: adc/v1/adc.h:178
static void ADC_enableConverter(uint32_t base)
Definition: adc/v1/adc.h:621
@ ADC_PPB_NUMBER4
Post-processing block 4.
Definition: adc/v1/adc.h:310
@ ADC_TRIGGER_EPWM13_SOCB
ePWM13, ADCSOCB
Definition: adc/v1/adc.h:193
static uint16_t ADC_readResult(uint32_t resultBase, ADC_SOCNumber socNumber)
Definition: adc/v1/adc.h:837
@ ADC_CH_ADCIN5_ADCIN4
differential, ADCIN5 and ADCIN4
Definition: adc/v1/adc.h:264
@ ADC_TRIGGER_ECAP6_SOCEVT
eCAP6, SOCEVT
Definition: adc/v1/adc.h:236
@ ADC_SOC_NUMBER13
SOC/EOC number 13.
Definition: adc/v1/adc.h:337
@ ADC_TRIGGER_ECAP2_SOCEVT
eCAP2, SOCEVT
Definition: adc/v1/adc.h:232
@ ADC_CLK_DIV_3_5
ADCCLK = (input clock) / 3.5.
Definition: adc/v1/adc.h:115
@ ADC_PRI_THRU_SOC9_HIPRI
SOC 0-9 hi pri, others in round robin.
Definition: adc/v1/adc.h:373
@ ADC_CH_ADCIN5
single-ended, ADCIN5
Definition: adc/v1/adc.h:256
@ ADC_TRIGGER_EPWM8_SOCA
ePWM8, ADCSOCA
Definition: adc/v1/adc.h:182
@ ADC_TRIGGER_ECAP5_SOCEVT
eCAP5, SOCEVT
Definition: adc/v1/adc.h:235
static void ADC_enablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v1/adc.h:1388
static void ADC_disableInterrupt(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v1/adc.h:1566
@ ADC_RESOLUTION_12BIT
12-bit conversion resolution
Definition: adc/v1/adc.h:136
static void ADC_setupPPB(uint32_t base, ADC_PPBNumber ppbNumber, ADC_SOCNumber socNumber)
Definition: adc/v1/adc.h:1028
static bool ADC_getInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v1/adc.h:781
@ ADC_PRI_THRU_SOC1_HIPRI
SOC 0-1 hi pri, others in round robin.
Definition: adc/v1/adc.h:365
@ ADC_TRIGGER_EPWM15_SOCA
ePWM15, ADCSOCA
Definition: adc/v1/adc.h:196
static void ADC_forceSOC(uint32_t base, ADC_SOCNumber socNumber)
Definition: adc/v1/adc.h:668
@ ADC_MODE_DIFFERENTIAL
Sample on pair of pins.
Definition: adc/v1/adc.h:148
@ ADC_TRIGGER_EPWM10_SOCB
ePWM10, ADCSOCB
Definition: adc/v1/adc.h:187
static void ADC_disableConverter(uint32_t base)
Definition: adc/v1/adc.h:642
static void ADC_enablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t intFlags)
Definition: adc/v1/adc.h:1123
@ ADC_TRIGGER_EPWM10_SOCA
ePWM10, ADCSOCA
Definition: adc/v1/adc.h:186
@ ADC_PRI_THRU_SOC12_HIPRI
SOC 0-12 hi pri, others in round robin.
Definition: adc/v1/adc.h:376
@ ADC_TRIGGER_EPWM31_SOCB
ePWM31, ADCSOCB
Definition: adc/v1/adc.h:229
@ ADC_CH_ADCIN4
single-ended, ADCIN4
Definition: adc/v1/adc.h:255
@ ADC_CLK_DIV_7_0
ADCCLK = (input clock) / 7.0.
Definition: adc/v1/adc.h:122
@ ADC_TRIGGER_EPWM19_SOCA
ePWM19, ADCSOCA
Definition: adc/v1/adc.h:204
static void ADC_disableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v1/adc.h:1694
@ ADC_TRIGGER_ECAP4_SOCEVT
eCAP4, SOCEVT
Definition: adc/v1/adc.h:234
@ ADC_SOC_NUMBER12
SOC/EOC number 12.
Definition: adc/v1/adc.h:336
@ ADC_TRIGGER_EPWM7_SOCA
ePWM7, ADCSOCA
Definition: adc/v1/adc.h:180
@ ADC_TRIGGER_EPWM16_SOCB
ePWM16, ADCSOCB
Definition: adc/v1/adc.h:199
static void ADC_setPrescaler(uint32_t base, ADC_ClkPrescale clkPrescale)
Definition: adc/v1/adc.h:427
@ ADC_SOC_NUMBER14
SOC/EOC number 14.
Definition: adc/v1/adc.h:338
@ ADC_TRIGGER_EPWM30_SOCA
ePWM30, ADCSOCA
Definition: adc/v1/adc.h:226
@ ADC_PRI_THRU_SOC2_HIPRI
SOC 0-2 hi pri, others in round robin.
Definition: adc/v1/adc.h:366
@ ADC_INT_NUMBER2
ADCINT2 Interrupt.
Definition: adc/v1/adc.h:294
@ ADC_PULSE_END_OF_ACQ_WIN
Occurs at the end of the acquisition window.
Definition: adc/v1/adc.h:277
@ ADC_TRIGGER_ECAP0_SOCEVT
eCAP0, SOCEVT
Definition: adc/v1/adc.h:230
@ ADC_TRIGGER_EPWM18_SOCB
ePWM18, ADCSOCB
Definition: adc/v1/adc.h:203
@ ADC_CH_ADCIN2_ADCIN3
differential, ADCIN2 and ADCIN3
Definition: adc/v1/adc.h:261
void ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, int32_t tripHiLimit, int32_t tripLoLimit)
ADC_SignalMode
Definition: adc/v1/adc.h:146
@ ADC_CH_ADCIN4_ADCIN5
differential, ADCIN4 and ADCIN5
Definition: adc/v1/adc.h:263
@ ADC_TRIGGER_EPWM18_SOCA
ePWM18, ADCSOCA
Definition: adc/v1/adc.h:202
@ ADC_CLK_DIV_1_0
ADCCLK = (input clock) / 1.0.
Definition: adc/v1/adc.h:111
@ ADC_TRIGGER_SW_ONLY
Software only.
Definition: adc/v1/adc.h:160
@ ADC_TRIGGER_INPUT_XBAR_OUT5
InputXBar.Out[5].
Definition: adc/v1/adc.h:165
@ ADC_TRIGGER_EPWM11_SOCA
ePWM11, ADCSOCA
Definition: adc/v1/adc.h:188
static int32_t ADC_readPPBResult(uint32_t resultBase, ADC_PPBNumber ppbNumber)
Definition: adc/v1/adc.h:1243
@ ADC_TRIGGER_EPWM3_SOCB
ePWM3, ADCSOCB
Definition: adc/v1/adc.h:173
@ ADC_PRI_ALL_HIPRI
All priorities based on SOC number.
Definition: adc/v1/adc.h:379
@ ADC_PRI_SOC0_HIPRI
SOC 0 hi pri, others in round robin.
Definition: adc/v1/adc.h:364
@ ADC_TRIGGER_EPWM0_SOCA
ePWM0, ADCSOCA
Definition: adc/v1/adc.h:166
@ ADC_CH_ADCIN0_ADCIN1
differential, ADCIN0 and ADCIN1
Definition: adc/v1/adc.h:259
@ ADC_SOC_NUMBER6
SOC/EOC number 6.
Definition: adc/v1/adc.h:330
static void ADC_enableInterrupt(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v1/adc.h:1526
@ ADC_TRIGGER_EPWM20_SOCB
ePWM20, ADCSOCB
Definition: adc/v1/adc.h:207
@ ADC_TRIGGER_EPWM1_SOCA
ePWM1, ADCSOCA
Definition: adc/v1/adc.h:168
@ ADC_SOC_NUMBER4
SOC/EOC number 4.
Definition: adc/v1/adc.h:328
@ ADC_CH_ADCIN3
single-ended, ADCIN3
Definition: adc/v1/adc.h:254
#define ADC_RESULT_ADCRESULTx_STEP
Register offset difference between 2 ADCRESULTx registers.
Definition: adc/v1/adc.h:400
@ ADC_TRIGGER_RTI2
RTI Timer 2.
Definition: adc/v1/adc.h:163
@ ADC_TRIGGER_EPWM19_SOCB
ePWM19, ADCSOCB
Definition: adc/v1/adc.h:205
@ ADC_TRIGGER_EPWM20_SOCA
ePWM20, ADCSOCA
Definition: adc/v1/adc.h:206
@ ADC_CLK_DIV_3_0
ADCCLK = (input clock) / 3.0.
Definition: adc/v1/adc.h:114
static void ADC_setSOCPriority(uint32_t base, ADC_PriorityMode priMode)
Definition: adc/v1/adc.h:991
@ ADC_TRIGGER_EPWM23_SOCB
ePWM23, ADCSOCB
Definition: adc/v1/adc.h:213
static void ADC_disableBurstMode(uint32_t base)
Definition: adc/v1/adc.h:953
static bool ADC_isBusy(uint32_t base)
Definition: adc/v1/adc.h:860
@ ADC_TRIGGER_RTI3
RTI Timer 3.
Definition: adc/v1/adc.h:164
static void ADC_setPPBReferenceOffset(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t offset)
Definition: adc/v1/adc.h:1353
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:177
@ ADC_CH_ADCIN1_ADCIN0
differential, ADCIN1 and ADCIN0
Definition: adc/v1/adc.h:260
@ ADC_TRIGGER_EPWM21_SOCA
ePWM21, ADCSOCA
Definition: adc/v1/adc.h:208
@ ADC_CLK_DIV_5_5
ADCCLK = (input clock) / 5.5.
Definition: adc/v1/adc.h:119
#define ADC_ADCPPBx_STEP
Register offset difference between 2 ADCPPBxCONFIG registers.
Definition: adc/v1/adc.h:392
@ ADC_TRIGGER_EPWM22_SOCA
ePWM22, ADCSOCA
Definition: adc/v1/adc.h:210
ADC_Channel
Definition: adc/v1/adc.h:250
@ ADC_CH_CAL1
single-ended, CAL1
Definition: adc/v1/adc.h:258
@ ADC_CLK_DIV_4_5
ADCCLK = (input clock) / 4.5.
Definition: adc/v1/adc.h:117
@ ADC_PPB_NUMBER1
Post-processing block 1.
Definition: adc/v1/adc.h:307
@ ADC_TRIGGER_EPWM8_SOCB
ePWM8, ADCSOCB
Definition: adc/v1/adc.h:183
@ ADC_TRIGGER_EPWM0_SOCB
ePWM0, ADCSOCB
Definition: adc/v1/adc.h:167
@ ADC_TRIGGER_EPWM24_SOCB
ePWM24, ADCSOCB
Definition: adc/v1/adc.h:215
@ ADC_CLK_DIV_2_5
ADCCLK = (input clock) / 2.5.
Definition: adc/v1/adc.h:113
ADC_IntNumber
Definition: adc/v1/adc.h:292
@ ADC_CH_CAL0_CAL1
differential, CAL0 and CAL1
Definition: adc/v1/adc.h:265
@ ADC_TRIGGER_EPWM13_SOCA
ePWM13, ADCSOCA
Definition: adc/v1/adc.h:192
@ ADC_TRIGGER_EPWM5_SOCA
ePWM5, ADCSOCA
Definition: adc/v1/adc.h:176
@ ADC_SOC_NUMBER2
SOC/EOC number 2.
Definition: adc/v1/adc.h:326
@ ADC_TRIGGER_EPWM21_SOCB
ePWM21, ADCSOCB
Definition: adc/v1/adc.h:209
@ ADC_TRIGGER_EPWM25_SOCB
ePWM25, ADCSOCB
Definition: adc/v1/adc.h:217
static void ADC_clearPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
Definition: adc/v1/adc.h:1209
@ ADC_TRIGGER_RTI0
RTI Timer 0.
Definition: adc/v1/adc.h:161
@ ADC_TRIGGER_EPWM14_SOCA
ePWM14, ADCSOCA
Definition: adc/v1/adc.h:194
@ ADC_TRIGGER_EPWM26_SOCB
ePWM26, ADCSOCB
Definition: adc/v1/adc.h:219
@ ADC_PPB_NUMBER2
Post-processing block 2.
Definition: adc/v1/adc.h:308
static void ADC_setupSOC(uint32_t base, ADC_SOCNumber socNumber, ADC_Trigger trigger, ADC_Channel channel, uint32_t sampleWindow)
Definition: adc/v1/adc.h:475
@ ADC_TRIGGER_EPWM4_SOCB
ePWM4, ADCSOCB
Definition: adc/v1/adc.h:175