7 #ifndef __MSP430WARE_DMA_H__
8 #define __MSP430WARE_DMA_H__
10 #include "inc/hw_memmap.h"
12 #if defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430_HAS_DMAX_6__)
25 #include "inc/hw_memmap.h"
124 #define DMA_TRIGGERSOURCE_0 (0x00)
125 #define DMA_TRIGGERSOURCE_1 (0x01)
126 #define DMA_TRIGGERSOURCE_2 (0x02)
127 #define DMA_TRIGGERSOURCE_3 (0x03)
128 #define DMA_TRIGGERSOURCE_4 (0x04)
129 #define DMA_TRIGGERSOURCE_5 (0x05)
130 #define DMA_TRIGGERSOURCE_6 (0x06)
131 #define DMA_TRIGGERSOURCE_7 (0x07)
132 #define DMA_TRIGGERSOURCE_8 (0x08)
133 #define DMA_TRIGGERSOURCE_9 (0x09)
134 #define DMA_TRIGGERSOURCE_10 (0x0A)
135 #define DMA_TRIGGERSOURCE_11 (0x0B)
136 #define DMA_TRIGGERSOURCE_12 (0x0C)
137 #define DMA_TRIGGERSOURCE_13 (0x0D)
138 #define DMA_TRIGGERSOURCE_14 (0x0E)
139 #define DMA_TRIGGERSOURCE_15 (0x0F)
140 #define DMA_TRIGGERSOURCE_16 (0x10)
141 #define DMA_TRIGGERSOURCE_17 (0x11)
142 #define DMA_TRIGGERSOURCE_18 (0x12)
143 #define DMA_TRIGGERSOURCE_19 (0x13)
144 #define DMA_TRIGGERSOURCE_20 (0x14)
145 #define DMA_TRIGGERSOURCE_21 (0x15)
146 #define DMA_TRIGGERSOURCE_22 (0x16)
147 #define DMA_TRIGGERSOURCE_23 (0x17)
148 #define DMA_TRIGGERSOURCE_24 (0x18)
149 #define DMA_TRIGGERSOURCE_25 (0x19)
150 #define DMA_TRIGGERSOURCE_26 (0x1A)
151 #define DMA_TRIGGERSOURCE_27 (0x1B)
152 #define DMA_TRIGGERSOURCE_28 (0x1C)
153 #define DMA_TRIGGERSOURCE_29 (0x1D)
154 #define DMA_TRIGGERSOURCE_30 (0x1E)
155 #define DMA_TRIGGERSOURCE_31 (0x1F)
164 #define DMA_TRANSFER_SINGLE (DMADT_0)
165 #define DMA_TRANSFER_BLOCK (DMADT_1)
166 #define DMA_TRANSFER_BURSTBLOCK (DMADT_2)
167 #define DMA_TRANSFER_REPEATED_SINGLE (DMADT_4)
168 #define DMA_TRANSFER_REPEATED_BLOCK (DMADT_5)
169 #define DMA_TRANSFER_REPEATED_BURSTBLOCK (DMADT_6)
182 #define DMA_CHANNEL_0 (0x00)
183 #define DMA_CHANNEL_1 (0x10)
184 #define DMA_CHANNEL_2 (0x20)
185 #define DMA_CHANNEL_3 (0x30)
186 #define DMA_CHANNEL_4 (0x40)
187 #define DMA_CHANNEL_5 (0x50)
188 #define DMA_CHANNEL_6 (0x60)
189 #define DMA_CHANNEL_7 (0x70)
198 #define DMA_TRIGGER_RISINGEDGE (!(DMALEVEL))
199 #define DMA_TRIGGER_HIGH (DMALEVEL)
208 #define DMA_SIZE_SRCWORD_DSTWORD (!(DMASRCBYTE + DMADSTBYTE))
209 #define DMA_SIZE_SRCBYTE_DSTWORD (DMASRCBYTE)
210 #define DMA_SIZE_SRCWORD_DSTBYTE (DMADSTBYTE)
211 #define DMA_SIZE_SRCBYTE_DSTBYTE (DMASRCBYTE + DMADSTBYTE)
219 #define DMA_DIRECTION_UNCHANGED (DMASRCINCR_0)
220 #define DMA_DIRECTION_DECREMENT (DMASRCINCR_2)
221 #define DMA_DIRECTION_INCREMENT (DMASRCINCR_3)
229 #define DMA_INT_INACTIVE (0x0)
230 #define DMA_INT_ACTIVE (DMAIFG)
238 #define DMA_NOTABORTED (0x0)
239 #define DMA_ABORTED (DMAABORT)
295 uint16_t transferSize);
357 uint16_t directionSelect);
394 uint16_t directionSelect);
716 #endif // __MSP430WARE_DMA_H__
uint8_t transferUnitSelect
Definition: dma.h:104
void DMA_startTransfer(uint8_t channelSelect)
Starts a transfer if using the default trigger source selected in initialization. ...
Definition: dma.c:91
void DMA_enableRoundRobinPriority(void)
Enables Round Robin prioritization.
Definition: dma.c:136
void DMA_enableNMIAbort(void)
Enables a NMI to interrupt a DMA transfer.
Definition: dma.c:146
uint16_t DMA_getTransferSize(uint8_t channelSelect)
Gets the amount of transfers for the selected DMA channel.
Definition: dma.c:49
void DMA_setTransferSize(uint8_t channelSelect, uint16_t transferSize)
Sets the specified amount of transfers for the selected DMA channel.
Definition: dma.c:42
uint16_t transferModeSelect
Definition: dma.h:57
void DMA_disableTransfers(uint8_t channelSelect)
Disables transfers from being triggered.
Definition: dma.c:86
void DMA_disableRoundRobinPriority(void)
Disables Round Robin prioritization.
Definition: dma.c:141
uint16_t DMA_getInterruptStatus(uint8_t channelSelect)
Returns the status of the interrupt flag for the selected channel.
Definition: dma.c:106
uint8_t channelSelect
Definition: dma.h:42
void DMA_enableTransfers(uint8_t channelSelect)
Enables transfers to be triggered.
Definition: dma.c:81
void DMA_enableTransferDuringReadModifyWrite(void)
Enables the DMA to stop the CPU during a Read-Modify-Write Operation to start a transfer.
Definition: dma.c:131
void DMA_clearNMIAbort(uint8_t channelSelect)
Clears the status of the NMIAbort to proceed with transfers for the selected channel.
Definition: dma.c:121
void DMA_setDstAddress(uint8_t channelSelect, uint32_t dstAddress, uint16_t directionSelect)
Sets the destination address and the direction that the destination address will move after a transfe...
Definition: dma.c:68
uint8_t triggerSourceSelect
Definition: dma.h:97
void DMA_setSrcAddress(uint8_t channelSelect, uint32_t srcAddress, uint16_t directionSelect)
Sets source address and the direction that the source address will move after a transfer.
Definition: dma.c:55
void DMA_init(DMA_initParam *param)
Initializes the specified DMA channel.
Definition: dma.c:21
void DMA_disableTransferDuringReadModifyWrite(void)
Disables the DMA from stopping the CPU during a Read-Modify-Write Operation to start a transfer...
Definition: dma.c:126
void DMA_enableInterrupt(uint8_t channelSelect)
Enables the DMA interrupt for the selected channel.
Definition: dma.c:96
uint8_t triggerTypeSelect
Definition: dma.h:112
void DMA_disableNMIAbort(void)
Disables any NMI from interrupting a DMA transfer.
Definition: dma.c:151
uint16_t transferSize
Definition: dma.h:61
uint16_t DMA_getNMIAbortStatus(uint8_t channelSelect)
Returns the status of the NMIAbort for the selected channel.
Definition: dma.c:116
Used in the DMA_init() function as the param parameter.
Definition: dma.h:31
void DMA_clearInterrupt(uint8_t channelSelect)
Clears the interrupt flag for the selected channel.
Definition: dma.c:111
void DMA_disableInterrupt(uint8_t channelSelect)
Disables the DMA interrupt for the selected channel.
Definition: dma.c:101