MSP430 Driver Library  1.80.00.18
CCS/msp430f5xx_6xxgeneric.h
Go to the documentation of this file.
1 /* ============================================================================ */
2 /* Copyright (c) 2013, Texas Instruments Incorporated */
3 /* All rights reserved. */
4 /* */
5 /* Redistribution and use in source and binary forms, with or without */
6 /* modification, are permitted provided that the following conditions */
7 /* are met: */
8 /* */
9 /* * Redistributions of source code must retain the above copyright */
10 /* notice, this list of conditions and the following disclaimer. */
11 /* */
12 /* * Redistributions in binary form must reproduce the above copyright */
13 /* notice, this list of conditions and the following disclaimer in the */
14 /* documentation and/or other materials provided with the distribution. */
15 /* */
16 /* * Neither the name of Texas Instruments Incorporated nor the names of */
17 /* its contributors may be used to endorse or promote products derived */
18 /* from this software without specific prior written permission. */
19 /* */
20 /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
21 /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
22 /* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
23 /* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
24 /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
25 /* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
26 /* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
27 /* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
28 /* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
29 /* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
30 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
31 /* ============================================================================ */
32 
33 /********************************************************************
34 *
35 * Standard register and bit definitions for the Texas Instruments
36 * MSP430 microcontroller.
37 *
38 * This file supports assembler and C development for
39 * MSP430F5XX_F6XXGENERIC device.
40 *
41 * Texas Instruments, Version 1.0
42 *
43 * Rev. 1.0, Setup
44 *
45 *
46 ********************************************************************/
47 
48 #ifndef __msp430F5XX_F6XXGENERIC
49 #define __msp430F5XX_F6XXGENERIC
50 
51 //#define __MSP430_HEADER_VERSION__ 1125
52 
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
56 
57 
58 /*----------------------------------------------------------------------------*/
59 /* PERIPHERAL FILE MAP */
60 /*----------------------------------------------------------------------------*/
61 
62 #ifndef SFR_8BIT
63 /* External references resolved by a device-specific linker command file */
64 #define SFR_8BIT(address) extern volatile unsigned char address
65 #define SFR_16BIT(address) extern volatile unsigned int address
66 //#define SFR_20BIT(address) extern volatile unsigned int address
67 typedef void (* __SFR_FARPTR)();
68 #define SFR_20BIT(address) extern __SFR_FARPTR address
69 #define SFR_32BIT(address) extern volatile unsigned long address
70 
71 #endif
72 
73 
74 /************************************************************
75 * STANDARD BITS
76 ************************************************************/
77 
78 #define BIT0 (0x0001)
79 #define BIT1 (0x0002)
80 #define BIT2 (0x0004)
81 #define BIT3 (0x0008)
82 #define BIT4 (0x0010)
83 #define BIT5 (0x0020)
84 #define BIT6 (0x0040)
85 #define BIT7 (0x0080)
86 #define BIT8 (0x0100)
87 #define BIT9 (0x0200)
88 #define BITA (0x0400)
89 #define BITB (0x0800)
90 #define BITC (0x1000)
91 #define BITD (0x2000)
92 #define BITE (0x4000)
93 #define BITF (0x8000)
94 
95 /************************************************************
96 * STATUS REGISTER BITS
97 ************************************************************/
98 
99 #define C (0x0001)
100 #define Z (0x0002)
101 #define N (0x0004)
102 #define V (0x0100)
103 #define GIE (0x0008)
104 #define CPUOFF (0x0010)
105 #define OSCOFF (0x0020)
106 #define SCG0 (0x0040)
107 #define SCG1 (0x0080)
108 
109 /* Low Power Modes coded with Bits 4-7 in SR */
110 
111 #ifdef __ASM_HEADER__ /* Begin #defines for assembler */
112 #define LPM0 (CPUOFF)
113 #define LPM1 (SCG0+CPUOFF)
114 #define LPM2 (SCG1+CPUOFF)
115 #define LPM3 (SCG1+SCG0+CPUOFF)
116 #define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
117 /* End #defines for assembler */
118 
119 #else /* Begin #defines for C */
120 #define LPM0_bits (CPUOFF)
121 #define LPM1_bits (SCG0+CPUOFF)
122 #define LPM2_bits (SCG1+CPUOFF)
123 #define LPM3_bits (SCG1+SCG0+CPUOFF)
124 #define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
125 
126 #include "in430.h"
127 #include <intrinsics.h>
128 
129 #if __MSP430_HEADER_VERSION__ < 1107
130  #define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
131  #define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
132  #define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
133  #define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
134  #define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
135  #define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
136  #define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
137  #define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
138  #define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
139  #define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
140 #else
141  #define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
142  #define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
143  #define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
144  #define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
145  #define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
146  #define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
147  #define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
148  #define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
149  #define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
150  #define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
151 #endif
152 
153 #endif /* End #defines for C */
154 
155 /************************************************************
156 * CPU
157 ************************************************************/
158 #define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */
159 
160 #if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \
161  || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \
162  || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \
163  || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__)
164  #define __MSP430_HAS_TxA7__
165 #endif
166 #if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \
167  || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__)
168  #define __MSP430_HAS_TxB7__
169 #endif
170 #if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \
171  || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__)
172  #define __MSP430_HAS_TxD7__
173 #endif
174 #if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__)
175  #define __MSP430_HAS_USCI_Ax__
176 #endif
177 #if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__)
178  #define __MSP430_HAS_USCI_Bx__
179 #endif
180 #if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__)
181  #define __MSP430_HAS_EUSCI_Ax__
182 #endif
183 #if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__)
184  #define __MSP430_HAS_EUSCI_Bx__
185 #endif
186 #ifdef __MSP430_HAS_EUSCI_B0__
187  #define __MSP430_HAS_EUSCI_Bx__
188 #endif
189 
190 /************************************************************
191 * ADC10_A
192 ************************************************************/
193 #ifdef __MSP430_HAS_ADC10_A__ /* Definition to show that Module is available */
194 
195 #define OFS_ADC10CTL0 (0x0000) /* ADC10 Control 0 */
196 #define OFS_ADC10CTL0_L OFS_ADC10CTL0
197 #define OFS_ADC10CTL0_H OFS_ADC10CTL0+1
198 #define OFS_ADC10CTL1 (0x0002) /* ADC10 Control 1 */
199 #define OFS_ADC10CTL1_L OFS_ADC10CTL1
200 #define OFS_ADC10CTL1_H OFS_ADC10CTL1+1
201 #define OFS_ADC10CTL2 (0x0004) /* ADC10 Control 2 */
202 #define OFS_ADC10CTL2_L OFS_ADC10CTL2
203 #define OFS_ADC10CTL2_H OFS_ADC10CTL2+1
204 #define OFS_ADC10LO (0x0006) /* ADC10 Window Comparator High Threshold */
205 #define OFS_ADC10LO_L OFS_ADC10LO
206 #define OFS_ADC10LO_H OFS_ADC10LO+1
207 #define OFS_ADC10HI (0x0008) /* ADC10 Window Comparator High Threshold */
208 #define OFS_ADC10HI_L OFS_ADC10HI
209 #define OFS_ADC10HI_H OFS_ADC10HI+1
210 #define OFS_ADC10MCTL0 (0x000A) /* ADC10 Memory Control 0 */
211 #define OFS_ADC10MCTL0_L OFS_ADC10MCTL0
212 #define OFS_ADC10MCTL0_H OFS_ADC10MCTL0+1
213 #define OFS_ADC10MEM0 (0x0012) /* ADC10 Conversion Memory 0 */
214 #define OFS_ADC10MEM0_L OFS_ADC10MEM0
215 #define OFS_ADC10MEM0_H OFS_ADC10MEM0+1
216 #define OFS_ADC10IE (0x001A) /* ADC10 Interrupt Enable */
217 #define OFS_ADC10IE_L OFS_ADC10IE
218 #define OFS_ADC10IE_H OFS_ADC10IE+1
219 #define OFS_ADC10IFG (0x001C) /* ADC10 Interrupt Flag */
220 #define OFS_ADC10IFG_L OFS_ADC10IFG
221 #define OFS_ADC10IFG_H OFS_ADC10IFG+1
222 #define OFS_ADC10IV (0x001E) /* ADC10 Interrupt Vector Word */
223 #define OFS_ADC10IV_L OFS_ADC10IV
224 #define OFS_ADC10IV_H OFS_ADC10IV+1
225 
226 /* ADC10CTL0 Control Bits */
227 #define ADC10SC (0x0001) /* ADC10 Start Conversion */
228 #define ADC10ENC (0x0002) /* ADC10 Enable Conversion */
229 #define ADC10ON (0x0010) /* ADC10 On/enable */
230 #define ADC10MSC (0x0080) /* ADC10 Multiple SampleConversion */
231 #define ADC10SHT0 (0x0100) /* ADC10 Sample Hold Select Bit: 0 */
232 #define ADC10SHT1 (0x0200) /* ADC10 Sample Hold Select Bit: 1 */
233 #define ADC10SHT2 (0x0400) /* ADC10 Sample Hold Select Bit: 2 */
234 #define ADC10SHT3 (0x0800) /* ADC10 Sample Hold Select Bit: 3 */
235 
236 /* ADC10CTL0 Control Bits */
237 #define ADC10SC_L (0x0001) /* ADC10 Start Conversion */
238 #define ADC10ENC_L (0x0002) /* ADC10 Enable Conversion */
239 #define ADC10ON_L (0x0010) /* ADC10 On/enable */
240 #define ADC10MSC_L (0x0080) /* ADC10 Multiple SampleConversion */
241 
242 /* ADC10CTL0 Control Bits */
243 #define ADC10SHT0_H (0x0001) /* ADC10 Sample Hold Select Bit: 0 */
244 #define ADC10SHT1_H (0x0002) /* ADC10 Sample Hold Select Bit: 1 */
245 #define ADC10SHT2_H (0x0004) /* ADC10 Sample Hold Select Bit: 2 */
246 #define ADC10SHT3_H (0x0008) /* ADC10 Sample Hold Select Bit: 3 */
247 
248 #define ADC10SHT_0 (0*0x100u) /* ADC10 Sample Hold Select 0 */
249 #define ADC10SHT_1 (1*0x100u) /* ADC10 Sample Hold Select 1 */
250 #define ADC10SHT_2 (2*0x100u) /* ADC10 Sample Hold Select 2 */
251 #define ADC10SHT_3 (3*0x100u) /* ADC10 Sample Hold Select 3 */
252 #define ADC10SHT_4 (4*0x100u) /* ADC10 Sample Hold Select 4 */
253 #define ADC10SHT_5 (5*0x100u) /* ADC10 Sample Hold Select 5 */
254 #define ADC10SHT_6 (6*0x100u) /* ADC10 Sample Hold Select 6 */
255 #define ADC10SHT_7 (7*0x100u) /* ADC10 Sample Hold Select 7 */
256 #define ADC10SHT_8 (8*0x100u) /* ADC10 Sample Hold Select 8 */
257 #define ADC10SHT_9 (9*0x100u) /* ADC10 Sample Hold Select 9 */
258 #define ADC10SHT_10 (10*0x100u) /* ADC10 Sample Hold Select 10 */
259 #define ADC10SHT_11 (11*0x100u) /* ADC10 Sample Hold Select 11 */
260 #define ADC10SHT_12 (12*0x100u) /* ADC10 Sample Hold Select 12 */
261 #define ADC10SHT_13 (13*0x100u) /* ADC10 Sample Hold Select 13 */
262 #define ADC10SHT_14 (14*0x100u) /* ADC10 Sample Hold Select 14 */
263 #define ADC10SHT_15 (15*0x100u) /* ADC10 Sample Hold Select 15 */
264 
265 /* ADC10CTL1 Control Bits */
266 #define ADC10BUSY (0x0001) /* ADC10 Busy */
267 #define ADC10CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */
268 #define ADC10CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */
269 #define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select 0 */
270 #define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select 1 */
271 #define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select 0 */
272 #define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select 1 */
273 #define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select 2 */
274 #define ADC10ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */
275 #define ADC10SHP (0x0200) /* ADC10 Sample/Hold Pulse Mode */
276 #define ADC10SHS0 (0x0400) /* ADC10 Sample/Hold Source 0 */
277 #define ADC10SHS1 (0x0800) /* ADC10 Sample/Hold Source 1 */
278 
279 /* ADC10CTL1 Control Bits */
280 #define ADC10BUSY_L (0x0001) /* ADC10 Busy */
281 #define ADC10CONSEQ0_L (0x0002) /* ADC10 Conversion Sequence Select 0 */
282 #define ADC10CONSEQ1_L (0x0004) /* ADC10 Conversion Sequence Select 1 */
283 #define ADC10SSEL0_L (0x0008) /* ADC10 Clock Source Select 0 */
284 #define ADC10SSEL1_L (0x0010) /* ADC10 Clock Source Select 1 */
285 #define ADC10DIV0_L (0x0020) /* ADC10 Clock Divider Select 0 */
286 #define ADC10DIV1_L (0x0040) /* ADC10 Clock Divider Select 1 */
287 #define ADC10DIV2_L (0x0080) /* ADC10 Clock Divider Select 2 */
288 
289 /* ADC10CTL1 Control Bits */
290 #define ADC10ISSH_H (0x0001) /* ADC10 Invert Sample Hold Signal */
291 #define ADC10SHP_H (0x0002) /* ADC10 Sample/Hold Pulse Mode */
292 #define ADC10SHS0_H (0x0004) /* ADC10 Sample/Hold Source 0 */
293 #define ADC10SHS1_H (0x0008) /* ADC10 Sample/Hold Source 1 */
294 
295 #define ADC10CONSEQ_0 (0*2u) /* ADC10 Conversion Sequence Select: 0 */
296 #define ADC10CONSEQ_1 (1*2u) /* ADC10 Conversion Sequence Select: 1 */
297 #define ADC10CONSEQ_2 (2*2u) /* ADC10 Conversion Sequence Select: 2 */
298 #define ADC10CONSEQ_3 (3*2u) /* ADC10 Conversion Sequence Select: 3 */
299 
300 #define ADC10SSEL_0 (0*8u) /* ADC10 Clock Source Select: 0 */
301 #define ADC10SSEL_1 (1*8u) /* ADC10 Clock Source Select: 1 */
302 #define ADC10SSEL_2 (2*8u) /* ADC10 Clock Source Select: 2 */
303 #define ADC10SSEL_3 (3*8u) /* ADC10 Clock Source Select: 3 */
304 
305 #define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select: 0 */
306 #define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select: 1 */
307 #define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select: 2 */
308 #define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select: 3 */
309 #define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select: 4 */
310 #define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select: 5 */
311 #define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select: 6 */
312 #define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select: 7 */
313 
314 #define ADC10SHS_0 (0*0x400u) /* ADC10 Sample/Hold Source: 0 */
315 #define ADC10SHS_1 (1*0x400u) /* ADC10 Sample/Hold Source: 1 */
316 #define ADC10SHS_2 (2*0x400u) /* ADC10 Sample/Hold Source: 2 */
317 #define ADC10SHS_3 (3*0x400u) /* ADC10 Sample/Hold Source: 3 */
318 
319 /* ADC10CTL2 Control Bits */
320 #define ADC10REFBURST (0x0001) /* ADC10 Reference Burst */
321 #define ADC10SR (0x0004) /* ADC10 Sampling Rate */
322 #define ADC10DF (0x0008) /* ADC10 Data Format */
323 #define ADC10RES (0x0010) /* ADC10 Resolution Bit */
324 #define ADC10PDIV0 (0x0100) /* ADC10 predivider Bit: 0 */
325 #define ADC10PDIV1 (0x0200) /* ADC10 predivider Bit: 1 */
326 
327 /* ADC10CTL2 Control Bits */
328 #define ADC10REFBURST_L (0x0001) /* ADC10 Reference Burst */
329 #define ADC10SR_L (0x0004) /* ADC10 Sampling Rate */
330 #define ADC10DF_L (0x0008) /* ADC10 Data Format */
331 #define ADC10RES_L (0x0010) /* ADC10 Resolution Bit */
332 
333 /* ADC10CTL2 Control Bits */
334 #define ADC10PDIV0_H (0x0001) /* ADC10 predivider Bit: 0 */
335 #define ADC10PDIV1_H (0x0002) /* ADC10 predivider Bit: 1 */
336 
337 #define ADC10PDIV_0 (0x0000) /* ADC10 predivider /1 */
338 #define ADC10PDIV_1 (0x0100) /* ADC10 predivider /2 */
339 #define ADC10PDIV_2 (0x0200) /* ADC10 predivider /64 */
340 #define ADC10PDIV_3 (0x0300) /* ADC10 predivider reserved */
341 
342 #define ADC10PDIV__1 (0x0000) /* ADC10 predivider /1 */
343 #define ADC10PDIV__4 (0x0100) /* ADC10 predivider /2 */
344 #define ADC10PDIV__64 (0x0200) /* ADC10 predivider /64 */
345 
346 /* ADC10MCTL0 Control Bits */
347 #define ADC10INCH0 (0x0001) /* ADC10 Input Channel Select Bit 0 */
348 #define ADC10INCH1 (0x0002) /* ADC10 Input Channel Select Bit 1 */
349 #define ADC10INCH2 (0x0004) /* ADC10 Input Channel Select Bit 2 */
350 #define ADC10INCH3 (0x0008) /* ADC10 Input Channel Select Bit 3 */
351 #define ADC10SREF0 (0x0010) /* ADC10 Select Reference Bit 0 */
352 #define ADC10SREF1 (0x0020) /* ADC10 Select Reference Bit 1 */
353 #define ADC10SREF2 (0x0040) /* ADC10 Select Reference Bit 2 */
354 
355 /* ADC10MCTL0 Control Bits */
356 #define ADC10INCH0_L (0x0001) /* ADC10 Input Channel Select Bit 0 */
357 #define ADC10INCH1_L (0x0002) /* ADC10 Input Channel Select Bit 1 */
358 #define ADC10INCH2_L (0x0004) /* ADC10 Input Channel Select Bit 2 */
359 #define ADC10INCH3_L (0x0008) /* ADC10 Input Channel Select Bit 3 */
360 #define ADC10SREF0_L (0x0010) /* ADC10 Select Reference Bit 0 */
361 #define ADC10SREF1_L (0x0020) /* ADC10 Select Reference Bit 1 */
362 #define ADC10SREF2_L (0x0040) /* ADC10 Select Reference Bit 2 */
363 
364 #define ADC10INCH_0 (0) /* ADC10 Input Channel 0 */
365 #define ADC10INCH_1 (1) /* ADC10 Input Channel 1 */
366 #define ADC10INCH_2 (2) /* ADC10 Input Channel 2 */
367 #define ADC10INCH_3 (3) /* ADC10 Input Channel 3 */
368 #define ADC10INCH_4 (4) /* ADC10 Input Channel 4 */
369 #define ADC10INCH_5 (5) /* ADC10 Input Channel 5 */
370 #define ADC10INCH_6 (6) /* ADC10 Input Channel 6 */
371 #define ADC10INCH_7 (7) /* ADC10 Input Channel 7 */
372 #define ADC10INCH_8 (8) /* ADC10 Input Channel 8 */
373 #define ADC10INCH_9 (9) /* ADC10 Input Channel 9 */
374 #define ADC10INCH_10 (10) /* ADC10 Input Channel 10 */
375 #define ADC10INCH_11 (11) /* ADC10 Input Channel 11 */
376 #define ADC10INCH_12 (12) /* ADC10 Input Channel 12 */
377 #define ADC10INCH_13 (13) /* ADC10 Input Channel 13 */
378 #define ADC10INCH_14 (14) /* ADC10 Input Channel 14 */
379 #define ADC10INCH_15 (15) /* ADC10 Input Channel 15 */
380 
381 #define ADC10SREF_0 (0*0x10u) /* ADC10 Select Reference 0 */
382 #define ADC10SREF_1 (1*0x10u) /* ADC10 Select Reference 1 */
383 #define ADC10SREF_2 (2*0x10u) /* ADC10 Select Reference 2 */
384 #define ADC10SREF_3 (3*0x10u) /* ADC10 Select Reference 3 */
385 #define ADC10SREF_4 (4*0x10u) /* ADC10 Select Reference 4 */
386 #define ADC10SREF_5 (5*0x10u) /* ADC10 Select Reference 5 */
387 #define ADC10SREF_6 (6*0x10u) /* ADC10 Select Reference 6 */
388 #define ADC10SREF_7 (7*0x10u) /* ADC10 Select Reference 7 */
389 
390 /* ADC10IE Interrupt Enable Bits */
391 #define ADC10IE0 (0x0001) /* ADC10_A Interrupt enable */
392 #define ADC10INIE (0x0002) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */
393 #define ADC10LOIE (0x0004) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */
394 #define ADC10HIIE (0x0008) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */
395 #define ADC10OVIE (0x0010) /* ADC10_A ADC10MEM overflow Interrupt enable */
396 #define ADC10TOVIE (0x0020) /* ADC10_A conversion-time-overflow Interrupt enable */
397 
398 /* ADC10IE Interrupt Enable Bits */
399 #define ADC10IE0_L (0x0001) /* ADC10_A Interrupt enable */
400 #define ADC10INIE_L (0x0002) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */
401 #define ADC10LOIE_L (0x0004) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */
402 #define ADC10HIIE_L (0x0008) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */
403 #define ADC10OVIE_L (0x0010) /* ADC10_A ADC10MEM overflow Interrupt enable */
404 #define ADC10TOVIE_L (0x0020) /* ADC10_A conversion-time-overflow Interrupt enable */
405 
406 /* ADC10IFG Interrupt Flag Bits */
407 #define ADC10IFG0 (0x0001) /* ADC10_A Interrupt Flag */
408 #define ADC10INIFG (0x0002) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */
409 #define ADC10LOIFG (0x0004) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */
410 #define ADC10HIIFG (0x0008) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */
411 #define ADC10OVIFG (0x0010) /* ADC10_A ADC10MEM overflow Interrupt Flag */
412 #define ADC10TOVIFG (0x0020) /* ADC10_A conversion-time-overflow Interrupt Flag */
413 
414 /* ADC10IFG Interrupt Flag Bits */
415 #define ADC10IFG0_L (0x0001) /* ADC10_A Interrupt Flag */
416 #define ADC10INIFG_L (0x0002) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */
417 #define ADC10LOIFG_L (0x0004) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */
418 #define ADC10HIIFG_L (0x0008) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */
419 #define ADC10OVIFG_L (0x0010) /* ADC10_A ADC10MEM overflow Interrupt Flag */
420 #define ADC10TOVIFG_L (0x0020) /* ADC10_A conversion-time-overflow Interrupt Flag */
421 
422 /* ADC10IV Definitions */
423 #define ADC10IV_NONE (0x0000) /* No Interrupt pending */
424 #define ADC10IV_ADC10OVIFG (0x0002) /* ADC10OVIFG */
425 #define ADC10IV_ADC10TOVIFG (0x0004) /* ADC10TOVIFG */
426 #define ADC10IV_ADC10HIIFG (0x0006) /* ADC10HIIFG */
427 #define ADC10IV_ADC10LOIFG (0x0008) /* ADC10LOIFG */
428 #define ADC10IV_ADC10INIFG (0x000A) /* ADC10INIFG */
429 #define ADC10IV_ADC10IFG (0x000C) /* ADC10IFG */
430 
431 #endif
432 /************************************************************
433 * ADC12 PLUS
434 ************************************************************/
435 #ifdef __MSP430_HAS_ADC12_PLUS__ /* Definition to show that Module is available */
436 
437 #define OFS_ADC12CTL0 (0x0000) /* ADC12+ Control 0 */
438 #define OFS_ADC12CTL0_L OFS_ADC12CTL0
439 #define OFS_ADC12CTL0_H OFS_ADC12CTL0+1
440 #define OFS_ADC12CTL1 (0x0002) /* ADC12+ Control 1 */
441 #define OFS_ADC12CTL1_L OFS_ADC12CTL1
442 #define OFS_ADC12CTL1_H OFS_ADC12CTL1+1
443 #define OFS_ADC12CTL2 (0x0004) /* ADC12+ Control 2 */
444 #define OFS_ADC12CTL2_L OFS_ADC12CTL2
445 #define OFS_ADC12CTL2_H OFS_ADC12CTL2+1
446 #define OFS_ADC12IFG (0x000A) /* ADC12+ Interrupt Flag */
447 #define OFS_ADC12IFG_L OFS_ADC12IFG
448 #define OFS_ADC12IFG_H OFS_ADC12IFG+1
449 #define OFS_ADC12IE (0x000C) /* ADC12+ Interrupt Enable */
450 #define OFS_ADC12IE_L OFS_ADC12IE
451 #define OFS_ADC12IE_H OFS_ADC12IE+1
452 #define OFS_ADC12IV (0x000E) /* ADC12+ Interrupt Vector Word */
453 #define OFS_ADC12IV_L OFS_ADC12IV
454 #define OFS_ADC12IV_H OFS_ADC12IV+1
455 
456 #define OFS_ADC12MEM0 (0x0020) /* ADC12 Conversion Memory 0 */
457 #define OFS_ADC12MEM0_L OFS_ADC12MEM0
458 #define OFS_ADC12MEM0_H OFS_ADC12MEM0+1
459 #define OFS_ADC12MEM1 (0x0022) /* ADC12 Conversion Memory 1 */
460 #define OFS_ADC12MEM1_L OFS_ADC12MEM1
461 #define OFS_ADC12MEM1_H OFS_ADC12MEM1+1
462 #define OFS_ADC12MEM2 (0x0024) /* ADC12 Conversion Memory 2 */
463 #define OFS_ADC12MEM2_L OFS_ADC12MEM2
464 #define OFS_ADC12MEM2_H OFS_ADC12MEM2+1
465 #define OFS_ADC12MEM3 (0x0026) /* ADC12 Conversion Memory 3 */
466 #define OFS_ADC12MEM3_L OFS_ADC12MEM3
467 #define OFS_ADC12MEM3_H OFS_ADC12MEM3+1
468 #define OFS_ADC12MEM4 (0x0028) /* ADC12 Conversion Memory 4 */
469 #define OFS_ADC12MEM4_L OFS_ADC12MEM4
470 #define OFS_ADC12MEM4_H OFS_ADC12MEM4+1
471 #define OFS_ADC12MEM5 (0x002A) /* ADC12 Conversion Memory 5 */
472 #define OFS_ADC12MEM5_L OFS_ADC12MEM5
473 #define OFS_ADC12MEM5_H OFS_ADC12MEM5+1
474 #define OFS_ADC12MEM6 (0x002C) /* ADC12 Conversion Memory 6 */
475 #define OFS_ADC12MEM6_L OFS_ADC12MEM6
476 #define OFS_ADC12MEM6_H OFS_ADC12MEM6+1
477 #define OFS_ADC12MEM7 (0x002E) /* ADC12 Conversion Memory 7 */
478 #define OFS_ADC12MEM7_L OFS_ADC12MEM7
479 #define OFS_ADC12MEM7_H OFS_ADC12MEM7+1
480 #define OFS_ADC12MEM8 (0x0030) /* ADC12 Conversion Memory 8 */
481 #define OFS_ADC12MEM8_L OFS_ADC12MEM8
482 #define OFS_ADC12MEM8_H OFS_ADC12MEM8+1
483 #define OFS_ADC12MEM9 (0x0032) /* ADC12 Conversion Memory 9 */
484 #define OFS_ADC12MEM9_L OFS_ADC12MEM9
485 #define OFS_ADC12MEM9_H OFS_ADC12MEM9+1
486 #define OFS_ADC12MEM10 (0x0034) /* ADC12 Conversion Memory 10 */
487 #define OFS_ADC12MEM10_L OFS_ADC12MEM10
488 #define OFS_ADC12MEM10_H OFS_ADC12MEM10+1
489 #define OFS_ADC12MEM11 (0x0036) /* ADC12 Conversion Memory 11 */
490 #define OFS_ADC12MEM11_L OFS_ADC12MEM11
491 #define OFS_ADC12MEM11_H OFS_ADC12MEM11+1
492 #define OFS_ADC12MEM12 (0x0038) /* ADC12 Conversion Memory 12 */
493 #define OFS_ADC12MEM12_L OFS_ADC12MEM12
494 #define OFS_ADC12MEM12_H OFS_ADC12MEM12+1
495 #define OFS_ADC12MEM13 (0x003A) /* ADC12 Conversion Memory 13 */
496 #define OFS_ADC12MEM13_L OFS_ADC12MEM13
497 #define OFS_ADC12MEM13_H OFS_ADC12MEM13+1
498 #define OFS_ADC12MEM14 (0x003C) /* ADC12 Conversion Memory 14 */
499 #define OFS_ADC12MEM14_L OFS_ADC12MEM14
500 #define OFS_ADC12MEM14_H OFS_ADC12MEM14+1
501 #define OFS_ADC12MEM15 (0x003E) /* ADC12 Conversion Memory 15 */
502 #define OFS_ADC12MEM15_L OFS_ADC12MEM15
503 #define OFS_ADC12MEM15_H OFS_ADC12MEM15+1
504 #define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */
505 #ifdef __ASM_HEADER__
506 #define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */
507 #else
508 #define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
509 #endif
510 
511 #define OFS_ADC12MCTL0 (0x0010) /* ADC12 Memory Control 0 */
512 #define OFS_ADC12MCTL1 (0x0011) /* ADC12 Memory Control 1 */
513 #define OFS_ADC12MCTL2 (0x0012) /* ADC12 Memory Control 2 */
514 #define OFS_ADC12MCTL3 (0x0013) /* ADC12 Memory Control 3 */
515 #define OFS_ADC12MCTL4 (0x0014) /* ADC12 Memory Control 4 */
516 #define OFS_ADC12MCTL5 (0x0015) /* ADC12 Memory Control 5 */
517 #define OFS_ADC12MCTL6 (0x0016) /* ADC12 Memory Control 6 */
518 #define OFS_ADC12MCTL7 (0x0017) /* ADC12 Memory Control 7 */
519 #define OFS_ADC12MCTL8 (0x0018) /* ADC12 Memory Control 8 */
520 #define OFS_ADC12MCTL9 (0x0019) /* ADC12 Memory Control 9 */
521 #define OFS_ADC12MCTL10 (0x001A) /* ADC12 Memory Control 10 */
522 #define OFS_ADC12MCTL11 (0x001B) /* ADC12 Memory Control 11 */
523 #define OFS_ADC12MCTL12 (0x001C) /* ADC12 Memory Control 12 */
524 #define OFS_ADC12MCTL13 (0x001D) /* ADC12 Memory Control 13 */
525 #define OFS_ADC12MCTL14 (0x001E) /* ADC12 Memory Control 14 */
526 #define OFS_ADC12MCTL15 (0x001F) /* ADC12 Memory Control 15 */
527 #define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */
528 #ifdef __ASM_HEADER__
529 #define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */
530 #else
531 #define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */
532 #endif
533 
534 /* ADC12CTL0 Control Bits */
535 #define ADC12SC (0x0001) /* ADC12 Start Conversion */
536 #define ADC12ENC (0x0002) /* ADC12 Enable Conversion */
537 #define ADC12TOVIE (0x0004) /* ADC12 Timer Overflow interrupt enable */
538 #define ADC12OVIE (0x0008) /* ADC12 Overflow interrupt enable */
539 #define ADC12ON (0x0010) /* ADC12 On/enable */
540 #define ADC12REFON (0x0020) /* ADC12 Reference on */
541 #define ADC12REF2_5V (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */
542 #define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */
543 #define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */
544 #define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */
545 #define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */
546 #define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */
547 #define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */
548 #define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */
549 #define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */
550 #define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */
551 
552 /* ADC12CTL0 Control Bits */
553 #define ADC12SC_L (0x0001) /* ADC12 Start Conversion */
554 #define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */
555 #define ADC12TOVIE_L (0x0004) /* ADC12 Timer Overflow interrupt enable */
556 #define ADC12OVIE_L (0x0008) /* ADC12 Overflow interrupt enable */
557 #define ADC12ON_L (0x0010) /* ADC12 On/enable */
558 #define ADC12REFON_L (0x0020) /* ADC12 Reference on */
559 #define ADC12REF2_5V_L (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */
560 #define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */
561 
562 /* ADC12CTL0 Control Bits */
563 #define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */
564 #define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */
565 #define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */
566 #define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */
567 #define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */
568 #define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */
569 #define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */
570 #define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */
571 
572 #define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
573 #define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */
574 #define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */
575 #define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */
576 #define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */
577 #define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */
578 #define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */
579 #define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */
580 #define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */
581 #define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */
582 #define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */
583 #define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */
584 #define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */
585 #define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */
586 #define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */
587 #define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */
588 
589 #define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
590 #define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
591 #define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
592 #define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
593 #define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */
594 #define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */
595 #define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */
596 #define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */
597 #define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */
598 #define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */
599 #define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */
600 #define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */
601 #define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */
602 #define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */
603 #define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */
604 #define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */
605 
606 /* ADC12CTL1 Control Bits */
607 #define ADC12BUSY (0x0001) /* ADC12 Busy */
608 #define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
609 #define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
610 #define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */
611 #define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */
612 #define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
613 #define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
614 #define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
615 #define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */
616 #define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */
617 #define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */
618 #define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */
619 #define ADC12CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address Bit: 0 */
620 #define ADC12CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address Bit: 1 */
621 #define ADC12CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address Bit: 2 */
622 #define ADC12CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address Bit: 3 */
623 
624 /* ADC12CTL1 Control Bits */
625 #define ADC12BUSY_L (0x0001) /* ADC12 Busy */
626 #define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
627 #define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
628 #define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */
629 #define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */
630 #define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
631 #define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
632 #define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
633 
634 /* ADC12CTL1 Control Bits */
635 #define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */
636 #define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */
637 #define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */
638 #define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */
639 #define ADC12CSTARTADD0_H (0x0010) /* ADC12 Conversion Start Address Bit: 0 */
640 #define ADC12CSTARTADD1_H (0x0020) /* ADC12 Conversion Start Address Bit: 1 */
641 #define ADC12CSTARTADD2_H (0x0040) /* ADC12 Conversion Start Address Bit: 2 */
642 #define ADC12CSTARTADD3_H (0x0080) /* ADC12 Conversion Start Address Bit: 3 */
643 
644 #define ADC12CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */
645 #define ADC12CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */
646 #define ADC12CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */
647 #define ADC12CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */
648 
649 #define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */
650 #define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */
651 #define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */
652 #define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */
653 
654 #define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */
655 #define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */
656 #define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */
657 #define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */
658 #define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */
659 #define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */
660 #define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */
661 #define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */
662 
663 #define ADC12SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */
664 #define ADC12SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */
665 #define ADC12SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */
666 #define ADC12SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */
667 
668 #define ADC12CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */
669 #define ADC12CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */
670 #define ADC12CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */
671 #define ADC12CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */
672 #define ADC12CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */
673 #define ADC12CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */
674 #define ADC12CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */
675 #define ADC12CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */
676 #define ADC12CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */
677 #define ADC12CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */
678 #define ADC12CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */
679 #define ADC12CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */
680 #define ADC12CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */
681 #define ADC12CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */
682 #define ADC12CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */
683 #define ADC12CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 */
684 
685 /* ADC12CTL2 Control Bits */
686 #define ADC12REFBURST (0x0001) /* ADC12+ Reference Burst */
687 #define ADC12REFOUT (0x0002) /* ADC12+ Reference Out */
688 #define ADC12SR (0x0004) /* ADC12+ Sampling Rate */
689 #define ADC12DF (0x0008) /* ADC12+ Data Format */
690 #define ADC12RES0 (0x0010) /* ADC12+ Resolution Bit: 0 */
691 #define ADC12RES1 (0x0020) /* ADC12+ Resolution Bit: 1 */
692 #define ADC12TCOFF (0x0080) /* ADC12+ Temperature Sensor Off */
693 #define ADC12PDIV (0x0100) /* ADC12+ predivider 0:/1 1:/4 */
694 
695 /* ADC12CTL2 Control Bits */
696 #define ADC12REFBURST_L (0x0001) /* ADC12+ Reference Burst */
697 #define ADC12REFOUT_L (0x0002) /* ADC12+ Reference Out */
698 #define ADC12SR_L (0x0004) /* ADC12+ Sampling Rate */
699 #define ADC12DF_L (0x0008) /* ADC12+ Data Format */
700 #define ADC12RES0_L (0x0010) /* ADC12+ Resolution Bit: 0 */
701 #define ADC12RES1_L (0x0020) /* ADC12+ Resolution Bit: 1 */
702 #define ADC12TCOFF_L (0x0080) /* ADC12+ Temperature Sensor Off */
703 
704 /* ADC12CTL2 Control Bits */
705 #define ADC12PDIV_H (0x0001) /* ADC12+ predivider 0:/1 1:/4 */
706 
707 #define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */
708 #define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */
709 #define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */
710 #define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */
711 
712 /* ADC12MCTLx Control Bits */
713 #define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */
714 #define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */
715 #define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */
716 #define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */
717 #define ADC12SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */
718 #define ADC12SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */
719 #define ADC12SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */
720 #define ADC12EOS (0x0080) /* ADC12 End of Sequence */
721 
722 #define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */
723 #define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */
724 #define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */
725 #define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */
726 #define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */
727 #define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */
728 #define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */
729 #define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */
730 #define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */
731 #define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */
732 #define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */
733 #define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */
734 #define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */
735 #define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */
736 #define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */
737 #define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */
738 
739 #define ADC12SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */
740 #define ADC12SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */
741 #define ADC12SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */
742 #define ADC12SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */
743 #define ADC12SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */
744 #define ADC12SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */
745 #define ADC12SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */
746 #define ADC12SREF_7 (7*0x10u) /* ADC12 Select Reference 7 */
747 
748 #define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */
749 #define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */
750 #define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */
751 #define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */
752 #define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */
753 #define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */
754 #define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */
755 #define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */
756 #define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */
757 #define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */
758 #define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */
759 #define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */
760 #define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */
761 #define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */
762 #define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */
763 #define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */
764 
765 #define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */
766 #define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */
767 #define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */
768 #define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */
769 #define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */
770 #define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */
771 #define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */
772 #define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */
773 
774 #define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */
775 #define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */
776 #define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */
777 #define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */
778 #define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */
779 #define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */
780 #define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */
781 #define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */
782 
783 #define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */
784 #define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */
785 #define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */
786 #define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */
787 #define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */
788 #define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */
789 #define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */
790 #define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */
791 #define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */
792 #define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */
793 #define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */
794 #define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */
795 #define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */
796 #define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */
797 #define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */
798 #define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */
799 
800 #define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */
801 #define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */
802 #define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */
803 #define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */
804 #define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */
805 #define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */
806 #define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */
807 #define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */
808 
809 #define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */
810 #define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */
811 #define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */
812 #define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */
813 #define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */
814 #define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */
815 #define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */
816 #define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */
817 
818 /* ADC12IV Definitions */
819 #define ADC12IV_NONE (0x0000) /* No Interrupt pending */
820 #define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */
821 #define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */
822 #define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */
823 #define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */
824 #define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */
825 #define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */
826 #define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */
827 #define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */
828 #define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */
829 #define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */
830 #define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */
831 #define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */
832 #define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */
833 #define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */
834 #define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */
835 #define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */
836 #define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */
837 #define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */
838 
839 #endif
840 /************************************************************
841 * AES Accelerator
842 ************************************************************/
843 #ifdef __MSP430_HAS_AES__ /* Definition to show that Module is available */
844 
845 #define OFS_AESACTL0 (0x0000) /* AES accelerator control register 0 */
846 #define OFS_AESACTL0_L OFS_AESACTL0
847 #define OFS_AESACTL0_H OFS_AESACTL0+1
848 #define OFS_AESASTAT (0x0004) /* AES accelerator status register */
849 #define OFS_AESASTAT_L OFS_AESASTAT
850 #define OFS_AESASTAT_H OFS_AESASTAT+1
851 #define OFS_AESAKEY (0x0006) /* AES accelerator key register */
852 #define OFS_AESAKEY_L OFS_AESAKEY
853 #define OFS_AESAKEY_H OFS_AESAKEY+1
854 #define OFS_AESADIN (0x0008) /* AES accelerator data in register */
855 #define OFS_AESADIN_L OFS_AESADIN
856 #define OFS_AESADIN_H OFS_AESADIN+1
857 #define OFS_AESADOUT (0x000A) /* AES accelerator data out register */
858 #define OFS_AESADOUT_L OFS_AESADOUT
859 #define OFS_AESADOUT_H OFS_AESADOUT+1
860 
861 /* AESACTL0 Control Bits */
862 #define AESOP0 (0x0001) /* AES Operation Bit: 0 */
863 #define AESOP1 (0x0002) /* AES Operation Bit: 1 */
864 #define AESSWRST (0x0080) /* AES Software Reset */
865 #define AESRDYIFG (0x0100) /* AES ready interrupt flag */
866 #define AESERRFG (0x0800) /* AES Error Flag */
867 #define AESRDYIE (0x1000) /* AES ready interrupt enable*/
868 
869 /* AESACTL0 Control Bits */
870 #define AESOP0_L (0x0001) /* AES Operation Bit: 0 */
871 #define AESOP1_L (0x0002) /* AES Operation Bit: 1 */
872 #define AESSWRST_L (0x0080) /* AES Software Reset */
873 
874 /* AESACTL0 Control Bits */
875 #define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */
876 #define AESERRFG_H (0x0008) /* AES Error Flag */
877 #define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/
878 
879 #define AESOP_0 (0x0000) /* AES Operation: Encrypt */
880 #define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */
881 #define AESOP_2 (0x0002) /* AES Operation: Decrypt (frist round Key) */
882 #define AESOP_3 (0x0003) /* AES Operation: Generate first round Key */
883 
884 /* AESASTAT Control Bits */
885 #define AESBUSY (0x0001) /* AES Busy */
886 #define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */
887 #define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */
888 #define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */
889 #define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
890 #define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
891 #define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
892 #define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
893 #define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */
894 #define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */
895 #define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */
896 #define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */
897 #define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */
898 #define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */
899 #define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */
900 #define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */
901 
902 /* AESASTAT Control Bits */
903 #define AESBUSY_L (0x0001) /* AES Busy */
904 #define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */
905 #define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */
906 #define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */
907 #define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
908 #define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
909 #define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
910 #define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
911 
912 /* AESASTAT Control Bits */
913 #define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */
914 #define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */
915 #define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */
916 #define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */
917 #define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */
918 #define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */
919 #define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */
920 #define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */
921 
922 #endif
923 /*************************************************************
924 * Backup RAM Module
925 *************************************************************/
926 #ifdef __MSP430_HAS_BACKUP_RAM__ /* Definition to show that Module is available */
927 
928 #define OFS_BAKMEM0 (0x0000) /* Battery Backup Memory 0 */
929 #define OFS_BAKMEM0_L OFS_BAKMEM0
930 #define OFS_BAKMEM0_H OFS_BAKMEM0+1
931 #define OFS_BAKMEM1 (0x0002) /* Battery Backup Memory 1 */
932 #define OFS_BAKMEM1_L OFS_BAKMEM1
933 #define OFS_BAKMEM1_H OFS_BAKMEM1+1
934 #define OFS_BAKMEM2 (0x0004) /* Battery Backup Memory 2 */
935 #define OFS_BAKMEM2_L OFS_BAKMEM2
936 #define OFS_BAKMEM2_H OFS_BAKMEM2+1
937 #define OFS_BAKMEM3 (0x0006) /* Battery Backup Memory 3 */
938 #define OFS_BAKMEM3_L OFS_BAKMEM3
939 #define OFS_BAKMEM3_H OFS_BAKMEM3+1
940 
941 #endif
942 /*************************************************************
943 * Battery Charger Module
944 *************************************************************/
945 #ifdef __MSP430_HAS_BATTERY_CHARGER__ /* Definition to show that Module is available */
946 
947 #define OFS_BAKCTL (0x0000) /* Battery Backup Control */
948 #define OFS_BAKCTL_L OFS_BAKCTL
949 #define OFS_BAKCTL_H OFS_BAKCTL+1
950 #define OFS_BAKCHCTL (0x0002) /* Battery Charger Control */
951 #define OFS_BAKCHCTL_L OFS_BAKCHCTL
952 #define OFS_BAKCHCTL_H OFS_BAKCHCTL+1
953 
954 /* BAKCTL Control Bits */
955 #define LOCKBAK (0x0001) /* Lock backup sub-system */
956 #define BAKSW (0x0002) /* Manual switch to battery backup supply */
957 #define BAKADC (0x0004) /* Battery backup supply to ADC. */
958 #define BAKDIS (0x0008) /* Disable backup supply switching. */
959 
960 /* BAKCTL Control Bits */
961 #define LOCKBAK_L (0x0001) /* Lock backup sub-system */
962 #define BAKSW_L (0x0002) /* Manual switch to battery backup supply */
963 #define BAKADC_L (0x0004) /* Battery backup supply to ADC. */
964 #define BAKDIS_L (0x0008) /* Disable backup supply switching. */
965 
966 /* BAKCHCTL Control Bits */
967 #define CHEN (0x0001) /* Charger enable */
968 #define CHC0 (0x0002) /* Charger charge current Bit 0 */
969 #define CHC1 (0x0004) /* Charger charge current Bit 1 */
970 #define CHV0 (0x0010) /* Charger end voltage Bit 0 */
971 #define CHV1 (0x0020) /* Charger end voltage Bit 1 */
972 
973 /* BAKCHCTL Control Bits */
974 #define CHEN_L (0x0001) /* Charger enable */
975 #define CHC0_L (0x0002) /* Charger charge current Bit 0 */
976 #define CHC1_L (0x0004) /* Charger charge current Bit 1 */
977 #define CHV0_L (0x0010) /* Charger end voltage Bit 0 */
978 #define CHV1_L (0x0020) /* Charger end voltage Bit 1 */
979 
980 #define CHPWD (0x6900) /* Charger write password. */
981 
982 #endif
983 /************************************************************
984 * Comparator B
985 ************************************************************/
986 #ifdef __MSP430_HAS_COMPB__ /* Definition to show that Module is available */
987 
988 #define OFS_CBCTL0 (0x0000) /* Comparator B Control Register 0 */
989 #define OFS_CBCTL0_L OFS_CBCTL0
990 #define OFS_CBCTL0_H OFS_CBCTL0+1
991 #define OFS_CBCTL1 (0x0002) /* Comparator B Control Register 1 */
992 #define OFS_CBCTL1_L OFS_CBCTL1
993 #define OFS_CBCTL1_H OFS_CBCTL1+1
994 #define OFS_CBCTL2 (0x0004) /* Comparator B Control Register 2 */
995 #define OFS_CBCTL2_L OFS_CBCTL2
996 #define OFS_CBCTL2_H OFS_CBCTL2+1
997 #define OFS_CBCTL3 (0x0006) /* Comparator B Control Register 3 */
998 #define OFS_CBCTL3_L OFS_CBCTL3
999 #define OFS_CBCTL3_H OFS_CBCTL3+1
1000 #define OFS_CBINT (0x000C) /* Comparator B Interrupt Register */
1001 #define OFS_CBINT_L OFS_CBINT
1002 #define OFS_CBINT_H OFS_CBINT+1
1003 #define OFS_CBIV (0x000E) /* Comparator B Interrupt Vector Word */
1004 
1005 /* CBCTL0 Control Bits */
1006 #define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */
1007 #define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */
1008 #define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */
1009 #define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */
1010 //#define RESERVED (0x0010) /* Comp. B */
1011 //#define RESERVED (0x0020) /* Comp. B */
1012 //#define RESERVED (0x0040) /* Comp. B */
1013 #define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enable */
1014 #define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */
1015 #define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */
1016 #define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */
1017 #define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */
1018 //#define RESERVED (0x1000) /* Comp. B */
1019 //#define RESERVED (0x2000) /* Comp. B */
1020 //#define RESERVED (0x4000) /* Comp. B */
1021 #define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enable */
1022 
1023 /* CBCTL0 Control Bits */
1024 #define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */
1025 #define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */
1026 #define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */
1027 #define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */
1028 //#define RESERVED (0x0010) /* Comp. B */
1029 //#define RESERVED (0x0020) /* Comp. B */
1030 //#define RESERVED (0x0040) /* Comp. B */
1031 #define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enable */
1032 //#define RESERVED (0x1000) /* Comp. B */
1033 //#define RESERVED (0x2000) /* Comp. B */
1034 //#define RESERVED (0x4000) /* Comp. B */
1035 
1036 /* CBCTL0 Control Bits */
1037 //#define RESERVED (0x0010) /* Comp. B */
1038 //#define RESERVED (0x0020) /* Comp. B */
1039 //#define RESERVED (0x0040) /* Comp. B */
1040 #define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */
1041 #define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */
1042 #define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */
1043 #define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */
1044 //#define RESERVED (0x1000) /* Comp. B */
1045 //#define RESERVED (0x2000) /* Comp. B */
1046 //#define RESERVED (0x4000) /* Comp. B */
1047 #define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enable */
1048 
1049 #define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */
1050 #define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */
1051 #define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */
1052 #define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */
1053 #define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */
1054 #define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */
1055 #define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */
1056 #define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */
1057 #define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */
1058 #define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */
1059 #define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */
1060 #define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */
1061 #define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */
1062 #define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */
1063 #define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */
1064 #define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */
1065 
1066 #define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */
1067 #define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */
1068 #define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */
1069 #define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */
1070 #define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */
1071 #define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */
1072 #define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */
1073 #define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */
1074 #define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */
1075 #define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */
1076 #define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */
1077 #define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */
1078 #define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */
1079 #define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */
1080 #define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */
1081 #define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */
1082 
1083 /* CBCTL1 Control Bits */
1084 #define CBOUT (0x0001) /* Comp. B Output */
1085 #define CBOUTPOL (0x0002) /* Comp. B Output Polarity */
1086 #define CBF (0x0004) /* Comp. B Enable Output Filter */
1087 #define CBIES (0x0008) /* Comp. B Interrupt Edge Select */
1088 #define CBSHORT (0x0010) /* Comp. B Input Short */
1089 #define CBEX (0x0020) /* Comp. B Exchange Inputs */
1090 #define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */
1091 #define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */
1092 #define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */
1093 #define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */
1094 #define CBON (0x0400) /* Comp. B enable */
1095 #define CBMRVL (0x0800) /* Comp. B CBMRV Level */
1096 #define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/
1097 //#define RESERVED (0x2000) /* Comp. B */
1098 //#define RESERVED (0x4000) /* Comp. B */
1099 //#define RESERVED (0x8000) /* Comp. B */
1100 
1101 /* CBCTL1 Control Bits */
1102 #define CBOUT_L (0x0001) /* Comp. B Output */
1103 #define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */
1104 #define CBF_L (0x0004) /* Comp. B Enable Output Filter */
1105 #define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */
1106 #define CBSHORT_L (0x0010) /* Comp. B Input Short */
1107 #define CBEX_L (0x0020) /* Comp. B Exchange Inputs */
1108 #define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */
1109 #define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */
1110 //#define RESERVED (0x2000) /* Comp. B */
1111 //#define RESERVED (0x4000) /* Comp. B */
1112 //#define RESERVED (0x8000) /* Comp. B */
1113 
1114 /* CBCTL1 Control Bits */
1115 #define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */
1116 #define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */
1117 #define CBON_H (0x0004) /* Comp. B enable */
1118 #define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */
1119 #define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/
1120 //#define RESERVED (0x2000) /* Comp. B */
1121 //#define RESERVED (0x4000) /* Comp. B */
1122 //#define RESERVED (0x8000) /* Comp. B */
1123 
1124 #define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */
1125 #define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */
1126 #define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */
1127 #define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */
1128 
1129 #define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */
1130 #define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */
1131 #define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/
1132 #define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */
1133 
1134 /* CBCTL2 Control Bits */
1135 #define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
1136 #define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
1137 #define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
1138 #define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
1139 #define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
1140 #define CBRSEL (0x0020) /* Comp. B Reference select */
1141 #define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */
1142 #define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */
1143 #define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */
1144 #define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */
1145 #define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */
1146 #define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */
1147 #define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */
1148 #define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */
1149 #define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */
1150 #define CBREFACC (0x8000) /* Comp. B Reference Accuracy */
1151 
1152 /* CBCTL2 Control Bits */
1153 #define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
1154 #define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
1155 #define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
1156 #define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
1157 #define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
1158 #define CBRSEL_L (0x0020) /* Comp. B Reference select */
1159 #define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */
1160 #define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */
1161 
1162 /* CBCTL2 Control Bits */
1163 #define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */
1164 #define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */
1165 #define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */
1166 #define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */
1167 #define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */
1168 #define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */
1169 #define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */
1170 #define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */
1171 
1172 #define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */
1173 #define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */
1174 #define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */
1175 #define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */
1176 #define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */
1177 #define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */
1178 #define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */
1179 #define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */
1180 #define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */
1181 #define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */
1182 #define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */
1183 #define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */
1184 #define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */
1185 #define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */
1186 #define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */
1187 #define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */
1188 #define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */
1189 #define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */
1190 #define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */
1191 #define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */
1192 #define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */
1193 #define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */
1194 #define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */
1195 #define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */
1196 #define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */
1197 #define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */
1198 #define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */
1199 #define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */
1200 #define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */
1201 #define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */
1202 #define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */
1203 #define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */
1204 
1205 #define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */
1206 #define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */
1207 #define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */
1208 #define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */
1209 
1210 #define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */
1211 #define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */
1212 #define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */
1213 #define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */
1214 #define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */
1215 #define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */
1216 #define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */
1217 #define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */
1218 #define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */
1219 #define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */
1220 #define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */
1221 #define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */
1222 #define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */
1223 #define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */
1224 #define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */
1225 #define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */
1226 #define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */
1227 #define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */
1228 #define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */
1229 #define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */
1230 #define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */
1231 #define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */
1232 #define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */
1233 #define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */
1234 #define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */
1235 #define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */
1236 #define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */
1237 #define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */
1238 #define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */
1239 #define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */
1240 #define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */
1241 #define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */
1242 
1243 #define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */
1244 #define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */
1245 #define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */
1246 #define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */
1247 
1248 #define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
1249 #define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
1250 #define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
1251 #define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
1252 #define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
1253 #define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
1254 #define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
1255 #define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
1256 #define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */
1257 #define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */
1258 #define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */
1259 #define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */
1260 #define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */
1261 #define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */
1262 #define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */
1263 #define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */
1264 
1265 #define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
1266 #define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
1267 #define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
1268 #define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
1269 #define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
1270 #define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
1271 #define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
1272 #define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
1273 
1274 #define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */
1275 #define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */
1276 #define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */
1277 #define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */
1278 #define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */
1279 #define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */
1280 #define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */
1281 #define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */
1282 
1283 /* CBINT Control Bits */
1284 #define CBIFG (0x0001) /* Comp. B Interrupt Flag */
1285 #define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
1286 //#define RESERVED (0x0004) /* Comp. B */
1287 //#define RESERVED (0x0008) /* Comp. B */
1288 //#define RESERVED (0x0010) /* Comp. B */
1289 //#define RESERVED (0x0020) /* Comp. B */
1290 //#define RESERVED (0x0040) /* Comp. B */
1291 //#define RESERVED (0x0080) /* Comp. B */
1292 #define CBIE (0x0100) /* Comp. B Interrupt Enable */
1293 #define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */
1294 //#define RESERVED (0x0400) /* Comp. B */
1295 //#define RESERVED (0x0800) /* Comp. B */
1296 //#define RESERVED (0x1000) /* Comp. B */
1297 //#define RESERVED (0x2000) /* Comp. B */
1298 //#define RESERVED (0x4000) /* Comp. B */
1299 //#define RESERVED (0x8000) /* Comp. B */
1300 
1301 /* CBINT Control Bits */
1302 #define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */
1303 #define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
1304 //#define RESERVED (0x0004) /* Comp. B */
1305 //#define RESERVED (0x0008) /* Comp. B */
1306 //#define RESERVED (0x0010) /* Comp. B */
1307 //#define RESERVED (0x0020) /* Comp. B */
1308 //#define RESERVED (0x0040) /* Comp. B */
1309 //#define RESERVED (0x0080) /* Comp. B */
1310 //#define RESERVED (0x0400) /* Comp. B */
1311 //#define RESERVED (0x0800) /* Comp. B */
1312 //#define RESERVED (0x1000) /* Comp. B */
1313 //#define RESERVED (0x2000) /* Comp. B */
1314 //#define RESERVED (0x4000) /* Comp. B */
1315 //#define RESERVED (0x8000) /* Comp. B */
1316 
1317 /* CBINT Control Bits */
1318 //#define RESERVED (0x0004) /* Comp. B */
1319 //#define RESERVED (0x0008) /* Comp. B */
1320 //#define RESERVED (0x0010) /* Comp. B */
1321 //#define RESERVED (0x0020) /* Comp. B */
1322 //#define RESERVED (0x0040) /* Comp. B */
1323 //#define RESERVED (0x0080) /* Comp. B */
1324 #define CBIE_H (0x0001) /* Comp. B Interrupt Enable */
1325 #define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */
1326 //#define RESERVED (0x0400) /* Comp. B */
1327 //#define RESERVED (0x0800) /* Comp. B */
1328 //#define RESERVED (0x1000) /* Comp. B */
1329 //#define RESERVED (0x2000) /* Comp. B */
1330 //#define RESERVED (0x4000) /* Comp. B */
1331 //#define RESERVED (0x8000) /* Comp. B */
1332 
1333 /* CBIV Definitions */
1334 #define CBIV_NONE (0x0000) /* No Interrupt pending */
1335 #define CBIV_CBIFG (0x0002) /* CBIFG */
1336 #define CBIV_CBIIFG (0x0004) /* CBIIFG */
1337 
1338 #endif
1339 /************************************************************
1340 * CC1101 Radio Interface
1341 ************************************************************/
1342 #ifdef __MSP430_HAS_CC1101__ /* Definition to show that Module is available */
1343 
1344 #define OFS_RF1AIFCTL0 (0x0000) /* Radio interface control register 0 */
1345 #define OFS_RF1AIFCTL0_L OFS_RF1AIFCTL0
1346 #define OFS_RF1AIFCTL0_H OFS_RF1AIFCTL0+1
1347 #define OFS_RF1AIFCTL1 (0x0002) /* Radio interface control register 1 */
1348 #define OFS_RF1AIFCTL1_L OFS_RF1AIFCTL1
1349 #define OFS_RF1AIFCTL1_H OFS_RF1AIFCTL1+1
1350 #define RF1AIFIFG RF1AIFCTL1_L /* Radio interface interrupt flag register */
1351 #define RF1AIFIE RF1AIFCTL1_H /* Radio interface interrupt enable register */
1352 #define OFS_RF1AIFCTL2 (0x0004) /* (Radio interface control register 2) */
1353 #define OFS_RF1AIFCTL2_L OFS_RF1AIFCTL2
1354 #define OFS_RF1AIFCTL2_H OFS_RF1AIFCTL2+1
1355 #define OFS_RF1AIFERR (0x0006) /* Radio interface error flag register */
1356 #define OFS_RF1AIFERR_L OFS_RF1AIFERR
1357 #define OFS_RF1AIFERR_H OFS_RF1AIFERR+1
1358 #define OFS_RF1AIFERRV (0x000C) /* Radio interface error vector word register */
1359 #define OFS_RF1AIFERRV_L OFS_RF1AIFERRV
1360 #define OFS_RF1AIFERRV_H OFS_RF1AIFERRV+1
1361 #define OFS_RF1AIFIV (0x000E) /* Radio interface interrupt vector word register */
1362 #define OFS_RF1AIFIV_L OFS_RF1AIFIV
1363 #define OFS_RF1AIFIV_H OFS_RF1AIFIV+1
1364 #define OFS_RF1AINSTRW (0x0010) /* Radio instruction word register */
1365 #define OFS_RF1AINSTRW_L OFS_RF1AINSTRW
1366 #define OFS_RF1AINSTRW_H OFS_RF1AINSTRW+1
1367 #define RF1ADINB RF1AINSTRW_L /* Radio instruction byte register */
1368 #define RF1AINSTRB RF1AINSTRW_H /* Radio byte data in register */
1369 #define OFS_RF1AINSTR1W (0x0012) /* Radio instruction 1-byte register with autoread */
1370 #define OFS_RF1AINSTR1W_L OFS_RF1AINSTR1W
1371 #define OFS_RF1AINSTR1W_H OFS_RF1AINSTR1W+1
1372 #define RF1AINSTR1B RF1AINSTR1W_H /* Radio instruction 1-byte register with autoread */
1373 #define OFS_RF1AINSTR2W (0x0014) /* Radio instruction 2-byte register with autoread */
1374 #define OFS_RF1AINSTR2W_L OFS_RF1AINSTR2W
1375 #define OFS_RF1AINSTR2W_H OFS_RF1AINSTR2W+1
1376 #define RF1AINSTR2B RF1AINSTR1W_H /* Radio instruction 2-byte register with autoread */
1377 #define OFS_RF1ADINW (0x0016) /* Radio word data in register */
1378 #define OFS_RF1ADINW_L OFS_RF1ADINW
1379 #define OFS_RF1ADINW_H OFS_RF1ADINW+1
1380 
1381 #define OFS_RF1ASTAT0W (0x0020) /* Radio status word register without auto-read */
1382 #define OFS_RF1ASTAT0W_L OFS_RF1ASTAT0W
1383 #define OFS_RF1ASTAT0W_H OFS_RF1ASTAT0W+1
1384 #define RF1ADOUT0B RF1ASTAT0W_L /* Radio byte data out register without auto-read */
1385 #define RF1ASTAT0B RF1ASTAT0W_H /* Radio status byte register without auto-read */
1386 #define RF1ASTATW RF1ASTAT0W /* Radio status word register without auto-read */
1387 #define RF1ADOUTB RF1ASTAT0W_L /* Radio byte data out register without auto-read */
1388 #define RF1ASTATB RF1ASTAT0W_H /* Radio status byte register without auto-read */
1389 #define OFS_RF1ASTAT1W (0x0022) /* Radio status word register with 1-byte auto-read */
1390 #define OFS_RF1ASTAT1W_L OFS_RF1ASTAT1W
1391 #define OFS_RF1ASTAT1W_H OFS_RF1ASTAT1W+1
1392 #define RF1ADOUT1B RF1ASTAT1W_L /* Radio byte data out register with 1-byte auto-read */
1393 #define RF1ASTAT1B RF1ASTAT1W_H /* Radio status byte register with 1-byte auto-read */
1394 #define OFS_RF1ASTAT2W (0x0024) /* Radio status word register with 2-byte auto-read */
1395 #define OFS_RF1ASTAT2W_L OFS_RF1ASTAT2W
1396 #define OFS_RF1ASTAT2W_H OFS_RF1ASTAT2W+1
1397 #define RF1ADOUT2B RF1ASTAT2W_L /* Radio byte data out register with 2-byte auto-read */
1398 #define RF1ASTAT2B RF1ASTAT2W_H /* Radio status byte register with 2-byte auto-read */
1399 #define OFS_RF1ADOUT0W (0x0028) /* Radio core word data out register without auto-read */
1400 #define OFS_RF1ADOUT0W_L OFS_RF1ADOUT0W
1401 #define OFS_RF1ADOUT0W_H OFS_RF1ADOUT0W+1
1402 #define RF1ADOUTW RF1ADOUT0W /* Radio core word data out register without auto-read */
1403 #define RF1ADOUTW_L RF1ADOUT0W_L /* Radio core word data out register without auto-read */
1404 #define RF1ADOUTW_H RF1ADOUT0W_H /* Radio core word data out register without auto-read */
1405 #define OFS_RF1ADOUT1W (0x002A) /* Radio core word data out register with 1-byte auto-read */
1406 #define OFS_RF1ADOUT1W_L OFS_RF1ADOUT1W
1407 #define OFS_RF1ADOUT1W_H OFS_RF1ADOUT1W+1
1408 #define OFS_RF1ADOUT2W (0x002C) /* Radio core word data out register with 2-byte auto-read */
1409 #define OFS_RF1ADOUT2W_L OFS_RF1ADOUT2W
1410 #define OFS_RF1ADOUT2W_H OFS_RF1ADOUT2W+1
1411 #define OFS_RF1AIN (0x0030) /* Radio core signal input register */
1412 #define OFS_RF1AIN_L OFS_RF1AIN
1413 #define OFS_RF1AIN_H OFS_RF1AIN+1
1414 #define OFS_RF1AIFG (0x0032) /* Radio core interrupt flag register */
1415 #define OFS_RF1AIFG_L OFS_RF1AIFG
1416 #define OFS_RF1AIFG_H OFS_RF1AIFG+1
1417 #define OFS_RF1AIES (0x0034) /* Radio core interrupt edge select register */
1418 #define OFS_RF1AIES_L OFS_RF1AIES
1419 #define OFS_RF1AIES_H OFS_RF1AIES+1
1420 #define OFS_RF1AIE (0x0036) /* Radio core interrupt enable register */
1421 #define OFS_RF1AIE_L OFS_RF1AIE
1422 #define OFS_RF1AIE_H OFS_RF1AIE+1
1423 #define OFS_RF1AIV (0x0038) /* Radio core interrupt vector word register */
1424 #define OFS_RF1AIV_L OFS_RF1AIV
1425 #define OFS_RF1AIV_H OFS_RF1AIV+1
1426 #define OFS_RF1ARXFIFO (0x003C) /* Direct receive FIFO access register */
1427 #define OFS_RF1ARXFIFO_L OFS_RF1ARXFIFO
1428 #define OFS_RF1ARXFIFO_H OFS_RF1ARXFIFO+1
1429 #define OFS_RF1ATXFIFO (0x003E) /* Direct transmit FIFO access register */
1430 #define OFS_RF1ATXFIFO_L OFS_RF1ATXFIFO
1431 #define OFS_RF1ATXFIFO_H OFS_RF1ATXFIFO+1
1432 
1433 /* RF1AIFCTL0 Control Bits */
1434 #define RFFIFOEN (0x0001) /* CC1101 Direct FIFO access enable */
1435 #define RFENDIAN (0x0002) /* CC1101 Disable endianness conversion */
1436 
1437 /* RF1AIFCTL0 Control Bits */
1438 #define RFFIFOEN_L (0x0001) /* CC1101 Direct FIFO access enable */
1439 #define RFENDIAN_L (0x0002) /* CC1101 Disable endianness conversion */
1440 
1441 /* RF1AIFCTL1 Control Bits */
1442 #define RFRXIFG (0x0001) /* Radio interface direct FIFO access receive interrupt flag */
1443 #define RFTXIFG (0x0002) /* Radio interface direct FIFO access transmit interrupt flag */
1444 #define RFERRIFG (0x0004) /* Radio interface error interrupt flag */
1445 #define RFINSTRIFG (0x0010) /* Radio interface instruction interrupt flag */
1446 #define RFDINIFG (0x0020) /* Radio interface data in interrupt flag */
1447 #define RFSTATIFG (0x0040) /* Radio interface status interrupt flag */
1448 #define RFDOUTIFG (0x0080) /* Radio interface data out interrupt flag */
1449 #define RFRXIE (0x0100) /* Radio interface direct FIFO access receive interrupt enable */
1450 #define RFTXIE (0x0200) /* Radio interface direct FIFO access transmit interrupt enable */
1451 #define RFERRIE (0x0400) /* Radio interface error interrupt enable */
1452 #define RFINSTRIE (0x1000) /* Radio interface instruction interrupt enable */
1453 #define RFDINIE (0x2000) /* Radio interface data in interrupt enable */
1454 #define RFSTATIE (0x4000) /* Radio interface status interrupt enable */
1455 #define RFDOUTIE (0x8000) /* Radio interface data out interrupt enable */
1456 
1457 /* RF1AIFCTL1 Control Bits */
1458 #define RFRXIFG_L (0x0001) /* Radio interface direct FIFO access receive interrupt flag */
1459 #define RFTXIFG_L (0x0002) /* Radio interface direct FIFO access transmit interrupt flag */
1460 #define RFERRIFG_L (0x0004) /* Radio interface error interrupt flag */
1461 #define RFINSTRIFG_L (0x0010) /* Radio interface instruction interrupt flag */
1462 #define RFDINIFG_L (0x0020) /* Radio interface data in interrupt flag */
1463 #define RFSTATIFG_L (0x0040) /* Radio interface status interrupt flag */
1464 #define RFDOUTIFG_L (0x0080) /* Radio interface data out interrupt flag */
1465 
1466 /* RF1AIFCTL1 Control Bits */
1467 #define RFRXIE_H (0x0001) /* Radio interface direct FIFO access receive interrupt enable */
1468 #define RFTXIE_H (0x0002) /* Radio interface direct FIFO access transmit interrupt enable */
1469 #define RFERRIE_H (0x0004) /* Radio interface error interrupt enable */
1470 #define RFINSTRIE_H (0x0010) /* Radio interface instruction interrupt enable */
1471 #define RFDINIE_H (0x0020) /* Radio interface data in interrupt enable */
1472 #define RFSTATIE_H (0x0040) /* Radio interface status interrupt enable */
1473 #define RFDOUTIE_H (0x0080) /* Radio interface data out interrupt enable */
1474 
1475 /* RF1AIFERR Control Bits */
1476 #define LVERR (0x0001) /* Low Core Voltage Error Flag */
1477 #define OPERR (0x0002) /* Operand Error Flag */
1478 #define OUTERR (0x0004) /* Output data not available Error Flag */
1479 #define OPOVERR (0x0008) /* Operand Overwrite Error Flag */
1480 
1481 /* RF1AIFERR Control Bits */
1482 #define LVERR_L (0x0001) /* Low Core Voltage Error Flag */
1483 #define OPERR_L (0x0002) /* Operand Error Flag */
1484 #define OUTERR_L (0x0004) /* Output data not available Error Flag */
1485 #define OPOVERR_L (0x0008) /* Operand Overwrite Error Flag */
1486 
1487 /* RF1AIFERRV Definitions */
1488 #define RF1AIFERRV_NONE (0x0000) /* No Error pending */
1489 #define RF1AIFERRV_LVERR (0x0002) /* Low core voltage error */
1490 #define RF1AIFERRV_OPERR (0x0004) /* Operand Error */
1491 #define RF1AIFERRV_OUTERR (0x0006) /* Output data not available Error */
1492 #define RF1AIFERRV_OPOVERR (0x0008) /* Operand Overwrite Error */
1493 
1494 /* RF1AIFIV Definitions */
1495 #define RF1AIFIV_NONE (0x0000) /* No Interrupt pending */
1496 #define RF1AIFIV_RFERRIFG (0x0002) /* Radio interface error */
1497 #define RF1AIFIV_RFDOUTIFG (0x0004) /* Radio i/f data out */
1498 #define RF1AIFIV_RFSTATIFG (0x0006) /* Radio i/f status out */
1499 #define RF1AIFIV_RFDINIFG (0x0008) /* Radio i/f data in */
1500 #define RF1AIFIV_RFINSTRIFG (0x000A) /* Radio i/f instruction in */
1501 
1502 /* RF1AIV Definitions */
1503 #define RF1AIV_NONE (0x0000) /* No Interrupt pending */
1504 #define RF1AIV_RFIFG0 (0x0002) /* RFIFG0 */
1505 #define RF1AIV_RFIFG1 (0x0004) /* RFIFG1 */
1506 #define RF1AIV_RFIFG2 (0x0006) /* RFIFG2 */
1507 #define RF1AIV_RFIFG3 (0x0008) /* RFIFG3 */
1508 #define RF1AIV_RFIFG4 (0x000A) /* RFIFG4 */
1509 #define RF1AIV_RFIFG5 (0x000C) /* RFIFG5 */
1510 #define RF1AIV_RFIFG6 (0x000E) /* RFIFG6 */
1511 #define RF1AIV_RFIFG7 (0x0010) /* RFIFG7 */
1512 #define RF1AIV_RFIFG8 (0x0012) /* RFIFG8 */
1513 #define RF1AIV_RFIFG9 (0x0014) /* RFIFG9 */
1514 #define RF1AIV_RFIFG10 (0x0016) /* RFIFG10 */
1515 #define RF1AIV_RFIFG11 (0x0018) /* RFIFG11 */
1516 #define RF1AIV_RFIFG12 (0x001A) /* RFIFG12 */
1517 #define RF1AIV_RFIFG13 (0x001C) /* RFIFG13 */
1518 #define RF1AIV_RFIFG14 (0x001E) /* RFIFG14 */
1519 #define RF1AIV_RFIFG15 (0x0020) /* RFIFG15 */
1520 
1521 // Radio Core Registers
1522 #define IOCFG2 0x00 /* IOCFG2 - GDO2 output pin configuration */
1523 #define IOCFG1 0x01 /* IOCFG1 - GDO1 output pin configuration */
1524 #define IOCFG0 0x02 /* IOCFG1 - GDO0 output pin configuration */
1525 #define FIFOTHR 0x03 /* FIFOTHR - RX FIFO and TX FIFO thresholds */
1526 #define SYNC1 0x04 /* SYNC1 - Sync word, high byte */
1527 #define SYNC0 0x05 /* SYNC0 - Sync word, low byte */
1528 #define PKTLEN 0x06 /* PKTLEN - Packet length */
1529 #define PKTCTRL1 0x07 /* PKTCTRL1 - Packet automation control */
1530 #define PKTCTRL0 0x08 /* PKTCTRL0 - Packet automation control */
1531 #define ADDR 0x09 /* ADDR - Device address */
1532 #define CHANNR 0x0A /* CHANNR - Channel number */
1533 #define FSCTRL1 0x0B /* FSCTRL1 - Frequency synthesizer control */
1534 #define FSCTRL0 0x0C /* FSCTRL0 - Frequency synthesizer control */
1535 #define FREQ2 0x0D /* FREQ2 - Frequency control word, high byte */
1536 #define FREQ1 0x0E /* FREQ1 - Frequency control word, middle byte */
1537 #define FREQ0 0x0F /* FREQ0 - Frequency control word, low byte */
1538 #define MDMCFG4 0x10 /* MDMCFG4 - Modem configuration */
1539 #define MDMCFG3 0x11 /* MDMCFG3 - Modem configuration */
1540 #define MDMCFG2 0x12 /* MDMCFG2 - Modem configuration */
1541 #define MDMCFG1 0x13 /* MDMCFG1 - Modem configuration */
1542 #define MDMCFG0 0x14 /* MDMCFG0 - Modem configuration */
1543 #define DEVIATN 0x15 /* DEVIATN - Modem deviation setting */
1544 #define MCSM2 0x16 /* MCSM2 - Main Radio Control State Machine configuration */
1545 #define MCSM1 0x17 /* MCSM1 - Main Radio Control State Machine configuration */
1546 #define MCSM0 0x18 /* MCSM0 - Main Radio Control State Machine configuration */
1547 #define FOCCFG 0x19 /* FOCCFG - Frequency Offset Compensation configuration */
1548 #define BSCFG 0x1A /* BSCFG - Bit Synchronization configuration */
1549 #define AGCCTRL2 0x1B /* AGCCTRL2 - AGC control */
1550 #define AGCCTRL1 0x1C /* AGCCTRL1 - AGC control */
1551 #define AGCCTRL0 0x1D /* AGCCTRL0 - AGC control */
1552 #define WOREVT1 0x1E /* WOREVT1 - High byte Event0 timeout */
1553 #define WOREVT0 0x1F /* WOREVT0 - Low byte Event0 timeout */
1554 #define WORCTRL 0x20 /* WORCTRL - Wake On Radio control */
1555 #define FREND1 0x21 /* FREND1 - Front end RX configuration */
1556 #define FREND0 0x22 /* FREDN0 - Front end TX configuration */
1557 #define FSCAL3 0x23 /* FSCAL3 - Frequency synthesizer calibration */
1558 #define FSCAL2 0x24 /* FSCAL2 - Frequency synthesizer calibration */
1559 #define FSCAL1 0x25 /* FSCAL1 - Frequency synthesizer calibration */
1560 #define FSCAL0 0x26 /* FSCAL0 - Frequency synthesizer calibration */
1561 //#define RCCTRL1 0x27 /* RCCTRL1 - RC oscillator configuration */
1562 //#define RCCTRL0 0x28 /* RCCTRL0 - RC oscillator configuration */
1563 #define FSTEST 0x29 /* FSTEST - Frequency synthesizer calibration control */
1564 #define PTEST 0x2A /* PTEST - Production test */
1565 #define AGCTEST 0x2B /* AGCTEST - AGC test */
1566 #define TEST2 0x2C /* TEST2 - Various test settings */
1567 #define TEST1 0x2D /* TEST1 - Various test settings */
1568 #define TEST0 0x2E /* TEST0 - Various test settings */
1569 
1570 /* status registers */
1571 #define PARTNUM 0x30 /* PARTNUM - Chip ID */
1572 #define VERSION 0x31 /* VERSION - Chip ID */
1573 #define FREQEST 0x32 /* FREQEST – Frequency Offset Estimate from demodulator */
1574 #define LQI 0x33 /* LQI – Demodulator estimate for Link Quality */
1575 #define RSSI 0x34 /* RSSI – Received signal strength indication */
1576 #define MARCSTATE 0x35 /* MARCSTATE – Main Radio Control State Machine state */
1577 #define WORTIME1 0x36 /* WORTIME1 – High byte of WOR time */
1578 #define WORTIME0 0x37 /* WORTIME0 – Low byte of WOR time */
1579 #define PKTSTATUS 0x38 /* PKTSTATUS – Current GDOx status and packet status */
1580 #define VCO_VC_DAC 0x39 /* VCO_VC_DAC – Current setting from PLL calibration module */
1581 #define TXBYTES 0x3A /* TXBYTES – Underflow and number of bytes */
1582 #define RXBYTES 0x3B /* RXBYTES – Overflow and number of bytes */
1583 
1584 /* burst write registers */
1585 #define PATABLE 0x3E /* PATABLE - PA control settings table */
1586 #define TXFIFO 0x3F /* TXFIFO - Transmit FIFO */
1587 #define RXFIFO 0x3F /* RXFIFO - Receive FIFO */
1588 
1589 /* Radio Core Instructions */
1590 /* command strobes */
1591 #define RF_SRES 0x30 /* SRES - Reset chip. */
1592 #define RF_SFSTXON 0x31 /* SFSTXON - Enable and calibrate frequency synthesizer. */
1593 #define RF_SXOFF 0x32 /* SXOFF - Turn off crystal oscillator. */
1594 #define RF_SCAL 0x33 /* SCAL - Calibrate frequency synthesizer and turn it off. */
1595 #define RF_SRX 0x34 /* SRX - Enable RX. Perform calibration if enabled. */
1596 #define RF_STX 0x35 /* STX - Enable TX. If in RX state, only enable TX if CCA passes. */
1597 #define RF_SIDLE 0x36 /* SIDLE - Exit RX / TX, turn off frequency synthesizer. */
1598 //#define RF_SRSVD 0x37 /* SRVSD - Reserved. Do not use. */
1599 #define RF_SWOR 0x38 /* SWOR - Start automatic RX polling sequence (Wake-on-Radio) */
1600 #define RF_SPWD 0x39 /* SPWD - Enter power down mode when CSn goes high. */
1601 #define RF_SFRX 0x3A /* SFRX - Flush the RX FIFO buffer. */
1602 #define RF_SFTX 0x3B /* SFTX - Flush the TX FIFO buffer. */
1603 #define RF_SWORRST 0x3C /* SWORRST - Reset real time clock. */
1604 #define RF_SNOP 0x3D /* SNOP - No operation. Returns status byte. */
1605 
1606 #define RF_RXSTAT 0x80 /* Used in combination with strobe commands delivers number of availabe bytes in RX FIFO with return status */
1607 #define RF_TXSTAT 0x00 /* Used in combination with strobe commands delivers number of availabe bytes in TX FIFO with return status */
1608 
1609 /* other radio instr */
1610 #define RF_SNGLREGRD 0x80
1611 #define RF_SNGLREGWR 0x00
1612 #define RF_REGRD 0xC0
1613 #define RF_REGWR 0x40
1614 #define RF_STATREGRD 0xC0 /* Read single radio core status register */
1615 #define RF_SNGLPATABRD (RF_SNGLREGRD+PATABLE)
1616 #define RF_SNGLPATABWR (RF_SNGLREGWR+PATABLE)
1617 #define RF_PATABRD (RF_REGRD+PATABLE)
1618 #define RF_PATABWR (RF_REGWR+PATABLE)
1619 #define RF_SNGLRXRD (RF_SNGLREGRD+RXFIFO)
1620 #define RF_SNGLTXWR (RF_SNGLREGWR+TXFIFO)
1621 #define RF_RXFIFORD (RF_REGRD+RXFIFO)
1622 #define RF_TXFIFOWR (RF_REGWR+TXFIFO)
1623 
1624 #endif
1625 /*************************************************************
1626 * CRC Module
1627 *************************************************************/
1628 #ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */
1629 
1630 #define OFS_CRCDI (0x0000) /* CRC Data In Register */
1631 #define OFS_CRCDI_L OFS_CRCDI
1632 #define OFS_CRCDI_H OFS_CRCDI+1
1633 #define OFS_CRCDIRB (0x0002) /* CRC data in reverse byte Register */
1634 #define OFS_CRCDIRB_L OFS_CRCDIRB
1635 #define OFS_CRCDIRB_H OFS_CRCDIRB+1
1636 #define OFS_CRCINIRES (0x0004) /* CRC Initialisation Register and Result Register */
1637 #define OFS_CRCINIRES_L OFS_CRCINIRES
1638 #define OFS_CRCINIRES_H OFS_CRCINIRES+1
1639 #define OFS_CRCRESR (0x0006) /* CRC reverse result Register */
1640 #define OFS_CRCRESR_L OFS_CRCRESR
1641 #define OFS_CRCRESR_H OFS_CRCRESR+1
1642 
1643 #endif
1644 /************************************************************
1645 * DAC12
1646 ************************************************************/
1647 #ifdef __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */
1648 
1649 #define OFS_DAC12_0CTL0 (0x0000) /* DAC12_0 Control Register 0 */
1650 #define OFS_DAC12_0CTL1 (0x0002) /* DAC12_0 Control Register 1 */
1651 #define OFS_DAC12_0DAT (0x0004) /* DAC12_0 Data */
1652 #define OFS_DAC12_0CALCTL (0x0006) /* DAC12_0 Calibration Control Register */
1653 #define OFS_DAC12_0CALDAT (0x0008) /* DAC12_0 Calibration Data Register */
1654 #define OFS_DAC12_1CTL0 (0x0010) /* DAC12_1 Control Register 0 */
1655 #define OFS_DAC12_1CTL1 (0x0012) /* DAC12_1 Control Register 1 */
1656 #define OFS_DAC12_1DAT (0x0014) /* DAC12_1 Data */
1657 #define OFS_DAC12_1CALCTL (0x0016) /* DAC12_1 Calibration Control Register */
1658 #define OFS_DAC12_1CALDAT (0x0018) /* DAC12_1 Calibration Data Register */
1659 #define OFS_DAC12_IV (0x001E) /* DAC12 Interrupt Vector Word */
1660 
1661 /* DAC12_xCTL0 Control Bits */
1662 #define DAC12GRP (0x0001) /* DAC12 group */
1663 #define DAC12ENC (0x0002) /* DAC12 enable conversion */
1664 #define DAC12IFG (0x0004) /* DAC12 interrupt flag */
1665 #define DAC12IE (0x0008) /* DAC12 interrupt enable */
1666 #define DAC12DF (0x0010) /* DAC12 data format */
1667 #define DAC12AMP0 (0x0020) /* DAC12 amplifier bit 0 */
1668 #define DAC12AMP1 (0x0040) /* DAC12 amplifier bit 1 */
1669 #define DAC12AMP2 (0x0080) /* DAC12 amplifier bit 2 */
1670 #define DAC12IR (0x0100) /* DAC12 input reference and output range */
1671 #define DAC12CALON (0x0200) /* DAC12 calibration */
1672 #define DAC12LSEL0 (0x0400) /* DAC12 load select bit 0 */
1673 #define DAC12LSEL1 (0x0800) /* DAC12 load select bit 1 */
1674 #define DAC12RES (0x1000) /* DAC12 resolution */
1675 #define DAC12SREF0 (0x2000) /* DAC12 reference bit 0 */
1676 #define DAC12SREF1 (0x4000) /* DAC12 reference bit 1 */
1677 #define DAC12OPS (0x8000) /* DAC12 Operation Amp. */
1678 
1679 #define DAC12AMP_0 (0*0x0020u) /* DAC12 amplifier 0: off, 3-state */
1680 #define DAC12AMP_1 (1*0x0020u) /* DAC12 amplifier 1: off, off */
1681 #define DAC12AMP_2 (2*0x0020u) /* DAC12 amplifier 2: low, low */
1682 #define DAC12AMP_3 (3*0x0020u) /* DAC12 amplifier 3: low, medium */
1683 #define DAC12AMP_4 (4*0x0020u) /* DAC12 amplifier 4: low, high */
1684 #define DAC12AMP_5 (5*0x0020u) /* DAC12 amplifier 5: medium, medium */
1685 #define DAC12AMP_6 (6*0x0020u) /* DAC12 amplifier 6: medium, high */
1686 #define DAC12AMP_7 (7*0x0020u) /* DAC12 amplifier 7: high, high */
1687 
1688 #define DAC12LSEL_0 (0*0x0400u) /* DAC12 load select 0: direct */
1689 #define DAC12LSEL_1 (1*0x0400u) /* DAC12 load select 1: latched with DAT */
1690 #define DAC12LSEL_2 (2*0x0400u) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */
1691 #define DAC12LSEL_3 (3*0x0400u) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */
1692 
1693 #define DAC12SREF_0 (0*0x2000u) /* DAC12 reference 0: Vref+ */
1694 #define DAC12SREF_1 (1*0x2000u) /* DAC12 reference 1: Vref+ */
1695 #define DAC12SREF_2 (2*0x2000u) /* DAC12 reference 2: Veref+ */
1696 #define DAC12SREF_3 (3*0x2000u) /* DAC12 reference 3: Veref+ */
1697 
1698 /* DAC12_xCTL1 Control Bits */
1699 #define DAC12DFJ (0x0001) /* DAC12 Data Format Justification */
1700 #define DAC12OG (0x0002) /* DAC12 output buffer gain: 0: 3x gain / 1: 2x gain */
1701 
1702 /* DAC12_xCALCTL Control Bits */
1703 #define DAC12LOCK (0x0001) /* DAC12 Calibration Lock */
1704 
1705 #define DAC12PW (0xA500) /* DAC12 Calibration Register write Password */
1706 
1707 /* DACIV Definitions */
1708 #define DACIV_NONE (0x0000) /* No Interrupt pending */
1709 #define DACIV_DAC12IFG_0 (0x0002) /* DAC12IFG_0 */
1710 #define DACIV_DAC12IFG_1 (0x0004) /* DAC12IFG_1 */
1711 
1712 #endif
1713 /************************************************************
1714 * DMA_X
1715 ************************************************************/
1716 #ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
1717 
1718 #define OFS_DMACTL0 (0x0000) /* DMA Module Control 0 */
1719 #define OFS_DMACTL0_L OFS_DMACTL0
1720 #define OFS_DMACTL0_H OFS_DMACTL0+1
1721 #define OFS_DMACTL1 (0x0002) /* DMA Module Control 1 */
1722 #define OFS_DMACTL1_L OFS_DMACTL1
1723 #define OFS_DMACTL1_H OFS_DMACTL1+1
1724 #define OFS_DMACTL2 (0x0004) /* DMA Module Control 2 */
1725 #define OFS_DMACTL2_L OFS_DMACTL2
1726 #define OFS_DMACTL2_H OFS_DMACTL2+1
1727 #define OFS_DMACTL3 (0x0006) /* DMA Module Control 3 */
1728 #define OFS_DMACTL3_L OFS_DMACTL3
1729 #define OFS_DMACTL3_H OFS_DMACTL3+1
1730 #define OFS_DMACTL4 (0x0008) /* DMA Module Control 4 */
1731 #define OFS_DMACTL4_L OFS_DMACTL4
1732 #define OFS_DMACTL4_H OFS_DMACTL4+1
1733 #define OFS_DMAIV (0x000E) /* DMA Interrupt Vector Word */
1734 #define OFS_DMAIV_L OFS_DMAIV
1735 #define OFS_DMAIV_H OFS_DMAIV+1
1736 
1737 #define OFS_DMA0CTL (0x0010) /* DMA Channel 0 Control */
1738 #define OFS_DMA0CTL_L OFS_DMA0CTL
1739 #define OFS_DMA0CTL_H OFS_DMA0CTL+1
1740 #define OFS_DMA0SA (0x0012) /* DMA Channel 0 Source Address */
1741 #define OFS_DMA0DA (0x0016) /* DMA Channel 0 Destination Address */
1742 #define OFS_DMA0SZ (0x001A) /* DMA Channel 0 Transfer Size */
1743 
1744 #define OFS_DMA1CTL (0x0020) /* DMA Channel 1 Control */
1745 #define OFS_DMA1CTL_L OFS_DMA1CTL
1746 #define OFS_DMA1CTL_H OFS_DMA1CTL+1
1747 #define OFS_DMA1SA (0x0022) /* DMA Channel 1 Source Address */
1748 #define OFS_DMA1DA (0x0026) /* DMA Channel 1 Destination Address */
1749 #define OFS_DMA1SZ (0x002A) /* DMA Channel 1 Transfer Size */
1750 
1751 #define OFS_DMA2CTL (0x0030) /* DMA Channel 2 Control */
1752 #define OFS_DMA2CTL_L OFS_DMA2CTL
1753 #define OFS_DMA2CTL_H OFS_DMA2CTL+1
1754 #define OFS_DMA2SA (0x0032) /* DMA Channel 2 Source Address */
1755 #define OFS_DMA2DA (0x0036) /* DMA Channel 2 Destination Address */
1756 #define OFS_DMA2SZ (0x003A) /* DMA Channel 2 Transfer Size */
1757 
1758 /* DMACTL0 Control Bits */
1759 #define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
1760 #define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
1761 #define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
1762 #define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
1763 #define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
1764 #define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
1765 #define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
1766 #define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
1767 #define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
1768 #define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
1769 
1770 /* DMACTL0 Control Bits */
1771 #define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
1772 #define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
1773 #define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
1774 #define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
1775 #define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
1776 
1777 /* DMACTL0 Control Bits */
1778 #define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
1779 #define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
1780 #define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
1781 #define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
1782 #define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
1783 
1784 /* DMACTL01 Control Bits */
1785 #define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
1786 #define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
1787 #define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
1788 #define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
1789 #define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
1790 
1791 /* DMACTL01 Control Bits */
1792 #define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
1793 #define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
1794 #define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
1795 #define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
1796 #define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
1797 
1798 /* DMACTL4 Control Bits */
1799 #define ENNMI (0x0001) /* Enable NMI interruption of DMA */
1800 #define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
1801 #define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
1802 
1803 /* DMACTL4 Control Bits */
1804 #define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
1805 #define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
1806 #define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
1807 
1808 /* DMAxCTL Control Bits */
1809 #define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
1810 #define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
1811 #define DMAIE (0x0004) /* DMA interrupt enable */
1812 #define DMAIFG (0x0008) /* DMA interrupt flag */
1813 #define DMAEN (0x0010) /* DMA enable */
1814 #define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
1815 #define DMASRCBYTE (0x0040) /* DMA source byte */
1816 #define DMADSTBYTE (0x0080) /* DMA destination byte */
1817 #define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
1818 #define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
1819 #define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
1820 #define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
1821 #define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
1822 #define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
1823 #define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
1824 
1825 /* DMAxCTL Control Bits */
1826 #define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
1827 #define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
1828 #define DMAIE_L (0x0004) /* DMA interrupt enable */
1829 #define DMAIFG_L (0x0008) /* DMA interrupt flag */
1830 #define DMAEN_L (0x0010) /* DMA enable */
1831 #define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
1832 #define DMASRCBYTE_L (0x0040) /* DMA source byte */
1833 #define DMADSTBYTE_L (0x0080) /* DMA destination byte */
1834 
1835 /* DMAxCTL Control Bits */
1836 #define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
1837 #define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
1838 #define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
1839 #define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
1840 #define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
1841 #define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
1842 #define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
1843 
1844 #define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
1845 #define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
1846 #define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
1847 #define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
1848 
1849 #define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
1850 #define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
1851 #define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
1852 #define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
1853 
1854 #define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
1855 #define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
1856 #define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
1857 #define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
1858 
1859 #define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
1860 #define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
1861 #define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
1862 #define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
1863 #define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
1864 #define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
1865 #define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
1866 #define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
1867 
1868 /* DMAIV Definitions */
1869 #define DMAIV_NONE (0x0000) /* No Interrupt pending */
1870 #define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
1871 #define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
1872 #define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
1873 
1874 #endif
1875 /************************************************************
1876 * DMA_X
1877 ************************************************************/
1878 #ifdef __MSP430_HAS_DMAX_6__ /* Definition to show that Module is available */
1879 
1880 #define OFS_DMACTL0 (0x0000) /* DMA Module Control 0 */
1881 #define OFS_DMACTL0_L OFS_DMACTL0
1882 #define OFS_DMACTL0_H OFS_DMACTL0+1
1883 #define OFS_DMACTL1 (0x0002) /* DMA Module Control 1 */
1884 #define OFS_DMACTL1_L OFS_DMACTL1
1885 #define OFS_DMACTL1_H OFS_DMACTL1+1
1886 #define OFS_DMACTL2 (0x0004) /* DMA Module Control 2 */
1887 #define OFS_DMACTL2_L OFS_DMACTL2
1888 #define OFS_DMACTL2_H OFS_DMACTL2+1
1889 #define OFS_DMACTL3 (0x0006) /* DMA Module Control 3 */
1890 #define OFS_DMACTL3_L OFS_DMACTL3
1891 #define OFS_DMACTL3_H OFS_DMACTL3+1
1892 #define OFS_DMACTL4 (0x0008) /* DMA Module Control 4 */
1893 #define OFS_DMACTL4_L OFS_DMACTL4
1894 #define OFS_DMACTL4_H OFS_DMACTL4+1
1895 #define OFS_DMAIV (0x000E) /* DMA Interrupt Vector Word */
1896 #define OFS_DMAIV_L OFS_DMAIV
1897 #define OFS_DMAIV_H OFS_DMAIV+1
1898 
1899 #define OFS_DMA0CTL (0x0010) /* DMA Channel 0 Control */
1900 #define OFS_DMA0CTL_L OFS_DMA0CTL
1901 #define OFS_DMA0CTL_H OFS_DMA0CTL+1
1902 #define OFS_DMA0SA (0x0012) /* DMA Channel 0 Source Address */
1903 #define OFS_DMA0DA (0x0016) /* DMA Channel 0 Destination Address */
1904 #define OFS_DMA0SZ (0x001A) /* DMA Channel 0 Transfer Size */
1905 
1906 #define OFS_DMA1CTL (0x0020) /* DMA Channel 1 Control */
1907 #define OFS_DMA1CTL_L OFS_DMA1CTL
1908 #define OFS_DMA1CTL_H OFS_DMA1CTL+1
1909 #define OFS_DMA1SA (0x0022) /* DMA Channel 1 Source Address */
1910 #define OFS_DMA1DA (0x0026) /* DMA Channel 1 Destination Address */
1911 #define OFS_DMA1SZ (0x002A) /* DMA Channel 1 Transfer Size */
1912 
1913 #define OFS_DMA2CTL (0x0030) /* DMA Channel 2 Control */
1914 #define OFS_DMA2CTL_L OFS_DMA2CTL
1915 #define OFS_DMA2CTL_H OFS_DMA2CTL+1
1916 #define OFS_DMA2SA (0x0032) /* DMA Channel 2 Source Address */
1917 #define OFS_DMA2DA (0x0036) /* DMA Channel 2 Destination Address */
1918 #define OFS_DMA2SZ (0x003A) /* DMA Channel 2 Transfer Size */
1919 
1920 #define OFS_DMA3CTL (0x0040) /* DMA Channel 3 Control */
1921 #define OFS_DMA3CTL_L OFS_DMA3CTL
1922 #define OFS_DMA3CTL_H OFS_DMA3CTL+1
1923 #define OFS_DMA3SA (0x0042) /* DMA Channel 3 Source Address */
1924 #define OFS_DMA3DA (0x0046) /* DMA Channel 3 Destination Address */
1925 #define OFS_DMA3SZ (0x004A) /* DMA Channel 3 Transfer Size */
1926 
1927 #define OFS_DMA4CTL (0x0050) /* DMA Channel 4 Control */
1928 #define OFS_DMA4CTL_L OFS_DMA4CTL
1929 #define OFS_DMA4CTL_H OFS_DMA4CTL+1
1930 #define OFS_DMA4SA (0x0052) /* DMA Channel 4 Source Address */
1931 #define OFS_DMA4DA (0x0056) /* DMA Channel 4 Destination Address */
1932 #define OFS_DMA4SZ (0x005A) /* DMA Channel 4 Transfer Size */
1933 
1934 #define OFS_DMA5CTL (0x0060) /* DMA Channel 5 Control */
1935 #define OFS_DMA5CTL_L OFS_DMA5CTL
1936 #define OFS_DMA5CTL_H OFS_DMA5CTL+1
1937 #define OFS_DMA5SA (0x0062) /* DMA Channel 5 Source Address */
1938 #define OFS_DMA5DA (0x0066) /* DMA Channel 5 Destination Address */
1939 #define OFS_DMA5SZ (0x006A) /* DMA Channel 5 Transfer Size */
1940 
1941 /* DMACTL0 Control Bits */
1942 #define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
1943 #define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
1944 #define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
1945 #define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
1946 #define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
1947 #define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
1948 #define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
1949 #define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
1950 #define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
1951 #define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
1952 
1953 /* DMACTL0 Control Bits */
1954 #define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
1955 #define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
1956 #define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
1957 #define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
1958 #define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
1959 
1960 /* DMACTL0 Control Bits */
1961 #define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
1962 #define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
1963 #define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
1964 #define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
1965 #define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
1966 
1967 /* DMACTL01 Control Bits */
1968 #define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
1969 #define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
1970 #define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
1971 #define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
1972 #define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
1973 #define DMA3TSEL0 (0x0100) /* DMA channel 3 transfer select bit 0 */
1974 #define DMA3TSEL1 (0x0200) /* DMA channel 3 transfer select bit 1 */
1975 #define DMA3TSEL2 (0x0400) /* DMA channel 3 transfer select bit 2 */
1976 #define DMA3TSEL3 (0x0800) /* DMA channel 3 transfer select bit 3 */
1977 #define DMA3TSEL4 (0x1000) /* DMA channel 3 transfer select bit 4 */
1978 
1979 /* DMACTL01 Control Bits */
1980 #define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
1981 #define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
1982 #define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
1983 #define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
1984 #define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
1985 
1986 /* DMACTL01 Control Bits */
1987 #define DMA3TSEL0_H (0x0001) /* DMA channel 3 transfer select bit 0 */
1988 #define DMA3TSEL1_H (0x0002) /* DMA channel 3 transfer select bit 1 */
1989 #define DMA3TSEL2_H (0x0004) /* DMA channel 3 transfer select bit 2 */
1990 #define DMA3TSEL3_H (0x0008) /* DMA channel 3 transfer select bit 3 */
1991 #define DMA3TSEL4_H (0x0010) /* DMA channel 3 transfer select bit 4 */
1992 
1993 /* DMACTL0 Control Bits */
1994 #define DMA4TSEL0 (0x0001) /* DMA channel 4 transfer select bit 0 */
1995 #define DMA4TSEL1 (0x0002) /* DMA channel 4 transfer select bit 1 */
1996 #define DMA4TSEL2 (0x0004) /* DMA channel 4 transfer select bit 2 */
1997 #define DMA4TSEL3 (0x0008) /* DMA channel 4 transfer select bit 3 */
1998 #define DMA4TSEL4 (0x0010) /* DMA channel 4 transfer select bit 4 */
1999 #define DMA5TSEL0 (0x0100) /* DMA channel 5 transfer select bit 0 */
2000 #define DMA5TSEL1 (0x0200) /* DMA channel 5 transfer select bit 1 */
2001 #define DMA5TSEL2 (0x0400) /* DMA channel 5 transfer select bit 2 */
2002 #define DMA5TSEL3 (0x0800) /* DMA channel 5 transfer select bit 3 */
2003 #define DMA5TSEL4 (0x1000) /* DMA channel 5 transfer select bit 4 */
2004 
2005 /* DMACTL0 Control Bits */
2006 #define DMA4TSEL0_L (0x0001) /* DMA channel 4 transfer select bit 0 */
2007 #define DMA4TSEL1_L (0x0002) /* DMA channel 4 transfer select bit 1 */
2008 #define DMA4TSEL2_L (0x0004) /* DMA channel 4 transfer select bit 2 */
2009 #define DMA4TSEL3_L (0x0008) /* DMA channel 4 transfer select bit 3 */
2010 #define DMA4TSEL4_L (0x0010) /* DMA channel 4 transfer select bit 4 */
2011 
2012 /* DMACTL0 Control Bits */
2013 #define DMA5TSEL0_H (0x0001) /* DMA channel 5 transfer select bit 0 */
2014 #define DMA5TSEL1_H (0x0002) /* DMA channel 5 transfer select bit 1 */
2015 #define DMA5TSEL2_H (0x0004) /* DMA channel 5 transfer select bit 2 */
2016 #define DMA5TSEL3_H (0x0008) /* DMA channel 5 transfer select bit 3 */
2017 #define DMA5TSEL4_H (0x0010) /* DMA channel 5 transfer select bit 4 */
2018 
2019 /* DMACTL4 Control Bits */
2020 #define ENNMI (0x0001) /* Enable NMI interruption of DMA */
2021 #define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
2022 #define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
2023 
2024 /* DMACTL4 Control Bits */
2025 #define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
2026 #define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
2027 #define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
2028 
2029 /* DMAxCTL Control Bits */
2030 #define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
2031 #define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
2032 #define DMAIE (0x0004) /* DMA interrupt enable */
2033 #define DMAIFG (0x0008) /* DMA interrupt flag */
2034 #define DMAEN (0x0010) /* DMA enable */
2035 #define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
2036 #define DMASRCBYTE (0x0040) /* DMA source byte */
2037 #define DMADSTBYTE (0x0080) /* DMA destination byte */
2038 #define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
2039 #define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
2040 #define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
2041 #define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
2042 #define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
2043 #define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
2044 #define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
2045 
2046 /* DMAxCTL Control Bits */
2047 #define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
2048 #define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
2049 #define DMAIE_L (0x0004) /* DMA interrupt enable */
2050 #define DMAIFG_L (0x0008) /* DMA interrupt flag */
2051 #define DMAEN_L (0x0010) /* DMA enable */
2052 #define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
2053 #define DMASRCBYTE_L (0x0040) /* DMA source byte */
2054 #define DMADSTBYTE_L (0x0080) /* DMA destination byte */
2055 
2056 /* DMAxCTL Control Bits */
2057 #define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
2058 #define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
2059 #define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
2060 #define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
2061 #define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
2062 #define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
2063 #define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
2064 
2065 #define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
2066 #define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
2067 #define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
2068 #define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
2069 
2070 #define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
2071 #define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
2072 #define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
2073 #define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
2074 
2075 #define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
2076 #define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
2077 #define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
2078 #define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
2079 
2080 #define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
2081 #define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
2082 #define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
2083 #define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
2084 #define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
2085 #define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
2086 #define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
2087 #define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
2088 
2089 /* DMAIV Definitions */
2090 #define DMAIV_NONE (0x0000) /* No Interrupt pending */
2091 #define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
2092 #define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
2093 #define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
2094 #define DMAIV_DMA3IFG (0x0008) /* DMA3IFG*/
2095 #define DMAIV_DMA4IFG (0x000A) /* DMA4IFG*/
2096 #define DMAIV_DMA5IFG (0x000C) /* DMA5IFG*/
2097 
2098 #endif
2099 /*************************************************************
2100 * Flash Memory
2101 *************************************************************/
2102 #ifdef __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
2103 
2104 #define OFS_FCTL1 (0x0000) /* FLASH Control 1 */
2105 #define OFS_FCTL1_L OFS_FCTL1
2106 #define OFS_FCTL1_H OFS_FCTL1+1
2107 //#define FCTL2_O (0x0002) /* FLASH Control 2 */
2108 #define OFS_FCTL3 (0x0004) /* FLASH Control 3 */
2109 #define OFS_FCTL3_L OFS_FCTL3
2110 #define OFS_FCTL3_H OFS_FCTL3+1
2111 #define OFS_FCTL4 (0x0006) /* FLASH Control 4 */
2112 #define OFS_FCTL4_L OFS_FCTL4
2113 #define OFS_FCTL4_H OFS_FCTL4+1
2114 
2115 #define FRPW (0x9600) /* Flash password returned by read */
2116 #define FWPW (0xA500) /* Flash password for write */
2117 #define FXPW (0x3300) /* for use with XOR instruction */
2118 #define FRKEY (0x9600) /* (legacy definition) Flash key returned by read */
2119 #define FWKEY (0xA500) /* (legacy definition) Flash key for write */
2120 #define FXKEY (0x3300) /* (legacy definition) for use with XOR instruction */
2121 
2122 /* FCTL1 Control Bits */
2123 //#define RESERVED (0x0001) /* Reserved */
2124 #define ERASE (0x0002) /* Enable bit for Flash segment erase */
2125 #define MERAS (0x0004) /* Enable bit for Flash mass erase */
2126 //#define RESERVED (0x0008) /* Reserved */
2127 //#define RESERVED (0x0010) /* Reserved */
2128 #define SWRT (0x0020) /* Smart Write enable */
2129 #define WRT (0x0040) /* Enable bit for Flash write */
2130 #define BLKWRT (0x0080) /* Enable bit for Flash segment write */
2131 
2132 /* FCTL1 Control Bits */
2133 //#define RESERVED (0x0001) /* Reserved */
2134 #define ERASE_L (0x0002) /* Enable bit for Flash segment erase */
2135 #define MERAS_L (0x0004) /* Enable bit for Flash mass erase */
2136 //#define RESERVED (0x0008) /* Reserved */
2137 //#define RESERVED (0x0010) /* Reserved */
2138 #define SWRT_L (0x0020) /* Smart Write enable */
2139 #define WRT_L (0x0040) /* Enable bit for Flash write */
2140 #define BLKWRT_L (0x0080) /* Enable bit for Flash segment write */
2141 
2142 /* FCTL3 Control Bits */
2143 #define BUSY (0x0001) /* Flash busy: 1 */
2144 #define KEYV (0x0002) /* Flash Key violation flag */
2145 #define ACCVIFG (0x0004) /* Flash Access violation flag */
2146 #define WAIT (0x0008) /* Wait flag for segment write */
2147 #define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
2148 #define EMEX (0x0020) /* Flash Emergency Exit */
2149 #define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
2150 //#define RESERVED (0x0080) /* Reserved */
2151 
2152 /* FCTL3 Control Bits */
2153 #define BUSY_L (0x0001) /* Flash busy: 1 */
2154 #define KEYV_L (0x0002) /* Flash Key violation flag */
2155 #define ACCVIFG_L (0x0004) /* Flash Access violation flag */
2156 #define WAIT_L (0x0008) /* Wait flag for segment write */
2157 #define LOCK_L (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
2158 #define EMEX_L (0x0020) /* Flash Emergency Exit */
2159 #define LOCKA_L (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
2160 //#define RESERVED (0x0080) /* Reserved */
2161 
2162 /* FCTL4 Control Bits */
2163 #define VPE (0x0001) /* Voltage Changed during Program Error Flag */
2164 #define MGR0 (0x0010) /* Marginal read 0 mode. */
2165 #define MGR1 (0x0020) /* Marginal read 1 mode. */
2166 #define LOCKINFO (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
2167 
2168 /* FCTL4 Control Bits */
2169 #define VPE_L (0x0001) /* Voltage Changed during Program Error Flag */
2170 #define MGR0_L (0x0010) /* Marginal read 0 mode. */
2171 #define MGR1_L (0x0020) /* Marginal read 1 mode. */
2172 #define LOCKINFO_L (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
2173 
2174 #endif
2175 /************************************************************
2176 * LCD_B
2177 ************************************************************/
2178 #ifdef __MSP430_HAS_LCD_B__ /* Definition to show that Module is available */
2179 
2180 #define OFS_LCDBCTL0 (0x0000) /* LCD_B Control Register 0 */
2181 #define OFS_LCDBCTL0_L OFS_LCDBCTL0
2182 #define OFS_LCDBCTL0_H OFS_LCDBCTL0+1
2183 #define OFS_LCDBCTL1 (0x0002) /* LCD_B Control Register 1 */
2184 #define OFS_LCDBCTL1_L OFS_LCDBCTL1
2185 #define OFS_LCDBCTL1_H OFS_LCDBCTL1+1
2186 #define OFS_LCDBBLKCTL (0x0004) /* LCD_B blinking control register */
2187 #define OFS_LCDBBLKCTL_L OFS_LCDBBLKCTL
2188 #define OFS_LCDBBLKCTL_H OFS_LCDBBLKCTL+1
2189 #define OFS_LCDBMEMCTL (0x0006) /* LCD_B memory control register */
2190 #define OFS_LCDBMEMCTL_L OFS_LCDBMEMCTL
2191 #define OFS_LCDBMEMCTL_H OFS_LCDBMEMCTL+1
2192 #define OFS_LCDBVCTL (0x0008) /* LCD_B Voltage Control Register */
2193 #define OFS_LCDBVCTL_L OFS_LCDBVCTL
2194 #define OFS_LCDBVCTL_H OFS_LCDBVCTL+1
2195 #define OFS_LCDBPCTL0 (0x000A) /* LCD_B Port Control Register 0 */
2196 #define OFS_LCDBPCTL0_L OFS_LCDBPCTL0
2197 #define OFS_LCDBPCTL0_H OFS_LCDBPCTL0+1
2198 #define OFS_LCDBPCTL1 (0x000C) /* LCD_B Port Control Register 1 */
2199 #define OFS_LCDBPCTL1_L OFS_LCDBPCTL1
2200 #define OFS_LCDBPCTL1_H OFS_LCDBPCTL1+1
2201 #define OFS_LCDBPCTL2 (0x000E) /* LCD_B Port Control Register 2 */
2202 #define OFS_LCDBPCTL2_L OFS_LCDBPCTL2
2203 #define OFS_LCDBPCTL2_H OFS_LCDBPCTL2+1
2204 #define OFS_LCDBPCTL3 (0x0010) /* LCD_B Port Control Register 3 */
2205 #define OFS_LCDBPCTL3_L OFS_LCDBPCTL3
2206 #define OFS_LCDBPCTL3_H OFS_LCDBPCTL3+1
2207 #define OFS_LCDBCPCTL (0x0012) /* LCD_B Charge Pump Control Register 3 */
2208 #define OFS_LCDBCPCTL_L OFS_LCDBCPCTL
2209 #define OFS_LCDBCPCTL_H OFS_LCDBCPCTL+1
2210 #define OFS_LCDBIV (0x001E) /* LCD_B Interrupt Vector Register */
2211 
2212 // LCDBCTL0
2213 #define LCDON (0x0001) /* LCD_B LCD On */
2214 #define LCDSON (0x0004) /* LCD_B LCD Segments On */
2215 #define LCDMX0 (0x0008) /* LCD_B Mux Rate Bit: 0 */
2216 #define LCDMX1 (0x0010) /* LCD_B Mux Rate Bit: 1 */
2217 //#define RESERVED (0x0020) /* LCD_B RESERVED */
2218 //#define RESERVED (0x0040) /* LCD_B RESERVED */
2219 #define LCDSSEL (0x0080) /* LCD_B Clock Select */
2220 #define LCDPRE0 (0x0100) /* LCD_B LCD frequency pre-scaler Bit: 0 */
2221 #define LCDPRE1 (0x0200) /* LCD_B LCD frequency pre-scaler Bit: 1 */
2222 #define LCDPRE2 (0x0400) /* LCD_B LCD frequency pre-scaler Bit: 2 */
2223 #define LCDDIV0 (0x0800) /* LCD_B LCD frequency divider Bit: 0 */
2224 #define LCDDIV1 (0x1000) /* LCD_B LCD frequency divider Bit: 1 */
2225 #define LCDDIV2 (0x2000) /* LCD_B LCD frequency divider Bit: 2 */
2226 #define LCDDIV3 (0x4000) /* LCD_B LCD frequency divider Bit: 3 */
2227 #define LCDDIV4 (0x8000) /* LCD_B LCD frequency divider Bit: 4 */
2228 
2229 // LCDBCTL0
2230 #define LCDON_L (0x0001) /* LCD_B LCD On */
2231 #define LCDSON_L (0x0004) /* LCD_B LCD Segments On */
2232 #define LCDMX0_L (0x0008) /* LCD_B Mux Rate Bit: 0 */
2233 #define LCDMX1_L (0x0010) /* LCD_B Mux Rate Bit: 1 */
2234 //#define RESERVED (0x0020) /* LCD_B RESERVED */
2235 //#define RESERVED (0x0040) /* LCD_B RESERVED */
2236 #define LCDSSEL_L (0x0080) /* LCD_B Clock Select */
2237 
2238 // LCDBCTL0
2239 //#define RESERVED (0x0020) /* LCD_B RESERVED */
2240 //#define RESERVED (0x0040) /* LCD_B RESERVED */
2241 #define LCDPRE0_H (0x0001) /* LCD_B LCD frequency pre-scaler Bit: 0 */
2242 #define LCDPRE1_H (0x0002) /* LCD_B LCD frequency pre-scaler Bit: 1 */
2243 #define LCDPRE2_H (0x0004) /* LCD_B LCD frequency pre-scaler Bit: 2 */
2244 #define LCDDIV0_H (0x0008) /* LCD_B LCD frequency divider Bit: 0 */
2245 #define LCDDIV1_H (0x0010) /* LCD_B LCD frequency divider Bit: 1 */
2246 #define LCDDIV2_H (0x0020) /* LCD_B LCD frequency divider Bit: 2 */
2247 #define LCDDIV3_H (0x0040) /* LCD_B LCD frequency divider Bit: 3 */
2248 #define LCDDIV4_H (0x0080) /* LCD_B LCD frequency divider Bit: 4 */
2249 
2250 #define LCDPRE_0 (0x0000) /* LCD_B LCD frequency pre-scaler: /1 */
2251 #define LCDPRE_1 (0x0100) /* LCD_B LCD frequency pre-scaler: /2 */
2252 #define LCDPRE_2 (0x0200) /* LCD_B LCD frequency pre-scaler: /4 */
2253 #define LCDPRE_3 (0x0300) /* LCD_B LCD frequency pre-scaler: /8 */
2254 #define LCDPRE_4 (0x0400) /* LCD_B LCD frequency pre-scaler: /16 */
2255 #define LCDPRE_5 (0x0500) /* LCD_B LCD frequency pre-scaler: /32 */
2256 #define LCDPRE__1 (0x0000) /* LCD_B LCD frequency pre-scaler: /1 */
2257 #define LCDPRE__2 (0x0100) /* LCD_B LCD frequency pre-scaler: /2 */
2258 #define LCDPRE__4 (0x0200) /* LCD_B LCD frequency pre-scaler: /4 */
2259 #define LCDPRE__8 (0x0300) /* LCD_B LCD frequency pre-scaler: /8 */
2260 #define LCDPRE__16 (0x0400) /* LCD_B LCD frequency pre-scaler: /16 */
2261 #define LCDPRE__32 (0x0500) /* LCD_B LCD frequency pre-scaler: /32 */
2262 
2263 #define LCDDIV_0 (0x0000) /* LCD_B LCD frequency divider: /1 */
2264 #define LCDDIV_1 (0x0800) /* LCD_B LCD frequency divider: /2 */
2265 #define LCDDIV_2 (0x1000) /* LCD_B LCD frequency divider: /3 */
2266 #define LCDDIV_3 (0x1800) /* LCD_B LCD frequency divider: /4 */
2267 #define LCDDIV_4 (0x2000) /* LCD_B LCD frequency divider: /5 */
2268 #define LCDDIV_5 (0x2800) /* LCD_B LCD frequency divider: /6 */
2269 #define LCDDIV_6 (0x3000) /* LCD_B LCD frequency divider: /7 */
2270 #define LCDDIV_7 (0x3800) /* LCD_B LCD frequency divider: /8 */
2271 #define LCDDIV_8 (0x4000) /* LCD_B LCD frequency divider: /9 */
2272 #define LCDDIV_9 (0x4800) /* LCD_B LCD frequency divider: /10 */
2273 #define LCDDIV_10 (0x5000) /* LCD_B LCD frequency divider: /11 */
2274 #define LCDDIV_11 (0x5800) /* LCD_B LCD frequency divider: /12 */
2275 #define LCDDIV_12 (0x6000) /* LCD_B LCD frequency divider: /13 */
2276 #define LCDDIV_13 (0x6800) /* LCD_B LCD frequency divider: /14 */
2277 #define LCDDIV_14 (0x7000) /* LCD_B LCD frequency divider: /15 */
2278 #define LCDDIV_15 (0x7800) /* LCD_B LCD frequency divider: /16 */
2279 #define LCDDIV_16 (0x8000) /* LCD_B LCD frequency divider: /17 */
2280 #define LCDDIV_17 (0x8800) /* LCD_B LCD frequency divider: /18 */
2281 #define LCDDIV_18 (0x9000) /* LCD_B LCD frequency divider: /19 */
2282 #define LCDDIV_19 (0x9800) /* LCD_B LCD frequency divider: /20 */
2283 #define LCDDIV_20 (0xA000) /* LCD_B LCD frequency divider: /21 */
2284 #define LCDDIV_21 (0xA800) /* LCD_B LCD frequency divider: /22 */
2285 #define LCDDIV_22 (0xB000) /* LCD_B LCD frequency divider: /23 */
2286 #define LCDDIV_23 (0xB800) /* LCD_B LCD frequency divider: /24 */
2287 #define LCDDIV_24 (0xC000) /* LCD_B LCD frequency divider: /25 */
2288 #define LCDDIV_25 (0xC800) /* LCD_B LCD frequency divider: /26 */
2289 #define LCDDIV_26 (0xD000) /* LCD_B LCD frequency divider: /27 */
2290 #define LCDDIV_27 (0xD800) /* LCD_B LCD frequency divider: /28 */
2291 #define LCDDIV_28 (0xE000) /* LCD_B LCD frequency divider: /29 */
2292 #define LCDDIV_29 (0xE800) /* LCD_B LCD frequency divider: /30 */
2293 #define LCDDIV_30 (0xF000) /* LCD_B LCD frequency divider: /31 */
2294 #define LCDDIV_31 (0xF800) /* LCD_B LCD frequency divider: /32 */
2295 #define LCDDIV__1 (0x0000) /* LCD_B LCD frequency divider: /1 */
2296 #define LCDDIV__2 (0x0800) /* LCD_B LCD frequency divider: /2 */
2297 #define LCDDIV__3 (0x1000) /* LCD_B LCD frequency divider: /3 */
2298 #define LCDDIV__4 (0x1800) /* LCD_B LCD frequency divider: /4 */
2299 #define LCDDIV__5 (0x2000) /* LCD_B LCD frequency divider: /5 */
2300 #define LCDDIV__6 (0x2800) /* LCD_B LCD frequency divider: /6 */
2301 #define LCDDIV__7 (0x3000) /* LCD_B LCD frequency divider: /7 */
2302 #define LCDDIV__8 (0x3800) /* LCD_B LCD frequency divider: /8 */
2303 #define LCDDIV__9 (0x4000) /* LCD_B LCD frequency divider: /9 */
2304 #define LCDDIV__10 (0x4800) /* LCD_B LCD frequency divider: /10 */
2305 #define LCDDIV__11 (0x5000) /* LCD_B LCD frequency divider: /11 */
2306 #define LCDDIV__12 (0x5800) /* LCD_B LCD frequency divider: /12 */
2307 #define LCDDIV__13 (0x6000) /* LCD_B LCD frequency divider: /13 */
2308 #define LCDDIV__14 (0x6800) /* LCD_B LCD frequency divider: /14 */
2309 #define LCDDIV__15 (0x7000) /* LCD_B LCD frequency divider: /15 */
2310 #define LCDDIV__16 (0x7800) /* LCD_B LCD frequency divider: /16 */
2311 #define LCDDIV__17 (0x8000) /* LCD_B LCD frequency divider: /17 */
2312 #define LCDDIV__18 (0x8800) /* LCD_B LCD frequency divider: /18 */
2313 #define LCDDIV__19 (0x9000) /* LCD_B LCD frequency divider: /19 */
2314 #define LCDDIV__20 (0x9800) /* LCD_B LCD frequency divider: /20 */
2315 #define LCDDIV__21 (0xA000) /* LCD_B LCD frequency divider: /21 */
2316 #define LCDDIV__22 (0xA800) /* LCD_B LCD frequency divider: /22 */
2317 #define LCDDIV__23 (0xB000) /* LCD_B LCD frequency divider: /23 */
2318 #define LCDDIV__24 (0xB800) /* LCD_B LCD frequency divider: /24 */
2319 #define LCDDIV__25 (0xC000) /* LCD_B LCD frequency divider: /25 */
2320 #define LCDDIV__26 (0xC800) /* LCD_B LCD frequency divider: /26 */
2321 #define LCDDIV__27 (0xD000) /* LCD_B LCD frequency divider: /27 */
2322 #define LCDDIV__28 (0xD800) /* LCD_B LCD frequency divider: /28 */
2323 #define LCDDIV__29 (0xE000) /* LCD_B LCD frequency divider: /29 */
2324 #define LCDDIV__30 (0xE800) /* LCD_B LCD frequency divider: /30 */
2325 #define LCDDIV__31 (0xF000) /* LCD_B LCD frequency divider: /31 */
2326 #define LCDDIV__32 (0xF800) /* LCD_B LCD frequency divider: /32 */
2327 
2328 /* Display modes coded with Bits 2-4 */
2329 #define LCDSTATIC (LCDSON)
2330 #define LCD2MUX (LCDMX0+LCDSON)
2331 #define LCD3MUX (LCDMX1+LCDSON)
2332 #define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
2333 
2334 // LCDBCTL1
2335 #define LCDFRMIFG (0x0001) /* LCD_B LCD frame interrupt flag */
2336 #define LCDBLKOFFIFG (0x0002) /* LCD_B LCD blinking off interrupt flag, */
2337 #define LCDBLKONIFG (0x0004) /* LCD_B LCD blinking on interrupt flag, */
2338 #define LCDNOCAPIFG (0x0008) /* LCD_B No cpacitance connected interrupt flag */
2339 #define LCDFRMIE (0x0100) /* LCD_B LCD frame interrupt enable */
2340 #define LCDBLKOFFIE (0x0200) /* LCD_B LCD blinking off interrupt flag, */
2341 #define LCDBLKONIE (0x0400) /* LCD_B LCD blinking on interrupt flag, */
2342 #define LCDNOCAPIE (0x0800) /* LCD_B No cpacitance connected interrupt enable */
2343 
2344 // LCDBCTL1
2345 #define LCDFRMIFG_L (0x0001) /* LCD_B LCD frame interrupt flag */
2346 #define LCDBLKOFFIFG_L (0x0002) /* LCD_B LCD blinking off interrupt flag, */
2347 #define LCDBLKONIFG_L (0x0004) /* LCD_B LCD blinking on interrupt flag, */
2348 #define LCDNOCAPIFG_L (0x0008) /* LCD_B No cpacitance connected interrupt flag */
2349 
2350 // LCDBCTL1
2351 #define LCDFRMIE_H (0x0001) /* LCD_B LCD frame interrupt enable */
2352 #define LCDBLKOFFIE_H (0x0002) /* LCD_B LCD blinking off interrupt flag, */
2353 #define LCDBLKONIE_H (0x0004) /* LCD_B LCD blinking on interrupt flag, */
2354 #define LCDNOCAPIE_H (0x0008) /* LCD_B No cpacitance connected interrupt enable */
2355 
2356 // LCDBBLKCTL
2357 #define LCDBLKMOD0 (0x0001) /* LCD_B Blinking mode Bit: 0 */
2358 #define LCDBLKMOD1 (0x0002) /* LCD_B Blinking mode Bit: 1 */
2359 #define LCDBLKPRE0 (0x0004) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */
2360 #define LCDBLKPRE1 (0x0008) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */
2361 #define LCDBLKPRE2 (0x0010) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */
2362 #define LCDBLKDIV0 (0x0020) /* LCD_B Clock divider for blinking frequency Bit: 0 */
2363 #define LCDBLKDIV1 (0x0040) /* LCD_B Clock divider for blinking frequency Bit: 1 */
2364 #define LCDBLKDIV2 (0x0080) /* LCD_B Clock divider for blinking frequency Bit: 2 */
2365 
2366 // LCDBBLKCTL
2367 #define LCDBLKMOD0_L (0x0001) /* LCD_B Blinking mode Bit: 0 */
2368 #define LCDBLKMOD1_L (0x0002) /* LCD_B Blinking mode Bit: 1 */
2369 #define LCDBLKPRE0_L (0x0004) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */
2370 #define LCDBLKPRE1_L (0x0008) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */
2371 #define LCDBLKPRE2_L (0x0010) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */
2372 #define LCDBLKDIV0_L (0x0020) /* LCD_B Clock divider for blinking frequency Bit: 0 */
2373 #define LCDBLKDIV1_L (0x0040) /* LCD_B Clock divider for blinking frequency Bit: 1 */
2374 #define LCDBLKDIV2_L (0x0080) /* LCD_B Clock divider for blinking frequency Bit: 2 */
2375 
2376 #define LCDBLKMOD_0 (0x0000) /* LCD_B Blinking mode: Off */
2377 #define LCDBLKMOD_1 (0x0001) /* LCD_B Blinking mode: Individual */
2378 #define LCDBLKMOD_2 (0x0002) /* LCD_B Blinking mode: All */
2379 #define LCDBLKMOD_3 (0x0003) /* LCD_B Blinking mode: Switching */
2380 
2381 // LCDBMEMCTL
2382 #define LCDDISP (0x0001) /* LCD_B LCD memory registers for display */
2383 #define LCDCLRM (0x0002) /* LCD_B Clear LCD memory */
2384 #define LCDCLRBM (0x0004) /* LCD_B Clear LCD blinking memory */
2385 
2386 // LCDBMEMCTL
2387 #define LCDDISP_L (0x0001) /* LCD_B LCD memory registers for display */
2388 #define LCDCLRM_L (0x0002) /* LCD_B Clear LCD memory */
2389 #define LCDCLRBM_L (0x0004) /* LCD_B Clear LCD blinking memory */
2390 
2391 // LCDBVCTL
2392 #define LCD2B (0x0001) /* Selects 1/2 bias. */
2393 #define VLCDREF0 (0x0002) /* Selects reference voltage for regulated charge pump: 0 */
2394 #define VLCDREF1 (0x0004) /* Selects reference voltage for regulated charge pump: 1 */
2395 #define LCDCPEN (0x0008) /* LCD Voltage Charge Pump Enable. */
2396 #define VLCDEXT (0x0010) /* Select external source for VLCD. */
2397 #define LCDEXTBIAS (0x0020) /* V2 - V4 voltage select. */
2398 #define R03EXT (0x0040) /* Selects external connections for LCD mid voltages. */
2399 #define LCDREXT (0x0080) /* Selects external connection for lowest LCD voltage. */
2400 #define VLCD0 (0x0200) /* VLCD select: 0 */
2401 #define VLCD1 (0x0400) /* VLCD select: 1 */
2402 #define VLCD2 (0x0800) /* VLCD select: 2 */
2403 #define VLCD3 (0x1000) /* VLCD select: 3 */
2404 
2405 // LCDBVCTL
2406 #define LCD2B_L (0x0001) /* Selects 1/2 bias. */
2407 #define VLCDREF0_L (0x0002) /* Selects reference voltage for regulated charge pump: 0 */
2408 #define VLCDREF1_L (0x0004) /* Selects reference voltage for regulated charge pump: 1 */
2409 #define LCDCPEN_L (0x0008) /* LCD Voltage Charge Pump Enable. */
2410 #define VLCDEXT_L (0x0010) /* Select external source for VLCD. */
2411 #define LCDEXTBIAS_L (0x0020) /* V2 - V4 voltage select. */
2412 #define R03EXT_L (0x0040) /* Selects external connections for LCD mid voltages. */
2413 #define LCDREXT_L (0x0080) /* Selects external connection for lowest LCD voltage. */
2414 
2415 // LCDBVCTL
2416 #define VLCD0_H (0x0002) /* VLCD select: 0 */
2417 #define VLCD1_H (0x0004) /* VLCD select: 1 */
2418 #define VLCD2_H (0x0008) /* VLCD select: 2 */
2419 #define VLCD3_H (0x0010) /* VLCD select: 3 */
2420 
2421 /* Reference voltage source select for the regulated charge pump */
2422 #define VLCDREF_0 (0<<1) /* Internal */
2423 #define VLCDREF_1 (1<<1) /* External */
2424 #define VLCDREF_2 (2<<1) /* Reserved */
2425 #define VLCDREF_3 (3<<1) /* Reserved */
2426 
2427 /* Charge pump voltage selections */
2428 #define VLCD_0 (0<<9) /* Charge pump disabled */
2429 #define VLCD_1 (1<<9) /* VLCD = 2.60V */
2430 #define VLCD_2 (2<<9) /* VLCD = 2.66V */
2431 #define VLCD_3 (3<<9) /* VLCD = 2.72V */
2432 #define VLCD_4 (4<<9) /* VLCD = 2.78V */
2433 #define VLCD_5 (5<<9) /* VLCD = 2.84V */
2434 #define VLCD_6 (6<<9) /* VLCD = 2.90V */
2435 #define VLCD_7 (7<<9) /* VLCD = 2.96V */
2436 #define VLCD_8 (8<<9) /* VLCD = 3.02V */
2437 #define VLCD_9 (9<<9) /* VLCD = 3.08V */
2438 #define VLCD_10 (10<<9) /* VLCD = 3.14V */
2439 #define VLCD_11 (11<<9) /* VLCD = 3.20V */
2440 #define VLCD_12 (12<<9) /* VLCD = 3.26V */
2441 #define VLCD_13 (13<<9) /* VLCD = 3.32V */
2442 #define VLCD_14 (14<<9) /* VLCD = 3.38V */
2443 #define VLCD_15 (15<<9) /* VLCD = 3.44V */
2444 
2445 #define VLCD_DISABLED (0<<9) /* Charge pump disabled */
2446 #define VLCD_2_60 (1<<9) /* VLCD = 2.60V */
2447 #define VLCD_2_66 (2<<9) /* VLCD = 2.66V */
2448 #define VLCD_2_72 (3<<9) /* VLCD = 2.72V */
2449 #define VLCD_2_78 (4<<9) /* VLCD = 2.78V */
2450 #define VLCD_2_84 (5<<9) /* VLCD = 2.84V */
2451 #define VLCD_2_90 (6<<9) /* VLCD = 2.90V */
2452 #define VLCD_2_96 (7<<9) /* VLCD = 2.96V */
2453 #define VLCD_3_02 (8<<9) /* VLCD = 3.02V */
2454 #define VLCD_3_08 (9<<9) /* VLCD = 3.08V */
2455 #define VLCD_3_14 (10<<9) /* VLCD = 3.14V */
2456 #define VLCD_3_20 (11<<9) /* VLCD = 3.20V */
2457 #define VLCD_3_26 (12<<9) /* VLCD = 3.26V */
2458 #define VLCD_3_32 (13<<9) /* VLCD = 3.32V */
2459 #define VLCD_3_38 (14<<9) /* VLCD = 3.38V */
2460 #define VLCD_3_44 (15<<9) /* VLCD = 3.44V */
2461 
2462 // LCDBPCTL0
2463 #define LCDS0 (0x0001) /* LCD Segment 0 enable. */
2464 #define LCDS1 (0x0002) /* LCD Segment 1 enable. */
2465 #define LCDS2 (0x0004) /* LCD Segment 2 enable. */
2466 #define LCDS3 (0x0008) /* LCD Segment 3 enable. */
2467 #define LCDS4 (0x0010) /* LCD Segment 4 enable. */
2468 #define LCDS5 (0x0020) /* LCD Segment 5 enable. */
2469 #define LCDS6 (0x0040) /* LCD Segment 6 enable. */
2470 #define LCDS7 (0x0080) /* LCD Segment 7 enable. */
2471 #define LCDS8 (0x0100) /* LCD Segment 8 enable. */
2472 #define LCDS9 (0x0200) /* LCD Segment 9 enable. */
2473 #define LCDS10 (0x0400) /* LCD Segment 10 enable. */
2474 #define LCDS11 (0x0800) /* LCD Segment 11 enable. */
2475 #define LCDS12 (0x1000) /* LCD Segment 12 enable. */
2476 #define LCDS13 (0x2000) /* LCD Segment 13 enable. */
2477 #define LCDS14 (0x4000) /* LCD Segment 14 enable. */
2478 #define LCDS15 (0x8000) /* LCD Segment 15 enable. */
2479 
2480 // LCDBPCTL0
2481 #define LCDS0_L (0x0001) /* LCD Segment 0 enable. */
2482 #define LCDS1_L (0x0002) /* LCD Segment 1 enable. */
2483 #define LCDS2_L (0x0004) /* LCD Segment 2 enable. */
2484 #define LCDS3_L (0x0008) /* LCD Segment 3 enable. */
2485 #define LCDS4_L (0x0010) /* LCD Segment 4 enable. */
2486 #define LCDS5_L (0x0020) /* LCD Segment 5 enable. */
2487 #define LCDS6_L (0x0040) /* LCD Segment 6 enable. */
2488 #define LCDS7_L (0x0080) /* LCD Segment 7 enable. */
2489 
2490 // LCDBPCTL0
2491 #define LCDS8_H (0x0001) /* LCD Segment 8 enable. */
2492 #define LCDS9_H (0x0002) /* LCD Segment 9 enable. */
2493 #define LCDS10_H (0x0004) /* LCD Segment 10 enable. */
2494 #define LCDS11_H (0x0008) /* LCD Segment 11 enable. */
2495 #define LCDS12_H (0x0010) /* LCD Segment 12 enable. */
2496 #define LCDS13_H (0x0020) /* LCD Segment 13 enable. */
2497 #define LCDS14_H (0x0040) /* LCD Segment 14 enable. */
2498 #define LCDS15_H (0x0080) /* LCD Segment 15 enable. */
2499 
2500 // LCDBPCTL1
2501 #define LCDS16 (0x0001) /* LCD Segment 16 enable. */
2502 #define LCDS17 (0x0002) /* LCD Segment 17 enable. */
2503 #define LCDS18 (0x0004) /* LCD Segment 18 enable. */
2504 #define LCDS19 (0x0008) /* LCD Segment 19 enable. */
2505 #define LCDS20 (0x0010) /* LCD Segment 20 enable. */
2506 #define LCDS21 (0x0020) /* LCD Segment 21 enable. */
2507 #define LCDS22 (0x0040) /* LCD Segment 22 enable. */
2508 #define LCDS23 (0x0080) /* LCD Segment 23 enable. */
2509 #define LCDS24 (0x0100) /* LCD Segment 24 enable. */
2510 #define LCDS25 (0x0200) /* LCD Segment 25 enable. */
2511 #define LCDS26 (0x0400) /* LCD Segment 26 enable. */
2512 #define LCDS27 (0x0800) /* LCD Segment 27 enable. */
2513 #define LCDS28 (0x1000) /* LCD Segment 28 enable. */
2514 #define LCDS29 (0x2000) /* LCD Segment 29 enable. */
2515 #define LCDS30 (0x4000) /* LCD Segment 30 enable. */
2516 #define LCDS31 (0x8000) /* LCD Segment 31 enable. */
2517 
2518 // LCDBPCTL1
2519 #define LCDS16_L (0x0001) /* LCD Segment 16 enable. */
2520 #define LCDS17_L (0x0002) /* LCD Segment 17 enable. */
2521 #define LCDS18_L (0x0004) /* LCD Segment 18 enable. */
2522 #define LCDS19_L (0x0008) /* LCD Segment 19 enable. */
2523 #define LCDS20_L (0x0010) /* LCD Segment 20 enable. */
2524 #define LCDS21_L (0x0020) /* LCD Segment 21 enable. */
2525 #define LCDS22_L (0x0040) /* LCD Segment 22 enable. */
2526 #define LCDS23_L (0x0080) /* LCD Segment 23 enable. */
2527 
2528 // LCDBPCTL1
2529 #define LCDS24_H (0x0001) /* LCD Segment 24 enable. */
2530 #define LCDS25_H (0x0002) /* LCD Segment 25 enable. */
2531 #define LCDS26_H (0x0004) /* LCD Segment 26 enable. */
2532 #define LCDS27_H (0x0008) /* LCD Segment 27 enable. */
2533 #define LCDS28_H (0x0010) /* LCD Segment 28 enable. */
2534 #define LCDS29_H (0x0020) /* LCD Segment 29 enable. */
2535 #define LCDS30_H (0x0040) /* LCD Segment 30 enable. */
2536 #define LCDS31_H (0x0080) /* LCD Segment 31 enable. */
2537 
2538 // LCDBPCTL2
2539 #define LCDS32 (0x0001) /* LCD Segment 32 enable. */
2540 #define LCDS33 (0x0002) /* LCD Segment 33 enable. */
2541 #define LCDS34 (0x0004) /* LCD Segment 34 enable. */
2542 #define LCDS35 (0x0008) /* LCD Segment 35 enable. */
2543 #define LCDS36 (0x0010) /* LCD Segment 36 enable. */
2544 #define LCDS37 (0x0020) /* LCD Segment 37 enable. */
2545 #define LCDS38 (0x0040) /* LCD Segment 38 enable. */
2546 #define LCDS39 (0x0080) /* LCD Segment 39 enable. */
2547 #define LCDS40 (0x0100) /* LCD Segment 40 enable. */
2548 #define LCDS41 (0x0200) /* LCD Segment 41 enable. */
2549 #define LCDS42 (0x0400) /* LCD Segment 42 enable. */
2550 #define LCDS43 (0x0800) /* LCD Segment 43 enable. */
2551 #define LCDS44 (0x1000) /* LCD Segment 44 enable. */
2552 #define LCDS45 (0x2000) /* LCD Segment 45 enable. */
2553 #define LCDS46 (0x4000) /* LCD Segment 46 enable. */
2554 #define LCDS47 (0x8000) /* LCD Segment 47 enable. */
2555 
2556 // LCDBPCTL2
2557 #define LCDS32_L (0x0001) /* LCD Segment 32 enable. */
2558 #define LCDS33_L (0x0002) /* LCD Segment 33 enable. */
2559 #define LCDS34_L (0x0004) /* LCD Segment 34 enable. */
2560 #define LCDS35_L (0x0008) /* LCD Segment 35 enable. */
2561 #define LCDS36_L (0x0010) /* LCD Segment 36 enable. */
2562 #define LCDS37_L (0x0020) /* LCD Segment 37 enable. */
2563 #define LCDS38_L (0x0040) /* LCD Segment 38 enable. */
2564 #define LCDS39_L (0x0080) /* LCD Segment 39 enable. */
2565 
2566 // LCDBPCTL2
2567 #define LCDS40_H (0x0001) /* LCD Segment 40 enable. */
2568 #define LCDS41_H (0x0002) /* LCD Segment 41 enable. */
2569 #define LCDS42_H (0x0004) /* LCD Segment 42 enable. */
2570 #define LCDS43_H (0x0008) /* LCD Segment 43 enable. */
2571 #define LCDS44_H (0x0010) /* LCD Segment 44 enable. */
2572 #define LCDS45_H (0x0020) /* LCD Segment 45 enable. */
2573 #define LCDS46_H (0x0040) /* LCD Segment 46 enable. */
2574 #define LCDS47_H (0x0080) /* LCD Segment 47 enable. */
2575 
2576 // LCDBPCTL3
2577 #define LCDS48 (0x0001) /* LCD Segment 48 enable. */
2578 #define LCDS49 (0x0002) /* LCD Segment 49 enable. */
2579 #define LCDS50 (0x0004) /* LCD Segment 50 enable. */
2580 
2581 // LCDBPCTL3
2582 #define LCDS48_L (0x0001) /* LCD Segment 48 enable. */
2583 #define LCDS49_L (0x0002) /* LCD Segment 49 enable. */
2584 #define LCDS50_L (0x0004) /* LCD Segment 50 enable. */
2585 
2586 // LCDBCPCTL
2587 #define LCDCPDIS0 (0x0001) /* LCD charge pump disable */
2588 #define LCDCPDIS1 (0x0002) /* LCD charge pump disable */
2589 #define LCDCPDIS2 (0x0004) /* LCD charge pump disable */
2590 #define LCDCPDIS3 (0x0008) /* LCD charge pump disable */
2591 #define LCDCPDIS4 (0x0010) /* LCD charge pump disable */
2592 #define LCDCPDIS5 (0x0020) /* LCD charge pump disable */
2593 #define LCDCPDIS6 (0x0040) /* LCD charge pump disable */
2594 #define LCDCPDIS7 (0x0080) /* LCD charge pump disable */
2595 #define LCDCPCLKSYNC (0x8000) /* LCD charge pump clock synchronization */
2596 
2597 // LCDBCPCTL
2598 #define LCDCPDIS0_L (0x0001) /* LCD charge pump disable */
2599 #define LCDCPDIS1_L (0x0002) /* LCD charge pump disable */
2600 #define LCDCPDIS2_L (0x0004) /* LCD charge pump disable */
2601 #define LCDCPDIS3_L (0x0008) /* LCD charge pump disable */
2602 #define LCDCPDIS4_L (0x0010) /* LCD charge pump disable */
2603 #define LCDCPDIS5_L (0x0020) /* LCD charge pump disable */
2604 #define LCDCPDIS6_L (0x0040) /* LCD charge pump disable */
2605 #define LCDCPDIS7_L (0x0080) /* LCD charge pump disable */
2606 
2607 // LCDBCPCTL
2608 #define LCDCPCLKSYNC_H (0x0080) /* LCD charge pump clock synchronization */
2609 
2610 #define OFS_LCDM1 (0x0020) /* LCD Memory 1 */
2611 #define LCDMEM_ LCDM1 /* LCD Memory */
2612 #ifdef __ASM_HEADER__
2613 #define LCDMEM LCDM1 /* LCD Memory (for assembler) */
2614 #else
2615 #define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */
2616 #endif
2617 #define OFS_LCDM2 (0x0021) /* LCD Memory 2 */
2618 #define OFS_LCDM3 (0x0022) /* LCD Memory 3 */
2619 #define OFS_LCDM4 (0x0023) /* LCD Memory 4 */
2620 #define OFS_LCDM5 (0x0024) /* LCD Memory 5 */
2621 #define OFS_LCDM6 (0x0025) /* LCD Memory 6 */
2622 #define OFS_LCDM7 (0x0026) /* LCD Memory 7 */
2623 #define OFS_LCDM8 (0x0027) /* LCD Memory 8 */
2624 #define OFS_LCDM9 (0x0028) /* LCD Memory 9 */
2625 #define OFS_LCDM10 (0x0029) /* LCD Memory 10 */
2626 #define OFS_LCDM11 (0x002A) /* LCD Memory 11 */
2627 #define OFS_LCDM12 (0x002B) /* LCD Memory 12 */
2628 #define OFS_LCDM13 (0x002C) /* LCD Memory 13 */
2629 #define OFS_LCDM14 (0x002D) /* LCD Memory 14 */
2630 #define OFS_LCDM15 (0x002E) /* LCD Memory 15 */
2631 #define OFS_LCDM16 (0x002F) /* LCD Memory 16 */
2632 #define OFS_LCDM17 (0x0030) /* LCD Memory 17 */
2633 #define OFS_LCDM18 (0x0031) /* LCD Memory 18 */
2634 #define OFS_LCDM19 (0x0032) /* LCD Memory 19 */
2635 #define OFS_LCDM20 (0x0033) /* LCD Memory 20 */
2636 #define OFS_LCDM21 (0x0034) /* LCD Memory 21 */
2637 #define OFS_LCDM22 (0x0035) /* LCD Memory 22 */
2638 #define OFS_LCDM23 (0x0036) /* LCD Memory 23 */
2639 #define OFS_LCDM24 (0x0037) /* LCD Memory 24 */
2640 
2641 #define OFS_LCDBM1 (0x0040) /* LCD Blinking Memory 1 */
2642 #define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */
2643 #ifdef __ASM_HEADER__
2644 #define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */
2645 #else
2646 #define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */
2647 #endif
2648 #define OFS_LCDBM2 (0x0041) /* LCD Blinking Memory 2 */
2649 #define OFS_LCDBM3 (0x0042) /* LCD Blinking Memory 3 */
2650 #define OFS_LCDBM4 (0x0043) /* LCD Blinking Memory 4 */
2651 #define OFS_LCDBM5 (0x0044) /* LCD Blinking Memory 5 */
2652 #define OFS_LCDBM6 (0x0045) /* LCD Blinking Memory 6 */
2653 #define OFS_LCDBM7 (0x0046) /* LCD Blinking Memory 7 */
2654 #define OFS_LCDBM8 (0x0047) /* LCD Blinking Memory 8 */
2655 #define OFS_LCDBM9 (0x0048) /* LCD Blinking Memory 9 */
2656 #define OFS_LCDBM10 (0x0049) /* LCD Blinking Memory 10 */
2657 #define OFS_LCDBM11 (0x004A) /* LCD Blinking Memory 11 */
2658 #define OFS_LCDBM12 (0x004B) /* LCD Blinking Memory 12 */
2659 #define OFS_LCDBM13 (0x004C) /* LCD Blinking Memory 13 */
2660 #define OFS_LCDBM14 (0x004D) /* LCD Blinking Memory 14 */
2661 #define OFS_LCDBM15 (0x004E) /* LCD Blinking Memory 15 */
2662 #define OFS_LCDBM16 (0x004F) /* LCD Blinking Memory 16 */
2663 #define OFS_LCDBM17 (0x0050) /* LCD Blinking Memory 17 */
2664 #define OFS_LCDBM18 (0x0051) /* LCD Blinking Memory 18 */
2665 #define OFS_LCDBM19 (0x0052) /* LCD Blinking Memory 19 */
2666 #define OFS_LCDBM20 (0x0053) /* LCD Blinking Memory 20 */
2667 #define OFS_LCDBM21 (0x0054) /* LCD Blinking Memory 21 */
2668 #define OFS_LCDBM22 (0x0055) /* LCD Blinking Memory 22 */
2669 #define OFS_LCDBM23 (0x0056) /* LCD Blinking Memory 23 */
2670 #define OFS_LCDBM24 (0x0057) /* LCD Blinking Memory 24 */
2671 
2672 /* LCDBIV Definitions */
2673 #define LCDBIV_NONE (0x0000) /* No Interrupt pending */
2674 #define LCDBIV_LCDNOCAPIFG (0x0002) /* No capacitor connected */
2675 #define LCDBIV_LCDBLKOFFIFG (0x0004) /* Blink, segments off */
2676 #define LCDBIV_LCDBLKONIFG (0x0006) /* Blink, segments on */
2677 #define LCDBIV_LCDFRMIFG (0x0008) /* Frame interrupt */
2678 
2679 #endif
2680 /************************************************************
2681 * LCD_C
2682 ************************************************************/
2683 #ifdef __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */
2684 
2685 #define OFS_LCDCCTL0 (0x0000) /* LCD_C Control Register 0 */
2686 #define OFS_LCDCCTL0_L OFS_LCDCCTL0
2687 #define OFS_LCDCCTL0_H OFS_LCDCCTL0+1
2688 #define OFS_LCDCCTL1 (0x0002) /* LCD_C Control Register 1 */
2689 #define OFS_LCDCCTL1_L OFS_LCDCCTL1
2690 #define OFS_LCDCCTL1_H OFS_LCDCCTL1+1
2691 #define OFS_LCDCBLKCTL (0x0004) /* LCD_C blinking control register */
2692 #define OFS_LCDCBLKCTL_L OFS_LCDCBLKCTL
2693 #define OFS_LCDCBLKCTL_H OFS_LCDCBLKCTL+1
2694 #define OFS_LCDCMEMCTL (0x0006) /* LCD_C memory control register */
2695 #define OFS_LCDCMEMCTL_L OFS_LCDCMEMCTL
2696 #define OFS_LCDCMEMCTL_H OFS_LCDCMEMCTL+1
2697 #define OFS_LCDCVCTL (0x0008) /* LCD_C Voltage Control Register */
2698 #define OFS_LCDCVCTL_L OFS_LCDCVCTL
2699 #define OFS_LCDCVCTL_H OFS_LCDCVCTL+1
2700 #define OFS_LCDCPCTL0 (0x000A) /* LCD_C Port Control Register 0 */
2701 #define OFS_LCDCPCTL0_L OFS_LCDCPCTL0
2702 #define OFS_LCDCPCTL0_H OFS_LCDCPCTL0+1
2703 #define OFS_LCDCPCTL1 (0x000C) /* LCD_C Port Control Register 1 */
2704 #define OFS_LCDCPCTL1_L OFS_LCDCPCTL1
2705 #define OFS_LCDCPCTL1_H OFS_LCDCPCTL1+1
2706 #define OFS_LCDCPCTL2 (0x000E) /* LCD_C Port Control Register 2 */
2707 #define OFS_LCDCPCTL2_L OFS_LCDCPCTL2
2708 #define OFS_LCDCPCTL2_H OFS_LCDCPCTL2+1
2709 #define OFS_LCDCCPCTL (0x0012) /* LCD_C Charge Pump Control Register 3 */
2710 #define OFS_LCDCCPCTL_L OFS_LCDCCPCTL
2711 #define OFS_LCDCCPCTL_H OFS_LCDCCPCTL+1
2712 #define OFS_LCDCIV (0x001E) /* LCD_C Interrupt Vector Register */
2713 
2714 // LCDCCTL0
2715 #define LCDON (0x0001) /* LCD_C LCD On */
2716 #define LCDLP (0x0002) /* LCD_C Low Power Waveform */
2717 #define LCDSON (0x0004) /* LCD_C LCD Segments On */
2718 #define LCDMX0 (0x0008) /* LCD_C Mux Rate Bit: 0 */
2719 #define LCDMX1 (0x0010) /* LCD_C Mux Rate Bit: 1 */
2720 #define LCDMX2 (0x0020) /* LCD_C Mux Rate Bit: 2 */
2721 //#define RESERVED (0x0040) /* LCD_C RESERVED */
2722 #define LCDSSEL (0x0080) /* LCD_C Clock Select */
2723 #define LCDPRE0 (0x0100) /* LCD_C LCD frequency pre-scaler Bit: 0 */
2724 #define LCDPRE1 (0x0200) /* LCD_C LCD frequency pre-scaler Bit: 1 */
2725 #define LCDPRE2 (0x0400) /* LCD_C LCD frequency pre-scaler Bit: 2 */
2726 #define LCDDIV0 (0x0800) /* LCD_C LCD frequency divider Bit: 0 */
2727 #define LCDDIV1 (0x1000) /* LCD_C LCD frequency divider Bit: 1 */
2728 #define LCDDIV2 (0x2000) /* LCD_C LCD frequency divider Bit: 2 */
2729 #define LCDDIV3 (0x4000) /* LCD_C LCD frequency divider Bit: 3 */
2730 #define LCDDIV4 (0x8000) /* LCD_C LCD frequency divider Bit: 4 */
2731 
2732 // LCDCCTL0
2733 #define LCDON_L (0x0001) /* LCD_C LCD On */
2734 #define LCDLP_L (0x0002) /* LCD_C Low Power Waveform */
2735 #define LCDSON_L (0x0004) /* LCD_C LCD Segments On */
2736 #define LCDMX0_L (0x0008) /* LCD_C Mux Rate Bit: 0 */
2737 #define LCDMX1_L (0x0010) /* LCD_C Mux Rate Bit: 1 */
2738 #define LCDMX2_L (0x0020) /* LCD_C Mux Rate Bit: 2 */
2739 //#define RESERVED (0x0040) /* LCD_C RESERVED */
2740 #define LCDSSEL_L (0x0080) /* LCD_C Clock Select */
2741 
2742 // LCDCCTL0
2743 //#define RESERVED (0x0040) /* LCD_C RESERVED */
2744 #define LCDPRE0_H (0x0001) /* LCD_C LCD frequency pre-scaler Bit: 0 */
2745 #define LCDPRE1_H (0x0002) /* LCD_C LCD frequency pre-scaler Bit: 1 */
2746 #define LCDPRE2_H (0x0004) /* LCD_C LCD frequency pre-scaler Bit: 2 */
2747 #define LCDDIV0_H (0x0008) /* LCD_C LCD frequency divider Bit: 0 */
2748 #define LCDDIV1_H (0x0010) /* LCD_C LCD frequency divider Bit: 1 */
2749 #define LCDDIV2_H (0x0020) /* LCD_C LCD frequency divider Bit: 2 */
2750 #define LCDDIV3_H (0x0040) /* LCD_C LCD frequency divider Bit: 3 */
2751 #define LCDDIV4_H (0x0080) /* LCD_C LCD frequency divider Bit: 4 */
2752 
2753 #define LCDPRE_0 (0x0000) /* LCD_C LCD frequency pre-scaler: /1 */
2754 #define LCDPRE_1 (0x0100) /* LCD_C LCD frequency pre-scaler: /2 */
2755 #define LCDPRE_2 (0x0200) /* LCD_C LCD frequency pre-scaler: /4 */
2756 #define LCDPRE_3 (0x0300) /* LCD_C LCD frequency pre-scaler: /8 */
2757 #define LCDPRE_4 (0x0400) /* LCD_C LCD frequency pre-scaler: /16 */
2758 #define LCDPRE_5 (0x0500) /* LCD_C LCD frequency pre-scaler: /32 */
2759 #define LCDPRE__1 (0x0000) /* LCD_C LCD frequency pre-scaler: /1 */
2760 #define LCDPRE__2 (0x0100) /* LCD_C LCD frequency pre-scaler: /2 */
2761 #define LCDPRE__4 (0x0200) /* LCD_C LCD frequency pre-scaler: /4 */
2762 #define LCDPRE__8 (0x0300) /* LCD_C LCD frequency pre-scaler: /8 */
2763 #define LCDPRE__16 (0x0400) /* LCD_C LCD frequency pre-scaler: /16 */
2764 #define LCDPRE__32 (0x0500) /* LCD_C LCD frequency pre-scaler: /32 */
2765 
2766 #define LCDDIV_0 (0x0000) /* LCD_C LCD frequency divider: /1 */
2767 #define LCDDIV_1 (0x0800) /* LCD_C LCD frequency divider: /2 */
2768 #define LCDDIV_2 (0x1000) /* LCD_C LCD frequency divider: /3 */
2769 #define LCDDIV_3 (0x1800) /* LCD_C LCD frequency divider: /4 */
2770 #define LCDDIV_4 (0x2000) /* LCD_C LCD frequency divider: /5 */
2771 #define LCDDIV_5 (0x2800) /* LCD_C LCD frequency divider: /6 */
2772 #define LCDDIV_6 (0x3000) /* LCD_C LCD frequency divider: /7 */
2773 #define LCDDIV_7 (0x3800) /* LCD_C LCD frequency divider: /8 */
2774 #define LCDDIV_8 (0x4000) /* LCD_C LCD frequency divider: /9 */
2775 #define LCDDIV_9 (0x4800) /* LCD_C LCD frequency divider: /10 */
2776 #define LCDDIV_10 (0x5000) /* LCD_C LCD frequency divider: /11 */
2777 #define LCDDIV_11 (0x5800) /* LCD_C LCD frequency divider: /12 */
2778 #define LCDDIV_12 (0x6000) /* LCD_C LCD frequency divider: /13 */
2779 #define LCDDIV_13 (0x6800) /* LCD_C LCD frequency divider: /14 */
2780 #define LCDDIV_14 (0x7000) /* LCD_C LCD frequency divider: /15 */
2781 #define LCDDIV_15 (0x7800) /* LCD_C LCD frequency divider: /16 */
2782 #define LCDDIV_16 (0x8000) /* LCD_C LCD frequency divider: /17 */
2783 #define LCDDIV_17 (0x8800) /* LCD_C LCD frequency divider: /18 */
2784 #define LCDDIV_18 (0x9000) /* LCD_C LCD frequency divider: /19 */
2785 #define LCDDIV_19 (0x9800) /* LCD_C LCD frequency divider: /20 */
2786 #define LCDDIV_20 (0xA000) /* LCD_C LCD frequency divider: /21 */
2787 #define LCDDIV_21 (0xA800) /* LCD_C LCD frequency divider: /22 */
2788 #define LCDDIV_22 (0xB000) /* LCD_C LCD frequency divider: /23 */
2789 #define LCDDIV_23 (0xB800) /* LCD_C LCD frequency divider: /24 */
2790 #define LCDDIV_24 (0xC000) /* LCD_C LCD frequency divider: /25 */
2791 #define LCDDIV_25 (0xC800) /* LCD_C LCD frequency divider: /26 */
2792 #define LCDDIV_26 (0xD000) /* LCD_C LCD frequency divider: /27 */
2793 #define LCDDIV_27 (0xD800) /* LCD_C LCD frequency divider: /28 */
2794 #define LCDDIV_28 (0xE000) /* LCD_C LCD frequency divider: /29 */
2795 #define LCDDIV_29 (0xE800) /* LCD_C LCD frequency divider: /30 */
2796 #define LCDDIV_30 (0xF000) /* LCD_C LCD frequency divider: /31 */
2797 #define LCDDIV_31 (0xF800) /* LCD_C LCD frequency divider: /32 */
2798 #define LCDDIV__1 (0x0000) /* LCD_C LCD frequency divider: /1 */
2799 #define LCDDIV__2 (0x0800) /* LCD_C LCD frequency divider: /2 */
2800 #define LCDDIV__3 (0x1000) /* LCD_C LCD frequency divider: /3 */
2801 #define LCDDIV__4 (0x1800) /* LCD_C LCD frequency divider: /4 */
2802 #define LCDDIV__5 (0x2000) /* LCD_C LCD frequency divider: /5 */
2803 #define LCDDIV__6 (0x2800) /* LCD_C LCD frequency divider: /6 */
2804 #define LCDDIV__7 (0x3000) /* LCD_C LCD frequency divider: /7 */
2805 #define LCDDIV__8 (0x3800) /* LCD_C LCD frequency divider: /8 */
2806 #define LCDDIV__9 (0x4000) /* LCD_C LCD frequency divider: /9 */
2807 #define LCDDIV__10 (0x4800) /* LCD_C LCD frequency divider: /10 */
2808 #define LCDDIV__11 (0x5000) /* LCD_C LCD frequency divider: /11 */
2809 #define LCDDIV__12 (0x5800) /* LCD_C LCD frequency divider: /12 */
2810 #define LCDDIV__13 (0x6000) /* LCD_C LCD frequency divider: /13 */
2811 #define LCDDIV__14 (0x6800) /* LCD_C LCD frequency divider: /14 */
2812 #define LCDDIV__15 (0x7000) /* LCD_C LCD frequency divider: /15 */
2813 #define LCDDIV__16 (0x7800) /* LCD_C LCD frequency divider: /16 */
2814 #define LCDDIV__17 (0x8000) /* LCD_C LCD frequency divider: /17 */
2815 #define LCDDIV__18 (0x8800) /* LCD_C LCD frequency divider: /18 */
2816 #define LCDDIV__19 (0x9000) /* LCD_C LCD frequency divider: /19 */
2817 #define LCDDIV__20 (0x9800) /* LCD_C LCD frequency divider: /20 */
2818 #define LCDDIV__21 (0xA000) /* LCD_C LCD frequency divider: /21 */
2819 #define LCDDIV__22 (0xA800) /* LCD_C LCD frequency divider: /22 */
2820 #define LCDDIV__23 (0xB000) /* LCD_C LCD frequency divider: /23 */
2821 #define LCDDIV__24 (0xB800) /* LCD_C LCD frequency divider: /24 */
2822 #define LCDDIV__25 (0xC000) /* LCD_C LCD frequency divider: /25 */
2823 #define LCDDIV__26 (0xC800) /* LCD_C LCD frequency divider: /26 */
2824 #define LCDDIV__27 (0xD000) /* LCD_C LCD frequency divider: /27 */
2825 #define LCDDIV__28 (0xD800) /* LCD_C LCD frequency divider: /28 */
2826 #define LCDDIV__29 (0xE000) /* LCD_C LCD frequency divider: /29 */
2827 #define LCDDIV__30 (0xE800) /* LCD_C LCD frequency divider: /30 */
2828 #define LCDDIV__31 (0xF000) /* LCD_C LCD frequency divider: /31 */
2829 #define LCDDIV__32 (0xF800) /* LCD_C LCD frequency divider: /32 */
2830 
2831 /* Display modes coded with Bits 2-4 */
2832 #define LCDSTATIC (LCDSON)
2833 #define LCD2MUX (LCDMX0+LCDSON)
2834 #define LCD3MUX (LCDMX1+LCDSON)
2835 #define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
2836 #define LCD5MUX (LCDMX2+LCDSON)
2837 #define LCD6MUX (LCDMX2+LCDMX0+LCDSON)
2838 #define LCD7MUX (LCDMX2+LCDMX1+LCDSON)
2839 #define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON)
2840 
2841 // LCDCCTL1
2842 #define LCDFRMIFG (0x0001) /* LCD_C LCD frame interrupt flag */
2843 #define LCDBLKOFFIFG (0x0002) /* LCD_C LCD blinking off interrupt flag, */
2844 #define LCDBLKONIFG (0x0004) /* LCD_C LCD blinking on interrupt flag, */
2845 #define LCDNOCAPIFG (0x0008) /* LCD_C No cpacitance connected interrupt flag */
2846 #define LCDFRMIE (0x0100) /* LCD_C LCD frame interrupt enable */
2847 #define LCDBLKOFFIE (0x0200) /* LCD_C LCD blinking off interrupt flag, */
2848 #define LCDBLKONIE (0x0400) /* LCD_C LCD blinking on interrupt flag, */
2849 #define LCDNOCAPIE (0x0800) /* LCD_C No cpacitance connected interrupt enable */
2850 
2851 // LCDCCTL1
2852 #define LCDFRMIFG_L (0x0001) /* LCD_C LCD frame interrupt flag */
2853 #define LCDBLKOFFIFG_L (0x0002) /* LCD_C LCD blinking off interrupt flag, */
2854 #define LCDBLKONIFG_L (0x0004) /* LCD_C LCD blinking on interrupt flag, */
2855 #define LCDNOCAPIFG_L (0x0008) /* LCD_C No cpacitance connected interrupt flag */
2856 
2857 // LCDCCTL1
2858 #define LCDFRMIE_H (0x0001) /* LCD_C LCD frame interrupt enable */
2859 #define LCDBLKOFFIE_H (0x0002) /* LCD_C LCD blinking off interrupt flag, */
2860 #define LCDBLKONIE_H (0x0004) /* LCD_C LCD blinking on interrupt flag, */
2861 #define LCDNOCAPIE_H (0x0008) /* LCD_C No cpacitance connected interrupt enable */
2862 
2863 // LCDCBLKCTL
2864 #define LCDBLKMOD0 (0x0001) /* LCD_C Blinking mode Bit: 0 */
2865 #define LCDBLKMOD1 (0x0002) /* LCD_C Blinking mode Bit: 1 */
2866 #define LCDBLKPRE0 (0x0004) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */
2867 #define LCDBLKPRE1 (0x0008) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */
2868 #define LCDBLKPRE2 (0x0010) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */
2869 #define LCDBLKDIV0 (0x0020) /* LCD_C Clock divider for blinking frequency Bit: 0 */
2870 #define LCDBLKDIV1 (0x0040) /* LCD_C Clock divider for blinking frequency Bit: 1 */
2871 #define LCDBLKDIV2 (0x0080) /* LCD_C Clock divider for blinking frequency Bit: 2 */
2872 
2873 // LCDCBLKCTL
2874 #define LCDBLKMOD0_L (0x0001) /* LCD_C Blinking mode Bit: 0 */
2875 #define LCDBLKMOD1_L (0x0002) /* LCD_C Blinking mode Bit: 1 */
2876 #define LCDBLKPRE0_L (0x0004) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */
2877 #define LCDBLKPRE1_L (0x0008) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */
2878 #define LCDBLKPRE2_L (0x0010) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */
2879 #define LCDBLKDIV0_L (0x0020) /* LCD_C Clock divider for blinking frequency Bit: 0 */
2880 #define LCDBLKDIV1_L (0x0040) /* LCD_C Clock divider for blinking frequency Bit: 1 */
2881 #define LCDBLKDIV2_L (0x0080) /* LCD_C Clock divider for blinking frequency Bit: 2 */
2882 
2883 #define LCDBLKMOD_0 (0x0000) /* LCD_C Blinking mode: Off */
2884 #define LCDBLKMOD_1 (0x0001) /* LCD_C Blinking mode: Individual */
2885 #define LCDBLKMOD_2 (0x0002) /* LCD_C Blinking mode: All */
2886 #define LCDBLKMOD_3 (0x0003) /* LCD_C Blinking mode: Switching */
2887 
2888 // LCDCMEMCTL
2889 #define LCDDISP (0x0001) /* LCD_C LCD memory registers for display */
2890 #define LCDCLRM (0x0002) /* LCD_C Clear LCD memory */
2891 #define LCDCLRBM (0x0004) /* LCD_C Clear LCD blinking memory */
2892 
2893 // LCDCMEMCTL
2894 #define LCDDISP_L (0x0001) /* LCD_C LCD memory registers for display */
2895 #define LCDCLRM_L (0x0002) /* LCD_C Clear LCD memory */
2896 #define LCDCLRBM_L (0x0004) /* LCD_C Clear LCD blinking memory */
2897 
2898 // LCDCVCTL
2899 #define LCD2B (0x0001) /* Selects 1/2 bias. */
2900 #define VLCDREF0 (0x0002) /* Selects reference voltage for regulated charge pump: 0 */
2901 #define VLCDREF1 (0x0004) /* Selects reference voltage for regulated charge pump: 1 */
2902 #define LCDCPEN (0x0008) /* LCD Voltage Charge Pump Enable. */
2903 #define VLCDEXT (0x0010) /* Select external source for VLCD. */
2904 #define LCDEXTBIAS (0x0020) /* V2 - V4 voltage select. */
2905 #define R03EXT (0x0040) /* Selects external connections for LCD mid voltages. */
2906 #define LCDREXT (0x0080) /* Selects external connection for lowest LCD voltage. */
2907 #define VLCD0 (0x0200) /* VLCD select: 0 */
2908 #define VLCD1 (0x0400) /* VLCD select: 1 */
2909 #define VLCD2 (0x0800) /* VLCD select: 2 */
2910 #define VLCD3 (0x1000) /* VLCD select: 3 */
2911 #define VLCD4 (0x2000) /* VLCD select: 4 */
2912 #define VLCD5 (0x4000) /* VLCD select: 5 */
2913 
2914 // LCDCVCTL
2915 #define LCD2B_L (0x0001) /* Selects 1/2 bias. */
2916 #define VLCDREF0_L (0x0002) /* Selects reference voltage for regulated charge pump: 0 */
2917 #define VLCDREF1_L (0x0004) /* Selects reference voltage for regulated charge pump: 1 */
2918 #define LCDCPEN_L (0x0008) /* LCD Voltage Charge Pump Enable. */
2919 #define VLCDEXT_L (0x0010) /* Select external source for VLCD. */
2920 #define LCDEXTBIAS_L (0x0020) /* V2 - V4 voltage select. */
2921 #define R03EXT_L (0x0040) /* Selects external connections for LCD mid voltages. */
2922 #define LCDREXT_L (0x0080) /* Selects external connection for lowest LCD voltage. */
2923 
2924 // LCDCVCTL
2925 #define VLCD0_H (0x0002) /* VLCD select: 0 */
2926 #define VLCD1_H (0x0004) /* VLCD select: 1 */
2927 #define VLCD2_H (0x0008) /* VLCD select: 2 */
2928 #define VLCD3_H (0x0010) /* VLCD select: 3 */
2929 #define VLCD4_H (0x0020) /* VLCD select: 4 */
2930 #define VLCD5_H (0x0040) /* VLCD select: 5 */
2931 
2932 /* Reference voltage source select for the regulated charge pump */
2933 #define VLCDREF_0 (0x0000) /* Internal */
2934 #define VLCDREF_1 (0x0002) /* External */
2935 #define VLCDREF_2 (0x0004) /* Reserved */
2936 #define VLCDREF_3 (0x0006) /* Reserved */
2937 
2938 /* Charge pump voltage selections */
2939 #define VLCD_0 (0x0000) /* Charge pump disabled */
2940 #define VLCD_1 (0x0200) /* VLCD = 2.60V */
2941 #define VLCD_2 (0x0400) /* VLCD = 2.66V */
2942 #define VLCD_3 (0x0600) /* VLCD = 2.72V */
2943 #define VLCD_4 (0x0800) /* VLCD = 2.78V */
2944 #define VLCD_5 (0x0A00) /* VLCD = 2.84V */
2945 #define VLCD_6 (0x0C00) /* VLCD = 2.90V */
2946 #define VLCD_7 (0x0E00) /* VLCD = 2.96V */
2947 #define VLCD_8 (0x1000) /* VLCD = 3.02V */
2948 #define VLCD_9 (0x1200) /* VLCD = 3.08V */
2949 #define VLCD_10 (0x1400) /* VLCD = 3.14V */
2950 #define VLCD_11 (0x1600) /* VLCD = 3.20V */
2951 #define VLCD_12 (0x1800) /* VLCD = 3.26V */
2952 #define VLCD_13 (0x1A00) /* VLCD = 3.32V */
2953 #define VLCD_14 (0x1C00) /* VLCD = 3.38V */
2954 #define VLCD_15 (0x1E00) /* VLCD = 3.44V */
2955 
2956 #define VLCD_DISABLED (0x0000) /* Charge pump disabled */
2957 #define VLCD_2_60 (0x0200) /* VLCD = 2.60V */
2958 #define VLCD_2_66 (0x0400) /* VLCD = 2.66V */
2959 #define VLCD_2_72 (0x0600) /* VLCD = 2.72V */
2960 #define VLCD_2_78 (0x0800) /* VLCD = 2.78V */
2961 #define VLCD_2_84 (0x0A00) /* VLCD = 2.84V */
2962 #define VLCD_2_90 (0x0C00) /* VLCD = 2.90V */
2963 #define VLCD_2_96 (0x0E00) /* VLCD = 2.96V */
2964 #define VLCD_3_02 (0x1000) /* VLCD = 3.02V */
2965 #define VLCD_3_08 (0x1200) /* VLCD = 3.08V */
2966 #define VLCD_3_14 (0x1400) /* VLCD = 3.14V */
2967 #define VLCD_3_20 (0x1600) /* VLCD = 3.20V */
2968 #define VLCD_3_26 (0x1800) /* VLCD = 3.26V */
2969 #define VLCD_3_32 (0x1A00) /* VLCD = 3.32V */
2970 #define VLCD_3_38 (0x1C00) /* VLCD = 3.38V */
2971 #define VLCD_3_44 (0x1E00) /* VLCD = 3.44V */
2972 
2973 // LCDCPCTL0
2974 #define LCDS0 (0x0001) /* LCD Segment 0 enable. */
2975 #define LCDS1 (0x0002) /* LCD Segment 1 enable. */
2976 #define LCDS2 (0x0004) /* LCD Segment 2 enable. */
2977 #define LCDS3 (0x0008) /* LCD Segment 3 enable. */
2978 #define LCDS4 (0x0010) /* LCD Segment 4 enable. */
2979 #define LCDS5 (0x0020) /* LCD Segment 5 enable. */
2980 #define LCDS6 (0x0040) /* LCD Segment 6 enable. */
2981 #define LCDS7 (0x0080) /* LCD Segment 7 enable. */
2982 #define LCDS8 (0x0100) /* LCD Segment 8 enable. */
2983 #define LCDS9 (0x0200) /* LCD Segment 9 enable. */
2984 #define LCDS10 (0x0400) /* LCD Segment 10 enable. */
2985 #define LCDS11 (0x0800) /* LCD Segment 11 enable. */
2986 #define LCDS12 (0x1000) /* LCD Segment 12 enable. */
2987 #define LCDS13 (0x2000) /* LCD Segment 13 enable. */
2988 #define LCDS14 (0x4000) /* LCD Segment 14 enable. */
2989 #define LCDS15 (0x8000) /* LCD Segment 15 enable. */
2990 
2991 // LCDCPCTL0
2992 #define LCDS0_L (0x0001) /* LCD Segment 0 enable. */
2993 #define LCDS1_L (0x0002) /* LCD Segment 1 enable. */
2994 #define LCDS2_L (0x0004) /* LCD Segment 2 enable. */
2995 #define LCDS3_L (0x0008) /* LCD Segment 3 enable. */
2996 #define LCDS4_L (0x0010) /* LCD Segment 4 enable. */
2997 #define LCDS5_L (0x0020) /* LCD Segment 5 enable. */
2998 #define LCDS6_L (0x0040) /* LCD Segment 6 enable. */
2999 #define LCDS7_L (0x0080) /* LCD Segment 7 enable. */
3000 
3001 // LCDCPCTL0
3002 #define LCDS8_H (0x0001) /* LCD Segment 8 enable. */
3003 #define LCDS9_H (0x0002) /* LCD Segment 9 enable. */
3004 #define LCDS10_H (0x0004) /* LCD Segment 10 enable. */
3005 #define LCDS11_H (0x0008) /* LCD Segment 11 enable. */
3006 #define LCDS12_H (0x0010) /* LCD Segment 12 enable. */
3007 #define LCDS13_H (0x0020) /* LCD Segment 13 enable. */
3008 #define LCDS14_H (0x0040) /* LCD Segment 14 enable. */
3009 #define LCDS15_H (0x0080) /* LCD Segment 15 enable. */
3010 
3011 // LCDCPCTL1
3012 #define LCDS16 (0x0001) /* LCD Segment 16 enable. */
3013 #define LCDS17 (0x0002) /* LCD Segment 17 enable. */
3014 #define LCDS18 (0x0004) /* LCD Segment 18 enable. */
3015 #define LCDS19 (0x0008) /* LCD Segment 19 enable. */
3016 #define LCDS20 (0x0010) /* LCD Segment 20 enable. */
3017 #define LCDS21 (0x0020) /* LCD Segment 21 enable. */
3018 #define LCDS22 (0x0040) /* LCD Segment 22 enable. */
3019 #define LCDS23 (0x0080) /* LCD Segment 23 enable. */
3020 #define LCDS24 (0x0100) /* LCD Segment 24 enable. */
3021 #define LCDS25 (0x0200) /* LCD Segment 25 enable. */
3022 #define LCDS26 (0x0400) /* LCD Segment 26 enable. */
3023 #define LCDS27 (0x0800) /* LCD Segment 27 enable. */
3024 #define LCDS28 (0x1000) /* LCD Segment 28 enable. */
3025 #define LCDS29 (0x2000) /* LCD Segment 29 enable. */
3026 #define LCDS30 (0x4000) /* LCD Segment 30 enable. */
3027 #define LCDS31 (0x8000) /* LCD Segment 31 enable. */
3028 
3029 // LCDCPCTL1
3030 #define LCDS16_L (0x0001) /* LCD Segment 16 enable. */
3031 #define LCDS17_L (0x0002) /* LCD Segment 17 enable. */
3032 #define LCDS18_L (0x0004) /* LCD Segment 18 enable. */
3033 #define LCDS19_L (0x0008) /* LCD Segment 19 enable. */
3034 #define LCDS20_L (0x0010) /* LCD Segment 20 enable. */
3035 #define LCDS21_L (0x0020) /* LCD Segment 21 enable. */
3036 #define LCDS22_L (0x0040) /* LCD Segment 22 enable. */
3037 #define LCDS23_L (0x0080) /* LCD Segment 23 enable. */
3038 
3039 // LCDCPCTL1
3040 #define LCDS24_H (0x0001) /* LCD Segment 24 enable. */
3041 #define LCDS25_H (0x0002) /* LCD Segment 25 enable. */
3042 #define LCDS26_H (0x0004) /* LCD Segment 26 enable. */
3043 #define LCDS27_H (0x0008) /* LCD Segment 27 enable. */
3044 #define LCDS28_H (0x0010) /* LCD Segment 28 enable. */
3045 #define LCDS29_H (0x0020) /* LCD Segment 29 enable. */
3046 #define LCDS30_H (0x0040) /* LCD Segment 30 enable. */
3047 #define LCDS31_H (0x0080) /* LCD Segment 31 enable. */
3048 
3049 // LCDCPCTL2
3050 #define LCDS32 (0x0001) /* LCD Segment 32 enable. */
3051 #define LCDS33 (0x0002) /* LCD Segment 33 enable. */
3052 #define LCDS34 (0x0004) /* LCD Segment 34 enable. */
3053 #define LCDS35 (0x0008) /* LCD Segment 35 enable. */
3054 #define LCDS36 (0x0010) /* LCD Segment 36 enable. */
3055 #define LCDS37 (0x0020) /* LCD Segment 37 enable. */
3056 #define LCDS38 (0x0040) /* LCD Segment 38 enable. */
3057 #define LCDS39 (0x0080) /* LCD Segment 39 enable. */
3058 #define LCDS40 (0x0100) /* LCD Segment 40 enable. */
3059 #define LCDS41 (0x0200) /* LCD Segment 41 enable. */
3060 #define LCDS42 (0x0400) /* LCD Segment 42 enable. */
3061 #define LCDS43 (0x0800) /* LCD Segment 43 enable. */
3062 #define LCDS44 (0x1000) /* LCD Segment 44 enable. */
3063 #define LCDS45 (0x2000) /* LCD Segment 45 enable. */
3064 #define LCDS46 (0x4000) /* LCD Segment 46 enable. */
3065 #define LCDS47 (0x8000) /* LCD Segment 47 enable. */
3066 
3067 // LCDCPCTL2
3068 #define LCDS32_L (0x0001) /* LCD Segment 32 enable. */
3069 #define LCDS33_L (0x0002) /* LCD Segment 33 enable. */
3070 #define LCDS34_L (0x0004) /* LCD Segment 34 enable. */
3071 #define LCDS35_L (0x0008) /* LCD Segment 35 enable. */
3072 #define LCDS36_L (0x0010) /* LCD Segment 36 enable. */
3073 #define LCDS37_L (0x0020) /* LCD Segment 37 enable. */
3074 #define LCDS38_L (0x0040) /* LCD Segment 38 enable. */
3075 #define LCDS39_L (0x0080) /* LCD Segment 39 enable. */
3076 
3077 // LCDCPCTL2
3078 #define LCDS40_H (0x0001) /* LCD Segment 40 enable. */
3079 #define LCDS41_H (0x0002) /* LCD Segment 41 enable. */
3080 #define LCDS42_H (0x0004) /* LCD Segment 42 enable. */
3081 #define LCDS43_H (0x0008) /* LCD Segment 43 enable. */
3082 #define LCDS44_H (0x0010) /* LCD Segment 44 enable. */
3083 #define LCDS45_H (0x0020) /* LCD Segment 45 enable. */
3084 #define LCDS46_H (0x0040) /* LCD Segment 46 enable. */
3085 #define LCDS47_H (0x0080) /* LCD Segment 47 enable. */
3086 
3087 // LCDCCPCTL
3088 #define LCDCPDIS0 (0x0001) /* LCD charge pump disable */
3089 #define LCDCPDIS1 (0x0002) /* LCD charge pump disable */
3090 #define LCDCPDIS2 (0x0004) /* LCD charge pump disable */
3091 #define LCDCPDIS3 (0x0008) /* LCD charge pump disable */
3092 #define LCDCPDIS4 (0x0010) /* LCD charge pump disable */
3093 #define LCDCPDIS5 (0x0020) /* LCD charge pump disable */
3094 #define LCDCPDIS6 (0x0040) /* LCD charge pump disable */
3095 #define LCDCPDIS7 (0x0080) /* LCD charge pump disable */
3096 #define LCDCPCLKSYNC (0x8000) /* LCD charge pump clock synchronization */
3097 
3098 // LCDCCPCTL
3099 #define LCDCPDIS0_L (0x0001) /* LCD charge pump disable */
3100 #define LCDCPDIS1_L (0x0002) /* LCD charge pump disable */
3101 #define LCDCPDIS2_L (0x0004) /* LCD charge pump disable */
3102 #define LCDCPDIS3_L (0x0008) /* LCD charge pump disable */
3103 #define LCDCPDIS4_L (0x0010) /* LCD charge pump disable */
3104 #define LCDCPDIS5_L (0x0020) /* LCD charge pump disable */
3105 #define LCDCPDIS6_L (0x0040) /* LCD charge pump disable */
3106 #define LCDCPDIS7_L (0x0080) /* LCD charge pump disable */
3107 
3108 // LCDCCPCTL
3109 #define LCDCPCLKSYNC_H (0x0080) /* LCD charge pump clock synchronization */
3110 
3111 #define OFS_LCDM1 (0x0020) /* LCD Memory 1 */
3112 #define LCDMEM_ LCDM1 /* LCD Memory */
3113 #ifdef __ASM_HEADER__
3114 #define LCDMEM LCDM1 /* LCD Memory (for assembler) */
3115 #else
3116 #define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */
3117 #endif
3118 #define OFS_LCDM2 (0x0021) /* LCD Memory 2 */
3119 #define OFS_LCDM3 (0x0022) /* LCD Memory 3 */
3120 #define OFS_LCDM4 (0x0023) /* LCD Memory 4 */
3121 #define OFS_LCDM5 (0x0024) /* LCD Memory 5 */
3122 #define OFS_LCDM6 (0x0025) /* LCD Memory 6 */
3123 #define OFS_LCDM7 (0x0026) /* LCD Memory 7 */
3124 #define OFS_LCDM8 (0x0027) /* LCD Memory 8 */
3125 #define OFS_LCDM9 (0x0028) /* LCD Memory 9 */
3126 #define OFS_LCDM10 (0x0029) /* LCD Memory 10 */
3127 #define OFS_LCDM11 (0x002A) /* LCD Memory 11 */
3128 #define OFS_LCDM12 (0x002B) /* LCD Memory 12 */
3129 #define OFS_LCDM13 (0x002C) /* LCD Memory 13 */
3130 #define OFS_LCDM14 (0x002D) /* LCD Memory 14 */
3131 #define OFS_LCDM15 (0x002E) /* LCD Memory 15 */
3132 #define OFS_LCDM16 (0x002F) /* LCD Memory 16 */
3133 #define OFS_LCDM17 (0x0030) /* LCD Memory 17 */
3134 #define OFS_LCDM18 (0x0031) /* LCD Memory 18 */
3135 #define OFS_LCDM19 (0x0032) /* LCD Memory 19 */
3136 #define OFS_LCDM20 (0x0033) /* LCD Memory 20 */
3137 #define OFS_LCDM21 (0x0034) /* LCD Memory 21 */
3138 #define OFS_LCDM22 (0x0035) /* LCD Memory 22 */
3139 #define OFS_LCDM23 (0x0036) /* LCD Memory 23 */
3140 #define OFS_LCDM24 (0x0037) /* LCD Memory 24 */
3141 #define OFS_LCDM25 (0x0038) /* LCD Memory 25 */
3142 #define OFS_LCDM26 (0x0039) /* LCD Memory 26 */
3143 #define OFS_LCDM27 (0x003A) /* LCD Memory 27 */
3144 #define OFS_LCDM28 (0x003B) /* LCD Memory 28 */
3145 #define OFS_LCDM29 (0x003C) /* LCD Memory 29 */
3146 #define OFS_LCDM30 (0x003D) /* LCD Memory 30 */
3147 #define OFS_LCDM31 (0x003E) /* LCD Memory 31 */
3148 #define OFS_LCDM32 (0x003F) /* LCD Memory 32 */
3149 #define OFS_LCDM33 (0x0040) /* LCD Memory 33 */
3150 #define OFS_LCDM34 (0x0041) /* LCD Memory 34 */
3151 #define OFS_LCDM35 (0x0042) /* LCD Memory 35 */
3152 #define OFS_LCDM36 (0x0043) /* LCD Memory 36 */
3153 #define OFS_LCDM37 (0x0044) /* LCD Memory 37 */
3154 #define OFS_LCDM38 (0x0045) /* LCD Memory 38 */
3155 #define OFS_LCDM39 (0x0046) /* LCD Memory 39 */
3156 #define OFS_LCDM40 (0x0047) /* LCD Memory 40 */
3157 
3158 #define OFS_LCDBM1 (0x0040) /* LCD Blinking Memory 1 */
3159 #define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */
3160 #ifdef __ASM_HEADER__
3161 #define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */
3162 #else
3163 #define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */
3164 #endif
3165 #define OFS_LCDBM2 (0x0041) /* LCD Blinking Memory 2 */
3166 #define OFS_LCDBM3 (0x0042) /* LCD Blinking Memory 3 */
3167 #define OFS_LCDBM4 (0x0043) /* LCD Blinking Memory 4 */
3168 #define OFS_LCDBM5 (0x0044) /* LCD Blinking Memory 5 */
3169 #define OFS_LCDBM6 (0x0045) /* LCD Blinking Memory 6 */
3170 #define OFS_LCDBM7 (0x0046) /* LCD Blinking Memory 7 */
3171 #define OFS_LCDBM8 (0x0047) /* LCD Blinking Memory 8 */
3172 #define OFS_LCDBM9 (0x0048) /* LCD Blinking Memory 9 */
3173 #define OFS_LCDBM10 (0x0049) /* LCD Blinking Memory 10 */
3174 #define OFS_LCDBM11 (0x004A) /* LCD Blinking Memory 11 */
3175 #define OFS_LCDBM12 (0x004B) /* LCD Blinking Memory 12 */
3176 #define OFS_LCDBM13 (0x004C) /* LCD Blinking Memory 13 */
3177 #define OFS_LCDBM14 (0x004D) /* LCD Blinking Memory 14 */
3178 #define OFS_LCDBM15 (0x004E) /* LCD Blinking Memory 15 */
3179 #define OFS_LCDBM16 (0x004F) /* LCD Blinking Memory 16 */
3180 #define OFS_LCDBM17 (0x0050) /* LCD Blinking Memory 17 */
3181 #define OFS_LCDBM18 (0x0051) /* LCD Blinking Memory 18 */
3182 #define OFS_LCDBM19 (0x0052) /* LCD Blinking Memory 19 */
3183 #define OFS_LCDBM20 (0x0053) /* LCD Blinking Memory 20 */
3184 
3185 /* LCDCIV Definitions */
3186 #define LCDCIV_NONE (0x0000) /* No Interrupt pending */
3187 #define LCDCIV_LCDNOCAPIFG (0x0002) /* No capacitor connected */
3188 #define LCDCIV_LCDCLKOFFIFG (0x0004) /* Blink, segments off */
3189 #define LCDCIV_LCDCLKONIFG (0x0006) /* Blink, segments on */
3190 #define LCDCIV_LCDFRMIFG (0x0008) /* Frame interrupt */
3191 
3192 #endif
3193 /************************************************************
3194 * HARDWARE MULTIPLIER 32Bit
3195 ************************************************************/
3196 #ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */
3197 
3198 #define OFS_MPY (0x0000) /* Multiply Unsigned/Operand 1 */
3199 #define OFS_MPY_L OFS_MPY
3200 #define OFS_MPY_H OFS_MPY+1
3201 #define OFS_MPYS (0x0002) /* Multiply Signed/Operand 1 */
3202 #define OFS_MPYS_L OFS_MPYS
3203 #define OFS_MPYS_H OFS_MPYS+1
3204 #define OFS_MAC (0x0004) /* Multiply Unsigned and Accumulate/Operand 1 */
3205 #define OFS_MAC_L OFS_MAC
3206 #define OFS_MAC_H OFS_MAC+1
3207 #define OFS_MACS (0x0006) /* Multiply Signed and Accumulate/Operand 1 */
3208 #define OFS_MACS_L OFS_MACS
3209 #define OFS_MACS_H OFS_MACS+1
3210 #define OFS_OP2 (0x0008) /* Operand 2 */
3211 #define OFS_OP2_L OFS_OP2
3212 #define OFS_OP2_H OFS_OP2+1
3213 #define OFS_RESLO (0x000A) /* Result Low Word */
3214 #define OFS_RESLO_L OFS_RESLO
3215 #define OFS_RESLO_H OFS_RESLO+1
3216 #define OFS_RESHI (0x000C) /* Result High Word */
3217 #define OFS_RESHI_L OFS_RESHI
3218 #define OFS_RESHI_H OFS_RESHI+1
3219 #define OFS_SUMEXT (0x000E) /* Sum Extend */
3220 #define OFS_SUMEXT_L OFS_SUMEXT
3221 #define OFS_SUMEXT_H OFS_SUMEXT+1
3222 #define OFS_MPY32CTL0 (0x002C)
3223 #define OFS_MPY32CTL0_L OFS_MPY32CTL0
3224 #define OFS_MPY32CTL0_H OFS_MPY32CTL0+1
3225 
3226 #define OFS_MPY32L (0x0010) /* 32-bit operand 1 - multiply - low word */
3227 #define OFS_MPY32L_L OFS_MPY32L
3228 #define OFS_MPY32L_H OFS_MPY32L+1
3229 #define OFS_MPY32H (0x0012) /* 32-bit operand 1 - multiply - high word */
3230 #define OFS_MPY32H_L OFS_MPY32H
3231 #define OFS_MPY32H_H OFS_MPY32H+1
3232 #define OFS_MPYS32L (0x0014) /* 32-bit operand 1 - signed multiply - low word */
3233 #define OFS_MPYS32L_L OFS_MPYS32L
3234 #define OFS_MPYS32L_H OFS_MPYS32L+1
3235 #define OFS_MPYS32H (0x0016) /* 32-bit operand 1 - signed multiply - high word */
3236 #define OFS_MPYS32H_L OFS_MPYS32H
3237 #define OFS_MPYS32H_H OFS_MPYS32H+1
3238 #define OFS_MAC32L (0x0018) /* 32-bit operand 1 - multiply accumulate - low word */
3239 #define OFS_MAC32L_L OFS_MAC32L
3240 #define OFS_MAC32L_H OFS_MAC32L+1
3241 #define OFS_MAC32H (0x001A) /* 32-bit operand 1 - multiply accumulate - high word */
3242 #define OFS_MAC32H_L OFS_MAC32H
3243 #define OFS_MAC32H_H OFS_MAC32H+1
3244 #define OFS_MACS32L (0x001C) /* 32-bit operand 1 - signed multiply accumulate - low word */
3245 #define OFS_MACS32L_L OFS_MACS32L
3246 #define OFS_MACS32L_H OFS_MACS32L+1
3247 #define OFS_MACS32H (0x001E) /* 32-bit operand 1 - signed multiply accumulate - high word */
3248 #define OFS_MACS32H_L OFS_MACS32H
3249 #define OFS_MACS32H_H OFS_MACS32H+1
3250 #define OFS_OP2L (0x0020) /* 32-bit operand 2 - low word */
3251 #define OFS_OP2L_L OFS_OP2L
3252 #define OFS_OP2L_H OFS_OP2L+1
3253 #define OFS_OP2H (0x0022) /* 32-bit operand 2 - high word */
3254 #define OFS_OP2H_L OFS_OP2H
3255 #define OFS_OP2H_H OFS_OP2H+1
3256 #define OFS_RES0 (0x0024) /* 32x32-bit result 0 - least significant word */
3257 #define OFS_RES0_L OFS_RES0
3258 #define OFS_RES0_H OFS_RES0+1
3259 #define OFS_RES1 (0x0026) /* 32x32-bit result 1 */
3260 #define OFS_RES1_L OFS_RES1
3261 #define OFS_RES1_H OFS_RES1+1
3262 #define OFS_RES2 (0x0028) /* 32x32-bit result 2 */
3263 #define OFS_RES2_L OFS_RES2
3264 #define OFS_RES2_H OFS_RES2+1
3265 #define OFS_RES3 (0x002A) /* 32x32-bit result 3 - most significant word */
3266 #define OFS_RES3_L OFS_RES3
3267 #define OFS_RES3_H OFS_RES3+1
3268 #define OFS_SUMEXT (0x000E)
3269 #define OFS_SUMEXT_L OFS_SUMEXT
3270 #define OFS_SUMEXT_H OFS_SUMEXT+1
3271 #define OFS_MPY32CTL0 (0x002C) /* MPY32 Control Register 0 */
3272 #define OFS_MPY32CTL0_L OFS_MPY32CTL0
3273 #define OFS_MPY32CTL0_H OFS_MPY32CTL0+1
3274 
3275 #define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
3276 #define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
3277 #define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
3278 #define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
3279 #define OP2_B OP2_L /* Operand 2 (Byte Access) */
3280 #define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
3281 #define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
3282 #define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
3283 #define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
3284 #define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
3285 #define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
3286 #define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
3287 #define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
3288 #define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
3289 #define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */
3290 
3291 /* MPY32CTL0 Control Bits */
3292 #define MPYC (0x0001) /* Carry of the multiplier */
3293 //#define RESERVED (0x0002) /* Reserved */
3294 #define MPYFRAC (0x0004) /* Fractional mode */
3295 #define MPYSAT (0x0008) /* Saturation mode */
3296 #define MPYM0 (0x0010) /* Multiplier mode Bit:0 */
3297 #define MPYM1 (0x0020) /* Multiplier mode Bit:1 */
3298 #define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
3299 #define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
3300 #define MPYDLYWRTEN (0x0100) /* Delayed write enable */
3301 #define MPYDLY32 (0x0200) /* Delayed write mode */
3302 
3303 /* MPY32CTL0 Control Bits */
3304 #define MPYC_L (0x0001) /* Carry of the multiplier */
3305 //#define RESERVED (0x0002) /* Reserved */
3306 #define MPYFRAC_L (0x0004) /* Fractional mode */
3307 #define MPYSAT_L (0x0008) /* Saturation mode */
3308 #define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */
3309 #define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */
3310 #define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
3311 #define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
3312 
3313 /* MPY32CTL0 Control Bits */
3314 //#define RESERVED (0x0002) /* Reserved */
3315 #define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */
3316 #define MPYDLY32_H (0x0002) /* Delayed write mode */
3317 
3318 #define MPYM_0 (0x0000) /* Multiplier mode: MPY */
3319 #define MPYM_1 (0x0010) /* Multiplier mode: MPYS */
3320 #define MPYM_2 (0x0020) /* Multiplier mode: MAC */
3321 #define MPYM_3 (0x0030) /* Multiplier mode: MACS */
3322 #define MPYM__MPY (0x0000) /* Multiplier mode: MPY */
3323 #define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */
3324 #define MPYM__MAC (0x0020) /* Multiplier mode: MAC */
3325 #define MPYM__MACS (0x0030) /* Multiplier mode: MACS */
3326 
3327 #endif
3328 /************************************************************
3329 * DIGITAL I/O Port1/2 Pull up / Pull down Resistors
3330 ************************************************************/
3331 #ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
3332 #ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
3333 #ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */
3334 
3335 #define OFS_PAIN (0x0000) /* Port A Input */
3336 #define OFS_PAIN_L OFS_PAIN
3337 #define OFS_PAIN_H OFS_PAIN+1
3338 #define OFS_PAOUT (0x0002) /* Port A Output */
3339 #define OFS_PAOUT_L OFS_PAOUT
3340 #define OFS_PAOUT_H OFS_PAOUT+1
3341 #define OFS_PADIR (0x0004) /* Port A Direction */
3342 #define OFS_PADIR_L OFS_PADIR
3343 #define OFS_PADIR_H OFS_PADIR+1
3344 #define OFS_PAREN (0x0006) /* Port A Resistor Enable */
3345 #define OFS_PAREN_L OFS_PAREN
3346 #define OFS_PAREN_H OFS_PAREN+1
3347 #define OFS_PADS (0x0008) /* Port A Drive Strenght */
3348 #define OFS_PADS_L OFS_PADS
3349 #define OFS_PADS_H OFS_PADS+1
3350 #define OFS_PASEL (0x000A) /* Port A Selection */
3351 #define OFS_PASEL_L OFS_PASEL
3352 #define OFS_PASEL_H OFS_PASEL+1
3353 #define OFS_PAIES (0x0018) /* Port A Interrupt Edge Select */
3354 #define OFS_PAIES_L OFS_PAIES
3355 #define OFS_PAIES_H OFS_PAIES+1
3356 #define OFS_PAIE (0x001A) /* Port A Interrupt Enable */
3357 #define OFS_PAIE_L OFS_PAIE
3358 #define OFS_PAIE_H OFS_PAIE+1
3359 #define OFS_PAIFG (0x001C) /* Port A Interrupt Flag */
3360 #define OFS_PAIFG_L OFS_PAIFG
3361 #define OFS_PAIFG_H OFS_PAIFG+1
3362 
3363 
3364 #define OFS_P1IN (0x0000)
3365 #define OFS_P1OUT (0x0002)
3366 #define OFS_P1DIR (0x0004)
3367 #define OFS_P1REN (0x0006)
3368 #define OFS_P1DS (0x0008)
3369 #define OFS_P1SEL (0x000A)
3370 #define OFS_P1IV (0x000E) /* Port 1 Interrupt Vector Word */
3371 #define OFS_P1IES (0x0018)
3372 #define OFS_P1IE (0x001A)
3373 #define OFS_P1IFG (0x001C)
3374 #define OFS_P2IN (0x0001)
3375 #define OFS_P2OUT (0x0003)
3376 #define OFS_P2DIR (0x0005)
3377 #define OFS_P2REN (0x0007)
3378 #define OFS_P2DS (0x0009)
3379 #define OFS_P2SEL (0x000B)
3380 #define OFS_P2IV (0x001E) /* Port 2 Interrupt Vector Word */
3381 #define OFS_P2IES (0x0019)
3382 #define OFS_P2IE (0x001B)
3383 #define OFS_P2IFG (0x001d)
3384 #define P1IN (PAIN_L) /* Port 1 Input */
3385 #define P1OUT (PAOUT_L) /* Port 1 Output */
3386 #define P1DIR (PADIR_L) /* Port 1 Direction */
3387 #define P1REN (PAREN_L) /* Port 1 Resistor Enable */
3388 #define P1DS (PADS_L) /* Port 1 Drive Strenght */
3389 #define P1SEL (PASEL_L) /* Port 1 Selection */
3390 #define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
3391 #define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
3392 #define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */
3393 
3394 //Definitions for P1IV
3395 #define P1IV_NONE (0x0000) /* No Interrupt pending */
3396 #define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */
3397 #define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */
3398 #define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */
3399 #define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */
3400 #define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */
3401 #define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */
3402 #define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */
3403 #define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */
3404 
3405 #define P2IN (PAIN_H) /* Port 2 Input */
3406 #define P2OUT (PAOUT_H) /* Port 2 Output */
3407 #define P2DIR (PADIR_H) /* Port 2 Direction */
3408 #define P2REN (PAREN_H) /* Port 2 Resistor Enable */
3409 #define P2DS (PADS_H) /* Port 2 Drive Strenght */
3410 #define P2SEL (PASEL_H) /* Port 2 Selection */
3411 #define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
3412 #define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
3413 #define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */
3414 
3415 //Definitions for P2IV
3416 #define P2IV_NONE (0x0000) /* No Interrupt pending */
3417 #define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */
3418 #define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */
3419 #define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */
3420 #define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */
3421 #define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */
3422 #define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */
3423 #define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */
3424 #define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */
3425 
3426 
3427 #endif
3428 #endif
3429 #endif
3430 /************************************************************
3431 * DIGITAL I/O Port3/4 Pull up / Pull down Resistors
3432 ************************************************************/
3433 #ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
3434 #ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */
3435 #ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */
3436 
3437 #define OFS_PBIN (0x0000) /* Port B Input */
3438 #define OFS_PBIN_L OFS_PBIN
3439 #define OFS_PBIN_H OFS_PBIN+1
3440 #define OFS_PBOUT (0x0002) /* Port B Output */
3441 #define OFS_PBOUT_L OFS_PBOUT
3442 #define OFS_PBOUT_H OFS_PBOUT+1
3443 #define OFS_PBDIR (0x0004) /* Port B Direction */
3444 #define OFS_PBDIR_L OFS_PBDIR
3445 #define OFS_PBDIR_H OFS_PBDIR+1
3446 #define OFS_PBREN (0x0006) /* Port B Resistor Enable */
3447 #define OFS_PBREN_L OFS_PBREN
3448 #define OFS_PBREN_H OFS_PBREN+1
3449 #define OFS_PBDS (0x0008) /* Port B Drive Strenght */
3450 #define OFS_PBDS_L OFS_PBDS
3451 #define OFS_PBDS_H OFS_PBDS+1
3452 #define OFS_PBSEL (0x000A) /* Port B Selection */
3453 #define OFS_PBSEL_L OFS_PBSEL
3454 #define OFS_PBSEL_H OFS_PBSEL+1
3455 #define OFS_PBIES (0x0018) /* Port B Interrupt Edge Select */
3456 #define OFS_PBIES_L OFS_PBIES
3457 #define OFS_PBIES_H OFS_PBIES+1
3458 #define OFS_PBIE (0x001A) /* Port B Interrupt Enable */
3459 #define OFS_PBIE_L OFS_PBIE
3460 #define OFS_PBIE_H OFS_PBIE+1
3461 #define OFS_PBIFG (0x001C) /* Port B Interrupt Flag */
3462 #define OFS_PBIFG_L OFS_PBIFG
3463 #define OFS_PBIFG_H OFS_PBIFG+1
3464 
3465 
3466 #define OFS_P3IN (0x0000)
3467 #define OFS_P3OUT (0x0002)
3468 #define OFS_P3DIR (0x0004)
3469 #define OFS_P3REN (0x0006)
3470 #define OFS_P3DS (0x0008)
3471 #define OFS_P3SEL (0x000A)
3472 #define OFS_P3IV (0x000E) /* Port 3 Interrupt Vector Word */
3473 #define OFS_P3IES (0x0018)
3474 #define OFS_P3IE (0x001A)
3475 #define OFS_P3IFG (0x001C)
3476 #define OFS_P4IN (0x0001)
3477 #define OFS_P4OUT (0x0003)
3478 #define OFS_P4DIR (0x0005)
3479 #define OFS_P4REN (0x0007)
3480 #define OFS_P4DS (0x0009)
3481 #define OFS_P4SEL (0x000B)
3482 #define OFS_P4IV (0x001E) /* Port 4 Interrupt Vector Word */
3483 #define OFS_P4IES (0x0019)
3484 #define OFS_P4IE (0x001B)
3485 #define OFS_P4IFG (0x001d)
3486 #define P3IN (PBIN_L) /* Port 3 Input */
3487 #define P3OUT (PBOUT_L) /* Port 3 Output */
3488 #define P3DIR (PBDIR_L) /* Port 3 Direction */
3489 #define P3REN (PBREN_L) /* Port 3 Resistor Enable */
3490 #define P3DS (PBDS_L) /* Port 3 Drive Strenght */
3491 #define P3SEL (PBSEL_L) /* Port 3 Selection */
3492 #define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */
3493 #define P3IE (PBIE_L) /* Port 3 Interrupt Enable */
3494 #define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */
3495 
3496 //Definitions for P3IV
3497 #define P3IV_NONE (0x0000) /* No Interrupt pending */
3498 #define P3IV_P3IFG0 (0x0002) /* P3IV P3IFG.0 */
3499 #define P3IV_P3IFG1 (0x0004) /* P3IV P3IFG.1 */
3500 #define P3IV_P3IFG2 (0x0006) /* P3IV P3IFG.2 */
3501 #define P3IV_P3IFG3 (0x0008) /* P3IV P3IFG.3 */
3502 #define P3IV_P3IFG4 (0x000A) /* P3IV P3IFG.4 */
3503 #define P3IV_P3IFG5 (0x000C) /* P3IV P3IFG.5 */
3504 #define P3IV_P3IFG6 (0x000E) /* P3IV P3IFG.6 */
3505 #define P3IV_P3IFG7 (0x0010) /* P3IV P3IFG.7 */
3506 
3507 #define P4IN (PBIN_H) /* Port 4 Input */
3508 #define P4OUT (PBOUT_H) /* Port 4 Output */
3509 #define P4DIR (PBDIR_H) /* Port 4 Direction */
3510 #define P4REN (PBREN_H) /* Port 4 Resistor Enable */
3511 #define P4DS (PBDS_H) /* Port 4 Drive Strenght */
3512 #define P4SEL (PBSEL_H) /* Port 4 Selection */
3513 #define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */
3514 #define P4IE (PBIE_H) /* Port 4 Interrupt Enable */
3515 #define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */
3516 
3517 //Definitions for P4IV
3518 #define P4IV_NONE (0x0000) /* No Interrupt pending */
3519 #define P4IV_P4IFG0 (0x0002) /* P4IV P4IFG.0 */
3520 #define P4IV_P4IFG1 (0x0004) /* P4IV P4IFG.1 */
3521 #define P4IV_P4IFG2 (0x0006) /* P4IV P4IFG.2 */
3522 #define P4IV_P4IFG3 (0x0008) /* P4IV P4IFG.3 */
3523 #define P4IV_P4IFG4 (0x000A) /* P4IV P4IFG.4 */
3524 #define P4IV_P4IFG5 (0x000C) /* P4IV P4IFG.5 */
3525 #define P4IV_P4IFG6 (0x000E) /* P4IV P4IFG.6 */
3526 #define P4IV_P4IFG7 (0x0010) /* P4IV P4IFG.7 */
3527 
3528 
3529 #endif
3530 #endif
3531 #endif
3532 /************************************************************
3533 * DIGITAL I/O Port5/6 Pull up / Pull down Resistors
3534 ************************************************************/
3535 #ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */
3536 #ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */
3537 #ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */
3538 
3539 #define OFS_PCIN (0x0000) /* Port C Input */
3540 #define OFS_PCIN_L OFS_PCIN
3541 #define OFS_PCIN_H OFS_PCIN+1
3542 #define OFS_PCOUT (0x0002) /* Port C Output */
3543 #define OFS_PCOUT_L OFS_PCOUT
3544 #define OFS_PCOUT_H OFS_PCOUT+1
3545 #define OFS_PCDIR (0x0004) /* Port C Direction */
3546 #define OFS_PCDIR_L OFS_PCDIR
3547 #define OFS_PCDIR_H OFS_PCDIR+1
3548 #define OFS_PCREN (0x0006) /* Port C Resistor Enable */
3549 #define OFS_PCREN_L OFS_PCREN
3550 #define OFS_PCREN_H OFS_PCREN+1
3551 #define OFS_PCDS (0x0008) /* Port C Drive Strenght */
3552 #define OFS_PCDS_L OFS_PCDS
3553 #define OFS_PCDS_H OFS_PCDS+1
3554 #define OFS_PCSEL (0x000A) /* Port C Selection */
3555 #define OFS_PCSEL_L OFS_PCSEL
3556 #define OFS_PCSEL_H OFS_PCSEL+1
3557 #define OFS_PCIES (0x0018) /* Port C Interrupt Edge Select */
3558 #define OFS_PCIES_L OFS_PCIES
3559 #define OFS_PCIES_H OFS_PCIES+1
3560 #define OFS_PCIE (0x001A) /* Port C Interrupt Enable */
3561 #define OFS_PCIE_L OFS_PCIE
3562 #define OFS_PCIE_H OFS_PCIE+1
3563 #define OFS_PCIFG (0x001C) /* Port C Interrupt Flag */
3564 #define OFS_PCIFG_L OFS_PCIFG
3565 #define OFS_PCIFG_H OFS_PCIFG+1
3566 
3567 
3568 #define OFS_P5IN (0x0000)
3569 #define OFS_P5OUT (0x0002)
3570 #define OFS_P5DIR (0x0004)
3571 #define OFS_P5REN (0x0006)
3572 #define OFS_P5DS (0x0008)
3573 #define OFS_P5SEL (0x000A)
3574 #define OFS_P5IV (0x000E) /* Port 5 Interrupt Vector Word */
3575 #define OFS_P5IES (0x0018)
3576 #define OFS_P5IE (0x001A)
3577 #define OFS_P5IFG (0x001C)
3578 #define OFS_P6IN (0x0001)
3579 #define OFS_P6OUT (0x0003)
3580 #define OFS_P6DIR (0x0005)
3581 #define OFS_P6REN (0x0007)
3582 #define OFS_P6DS (0x0009)
3583 #define OFS_P6SEL (0x000B)
3584 #define OFS_P6IV (0x001E) /* Port 6 Interrupt Vector Word */
3585 #define OFS_P6IES (0x0019)
3586 #define OFS_P6IE (0x001B)
3587 #define OFS_P6IFG (0x001d)
3588 #define P5IN (PCIN_L) /* Port 5 Input */
3589 #define P5OUT (PCOUT_L) /* Port 5 Output */
3590 #define P5DIR (PCDIR_L) /* Port 5 Direction */
3591 #define P5REN (PCREN_L) /* Port 5 Resistor Enable */
3592 #define P5DS (PCDS_L) /* Port 5 Drive Strenght */
3593 #define P5SEL (PCSEL_L) /* Port 5 Selection */
3594 #define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */
3595 #define P5IE (PCIE_L) /* Port 5 Interrupt Enable */
3596 #define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */
3597 
3598 //Definitions for P5IV
3599 #define P5IV_NONE (0x0000) /* No Interrupt pending */
3600 #define P5IV_P5IFG0 (0x0002) /* P5IV P5IFG.0 */
3601 #define P5IV_P5IFG1 (0x0004) /* P5IV P5IFG.1 */
3602 #define P5IV_P5IFG2 (0x0006) /* P5IV P5IFG.2 */
3603 #define P5IV_P5IFG3 (0x0008) /* P5IV P5IFG.3 */
3604 #define P5IV_P5IFG4 (0x000A) /* P5IV P5IFG.4 */
3605 #define P5IV_P5IFG5 (0x000C) /* P5IV P5IFG.5 */
3606 #define P5IV_P5IFG6 (0x000E) /* P5IV P5IFG.6 */
3607 #define P5IV_P5IFG7 (0x0010) /* P5IV P5IFG.7 */
3608 
3609 #define P6IN (PCIN_H) /* Port 6 Input */
3610 #define P6OUT (PCOUT_H) /* Port 6 Output */
3611 #define P6DIR (PCDIR_H) /* Port 6 Direction */
3612 #define P6REN (PCREN_H) /* Port 6 Resistor Enable */
3613 #define P6DS (PCDS_H) /* Port 6 Drive Strenght */
3614 #define P6SEL (PCSEL_H) /* Port 6 Selection */
3615 #define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */
3616 #define P6IE (PCIE_H) /* Port 6 Interrupt Enable */
3617 #define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */
3618 
3619 //Definitions for P6IV
3620 #define P6IV_NONE (0x0000) /* No Interrupt pending */
3621 #define P6IV_P6IFG0 (0x0002) /* P6IV P6IFG.0 */
3622 #define P6IV_P6IFG1 (0x0004) /* P6IV P6IFG.1 */
3623 #define P6IV_P6IFG2 (0x0006) /* P6IV P6IFG.2 */
3624 #define P6IV_P6IFG3 (0x0008) /* P6IV P6IFG.3 */
3625 #define P6IV_P6IFG4 (0x000A) /* P6IV P6IFG.4 */
3626 #define P6IV_P6IFG5 (0x000C) /* P6IV P6IFG.5 */
3627 #define P6IV_P6IFG6 (0x000E) /* P6IV P6IFG.6 */
3628 #define P6IV_P6IFG7 (0x0010) /* P6IV P6IFG.7 */
3629 
3630 
3631 #endif
3632 #endif
3633 #endif
3634 /************************************************************
3635 * DIGITAL I/O Port7/8 Pull up / Pull down Resistors
3636 ************************************************************/
3637 #ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */
3638 #ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */
3639 #ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */
3640 
3641 #define OFS_PDIN (0x0000) /* Port D Input */
3642 #define OFS_PDIN_L OFS_PDIN
3643 #define OFS_PDIN_H OFS_PDIN+1
3644 #define OFS_PDOUT (0x0002) /* Port D Output */
3645 #define OFS_PDOUT_L OFS_PDOUT
3646 #define OFS_PDOUT_H OFS_PDOUT+1
3647 #define OFS_PDDIR (0x0004) /* Port D Direction */
3648 #define OFS_PDDIR_L OFS_PDDIR
3649 #define OFS_PDDIR_H OFS_PDDIR+1
3650 #define OFS_PDREN (0x0006) /* Port D Resistor Enable */
3651 #define OFS_PDREN_L OFS_PDREN
3652 #define OFS_PDREN_H OFS_PDREN+1
3653 #define OFS_PDDS (0x0008) /* Port D Drive Strenght */
3654 #define OFS_PDDS_L OFS_PDDS
3655 #define OFS_PDDS_H OFS_PDDS+1
3656 #define OFS_PDSEL (0x000A) /* Port D Selection */
3657 #define OFS_PDSEL_L OFS_PDSEL
3658 #define OFS_PDSEL_H OFS_PDSEL+1
3659 #define OFS_PDIES (0x0018) /* Port D Interrupt Edge Select */
3660 #define OFS_PDIES_L OFS_PDIES
3661 #define OFS_PDIES_H OFS_PDIES+1
3662 #define OFS_PDIE (0x001A) /* Port D Interrupt Enable */
3663 #define OFS_PDIE_L OFS_PDIE
3664 #define OFS_PDIE_H OFS_PDIE+1
3665 #define OFS_PDIFG (0x001C) /* Port D Interrupt Flag */
3666 #define OFS_PDIFG_L OFS_PDIFG
3667 #define OFS_PDIFG_H OFS_PDIFG+1
3668 
3669 
3670 #define OFS_P7IN (0x0000)
3671 #define OFS_P7OUT (0x0002)
3672 #define OFS_P7DIR (0x0004)
3673 #define OFS_P7REN (0x0006)
3674 #define OFS_P7DS (0x0008)
3675 #define OFS_P7SEL (0x000A)
3676 #define OFS_P7IV (0x000E) /* Port 7 Interrupt Vector Word */
3677 #define OFS_P7IES (0x0018)
3678 #define OFS_P7IE (0x001A)
3679 #define OFS_P7IFG (0x001C)
3680 #define OFS_P8IN (0x0001)
3681 #define OFS_P8OUT (0x0003)
3682 #define OFS_P8DIR (0x0005)
3683 #define OFS_P8REN (0x0007)
3684 #define OFS_P8DS (0x0009)
3685 #define OFS_P8SEL (0x000B)
3686 #define OFS_P8IV (0x001E) /* Port 8 Interrupt Vector Word */
3687 #define OFS_P8IES (0x0019)
3688 #define OFS_P8IE (0x001B)
3689 #define OFS_P8IFG (0x001d)
3690 #define P7IN (PDIN_L) /* Port 7 Input */
3691 #define P7OUT (PDOUT_L) /* Port 7 Output */
3692 #define P7DIR (PDDIR_L) /* Port 7 Direction */
3693 #define P7REN (PDREN_L) /* Port 7 Resistor Enable */
3694 #define P7DS (PDDS_L) /* Port 7 Drive Strenght */
3695 #define P7SEL (PDSEL_L) /* Port 7 Selection */
3696 #define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */
3697 #define P7IE (PDIE_L) /* Port 7 Interrupt Enable */
3698 #define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */
3699 
3700 //Definitions for P7IV
3701 #define P7IV_NONE (0x0000) /* No Interrupt pending */
3702 #define P7IV_P7IFG0 (0x0002) /* P7IV P7IFG.0 */
3703 #define P7IV_P7IFG1 (0x0004) /* P7IV P7IFG.1 */
3704 #define P7IV_P7IFG2 (0x0006) /* P7IV P7IFG.2 */
3705 #define P7IV_P7IFG3 (0x0008) /* P7IV P7IFG.3 */
3706 #define P7IV_P7IFG4 (0x000A) /* P7IV P7IFG.4 */
3707 #define P7IV_P7IFG5 (0x000C) /* P7IV P7IFG.5 */
3708 #define P7IV_P7IFG6 (0x000E) /* P7IV P7IFG.6 */
3709 #define P7IV_P7IFG7 (0x0010) /* P7IV P7IFG.7 */
3710 
3711 #define P8IN (PDIN_H) /* Port 8 Input */
3712 #define P8OUT (PDOUT_H) /* Port 8 Output */
3713 #define P8DIR (PDDIR_H) /* Port 8 Direction */
3714 #define P8REN (PDREN_H) /* Port 8 Resistor Enable */
3715 #define P8DS (PDDS_H) /* Port 8 Drive Strenght */
3716 #define P8SEL (PDSEL_H) /* Port 8 Selection */
3717 #define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */
3718 #define P8IE (PDIE_H) /* Port 8 Interrupt Enable */
3719 #define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */
3720 
3721 //Definitions for P8IV
3722 #define P8IV_NONE (0x0000) /* No Interrupt pending */
3723 #define P8IV_P8IFG0 (0x0002) /* P8IV P8IFG.0 */
3724 #define P8IV_P8IFG1 (0x0004) /* P8IV P8IFG.1 */
3725 #define P8IV_P8IFG2 (0x0006) /* P8IV P8IFG.2 */
3726 #define P8IV_P8IFG3 (0x0008) /* P8IV P8IFG.3 */
3727 #define P8IV_P8IFG4 (0x000A) /* P8IV P8IFG.4 */
3728 #define P8IV_P8IFG5 (0x000C) /* P8IV P8IFG.5 */
3729 #define P8IV_P8IFG6 (0x000E) /* P8IV P8IFG.6 */
3730 #define P8IV_P8IFG7 (0x0010) /* P8IV P8IFG.7 */
3731 
3732 
3733 #endif
3734 #endif
3735 #endif
3736 /************************************************************
3737 * DIGITAL I/O Port9/10 Pull up / Pull down Resistors
3738 ************************************************************/
3739 #ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */
3740 #ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */
3741 #ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */
3742 
3743 #define OFS_PEIN (0x0000) /* Port E Input */
3744 #define OFS_PEIN_L OFS_PEIN
3745 #define OFS_PEIN_H OFS_PEIN+1
3746 #define OFS_PEOUT (0x0002) /* Port E Output */
3747 #define OFS_PEOUT_L OFS_PEOUT
3748 #define OFS_PEOUT_H OFS_PEOUT+1
3749 #define OFS_PEDIR (0x0004) /* Port E Direction */
3750 #define OFS_PEDIR_L OFS_PEDIR
3751 #define OFS_PEDIR_H OFS_PEDIR+1
3752 #define OFS_PEREN (0x0006) /* Port E Resistor Enable */
3753 #define OFS_PEREN_L OFS_PEREN
3754 #define OFS_PEREN_H OFS_PEREN+1
3755 #define OFS_PEDS (0x0008) /* Port E Drive Strenght */
3756 #define OFS_PEDS_L OFS_PEDS
3757 #define OFS_PEDS_H OFS_PEDS+1
3758 #define OFS_PESEL (0x000A) /* Port E Selection */
3759 #define OFS_PESEL_L OFS_PESEL
3760 #define OFS_PESEL_H OFS_PESEL+1
3761 #define OFS_PEIES (0x0018) /* Port E Interrupt Edge Select */
3762 #define OFS_PEIES_L OFS_PEIES
3763 #define OFS_PEIES_H OFS_PEIES+1
3764 #define OFS_PEIE (0x001A) /* Port E Interrupt Enable */
3765 #define OFS_PEIE_L OFS_PEIE
3766 #define OFS_PEIE_H OFS_PEIE+1
3767 #define OFS_PEIFG (0x001C) /* Port E Interrupt Flag */
3768 #define OFS_PEIFG_L OFS_PEIFG
3769 #define OFS_PEIFG_H OFS_PEIFG+1
3770 
3771 
3772 #define OFS_P9IN (0x0000)
3773 #define OFS_P9OUT (0x0002)
3774 #define OFS_P9DIR (0x0004)
3775 #define OFS_P9REN (0x0006)
3776 #define OFS_P9DS (0x0008)
3777 #define OFS_P9SEL (0x000A)
3778 #define OFS_P9IV (0x000E) /* Port 9 Interrupt Vector Word */
3779 #define OFS_P9IES (0x0018)
3780 #define OFS_P9IE (0x001A)
3781 #define OFS_P9IFG (0x001C)
3782 #define OFS_P10IN (0x0001)
3783 #define OFS_P10OUT (0x0003)
3784 #define OFS_P10DIR (0x0005)
3785 #define OFS_P10REN (0x0007)
3786 #define OFS_P10DS (0x0009)
3787 #define OFS_P10SEL (0x000B)
3788 #define OFS_P10IV (0x001E) /* Port 10 Interrupt Vector Word */
3789 #define OFS_P10IES (0x0019)
3790 #define OFS_P10IE (0x001B)
3791 #define OFS_P10IFG (0x001d)
3792 #define P9IN (PEIN_L) /* Port 9 Input */
3793 #define P9OUT (PEOUT_L) /* Port 9 Output */
3794 #define P9DIR (PEDIR_L) /* Port 9 Direction */
3795 #define P9REN (PEREN_L) /* Port 9 Resistor Enable */
3796 #define P9DS (PEDS_L) /* Port 9 Drive Strenght */
3797 #define P9SEL (PESEL_L) /* Port 9 Selection */
3798 #define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */
3799 #define P9IE (PEIE_L) /* Port 9 Interrupt Enable */
3800 #define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */
3801 
3802 //Definitions for P9IV
3803 #define P9IV_NONE (0x0000) /* No Interrupt pending */
3804 #define P9IV_P9IFG0 (0x0002) /* P9IV P9IFG.0 */
3805 #define P9IV_P9IFG1 (0x0004) /* P9IV P9IFG.1 */
3806 #define P9IV_P9IFG2 (0x0006) /* P9IV P9IFG.2 */
3807 #define P9IV_P9IFG3 (0x0008) /* P9IV P9IFG.3 */
3808 #define P9IV_P9IFG4 (0x000A) /* P9IV P9IFG.4 */
3809 #define P9IV_P9IFG5 (0x000C) /* P9IV P9IFG.5 */
3810 #define P9IV_P9IFG6 (0x000E) /* P9IV P9IFG.6 */
3811 #define P9IV_P9IFG7 (0x0010) /* P9IV P9IFG.7 */
3812 
3813 #define P10IN (PEIN_H) /* Port 10 Input */
3814 #define P10OUT (PEOUT_H) /* Port 10 Output */
3815 #define P10DIR (PEDIR_H) /* Port 10 Direction */
3816 #define P10REN (PEREN_H) /* Port 10 Resistor Enable */
3817 #define P10DS (PEDS_H) /* Port 10 Drive Strenght */
3818 #define P10SEL (PESEL_H) /* Port 10 Selection */
3819 #define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */
3820 #define P10IE (PEIE_H) /* Port 10 Interrupt Enable */
3821 #define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */
3822 
3823 //Definitions for P10IV
3824 #define P10IV_NONE (0x0000) /* No Interrupt pending */
3825 #define P10IV_P10IFG0 (0x0002) /* P10IV P10IFG.0 */
3826 #define P10IV_P10IFG1 (0x0004) /* P10IV P10IFG.1 */
3827 #define P10IV_P10IFG2 (0x0006) /* P10IV P10IFG.2 */
3828 #define P10IV_P10IFG3 (0x0008) /* P10IV P10IFG.3 */
3829 #define P10IV_P10IFG4 (0x000A) /* P10IV P10IFG.4 */
3830 #define P10IV_P10IFG5 (0x000C) /* P10IV P10IFG.5 */
3831 #define P10IV_P10IFG6 (0x000E) /* P10IV P10IFG.6 */
3832 #define P10IV_P10IFG7 (0x0010) /* P10IV P10IFG.7 */
3833 
3834 
3835 #endif
3836 #endif
3837 #endif
3838 /************************************************************
3839 * DIGITAL I/O Port11 Pull up / Pull down Resistors
3840 ************************************************************/
3841 #ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */
3842 #ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */
3843 
3844 #define OFS_PFIN (0x0000) /* Port F Input */
3845 #define OFS_PFIN_L OFS_PFIN
3846 #define OFS_PFIN_H OFS_PFIN+1
3847 #define OFS_PFOUT (0x0002) /* Port F Output */
3848 #define OFS_PFOUT_L OFS_PFOUT
3849 #define OFS_PFOUT_H OFS_PFOUT+1
3850 #define OFS_PFDIR (0x0004) /* Port F Direction */
3851 #define OFS_PFDIR_L OFS_PFDIR
3852 #define OFS_PFDIR_H OFS_PFDIR+1
3853 #define OFS_PFREN (0x0006) /* Port F Resistor Enable */
3854 #define OFS_PFREN_L OFS_PFREN
3855 #define OFS_PFREN_H OFS_PFREN+1
3856 #define OFS_PFDS (0x0008) /* Port F Drive Strenght */
3857 #define OFS_PFDS_L OFS_PFDS
3858 #define OFS_PFDS_H OFS_PFDS+1
3859 #define OFS_PFSEL (0x000A) /* Port F Selection */
3860 #define OFS_PFSEL_L OFS_PFSEL
3861 #define OFS_PFSEL_H OFS_PFSEL+1
3862 #define OFS_PFIES (0x0018) /* Port F Interrupt Edge Select */
3863 #define OFS_PFIES_L OFS_PFIES
3864 #define OFS_PFIES_H OFS_PFIES+1
3865 #define OFS_PFIE (0x001A) /* Port F Interrupt Enable */
3866 #define OFS_PFIE_L OFS_PFIE
3867 #define OFS_PFIE_H OFS_PFIE+1
3868 #define OFS_PFIFG (0x001C) /* Port F Interrupt Flag */
3869 #define OFS_PFIFG_L OFS_PFIFG
3870 #define OFS_PFIFG_H OFS_PFIFG+1
3871 
3872 
3873 #define OFS_P11IN (0x0000)
3874 #define OFS_P11OUT (0x0002)
3875 #define OFS_P11DIR (0x0004)
3876 #define OFS_P11REN (0x0006)
3877 #define OFS_P11DS (0x0008)
3878 #define OFS_P11SEL (0x000A)
3879 #define OFS_P11IV (0x000E) /* Port 11 Interrupt Vector Word */
3880 #define OFS_P11IES (0x0018)
3881 #define OFS_P11IE (0x001A)
3882 #define OFS_P11IFG (0x001C)
3883 #define P11IN (PFIN_L) /* Port 11 Input */
3884 #define P11OUT (PFOUT_L) /* Port 11 Output */
3885 #define P11DIR (PFDIR_L) /* Port 11 Direction */
3886 #define P11REN (PFREN_L) /* Port 11 Resistor Enable */
3887 #define P11DS (PFDS_L) /* Port 11 Drive Strenght */
3888 #define P11SEL (PFSEL_L) /* Port 11 Selection */
3889 
3890 #define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */
3891 #define P11IE (PFIE_L) /* Port 11 Interrupt Enable */
3892 #define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */
3893 
3894 //Definitions for P11IV
3895 #define P11IV_NONE (0x0000) /* No Interrupt pending */
3896 #define P11IV_P11IFG0 (0x0002) /* P11IV P11IFG.0 */
3897 #define P11IV_P11IFG1 (0x0004) /* P11IV P11IFG.1 */
3898 #define P11IV_P11IFG2 (0x0006) /* P11IV P11IFG.2 */
3899 #define P11IV_P11IFG3 (0x0008) /* P11IV P11IFG.3 */
3900 #define P11IV_P11IFG4 (0x000A) /* P11IV P11IFG.4 */
3901 #define P11IV_P11IFG5 (0x000C) /* P11IV P11IFG.5 */
3902 #define P11IV_P11IFG6 (0x000E) /* P11IV P11IFG.6 */
3903 #define P11IV_P11IFG7 (0x0010) /* P11IV P11IFG.7 */
3904 
3905 
3906 #endif
3907 #endif
3908 /************************************************************
3909 * DIGITAL I/O PortJ Pull up / Pull down Resistors
3910 ************************************************************/
3911 #ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */
3912 
3913 #define OFS_PJIN (0x0000) /* Port J Input */
3914 #define OFS_PJIN_L OFS_PJIN
3915 #define OFS_PJIN_H OFS_PJIN+1
3916 #define OFS_PJOUT (0x0002) /* Port J Output */
3917 #define OFS_PJOUT_L OFS_PJOUT
3918 #define OFS_PJOUT_H OFS_PJOUT+1
3919 #define OFS_PJDIR (0x0004) /* Port J Direction */
3920 #define OFS_PJDIR_L OFS_PJDIR
3921 #define OFS_PJDIR_H OFS_PJDIR+1
3922 #define OFS_PJREN (0x0006) /* Port J Resistor Enable */
3923 #define OFS_PJREN_L OFS_PJREN
3924 #define OFS_PJREN_H OFS_PJREN+1
3925 #define OFS_PJDS (0x0008) /* Port J Drive Strenght */
3926 #define OFS_PJDS_L OFS_PJDS
3927 #define OFS_PJDS_H OFS_PJDS+1
3928 #define OFS_PJSEL (0x000A) /* Port J Selection */
3929 #define OFS_PJSEL_L OFS_PJSEL
3930 #define OFS_PJSEL_H OFS_PJSEL+1
3931 
3932 #endif
3933 /************************************************************
3934 * PORT MAPPING CONTROLLER
3935 ************************************************************/
3936 #ifdef __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */
3937 
3938 #define OFS_PMAPKEYID (0x0000) /* Port Mapping Key register */
3939 #define OFS_PMAPKEYID_L OFS_PMAPKEYID
3940 #define OFS_PMAPKEYID_H OFS_PMAPKEYID+1
3941 #define OFS_PMAPCTL (0x0002) /* Port Mapping control register */
3942 #define OFS_PMAPCTL_L OFS_PMAPCTL
3943 #define OFS_PMAPCTL_H OFS_PMAPCTL+1
3944 
3945 #define PMAPKEY (0x2D52) /* Port Mapping Key */
3946 #define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */
3947 #define PMAPPW (0x2D52) /* Legacy Definition: Port Mapping Password */
3948 
3949 /* PMAPCTL Control Bits */
3950 #define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */
3951 #define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */
3952 
3953 /* PMAPCTL Control Bits */
3954 #define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */
3955 #define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */
3956 
3957 #endif
3958 /************************************************************
3959 * PORT 2 MAPPING CONTROLLER
3960 ************************************************************/
3961 #ifdef __MSP430_HAS_PORT2_MAPPING__ /* Definition to show that Module is available */
3962 
3963 #define OFS_P2MAP01 (0x0000) /* Port P2.0/1 mapping register */
3964 #define OFS_P2MAP01_L OFS_P2MAP01
3965 #define OFS_P2MAP01_H OFS_P2MAP01+1
3966 #define OFS_P2MAP23 (0x0002) /* Port P2.2/3 mapping register */
3967 #define OFS_P2MAP23_L OFS_P2MAP23
3968 #define OFS_P2MAP23_H OFS_P2MAP23+1
3969 #define OFS_P2MAP45 (0x0004) /* Port P2.4/5 mapping register */
3970 #define OFS_P2MAP45_L OFS_P2MAP45
3971 #define OFS_P2MAP45_H OFS_P2MAP45+1
3972 #define OFS_P2MAP67 (0x0006) /* Port P2.6/7 mapping register */
3973 #define OFS_P2MAP67_L OFS_P2MAP67
3974 #define OFS_P2MAP67_H OFS_P2MAP67+1
3975 #define OFS_P2MAP0 (0x0000)
3976 #define OFS_P2MAP1 (0x0001)
3977 #define OFS_P2MAP2 (0x0002)
3978 #define OFS_P2MAP3 (0x0003)
3979 #define OFS_P2MAP4 (0x0004)
3980 #define OFS_P2MAP5 (0x0005)
3981 #define OFS_P2MAP6 (0x0006)
3982 #define OFS_P2MAP7 (0x0007)
3983 
3984 #define P2MAP0 P2MAP01_L /* Port P2.0 mapping register */
3985 #define P2MAP1 P2MAP01_H /* Port P2.1 mapping register */
3986 #define P2MAP2 P2MAP23_L /* Port P2.2 mapping register */
3987 #define P2MAP3 P2MAP23_H /* Port P2.3 mapping register */
3988 #define P2MAP4 P2MAP45_L /* Port P2.4 mapping register */
3989 #define P2MAP5 P2MAP45_H /* Port P2.5 mapping register */
3990 #define P2MAP6 P2MAP67_L /* Port P2.6 mapping register */
3991 #define P2MAP7 P2MAP67_H /* Port P2.7 mapping register */
3992 
3993 #endif
3994 /************************************************************
3995 * PMM - Power Management System
3996 ************************************************************/
3997 #ifdef __MSP430_HAS_PMM__ /* Definition to show that Module is available */
3998 
3999 #define OFS_PMMCTL0 (0x0000) /* PMM Control 0 */
4000 #define OFS_PMMCTL0_L OFS_PMMCTL0
4001 #define OFS_PMMCTL0_H OFS_PMMCTL0+1
4002 #define OFS_PMMCTL1 (0x0002) /* PMM Control 1 */
4003 #define OFS_PMMCTL1_L OFS_PMMCTL1
4004 #define OFS_PMMCTL1_H OFS_PMMCTL1+1
4005 #define OFS_SVSMHCTL (0x0004) /* SVS and SVM high side control register */
4006 #define OFS_SVSMHCTL_L OFS_SVSMHCTL
4007 #define OFS_SVSMHCTL_H OFS_SVSMHCTL+1
4008 #define OFS_SVSMLCTL (0x0006) /* SVS and SVM low side control register */
4009 #define OFS_SVSMLCTL_L OFS_SVSMLCTL
4010 #define OFS_SVSMLCTL_H OFS_SVSMLCTL+1
4011 #define OFS_SVSMIO (0x0008) /* SVSIN and SVSOUT control register */
4012 #define OFS_SVSMIO_L OFS_SVSMIO
4013 #define OFS_SVSMIO_H OFS_SVSMIO+1
4014 #define OFS_PMMIFG (0x000C) /* PMM Interrupt Flag */
4015 #define OFS_PMMIFG_L OFS_PMMIFG
4016 #define OFS_PMMIFG_H OFS_PMMIFG+1
4017 #define OFS_PMMRIE (0x000E) /* PMM and RESET Interrupt Enable */
4018 #define OFS_PMMRIE_L OFS_PMMRIE
4019 #define OFS_PMMRIE_H OFS_PMMRIE+1
4020 
4021 #define PMMPW (0xA500) /* PMM Register Write Password */
4022 #define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */
4023 
4024 /* PMMCTL0 Control Bits */
4025 #define PMMCOREV0 (0x0001) /* PMM Core Voltage Bit: 0 */
4026 #define PMMCOREV1 (0x0002) /* PMM Core Voltage Bit: 1 */
4027 #define PMMSWBOR (0x0004) /* PMM Software BOR */
4028 #define PMMSWPOR (0x0008) /* PMM Software POR */
4029 #define PMMREGOFF (0x0010) /* PMM Turn Regulator off */
4030 #define PMMHPMRE (0x0080) /* PMM Global High Power Module Request Enable */
4031 
4032 /* PMMCTL0 Control Bits */
4033 #define PMMCOREV0_L (0x0001) /* PMM Core Voltage Bit: 0 */
4034 #define PMMCOREV1_L (0x0002) /* PMM Core Voltage Bit: 1 */
4035 #define PMMSWBOR_L (0x0004) /* PMM Software BOR */
4036 #define PMMSWPOR_L (0x0008) /* PMM Software POR */
4037 #define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */
4038 #define PMMHPMRE_L (0x0080) /* PMM Global High Power Module Request Enable */
4039 
4040 #define PMMCOREV_0 (0x0000) /* PMM Core Voltage 0 (1.35V) */
4041 #define PMMCOREV_1 (0x0001) /* PMM Core Voltage 1 (1.55V) */
4042 #define PMMCOREV_2 (0x0002) /* PMM Core Voltage 2 (1.75V) */
4043 #define PMMCOREV_3 (0x0003) /* PMM Core Voltage 3 (1.85V) */
4044 
4045 /* PMMCTL1 Control Bits */
4046 #define PMMREFMD (0x0001) /* PMM Reference Mode */
4047 #define PMMCMD0 (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */
4048 #define PMMCMD1 (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */
4049 
4050 /* PMMCTL1 Control Bits */
4051 #define PMMREFMD_L (0x0001) /* PMM Reference Mode */
4052 #define PMMCMD0_L (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */
4053 #define PMMCMD1_L (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */
4054 
4055 /* SVSMHCTL Control Bits */
4056 #define SVSMHRRL0 (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
4057 #define SVSMHRRL1 (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
4058 #define SVSMHRRL2 (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
4059 #define SVSMHDLYST (0x0008) /* SVS and SVM high side delay status */
4060 #define SVSHMD (0x0010) /* SVS high side mode */
4061 #define SVSMHEVM (0x0040) /* SVS and SVM high side event mask */
4062 #define SVSMHACE (0x0080) /* SVS and SVM high side auto control enable */
4063 #define SVSHRVL0 (0x0100) /* SVS high side reset voltage level Bit: 0 */
4064 #define SVSHRVL1 (0x0200) /* SVS high side reset voltage level Bit: 1 */
4065 #define SVSHE (0x0400) /* SVS high side enable */
4066 #define SVSHFP (0x0800) /* SVS high side full performace mode */
4067 #define SVMHOVPE (0x1000) /* SVM high side over-voltage enable */
4068 #define SVMHE (0x4000) /* SVM high side enable */
4069 #define SVMHFP (0x8000) /* SVM high side full performace mode */
4070 
4071 /* SVSMHCTL Control Bits */
4072 #define SVSMHRRL0_L (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
4073 #define SVSMHRRL1_L (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
4074 #define SVSMHRRL2_L (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
4075 #define SVSMHDLYST_L (0x0008) /* SVS and SVM high side delay status */
4076 #define SVSHMD_L (0x0010) /* SVS high side mode */
4077 #define SVSMHEVM_L (0x0040) /* SVS and SVM high side event mask */
4078 #define SVSMHACE_L (0x0080) /* SVS and SVM high side auto control enable */
4079 
4080 /* SVSMHCTL Control Bits */
4081 #define SVSHRVL0_H (0x0001) /* SVS high side reset voltage level Bit: 0 */
4082 #define SVSHRVL1_H (0x0002) /* SVS high side reset voltage level Bit: 1 */
4083 #define SVSHE_H (0x0004) /* SVS high side enable */
4084 #define SVSHFP_H (0x0008) /* SVS high side full performace mode */
4085 #define SVMHOVPE_H (0x0010) /* SVM high side over-voltage enable */
4086 #define SVMHE_H (0x0040) /* SVM high side enable */
4087 #define SVMHFP_H (0x0080) /* SVM high side full performace mode */
4088 
4089 #define SVSMHRRL_0 (0x0000) /* SVS and SVM high side Reset Release Voltage Level 0 */
4090 #define SVSMHRRL_1 (0x0001) /* SVS and SVM high side Reset Release Voltage Level 1 */
4091 #define SVSMHRRL_2 (0x0002) /* SVS and SVM high side Reset Release Voltage Level 2 */
4092 #define SVSMHRRL_3 (0x0003) /* SVS and SVM high side Reset Release Voltage Level 3 */
4093 #define SVSMHRRL_4 (0x0004) /* SVS and SVM high side Reset Release Voltage Level 4 */
4094 #define SVSMHRRL_5 (0x0005) /* SVS and SVM high side Reset Release Voltage Level 5 */
4095 #define SVSMHRRL_6 (0x0006) /* SVS and SVM high side Reset Release Voltage Level 6 */
4096 #define SVSMHRRL_7 (0x0007) /* SVS and SVM high side Reset Release Voltage Level 7 */
4097 
4098 #define SVSHRVL_0 (0x0000) /* SVS high side Reset Release Voltage Level 0 */
4099 #define SVSHRVL_1 (0x0100) /* SVS high side Reset Release Voltage Level 1 */
4100 #define SVSHRVL_2 (0x0200) /* SVS high side Reset Release Voltage Level 2 */
4101 #define SVSHRVL_3 (0x0300) /* SVS high side Reset Release Voltage Level 3 */
4102 
4103 /* SVSMLCTL Control Bits */
4104 #define SVSMLRRL0 (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
4105 #define SVSMLRRL1 (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
4106 #define SVSMLRRL2 (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
4107 #define SVSMLDLYST (0x0008) /* SVS and SVM low side delay status */
4108 #define SVSLMD (0x0010) /* SVS low side mode */
4109 #define SVSMLEVM (0x0040) /* SVS and SVM low side event mask */
4110 #define SVSMLACE (0x0080) /* SVS and SVM low side auto control enable */
4111 #define SVSLRVL0 (0x0100) /* SVS low side reset voltage level Bit: 0 */
4112 #define SVSLRVL1 (0x0200) /* SVS low side reset voltage level Bit: 1 */
4113 #define SVSLE (0x0400) /* SVS low side enable */
4114 #define SVSLFP (0x0800) /* SVS low side full performace mode */
4115 #define SVMLOVPE (0x1000) /* SVM low side over-voltage enable */
4116 #define SVMLE (0x4000) /* SVM low side enable */
4117 #define SVMLFP (0x8000) /* SVM low side full performace mode */
4118 
4119 /* SVSMLCTL Control Bits */
4120 #define SVSMLRRL0_L (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
4121 #define SVSMLRRL1_L (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
4122 #define SVSMLRRL2_L (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
4123 #define SVSMLDLYST_L (0x0008) /* SVS and SVM low side delay status */
4124 #define SVSLMD_L (0x0010) /* SVS low side mode */
4125 #define SVSMLEVM_L (0x0040) /* SVS and SVM low side event mask */
4126 #define SVSMLACE_L (0x0080) /* SVS and SVM low side auto control enable */
4127 
4128 /* SVSMLCTL Control Bits */
4129 #define SVSLRVL0_H (0x0001) /* SVS low side reset voltage level Bit: 0 */
4130 #define SVSLRVL1_H (0x0002) /* SVS low side reset voltage level Bit: 1 */
4131 #define SVSLE_H (0x0004) /* SVS low side enable */
4132 #define SVSLFP_H (0x0008) /* SVS low side full performace mode */
4133 #define SVMLOVPE_H (0x0010) /* SVM low side over-voltage enable */
4134 #define SVMLE_H (0x0040) /* SVM low side enable */
4135 #define SVMLFP_H (0x0080) /* SVM low side full performace mode */
4136 
4137 #define SVSMLRRL_0 (0x0000) /* SVS and SVM low side Reset Release Voltage Level 0 */
4138 #define SVSMLRRL_1 (0x0001) /* SVS and SVM low side Reset Release Voltage Level 1 */
4139 #define SVSMLRRL_2 (0x0002) /* SVS and SVM low side Reset Release Voltage Level 2 */
4140 #define SVSMLRRL_3 (0x0003) /* SVS and SVM low side Reset Release Voltage Level 3 */
4141 #define SVSMLRRL_4 (0x0004) /* SVS and SVM low side Reset Release Voltage Level 4 */
4142 #define SVSMLRRL_5 (0x0005) /* SVS and SVM low side Reset Release Voltage Level 5 */
4143 #define SVSMLRRL_6 (0x0006) /* SVS and SVM low side Reset Release Voltage Level 6 */
4144 #define SVSMLRRL_7 (0x0007) /* SVS and SVM low side Reset Release Voltage Level 7 */
4145 
4146 #define SVSLRVL_0 (0x0000) /* SVS low side Reset Release Voltage Level 0 */
4147 #define SVSLRVL_1 (0x0100) /* SVS low side Reset Release Voltage Level 1 */
4148 #define SVSLRVL_2 (0x0200) /* SVS low side Reset Release Voltage Level 2 */
4149 #define SVSLRVL_3 (0x0300) /* SVS low side Reset Release Voltage Level 3 */
4150 
4151 /* SVSMIO Control Bits */
4152 #define SVMLOE (0x0008) /* SVM low side output enable */
4153 #define SVMLVLROE (0x0010) /* SVM low side voltage level reached output enable */
4154 #define SVMOUTPOL (0x0020) /* SVMOUT pin polarity */
4155 #define SVMHOE (0x0800) /* SVM high side output enable */
4156 #define SVMHVLROE (0x1000) /* SVM high side voltage level reached output enable */
4157 
4158 /* SVSMIO Control Bits */
4159 #define SVMLOE_L (0x0008) /* SVM low side output enable */
4160 #define SVMLVLROE_L (0x0010) /* SVM low side voltage level reached output enable */
4161 #define SVMOUTPOL_L (0x0020) /* SVMOUT pin polarity */
4162 
4163 /* SVSMIO Control Bits */
4164 #define SVMHOE_H (0x0008) /* SVM high side output enable */
4165 #define SVMHVLROE_H (0x0010) /* SVM high side voltage level reached output enable */
4166 
4167 /* PMMIFG Control Bits */
4168 #define SVSMLDLYIFG (0x0001) /* SVS and SVM low side Delay expired interrupt flag */
4169 #define SVMLIFG (0x0002) /* SVM low side interrupt flag */
4170 #define SVMLVLRIFG (0x0004) /* SVM low side Voltage Level Reached interrupt flag */
4171 #define SVSMHDLYIFG (0x0010) /* SVS and SVM high side Delay expired interrupt flag */
4172 #define SVMHIFG (0x0020) /* SVM high side interrupt flag */
4173 #define SVMHVLRIFG (0x0040) /* SVM high side Voltage Level Reached interrupt flag */
4174 #define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */
4175 #define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */
4176 #define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */
4177 #define SVSHIFG (0x1000) /* SVS low side interrupt flag */
4178 #define SVSLIFG (0x2000) /* SVS high side interrupt flag */
4179 #define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */
4180 
4181 /* PMMIFG Control Bits */
4182 #define SVSMLDLYIFG_L (0x0001) /* SVS and SVM low side Delay expired interrupt flag */
4183 #define SVMLIFG_L (0x0002) /* SVM low side interrupt flag */
4184 #define SVMLVLRIFG_L (0x0004) /* SVM low side Voltage Level Reached interrupt flag */
4185 #define SVSMHDLYIFG_L (0x0010) /* SVS and SVM high side Delay expired interrupt flag */
4186 #define SVMHIFG_L (0x0020) /* SVM high side interrupt flag */
4187 #define SVMHVLRIFG_L (0x0040) /* SVM high side Voltage Level Reached interrupt flag */
4188 
4189 /* PMMIFG Control Bits */
4190 #define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */
4191 #define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */
4192 #define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */
4193 #define SVSHIFG_H (0x0010) /* SVS low side interrupt flag */
4194 #define SVSLIFG_H (0x0020) /* SVS high side interrupt flag */
4195 #define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */
4196 
4197 #define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */
4198 
4199 /* PMMIE and RESET Control Bits */
4200 #define SVSMLDLYIE (0x0001) /* SVS and SVM low side Delay expired interrupt enable */
4201 #define SVMLIE (0x0002) /* SVM low side interrupt enable */
4202 #define SVMLVLRIE (0x0004) /* SVM low side Voltage Level Reached interrupt enable */
4203 #define SVSMHDLYIE (0x0010) /* SVS and SVM high side Delay expired interrupt enable */
4204 #define SVMHIE (0x0020) /* SVM high side interrupt enable */
4205 #define SVMHVLRIE (0x0040) /* SVM high side Voltage Level Reached interrupt enable */
4206 #define SVSLPE (0x0100) /* SVS low side POR enable */
4207 #define SVMLVLRPE (0x0200) /* SVM low side Voltage Level reached POR enable */
4208 #define SVSHPE (0x1000) /* SVS high side POR enable */
4209 #define SVMHVLRPE (0x2000) /* SVM high side Voltage Level reached POR enable */
4210 
4211 /* PMMIE and RESET Control Bits */
4212 #define SVSMLDLYIE_L (0x0001) /* SVS and SVM low side Delay expired interrupt enable */
4213 #define SVMLIE_L (0x0002) /* SVM low side interrupt enable */
4214 #define SVMLVLRIE_L (0x0004) /* SVM low side Voltage Level Reached interrupt enable */
4215 #define SVSMHDLYIE_L (0x0010) /* SVS and SVM high side Delay expired interrupt enable */
4216 #define SVMHIE_L (0x0020) /* SVM high side interrupt enable */
4217 #define SVMHVLRIE_L (0x0040) /* SVM high side Voltage Level Reached interrupt enable */
4218 
4219 /* PMMIE and RESET Control Bits */
4220 #define SVSLPE_H (0x0001) /* SVS low side POR enable */
4221 #define SVMLVLRPE_H (0x0002) /* SVM low side Voltage Level reached POR enable */
4222 #define SVSHPE_H (0x0010) /* SVS high side POR enable */
4223 #define SVMHVLRPE_H (0x0020) /* SVM high side Voltage Level reached POR enable */
4224 
4225 #endif
4226 /************************************************************
4227 * Port U
4228 ************************************************************/
4229 #ifdef __MSP430_HAS_PU__ /* Definition to show that Module is available */
4230 
4231 /* ========================================================================= */
4232 /* Port U and LDO Control Registers */
4233 /* ========================================================================= */
4234 #define OFS_LDOKEYPID (0x0000) /* LDO Controller peripheral ID and key register */
4235 #define OFS_LDOKEYPID_L OFS_LDOKEYPID
4236 #define OFS_LDOKEYPID_H OFS_LDOKEYPID+1
4237 #define OFS_PUCTL (0x0004) /* PU Control register */
4238 #define OFS_PUCTL_L OFS_PUCTL
4239 #define OFS_PUCTL_H OFS_PUCTL+1
4240 #define OFS_LDOPWRCTL (0x0008) /* LDO Power control register */
4241 #define OFS_LDOPWRCTL_L OFS_LDOPWRCTL
4242 #define OFS_LDOPWRCTL_H OFS_LDOPWRCTL+1
4243 
4244 #define LDOKEY (0x9628) /* LDO Control Register key */
4245 #define LDOKEYID LDOKEYPID /* Legacy Definiton */
4246 
4247 /* PUCTL Control Bits */
4248 #define PUOUT0 (0x0001) /* PU - PU Output Signal Bit 0 */
4249 #define PUOUT1 (0x0002) /* PU - PU Output Signal Bit 1 */
4250 #define PUIN0 (0x0004) /* PU - PU0/DP Input Data */
4251 #define PUIN1 (0x0008) /* PU - PU1/DM Input Data */
4252 #define PUOPE (0x0020) /* PU - Port Output Enable */
4253 #define PUIPE (0x0100) /* PU - PHY Single Ended Input enable */
4254 
4255 /* PUCTL Control Bits */
4256 #define PUOUT0_L (0x0001) /* PU - PU Output Signal Bit 0 */
4257 #define PUOUT1_L (0x0002) /* PU - PU Output Signal Bit 1 */
4258 #define PUIN0_L (0x0004) /* PU - PU0/DP Input Data */
4259 #define PUIN1_L (0x0008) /* PU - PU1/DM Input Data */
4260 #define PUOPE_L (0x0020) /* PU - Port Output Enable */
4261 
4262 /* PUCTL Control Bits */
4263 #define PUIPE_H (0x0001) /* PU - PHY Single Ended Input enable */
4264 
4265 #define PUDIR (0x0020) /* Legacy Definiton */
4266 #define PSEIEN (0x0100) /* Legacy Definiton */
4267 
4268 /* LDOPWRCTL Control Bits */
4269 #define LDOOVLIFG (0x0001) /* PU - LDOO Overload Interrupt Flag */
4270 #define LDOONIFG (0x0002) /* PU - LDOI "Coming ON" Interrupt Flag */
4271 #define LDOOFFIFG (0x0004) /* PU - LDOI "Going OFF" Interrupt Flag */
4272 #define LDOBGVBV (0x0008) /* PU - LDO Bandgap and LDOI valid */
4273 #define OVLAOFF (0x0020) /* PU - LDO overload auto off enable */
4274 #define LDOOVLIE (0x0100) /* PU - Overload indication Interrupt Enable */
4275 #define LDOONIE (0x0200) /* PU - LDOI "Coming ON" Interrupt Enable */
4276 #define LDOOFFIE (0x0400) /* PU - LDOI "Going OFF" Interrupt Enable */
4277 #define LDOEN (0x0800) /* PU - LDO Enable (3.3V) */
4278 
4279 /* LDOPWRCTL Control Bits */
4280 #define LDOOVLIFG_L (0x0001) /* PU - LDOO Overload Interrupt Flag */
4281 #define LDOONIFG_L (0x0002) /* PU - LDOI "Coming ON" Interrupt Flag */
4282 #define LDOOFFIFG_L (0x0004) /* PU - LDOI "Going OFF" Interrupt Flag */
4283 #define LDOBGVBV_L (0x0008) /* PU - LDO Bandgap and LDOI valid */
4284 #define OVLAOFF_L (0x0020) /* PU - LDO overload auto off enable */
4285 
4286 /* LDOPWRCTL Control Bits */
4287 #define LDOOVLIE_H (0x0001) /* PU - Overload indication Interrupt Enable */
4288 #define LDOONIE_H (0x0002) /* PU - LDOI "Coming ON" Interrupt Enable */
4289 #define LDOOFFIE_H (0x0004) /* PU - LDOI "Going OFF" Interrupt Enable */
4290 #define LDOEN_H (0x0008) /* PU - LDO Enable (3.3V) */
4291 #define LDOOEN LDOEN /* Deprecated support for LDO Enable (3.3V) */
4292 #define LDOOEN_H LDOEN_H /* Deprecated support for LDO Enable (3.3V) */
4293 
4294 #define VUOVLIFG (0x0001) /* PU - Legacy Definiton: LDOO Overload Interrupt Flag */
4295 #define VBONIFG (0x0002) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Flag */
4296 #define VBOFFIFG (0x0004) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Flag */
4297 #define VUOVLIE (0x0100) /* PU - Legacy Definiton: Overload indication Interrupt Enable */
4298 #define VBONIE (0x0200) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Enable */
4299 #define VBOFFIE (0x0400) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Enable */
4300 
4301 
4302 #endif
4303 /*************************************************************
4304 * RAM Control Module
4305 *************************************************************/
4306 #ifdef __MSP430_HAS_RC__ /* Definition to show that Module is available */
4307 
4308 #define OFS_RCCTL0 (0x0000) /* Ram Controller Control Register */
4309 #define OFS_RCCTL0_L OFS_RCCTL0
4310 #define OFS_RCCTL0_H OFS_RCCTL0+1
4311 
4312 /* RCCTL0 Control Bits */
4313 #define RCRS0OFF (0x0001) /* RAM Controller RAM Sector 0 Off */
4314 #define RCRS1OFF (0x0002) /* RAM Controller RAM Sector 1 Off */
4315 #define RCRS2OFF (0x0004) /* RAM Controller RAM Sector 2 Off */
4316 #define RCRS3OFF (0x0008) /* RAM Controller RAM Sector 3 Off */
4317 #define RCRS4OFF (0x0010) /* RAM Controller RAM Sector 4 Off */
4318 #define RCRS5OFF (0x0020) /* RAM Controller RAM Sector 5 Off */
4319 #define RCRS6OFF (0x0040) /* RAM Controller RAM Sector 6 Off */
4320 #define RCRS7OFF (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */
4321 
4322 /* RCCTL0 Control Bits */
4323 #define RCRS0OFF_L (0x0001) /* RAM Controller RAM Sector 0 Off */
4324 #define RCRS1OFF_L (0x0002) /* RAM Controller RAM Sector 1 Off */
4325 #define RCRS2OFF_L (0x0004) /* RAM Controller RAM Sector 2 Off */
4326 #define RCRS3OFF_L (0x0008) /* RAM Controller RAM Sector 3 Off */
4327 #define RCRS4OFF_L (0x0010) /* RAM Controller RAM Sector 4 Off */
4328 #define RCRS5OFF_L (0x0020) /* RAM Controller RAM Sector 5 Off */
4329 #define RCRS6OFF_L (0x0040) /* RAM Controller RAM Sector 6 Off */
4330 #define RCRS7OFF_L (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */
4331 
4332 #define RCKEY (0x5A00)
4333 
4334 #endif
4335 /************************************************************
4336 * Shared Reference
4337 ************************************************************/
4338 #ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */
4339 
4340 #define OFS_REFCTL0 (0x0000) /* REF Shared Reference control register 0 */
4341 #define OFS_REFCTL0_L OFS_REFCTL0
4342 #define OFS_REFCTL0_H OFS_REFCTL0+1
4343 
4344 /* REFCTL0 Control Bits */
4345 #define REFON (0x0001) /* REF Reference On */
4346 #define REFOUT (0x0002) /* REF Reference output Buffer On */
4347 //#define RESERVED (0x0004) /* Reserved */
4348 #define REFTCOFF (0x0008) /* REF Temp.Sensor off */
4349 #define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
4350 #define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
4351 //#define RESERVED (0x0040) /* Reserved */
4352 #define REFMSTR (0x0080) /* REF Master Control */
4353 #define REFGENACT (0x0100) /* REF Reference generator active */
4354 #define REFBGACT (0x0200) /* REF Reference bandgap active */
4355 #define REFGENBUSY (0x0400) /* REF Reference generator busy */
4356 #define BGMODE (0x0800) /* REF Bandgap mode */
4357 //#define RESERVED (0x1000) /* Reserved */
4358 //#define RESERVED (0x2000) /* Reserved */
4359 //#define RESERVED (0x4000) /* Reserved */
4360 //#define RESERVED (0x8000) /* Reserved */
4361 
4362 /* REFCTL0 Control Bits */
4363 #define REFON_L (0x0001) /* REF Reference On */
4364 #define REFOUT_L (0x0002) /* REF Reference output Buffer On */
4365 //#define RESERVED (0x0004) /* Reserved */
4366 #define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
4367 #define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
4368 #define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
4369 //#define RESERVED (0x0040) /* Reserved */
4370 #define REFMSTR_L (0x0080) /* REF Master Control */
4371 //#define RESERVED (0x1000) /* Reserved */
4372 //#define RESERVED (0x2000) /* Reserved */
4373 //#define RESERVED (0x4000) /* Reserved */
4374 //#define RESERVED (0x8000) /* Reserved */
4375 
4376 /* REFCTL0 Control Bits */
4377 //#define RESERVED (0x0004) /* Reserved */
4378 //#define RESERVED (0x0040) /* Reserved */
4379 #define REFGENACT_H (0x0001) /* REF Reference generator active */
4380 #define REFBGACT_H (0x0002) /* REF Reference bandgap active */
4381 #define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
4382 #define BGMODE_H (0x0008) /* REF Bandgap mode */
4383 //#define RESERVED (0x1000) /* Reserved */
4384 //#define RESERVED (0x2000) /* Reserved */
4385 //#define RESERVED (0x4000) /* Reserved */
4386 //#define RESERVED (0x8000) /* Reserved */
4387 
4388 #define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */
4389 #define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
4390 #define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
4391 #define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
4392 
4393 #endif
4394 /************************************************************
4395 * Shared Reference
4396 ************************************************************/
4397 #ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */
4398 
4399 #define OFS_REFCTL0 (0x0000) /* REF Shared Reference control register 0 */
4400 #define OFS_REFCTL0_L OFS_REFCTL0
4401 #define OFS_REFCTL0_H OFS_REFCTL0+1
4402 
4403 /* REFCTL0 Control Bits */
4404 #define REFON (0x0001) /* REF Reference On */
4405 //#define RESERVED (0x0002) /* Reserved */
4406 //#define RESERVED (0x0004) /* Reserved */
4407 #define REFTCOFF (0x0008) /* REF Temp.Sensor off */
4408 #define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
4409 #define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
4410 //#define RESERVED (0x0040) /* Reserved */
4411 //#define RESERVED (0x0080) /* Reserved */
4412 #define REFGENACT (0x0100) /* REF Reference generator active */
4413 #define REFBGACT (0x0200) /* REF Reference bandgap active */
4414 #define REFGENBUSY (0x0400) /* REF Reference generator busy */
4415 #define BGMODE (0x0800) /* REF Bandgap mode */
4416 //#define RESERVED (0x1000) /* Reserved */
4417 //#define RESERVED (0x2000) /* Reserved */
4418 //#define RESERVED (0x4000) /* Reserved */
4419 //#define RESERVED (0x8000) /* Reserved */
4420 
4421 /* REFCTL0 Control Bits */
4422 #define REFON_L (0x0001) /* REF Reference On */
4423 //#define RESERVED (0x0002) /* Reserved */
4424 //#define RESERVED (0x0004) /* Reserved */
4425 #define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
4426 #define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
4427 #define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
4428 //#define RESERVED (0x0040) /* Reserved */
4429 //#define RESERVED (0x0080) /* Reserved */
4430 //#define RESERVED (0x1000) /* Reserved */
4431 //#define RESERVED (0x2000) /* Reserved */
4432 //#define RESERVED (0x4000) /* Reserved */
4433 //#define RESERVED (0x8000) /* Reserved */
4434 
4435 /* REFCTL0 Control Bits */
4436 //#define RESERVED (0x0002) /* Reserved */
4437 //#define RESERVED (0x0004) /* Reserved */
4438 //#define RESERVED (0x0040) /* Reserved */
4439 //#define RESERVED (0x0080) /* Reserved */
4440 #define REFGENACT_H (0x0001) /* REF Reference generator active */
4441 #define REFBGACT_H (0x0002) /* REF Reference bandgap active */
4442 #define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
4443 #define BGMODE_H (0x0008) /* REF Bandgap mode */
4444 //#define RESERVED (0x1000) /* Reserved */
4445 //#define RESERVED (0x2000) /* Reserved */
4446 //#define RESERVED (0x4000) /* Reserved */
4447 //#define RESERVED (0x8000) /* Reserved */
4448 
4449 #define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */
4450 #define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
4451 #define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
4452 #define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
4453 
4454 #endif
4455 /************************************************************
4456 * Real Time Clock
4457 ************************************************************/
4458 #ifdef __MSP430_HAS_RTC__ /* Definition to show that Module is available */
4459 
4460 #define OFS_RTCCTL01 (0x0000) /* Real Timer Control 0/1 */
4461 #define OFS_RTCCTL01_L OFS_RTCCTL01
4462 #define OFS_RTCCTL01_H OFS_RTCCTL01+1
4463 #define OFS_RTCCTL23 (0x0002) /* Real Timer Control 2/3 */
4464 #define OFS_RTCCTL23_L OFS_RTCCTL23
4465 #define OFS_RTCCTL23_H OFS_RTCCTL23+1
4466 #define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */
4467 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
4468 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
4469 #define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */
4470 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
4471 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
4472 #define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */
4473 #define OFS_RTCPS_L OFS_RTCPS
4474 #define OFS_RTCPS_H OFS_RTCPS+1
4475 #define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */
4476 #define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */
4477 #define OFS_RTCTIM0_L OFS_RTCTIM0
4478 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
4479 #define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */
4480 #define OFS_RTCTIM1_L OFS_RTCTIM1
4481 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
4482 #define OFS_RTCDATE (0x0014) /* Real Time Clock Date */
4483 #define OFS_RTCDATE_L OFS_RTCDATE
4484 #define OFS_RTCDATE_H OFS_RTCDATE+1
4485 #define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */
4486 #define OFS_RTCYEAR_L OFS_RTCYEAR
4487 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
4488 #define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */
4489 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
4490 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
4491 #define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */
4492 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
4493 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
4494 #define OFS_RTCSEC (0x0010)
4495 #define OFS_RTCMIN (0x0011)
4496 #define OFS_RTCHOUR (0x0012)
4497 #define OFS_RTCDOW (0x0013)
4498 #define OFS_RTCDAY (0x0014)
4499 #define OFS_RTCMON (0x0015)
4500 #define OFS_RTCAMIN (0x0018)
4501 #define OFS_RTCAHOUR (0x0019)
4502 #define OFS_RTCADOW (0x001A)
4503 #define OFS_RTCADAY (0x001B)
4504 
4505 #define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
4506 #define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
4507 #define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
4508 #define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
4509 #define RTCNT12 RTCTIM0
4510 #define RTCNT34 RTCTIM1
4511 #define RTCNT1 RTCTIM0_L
4512 #define RTCNT2 RTCTIM0_H
4513 #define RTCNT3 RTCTIM1_L
4514 #define RTCNT4 RTCTIM1_H
4515 #define RTCSEC RTCTIM0_L
4516 #define RTCMIN RTCTIM0_H
4517 #define RTCHOUR RTCTIM1_L
4518 #define RTCDOW RTCTIM1_H
4519 #define RTCDAY RTCDATE_L
4520 #define RTCMON RTCDATE_H
4521 #define RTCYEARL RTCYEAR_L
4522 #define RTCYEARH RTCYEAR_H
4523 #define RT0PS RTCPS_L
4524 #define RT1PS RTCPS_H
4525 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
4526 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
4527 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
4528 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
4529 
4530 /* RTCCTL01 Control Bits */
4531 #define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */
4532 #define RTCHOLD (0x4000) /* RTC Hold */
4533 #define RTCMODE (0x2000) /* RTC Mode 0:Counter / 1: Calendar */
4534 #define RTCRDY (0x1000) /* RTC Ready */
4535 #define RTCSSEL1 (0x0800) /* RTC Source Select 1 */
4536 #define RTCSSEL0 (0x0400) /* RTC Source Select 0 */
4537 #define RTCTEV1 (0x0200) /* RTC Time Event 1 */
4538 #define RTCTEV0 (0x0100) /* RTC Time Event 0 */
4539 //#define Reserved (0x0080)
4540 #define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
4541 #define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
4542 #define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
4543 //#define Reserved (0x0008)
4544 #define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
4545 #define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
4546 #define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
4547 
4548 /* RTCCTL01 Control Bits */
4549 //#define Reserved (0x0080)
4550 #define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
4551 #define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
4552 #define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
4553 //#define Reserved (0x0008)
4554 #define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
4555 #define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
4556 #define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
4557 
4558 /* RTCCTL01 Control Bits */
4559 #define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */
4560 #define RTCHOLD_H (0x0040) /* RTC Hold */
4561 #define RTCMODE_H (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
4562 #define RTCRDY_H (0x0010) /* RTC Ready */
4563 #define RTCSSEL1_H (0x0008) /* RTC Source Select 1 */
4564 #define RTCSSEL0_H (0x0004) /* RTC Source Select 0 */
4565 #define RTCTEV1_H (0x0002) /* RTC Time Event 1 */
4566 #define RTCTEV0_H (0x0001) /* RTC Time Event 0 */
4567 //#define Reserved (0x0080)
4568 //#define Reserved (0x0008)
4569 
4570 #define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */
4571 #define RTCSSEL_1 (0x0400) /* RTC Source Select SMCLK */
4572 #define RTCSSEL_2 (0x0800) /* RTC Source Select RT1PS */
4573 #define RTCSSEL_3 (0x0C00) /* RTC Source Select RT1PS */
4574 #define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */
4575 #define RTCSSEL__SMCLK (0x0400) /* RTC Source Select SMCLK */
4576 #define RTCSSEL__RT1PS (0x0800) /* RTC Source Select RT1PS */
4577 #define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
4578 #define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */
4579 #define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */
4580 #define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */
4581 #define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
4582 #define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */
4583 #define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */
4584 #define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */
4585 
4586 /* RTCCTL23 Control Bits */
4587 #define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
4588 #define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
4589 #define RTCCALS (0x0080) /* RTC Calibration Sign */
4590 //#define Reserved (0x0040)
4591 #define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */
4592 #define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */
4593 #define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */
4594 #define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */
4595 #define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */
4596 #define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */
4597 
4598 /* RTCCTL23 Control Bits */
4599 #define RTCCALS_L (0x0080) /* RTC Calibration Sign */
4600 //#define Reserved (0x0040)
4601 #define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */
4602 #define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */
4603 #define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */
4604 #define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */
4605 #define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */
4606 #define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */
4607 
4608 /* RTCCTL23 Control Bits */
4609 #define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
4610 #define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
4611 //#define Reserved (0x0040)
4612 
4613 #define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
4614 #define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
4615 #define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
4616 #define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
4617 
4618 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
4619 
4620 /* RTCPS0CTL Control Bits */
4621 //#define Reserved (0x8000)
4622 #define RT0SSEL (0x4000) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
4623 #define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
4624 #define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
4625 #define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
4626 //#define Reserved (0x0400)
4627 //#define Reserved (0x0200)
4628 #define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */
4629 //#define Reserved (0x0080)
4630 //#define Reserved (0x0040)
4631 //#define Reserved (0x0020)
4632 #define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4633 #define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4634 #define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4635 #define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4636 #define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
4637 
4638 /* RTCPS0CTL Control Bits */
4639 //#define Reserved (0x8000)
4640 //#define Reserved (0x0400)
4641 //#define Reserved (0x0200)
4642 //#define Reserved (0x0080)
4643 //#define Reserved (0x0040)
4644 //#define Reserved (0x0020)
4645 #define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4646 #define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4647 #define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4648 #define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4649 #define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
4650 
4651 /* RTCPS0CTL Control Bits */
4652 //#define Reserved (0x8000)
4653 #define RT0SSEL_H (0x0040) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
4654 #define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
4655 #define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
4656 #define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
4657 //#define Reserved (0x0400)
4658 //#define Reserved (0x0200)
4659 #define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */
4660 //#define Reserved (0x0080)
4661 //#define Reserved (0x0040)
4662 //#define Reserved (0x0020)
4663 
4664 #define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4665 #define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4666 #define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4667 #define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4668 #define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4669 #define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4670 #define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4671 #define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4672 
4673 #define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide /2 */
4674 #define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide /4 */
4675 #define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide /8 */
4676 #define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide /16 */
4677 #define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide /32 */
4678 #define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide /64 */
4679 #define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide /128 */
4680 #define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide /256 */
4681 
4682 /* RTCPS1CTL Control Bits */
4683 #define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */
4684 #define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */
4685 #define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
4686 #define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
4687 #define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
4688 //#define Reserved (0x0400)
4689 //#define Reserved (0x0200)
4690 #define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */
4691 //#define Reserved (0x0080)
4692 //#define Reserved (0x0040)
4693 //#define Reserved (0x0020)
4694 #define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4695 #define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4696 #define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4697 #define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4698 #define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
4699 
4700 /* RTCPS1CTL Control Bits */
4701 //#define Reserved (0x0400)
4702 //#define Reserved (0x0200)
4703 //#define Reserved (0x0080)
4704 //#define Reserved (0x0040)
4705 //#define Reserved (0x0020)
4706 #define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4707 #define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4708 #define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4709 #define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4710 #define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
4711 
4712 /* RTCPS1CTL Control Bits */
4713 #define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */
4714 #define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */
4715 #define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
4716 #define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
4717 #define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
4718 //#define Reserved (0x0400)
4719 //#define Reserved (0x0200)
4720 #define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */
4721 //#define Reserved (0x0080)
4722 //#define Reserved (0x0040)
4723 //#define Reserved (0x0020)
4724 
4725 #define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4726 #define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4727 #define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4728 #define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4729 #define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4730 #define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4731 #define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
4732 #define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
4733 
4734 #define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide /2 */
4735 #define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide /4 */
4736 #define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide /8 */
4737 #define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide /16 */
4738 #define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide /32 */
4739 #define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide /64 */
4740 #define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide /128 */
4741 #define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide /256 */
4742 
4743 #define RT1SSEL_0 (0x0000) /* RTC Prescale Timer Source Select ACLK */
4744 #define RT1SSEL_1 (0x4000) /* RTC Prescale Timer Source Select SMCLK */
4745 #define RT1SSEL_2 (0x8000) /* RTC Prescale Timer Source Select RT0PS */
4746 #define RT1SSEL_3 (0xC000) /* RTC Prescale Timer Source Select RT0PS */
4747 
4748 /* RTC Definitions */
4749 #define RTCIV_NONE (0x0000) /* No Interrupt pending */
4750 #define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
4751 #define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
4752 #define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
4753 #define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
4754 #define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
4755 
4756 /* Legacy Definitions */
4757 #define RTC_NONE (0x0000) /* No Interrupt pending */
4758 #define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
4759 #define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
4760 #define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
4761 #define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
4762 #define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
4763 
4764 #endif
4765 /************************************************************
4766 * Real Time Clock
4767 ************************************************************/
4768 #ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */
4769 
4770 #define OFS_RTCCTL01 (0x0000) /* Real Timer Control 0/1 */
4771 #define OFS_RTCCTL01_L OFS_RTCCTL01
4772 #define OFS_RTCCTL01_H OFS_RTCCTL01+1
4773 #define OFS_RTCCTL23 (0x0002) /* Real Timer Control 2/3 */
4774 #define OFS_RTCCTL23_L OFS_RTCCTL23
4775 #define OFS_RTCCTL23_H OFS_RTCCTL23+1
4776 #define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */
4777 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
4778 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
4779 #define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */
4780 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
4781 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
4782 #define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */
4783 #define OFS_RTCPS_L OFS_RTCPS
4784 #define OFS_RTCPS_H OFS_RTCPS+1
4785 #define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */
4786 #define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */
4787 #define OFS_RTCTIM0_L OFS_RTCTIM0
4788 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
4789 #define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */
4790 #define OFS_RTCTIM1_L OFS_RTCTIM1
4791 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
4792 #define OFS_RTCDATE (0x0014) /* Real Time Clock Date */
4793 #define OFS_RTCDATE_L OFS_RTCDATE
4794 #define OFS_RTCDATE_H OFS_RTCDATE+1
4795 #define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */
4796 #define OFS_RTCYEAR_L OFS_RTCYEAR
4797 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
4798 #define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */
4799 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
4800 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
4801 #define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */
4802 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
4803 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
4804 #define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */
4805 #define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */
4806 #define OFS_RTCSEC (0x0010)
4807 #define OFS_RTCMIN (0x0011)
4808 #define OFS_RTCHOUR (0x0012)
4809 #define OFS_RTCDOW (0x0013)
4810 #define OFS_RTCDAY (0x0014)
4811 #define OFS_RTCMON (0x0015)
4812 #define OFS_RTCAMIN (0x0018)
4813 #define OFS_RTCAHOUR (0x0019)
4814 #define OFS_RTCADOW (0x001A)
4815 #define OFS_RTCADAY (0x001B)
4816 
4817 #define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
4818 #define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
4819 #define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
4820 #define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
4821 #define RTCNT12 RTCTIM0
4822 #define RTCNT34 RTCTIM1
4823 #define RTCNT1 RTCTIM0_L
4824 #define RTCNT2 RTCTIM0_H
4825 #define RTCNT3 RTCTIM1_L
4826 #define RTCNT4 RTCTIM1_H
4827 #define RTCSEC RTCTIM0_L
4828 #define RTCMIN RTCTIM0_H
4829 #define RTCHOUR RTCTIM1_L
4830 #define RTCDOW RTCTIM1_H
4831 #define RTCDAY RTCDATE_L
4832 #define RTCMON RTCDATE_H
4833 #define RTCYEARL RTCYEAR_L
4834 #define RTCYEARH RTCYEAR_H
4835 #define RT0PS RTCPS_L
4836 #define RT1PS RTCPS_H
4837 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
4838 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
4839 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
4840 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
4841 
4842 /* RTCCTL01 Control Bits */
4843 #define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */
4844 #define RTCHOLD (0x4000) /* RTC Hold */
4845 //#define RESERVED (0x2000) /* RESERVED */
4846 #define RTCRDY (0x1000) /* RTC Ready */
4847 //#define RESERVED (0x0800) /* RESERVED */
4848 //#define RESERVED (0x0400) /* RESERVED */
4849 #define RTCTEV1 (0x0200) /* RTC Time Event 1 */
4850 #define RTCTEV0 (0x0100) /* RTC Time Event 0 */
4851 #define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4852 #define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
4853 #define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
4854 #define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
4855 #define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4856 #define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
4857 #define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
4858 #define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
4859 
4860 /* RTCCTL01 Control Bits */
4861 //#define RESERVED (0x2000) /* RESERVED */
4862 //#define RESERVED (0x0800) /* RESERVED */
4863 //#define RESERVED (0x0400) /* RESERVED */
4864 #define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4865 #define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
4866 #define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
4867 #define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
4868 #define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4869 #define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
4870 #define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
4871 #define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
4872 
4873 /* RTCCTL01 Control Bits */
4874 #define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */
4875 #define RTCHOLD_H (0x0040) /* RTC Hold */
4876 //#define RESERVED (0x2000) /* RESERVED */
4877 #define RTCRDY_H (0x0010) /* RTC Ready */
4878 //#define RESERVED (0x0800) /* RESERVED */
4879 //#define RESERVED (0x0400) /* RESERVED */
4880 #define RTCTEV1_H (0x0002) /* RTC Time Event 1 */
4881 #define RTCTEV0_H (0x0001) /* RTC Time Event 0 */
4882 
4883 #define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
4884 #define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */
4885 #define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */
4886 #define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */
4887 #define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
4888 #define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */
4889 #define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */
4890 #define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */
4891 
4892 /* RTCCTL23 Control Bits */
4893 #define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
4894 #define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
4895 #define RTCCALS (0x0080) /* RTC Calibration Sign */
4896 //#define Reserved (0x0040)
4897 #define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */
4898 #define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */
4899 #define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */
4900 #define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */
4901 #define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */
4902 #define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */
4903 
4904 /* RTCCTL23 Control Bits */
4905 #define RTCCALS_L (0x0080) /* RTC Calibration Sign */
4906 //#define Reserved (0x0040)
4907 #define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */
4908 #define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */
4909 #define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */
4910 #define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */
4911 #define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */
4912 #define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */
4913 
4914 /* RTCCTL23 Control Bits */
4915 #define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
4916 #define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
4917 //#define Reserved (0x0040)
4918 
4919 #define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
4920 #define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
4921 #define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
4922 #define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
4923 
4924 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
4925 
4926 /* RTCPS0CTL Control Bits */
4927 //#define Reserved (0x0080)
4928 //#define Reserved (0x0040)
4929 //#define Reserved (0x0020)
4930 #define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4931 #define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4932 #define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4933 #define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4934 #define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
4935 
4936 /* RTCPS0CTL Control Bits */
4937 //#define Reserved (0x0080)
4938 //#define Reserved (0x0040)
4939 //#define Reserved (0x0020)
4940 #define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4941 #define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4942 #define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4943 #define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4944 #define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
4945 
4946 #define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4947 #define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4948 #define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4949 #define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4950 #define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4951 #define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4952 #define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4953 #define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4954 
4955 #define RT0IP__2 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4956 #define RT0IP__4 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4957 #define RT0IP__8 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4958 #define RT0IP__16 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4959 #define RT0IP__32 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4960 #define RT0IP__64 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4961 #define RT0IP__128 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4962 #define RT0IP__256 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4963 
4964 /* RTCPS1CTL Control Bits */
4965 //#define Reserved (0x0080)
4966 //#define Reserved (0x0040)
4967 //#define Reserved (0x0020)
4968 #define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4969 #define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4970 #define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4971 #define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4972 #define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
4973 
4974 /* RTCPS1CTL Control Bits */
4975 //#define Reserved (0x0080)
4976 //#define Reserved (0x0040)
4977 //#define Reserved (0x0020)
4978 #define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4979 #define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4980 #define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4981 #define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4982 #define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
4983 
4984 #define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4985 #define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4986 #define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4987 #define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4988 #define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4989 #define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4990 #define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
4991 #define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
4992 
4993 #define RT1IP__2 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4994 #define RT1IP__4 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4995 #define RT1IP__8 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4996 #define RT1IP__16 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4997 #define RT1IP__32 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4998 #define RT1IP__64 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4999 #define RT1IP__128 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
5000 #define RT1IP__256 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
5001 
5002 /* RTC Definitions */
5003 #define RTCIV_NONE (0x0000) /* No Interrupt pending */
5004 #define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
5005 #define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
5006 #define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
5007 #define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
5008 #define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
5009 #define RTCIV_RTCOFIFG (0x000C) /* RTC Oscillator fault */
5010 
5011 /* Legacy Definitions */
5012 #define RTC_NONE (0x0000) /* No Interrupt pending */
5013 #define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
5014 #define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
5015 #define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
5016 #define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
5017 #define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
5018 #define RTC_RTCOFIFG (0x000C) /* RTC Oscillator fault */
5019 
5020 #endif
5021 /************************************************************
5022 * Real Time Clock
5023 ************************************************************/
5024 #ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */
5025 
5026 #define OFS_RTCCTL0 (0x0000) /* Real Timer Clock Control 0/Key */
5027 #define OFS_RTCCTL0_L OFS_RTCCTL0
5028 #define OFS_RTCCTL0_H OFS_RTCCTL0+1
5029 #define OFS_RTCCTL13 (0x0002) /* Real Timer Clock Control 1/3 */
5030 #define OFS_RTCCTL13_L OFS_RTCCTL13
5031 #define OFS_RTCCTL13_H OFS_RTCCTL13+1
5032 #define RTCCTL1 RTCCTL13_L
5033 #define RTCCTL3 RTCCTL13_H
5034 #define OFS_RTCOCAL (0x0004) /* Real Timer Clock Offset Calibartion */
5035 #define OFS_RTCOCAL_L OFS_RTCOCAL
5036 #define OFS_RTCOCAL_H OFS_RTCOCAL+1
5037 #define OFS_RTCTCMP (0x0006) /* Real Timer Temperature Compensation */
5038 #define OFS_RTCTCMP_L OFS_RTCTCMP
5039 #define OFS_RTCTCMP_H OFS_RTCTCMP+1
5040 #define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */
5041 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
5042 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
5043 #define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */
5044 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
5045 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
5046 #define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */
5047 #define OFS_RTCPS_L OFS_RTCPS
5048 #define OFS_RTCPS_H OFS_RTCPS+1
5049 #define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */
5050 #define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */
5051 #define OFS_RTCTIM0_L OFS_RTCTIM0
5052 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
5053 #define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */
5054 #define OFS_RTCTIM1_L OFS_RTCTIM1
5055 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
5056 #define OFS_RTCDATE (0x0014) /* Real Time Clock Date */
5057 #define OFS_RTCDATE_L OFS_RTCDATE
5058 #define OFS_RTCDATE_H OFS_RTCDATE+1
5059 #define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */
5060 #define OFS_RTCYEAR_L OFS_RTCYEAR
5061 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
5062 #define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */
5063 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
5064 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
5065 #define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */
5066 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
5067 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
5068 #define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */
5069 #define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */
5070 #define OFS_RTCSEC (0x0010)
5071 #define OFS_RTCMIN (0x0011)
5072 #define OFS_RTCHOUR (0x0012)
5073 #define OFS_RTCDOW (0x0013)
5074 #define OFS_RTCDAY (0x0014)
5075 #define OFS_RTCMON (0x0015)
5076 #define OFS_RTCAMIN (0x0018)
5077 #define OFS_RTCAHOUR (0x0019)
5078 #define OFS_RTCADOW (0x001A)
5079 #define OFS_RTCADAY (0x001B)
5080 
5081 #define RTCSEC RTCTIM0_L
5082 #define RTCMIN RTCTIM0_H
5083 #define RTCHOUR RTCTIM1_L
5084 #define RTCDOW RTCTIM1_H
5085 #define RTCDAY RTCDATE_L
5086 #define RTCMON RTCDATE_H
5087 #define RTCYEARL RTCYEAR_L
5088 #define RT0PS RTCPS_L
5089 #define RT1PS RTCPS_H
5090 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
5091 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
5092 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
5093 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
5094 
5095 /* RTCCTL0 Control Bits */
5096 #define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
5097 #define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
5098 #define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
5099 #define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
5100 #define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
5101 #define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
5102 #define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
5103 #define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
5104 
5105 /* RTCCTL0 Control Bits */
5106 #define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
5107 #define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
5108 #define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
5109 #define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
5110 #define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
5111 #define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
5112 #define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
5113 #define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
5114 
5115 #define RTCKEY (0xA500) /* RTC Key for RTC write access */
5116 #define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */
5117 
5118 /* RTCCTL13 Control Bits */
5119 #define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
5120 #define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
5121 #define RTCBCD (0x0080) /* RTC BCD 0:Binary / 1:BCD */
5122 #define RTCHOLD (0x0040) /* RTC Hold */
5123 #define RTCMODE (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
5124 #define RTCRDY (0x0010) /* RTC Ready */
5125 #define RTCSSEL1 (0x0008) /* RTC Source Select 1 */
5126 #define RTCSSEL0 (0x0004) /* RTC Source Select 0 */
5127 #define RTCTEV1 (0x0002) /* RTC Time Event 1 */
5128 #define RTCTEV0 (0x0001) /* RTC Time Event 0 */
5129 
5130 /* RTCCTL13 Control Bits */
5131 #define RTCBCD_L (0x0080) /* RTC BCD 0:Binary / 1:BCD */
5132 #define RTCHOLD_L (0x0040) /* RTC Hold */
5133 #define RTCMODE_L (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
5134 #define RTCRDY_L (0x0010) /* RTC Ready */
5135 #define RTCSSEL1_L (0x0008) /* RTC Source Select 1 */
5136 #define RTCSSEL0_L (0x0004) /* RTC Source Select 0 */
5137 #define RTCTEV1_L (0x0002) /* RTC Time Event 1 */
5138 #define RTCTEV0_L (0x0001) /* RTC Time Event 0 */
5139 
5140 /* RTCCTL13 Control Bits */
5141 #define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
5142 #define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
5143 
5144 #define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */
5145 #define RTCSSEL_1 (0x0004) /* RTC Source Select SMCLK */
5146 #define RTCSSEL_2 (0x0008) /* RTC Source Select RT1PS */
5147 #define RTCSSEL_3 (0x000C) /* RTC Source Select RT1PS */
5148 #define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */
5149 #define RTCSSEL__SMCLK (0x0004) /* RTC Source Select SMCLK */
5150 #define RTCSSEL__RT1PS (0x0008) /* RTC Source Select RT1PS */
5151 
5152 #define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
5153 #define RTCTEV_1 (0x0001) /* RTC Time Event: 1 (Hour changed) */
5154 #define RTCTEV_2 (0x0002) /* RTC Time Event: 2 (12:00 changed) */
5155 #define RTCTEV_3 (0x0003) /* RTC Time Event: 3 (00:00 changed) */
5156 #define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
5157 #define RTCTEV__HOUR (0x0001) /* RTC Time Event: 1 (Hour changed) */
5158 #define RTCTEV__0000 (0x0002) /* RTC Time Event: 2 (00:00 changed) */
5159 #define RTCTEV__1200 (0x0003) /* RTC Time Event: 3 (12:00 changed) */
5160 
5161 #define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
5162 #define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
5163 #define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
5164 #define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
5165 
5166 /* RTCOCAL Control Bits */
5167 #define RTCOCALS (0x8000) /* RTC Offset Calibration Sign */
5168 #define RTCOCAL7 (0x0080) /* RTC Offset Calibration Bit 7 */
5169 #define RTCOCAL6 (0x0040) /* RTC Offset Calibration Bit 6 */
5170 #define RTCOCAL5 (0x0020) /* RTC Offset Calibration Bit 5 */
5171 #define RTCOCAL4 (0x0010) /* RTC Offset Calibration Bit 4 */
5172 #define RTCOCAL3 (0x0008) /* RTC Offset Calibration Bit 3 */
5173 #define RTCOCAL2 (0x0004) /* RTC Offset Calibration Bit 2 */
5174 #define RTCOCAL1 (0x0002) /* RTC Offset Calibration Bit 1 */
5175 #define RTCOCAL0 (0x0001) /* RTC Offset Calibration Bit 0 */
5176 
5177 /* RTCOCAL Control Bits */
5178 #define RTCOCAL7_L (0x0080) /* RTC Offset Calibration Bit 7 */
5179 #define RTCOCAL6_L (0x0040) /* RTC Offset Calibration Bit 6 */
5180 #define RTCOCAL5_L (0x0020) /* RTC Offset Calibration Bit 5 */
5181 #define RTCOCAL4_L (0x0010) /* RTC Offset Calibration Bit 4 */
5182 #define RTCOCAL3_L (0x0008) /* RTC Offset Calibration Bit 3 */
5183 #define RTCOCAL2_L (0x0004) /* RTC Offset Calibration Bit 2 */
5184 #define RTCOCAL1_L (0x0002) /* RTC Offset Calibration Bit 1 */
5185 #define RTCOCAL0_L (0x0001) /* RTC Offset Calibration Bit 0 */
5186 
5187 /* RTCOCAL Control Bits */
5188 #define RTCOCALS_H (0x0080) /* RTC Offset Calibration Sign */
5189 
5190 /* RTCTCMP Control Bits */
5191 #define RTCTCMPS (0x8000) /* RTC Temperature Compensation Sign */
5192 #define RTCTCRDY (0x4000) /* RTC Temperature compensation ready */
5193 #define RTCTCOK (0x2000) /* RTC Temperature compensation write OK */
5194 #define RTCTCMP7 (0x0080) /* RTC Temperature Compensation Bit 7 */
5195 #define RTCTCMP6 (0x0040) /* RTC Temperature Compensation Bit 6 */
5196 #define RTCTCMP5 (0x0020) /* RTC Temperature Compensation Bit 5 */
5197 #define RTCTCMP4 (0x0010) /* RTC Temperature Compensation Bit 4 */
5198 #define RTCTCMP3 (0x0008) /* RTC Temperature Compensation Bit 3 */
5199 #define RTCTCMP2 (0x0004) /* RTC Temperature Compensation Bit 2 */
5200 #define RTCTCMP1 (0x0002) /* RTC Temperature Compensation Bit 1 */
5201 #define RTCTCMP0 (0x0001) /* RTC Temperature Compensation Bit 0 */
5202 
5203 /* RTCTCMP Control Bits */
5204 #define RTCTCMP7_L (0x0080) /* RTC Temperature Compensation Bit 7 */
5205 #define RTCTCMP6_L (0x0040) /* RTC Temperature Compensation Bit 6 */
5206 #define RTCTCMP5_L (0x0020) /* RTC Temperature Compensation Bit 5 */
5207 #define RTCTCMP4_L (0x0010) /* RTC Temperature Compensation Bit 4 */
5208 #define RTCTCMP3_L (0x0008) /* RTC Temperature Compensation Bit 3 */
5209 #define RTCTCMP2_L (0x0004) /* RTC Temperature Compensation Bit 2 */
5210 #define RTCTCMP1_L (0x0002) /* RTC Temperature Compensation Bit 1 */
5211 #define RTCTCMP0_L (0x0001) /* RTC Temperature Compensation Bit 0 */
5212 
5213 /* RTCTCMP Control Bits */
5214 #define RTCTCMPS_H (0x0080) /* RTC Temperature Compensation Sign */
5215 #define RTCTCRDY_H (0x0040) /* RTC Temperature compensation ready */
5216 #define RTCTCOK_H (0x0020) /* RTC Temperature compensation write OK */
5217 
5218 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
5219 
5220 /* RTCPS0CTL Control Bits */
5221 //#define Reserved (0x8000)
5222 //#define Reserved (0x4000)
5223 #define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
5224 #define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
5225 #define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
5226 //#define Reserved (0x0400)
5227 //#define Reserved (0x0200)
5228 #define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */
5229 //#define Reserved (0x0080)
5230 //#define Reserved (0x0040)
5231 //#define Reserved (0x0020)
5232 #define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
5233 #define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
5234 #define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
5235 #define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
5236 #define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
5237 
5238 /* RTCPS0CTL Control Bits */
5239 //#define Reserved (0x8000)
5240 //#define Reserved (0x4000)
5241 //#define Reserved (0x0400)
5242 //#define Reserved (0x0200)
5243 //#define Reserved (0x0080)
5244 //#define Reserved (0x0040)
5245 //#define Reserved (0x0020)
5246 #define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
5247 #define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
5248 #define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
5249 #define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
5250 #define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
5251 
5252 /* RTCPS0CTL Control Bits */
5253 //#define Reserved (0x8000)
5254 //#define Reserved (0x4000)
5255 #define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
5256 #define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
5257 #define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
5258 //#define Reserved (0x0400)
5259 //#define Reserved (0x0200)
5260 #define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */
5261 //#define Reserved (0x0080)
5262 //#define Reserved (0x0040)
5263 //#define Reserved (0x0020)
5264 
5265 #define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
5266 #define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
5267 #define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
5268 #define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
5269 #define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
5270 #define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
5271 #define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
5272 #define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
5273 
5274 /* RTCPS1CTL Control Bits */
5275 #define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */
5276 #define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */
5277 #define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
5278 #define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
5279 #define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
5280 //#define Reserved (0x0400)
5281 //#define Reserved (0x0200)
5282 #define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */
5283 //#define Reserved (0x0080)
5284 //#define Reserved (0x0040)
5285 //#define Reserved (0x0020)
5286 #define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
5287 #define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
5288 #define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
5289 #define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
5290 #define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
5291 
5292 /* RTCPS1CTL Control Bits */
5293 //#define Reserved (0x0400)
5294 //#define Reserved (0x0200)
5295 //#define Reserved (0x0080)
5296 //#define Reserved (0x0040)
5297 //#define Reserved (0x0020)
5298 #define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
5299 #define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
5300 #define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
5301 #define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
5302 #define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
5303 
5304 /* RTCPS1CTL Control Bits */
5305 #define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */
5306 #define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */
5307 #define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
5308 #define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
5309 #define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
5310 //#define Reserved (0x0400)
5311 //#define Reserved (0x0200)
5312 #define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */
5313 //#define Reserved (0x0080)
5314 //#define Reserved (0x0040)
5315 //#define Reserved (0x0020)
5316 
5317 #define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
5318 #define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
5319 #define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
5320 #define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
5321 #define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
5322 #define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
5323 #define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
5324 #define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
5325 
5326 /* RTC Definitions */
5327 #define RTCIV_NONE (0x0000) /* No Interrupt pending */
5328 #define RTCIV_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */
5329 #define RTCIV_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */
5330 #define RTCIV_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */
5331 #define RTCIV_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */
5332 #define RTCIV_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */
5333 #define RTCIV_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */
5334 
5335 /* Legacy Definitions */
5336 #define RTC_NONE (0x0000) /* No Interrupt pending */
5337 #define RTC_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */
5338 #define RTC_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */
5339 #define RTC_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */
5340 #define RTC_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */
5341 #define RTC_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */
5342 #define RTC_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */
5343 
5344 #endif
5345 /************************************************************
5346 * Real Time Clock
5347 ************************************************************/
5348 #ifdef __MSP430_HAS_RTC_CE__ /* Definition to show that Module is available */
5349 
5350 #define OFS_RTCCTL0 (0x0000) /* Real Timer Clock Control 0/Key */
5351 #define OFS_RTCCTL0_L OFS_RTCCTL0
5352 #define OFS_RTCCTL0_H OFS_RTCCTL0+1
5353 #define OFS_RTCCTL13 (0x0002) /* Real Timer Clock Control 1/3 */
5354 #define OFS_RTCCTL13_L OFS_RTCCTL13
5355 #define OFS_RTCCTL13_H OFS_RTCCTL13+1
5356 #define RTCCTL1 RTCCTL13_L
5357 #define RTCCTL3 RTCCTL13_H
5358 #define OFS_RTCOCAL (0x0004) /* Real Timer Clock Offset Calibartion */
5359 #define OFS_RTCOCAL_L OFS_RTCOCAL
5360 #define OFS_RTCOCAL_H OFS_RTCOCAL+1
5361 #define OFS_RTCTCMP (0x0006) /* Real Timer Temperature Compensation */
5362 #define OFS_RTCTCMP_L OFS_RTCTCMP
5363 #define OFS_RTCTCMP_H OFS_RTCTCMP+1
5364 #define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */
5365 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
5366 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
5367 #define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */
5368 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
5369 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
5370 #define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */
5371 #define OFS_RTCPS_L OFS_RTCPS
5372 #define OFS_RTCPS_H OFS_RTCPS+1
5373 #define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */
5374 #define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */
5375 #define OFS_RTCTIM0_L OFS_RTCTIM0
5376 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
5377 #define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */
5378 #define OFS_RTCTIM1_L OFS_RTCTIM1
5379 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
5380 #define OFS_RTCDATE (0x0014) /* Real Time Clock Date */
5381 #define OFS_RTCDATE_L OFS_RTCDATE
5382 #define OFS_RTCDATE_H OFS_RTCDATE+1
5383 #define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */
5384 #define OFS_RTCYEAR_L OFS_RTCYEAR
5385 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
5386 #define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */
5387 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
5388 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
5389 #define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */
5390 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
5391 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
5392 #define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */
5393 #define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */
5394 #define OFS_RTCSEC (0x0010)
5395 #define OFS_RTCMIN (0x0011)
5396 #define OFS_RTCHOUR (0x0012)
5397 #define OFS_RTCDOW (0x0013)
5398 #define OFS_RTCDAY (0x0014)
5399 #define OFS_RTCMON (0x0015)
5400 #define OFS_RTCAMIN (0x0018)
5401 #define OFS_RTCAHOUR (0x0019)
5402 #define OFS_RTCADOW (0x001A)
5403 #define OFS_RTCADAY (0x001B)
5404 
5405 #define OFS_RTCTCCTL0 (0x0020) /* Real-Time Clock Time Capture Control Register 0 */
5406 #define OFS_RTCTCCTL1 (0x0021) /* Real-Time Clock Time Capture Control Register 1 */
5407 #define OFS_RTCCAP0CTL (0x0022) /* Tamper Detect Pin 0 Control Register */
5408 #define OFS_RTCCAP1CTL (0x0023) /* Tamper Detect Pin 1 Control Register */
5409 #define OFS_RTCSECBAK0 (0x0030) /* Real-Time Clock Seconds Backup Register 0 */
5410 #define OFS_RTCMINBAK0 (0x0031) /* Real-Time Clock Minutes Backup Register 0 */
5411 #define OFS_RTCHOURBAK0 (0x0032) /* Real-Time Clock Hours Backup Register 0 */
5412 #define OFS_RTCDAYBAK0 (0x0033) /* Real-Time Clock Days Backup Register 0 */
5413 #define OFS_RTCMONBAK0 (0x0034) /* Real-Time Clock Months Backup Register 0 */
5414 #define OFS_RTCYEARBAK0 (0x0036) /* Real-Time Clock year Backup Register 0 */
5415 #define OFS_RTCSECBAK1 (0x0038) /* Real-Time Clock Seconds Backup Register 1 */
5416 #define OFS_RTCMINBAK1 (0x0039) /* Real-Time Clock Minutes Backup Register 1 */
5417 #define OFS_RTCHOURBAK1 (0x003A) /* Real-Time Clock Hours Backup Register 1 */
5418 #define OFS_RTCDAYBAK1 (0x003B) /* Real-Time Clock Days Backup Register 1 */
5419 #define OFS_RTCMONBAK1 (0x003C) /* Real-Time Clock Months Backup Register 1 */
5420 #define OFS_RTCYEARBAK1 (0x003E) /* Real-Time Clock Year Backup Register 1 */
5421 
5422 #define RTCSEC RTCTIM0_L
5423 #define RTCMIN RTCTIM0_H
5424 #define RTCHOUR RTCTIM1_L
5425 #define RTCDOW RTCTIM1_H
5426 #define RTCDAY RTCDATE_L
5427 #define RTCMON RTCDATE_H
5428 #define RTCYEARL RTCYEAR_L
5429 #define RT0PS RTCPS_L
5430 #define RT1PS RTCPS_H
5431 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
5432 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
5433 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
5434 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
5435 
5436 /* RTCCTL0 Control Bits */
5437 #define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
5438 #define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
5439 #define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
5440 #define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
5441 #define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
5442 #define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
5443 #define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
5444 #define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
5445 
5446 /* RTCCTL0 Control Bits */
5447 #define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
5448 #define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
5449 #define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
5450 #define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
5451 #define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
5452 #define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
5453 #define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
5454 #define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
5455 
5456 #define RTCKEY (0xA500) /* RTC Key for RTC write access */
5457 #define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */
5458 
5459 /* RTCCTL13 Control Bits */
5460 #define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
5461 #define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
5462 #define RTCBCD (0x0080) /* RTC BCD 0:Binary / 1:BCD */
5463 #define RTCHOLD (0x0040) /* RTC Hold */
5464 #define RTCMODE (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
5465 #define RTCRDY (0x0010) /* RTC Ready */
5466 #define RTCSSEL1 (0x0008) /* RTC Source Select 1 */
5467 #define RTCSSEL0 (0x0004) /* RTC Source Select 0 */
5468 #define RTCTEV1 (0x0002) /* RTC Time Event 1 */
5469 #define RTCTEV0 (0x0001) /* RTC Time Event 0 */
5470 
5471 /* RTCCTL13 Control Bits */
5472 #define RTCBCD_L (0x0080) /* RTC BCD 0:Binary / 1:BCD */
5473 #define RTCHOLD_L (0x0040) /* RTC Hold */
5474 #define RTCMODE_L (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
5475 #define RTCRDY_L (0x0010) /* RTC Ready */
5476 #define RTCSSEL1_L (0x0008) /* RTC Source Select 1 */
5477 #define RTCSSEL0_L (0x0004) /* RTC Source Select 0 */
5478 #define RTCTEV1_L (0x0002) /* RTC Time Event 1 */
5479 #define RTCTEV0_L (0x0001) /* RTC Time Event 0 */
5480 
5481 /* RTCCTL13 Control Bits */
5482 #define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
5483 #define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
5484 
5485 #define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */
5486 #define RTCSSEL_1 (0x0004) /* RTC Source Select SMCLK */
5487 #define RTCSSEL_2 (0x0008) /* RTC Source Select RT1PS */
5488 #define RTCSSEL_3 (0x000C) /* RTC Source Select RT1PS */
5489 #define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */
5490 #define RTCSSEL__SMCLK (0x0004) /* RTC Source Select SMCLK */
5491 #define RTCSSEL__RT1PS (0x0008) /* RTC Source Select RT1PS */
5492 
5493 #define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
5494 #define RTCTEV_1 (0x0001) /* RTC Time Event: 1 (Hour changed) */
5495 #define RTCTEV_2 (0x0002) /* RTC Time Event: 2 (12:00 changed) */
5496 #define RTCTEV_3 (0x0003) /* RTC Time Event: 3 (00:00 changed) */
5497 #define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
5498 #define RTCTEV__HOUR (0x0001) /* RTC Time Event: 1 (Hour changed) */
5499 #define RTCTEV__0000 (0x0002) /* RTC Time Event: 2 (00:00 changed) */
5500 #define RTCTEV__1200 (0x0003) /* RTC Time Event: 3 (12:00 changed) */
5501 
5502 #define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
5503 #define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
5504 #define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
5505 #define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
5506 
5507 /* RTCOCAL Control Bits */
5508 #define RTCOCALS (0x8000) /* RTC Offset Calibration Sign */
5509 #define RTCOCAL7 (0x0080) /* RTC Offset Calibration Bit 7 */
5510 #define RTCOCAL6 (0x0040) /* RTC Offset Calibration Bit 6 */
5511 #define RTCOCAL5 (0x0020) /* RTC Offset Calibration Bit 5 */
5512 #define RTCOCAL4 (0x0010) /* RTC Offset Calibration Bit 4 */
5513 #define RTCOCAL3 (0x0008) /* RTC Offset Calibration Bit 3 */
5514 #define RTCOCAL2 (0x0004) /* RTC Offset Calibration Bit 2 */
5515 #define RTCOCAL1 (0x0002) /* RTC Offset Calibration Bit 1 */
5516 #define RTCOCAL0 (0x0001) /* RTC Offset Calibration Bit 0 */
5517 
5518 /* RTCOCAL Control Bits */
5519 #define RTCOCAL7_L (0x0080) /* RTC Offset Calibration Bit 7 */
5520 #define RTCOCAL6_L (0x0040) /* RTC Offset Calibration Bit 6 */
5521 #define RTCOCAL5_L (0x0020) /* RTC Offset Calibration Bit 5 */
5522 #define RTCOCAL4_L (0x0010) /* RTC Offset Calibration Bit 4 */
5523 #define RTCOCAL3_L (0x0008) /* RTC Offset Calibration Bit 3 */
5524 #define RTCOCAL2_L (0x0004) /* RTC Offset Calibration Bit 2 */
5525 #define RTCOCAL1_L (0x0002) /* RTC Offset Calibration Bit 1 */
5526 #define RTCOCAL0_L (0x0001) /* RTC Offset Calibration Bit 0 */
5527 
5528 /* RTCOCAL Control Bits */
5529 #define RTCOCALS_H (0x0080) /* RTC Offset Calibration Sign */
5530 
5531 /* RTCTCMP Control Bits */
5532 #define RTCTCMPS (0x8000) /* RTC Temperature Compensation Sign */
5533 #define RTCTCRDY (0x4000) /* RTC Temperature compensation ready */
5534 #define RTCTCOK (0x2000) /* RTC Temperature compensation write OK */
5535 #define RTCTCMP7 (0x0080) /* RTC Temperature Compensation Bit 7 */
5536 #define RTCTCMP6 (0x0040) /* RTC Temperature Compensation Bit 6 */
5537 #define RTCTCMP5 (0x0020) /* RTC Temperature Compensation Bit 5 */
5538 #define RTCTCMP4 (0x0010) /* RTC Temperature Compensation Bit 4 */
5539 #define RTCTCMP3 (0x0008) /* RTC Temperature Compensation Bit 3 */
5540 #define RTCTCMP2 (0x0004) /* RTC Temperature Compensation Bit 2 */
5541 #define RTCTCMP1 (0x0002) /* RTC Temperature Compensation Bit 1 */
5542 #define RTCTCMP0 (0x0001) /* RTC Temperature Compensation Bit 0 */
5543 
5544 /* RTCTCMP Control Bits */
5545 #define RTCTCMP7_L (0x0080) /* RTC Temperature Compensation Bit 7 */
5546 #define RTCTCMP6_L (0x0040) /* RTC Temperature Compensation Bit 6 */
5547 #define RTCTCMP5_L (0x0020) /* RTC Temperature Compensation Bit 5 */
5548 #define RTCTCMP4_L (0x0010) /* RTC Temperature Compensation Bit 4 */
5549 #define RTCTCMP3_L (0x0008) /* RTC Temperature Compensation Bit 3 */
5550 #define RTCTCMP2_L (0x0004) /* RTC Temperature Compensation Bit 2 */
5551 #define RTCTCMP1_L (0x0002) /* RTC Temperature Compensation Bit 1 */
5552 #define RTCTCMP0_L (0x0001) /* RTC Temperature Compensation Bit 0 */
5553 
5554 /* RTCTCMP Control Bits */
5555 #define RTCTCMPS_H (0x0080) /* RTC Temperature Compensation Sign */
5556 #define RTCTCRDY_H (0x0040) /* RTC Temperature compensation ready */
5557 #define RTCTCOK_H (0x0020) /* RTC Temperature compensation write OK */
5558 
5559 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
5560 
5561 /* RTCPS0CTL Control Bits */
5562 //#define Reserved (0x8000)
5563 //#define Reserved (0x4000)
5564 #define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
5565 #define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
5566 #define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
5567 //#define Reserved (0x0400)
5568 //#define Reserved (0x0200)
5569 #define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */
5570 //#define Reserved (0x0080)
5571 //#define Reserved (0x0040)
5572 //#define Reserved (0x0020)
5573 #define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
5574 #define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
5575 #define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
5576 #define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
5577 #define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
5578 
5579 /* RTCPS0CTL Control Bits */
5580 //#define Reserved (0x8000)
5581 //#define Reserved (0x4000)
5582 //#define Reserved (0x0400)
5583 //#define Reserved (0x0200)
5584 //#define Reserved (0x0080)
5585 //#define Reserved (0x0040)
5586 //#define Reserved (0x0020)
5587 #define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
5588 #define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
5589 #define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
5590 #define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
5591 #define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
5592 
5593 /* RTCPS0CTL Control Bits */
5594 //#define Reserved (0x8000)
5595 //#define Reserved (0x4000)
5596 #define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
5597 #define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
5598 #define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
5599 //#define Reserved (0x0400)
5600 //#define Reserved (0x0200)
5601 #define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */
5602 //#define Reserved (0x0080)
5603 //#define Reserved (0x0040)
5604 //#define Reserved (0x0020)
5605 
5606 #define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
5607 #define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
5608 #define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
5609 #define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
5610 #define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
5611 #define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
5612 #define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
5613 #define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
5614 
5615 /* RTCPS1CTL Control Bits */
5616 #define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */
5617 #define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */
5618 #define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
5619 #define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
5620 #define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
5621 //#define Reserved (0x0400)
5622 //#define Reserved (0x0200)
5623 #define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */
5624 //#define Reserved (0x0080)
5625 //#define Reserved (0x0040)
5626 //#define Reserved (0x0020)
5627 #define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
5628 #define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
5629 #define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
5630 #define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
5631 #define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
5632 
5633 /* RTCPS1CTL Control Bits */
5634 //#define Reserved (0x0400)
5635 //#define Reserved (0x0200)
5636 //#define Reserved (0x0080)
5637 //#define Reserved (0x0040)
5638 //#define Reserved (0x0020)
5639 #define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
5640 #define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
5641 #define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
5642 #define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
5643 #define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
5644 
5645 /* RTCPS1CTL Control Bits */
5646 #define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */
5647 #define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */
5648 #define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
5649 #define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
5650 #define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
5651 //#define Reserved (0x0400)
5652 //#define Reserved (0x0200)
5653 #define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */
5654 //#define Reserved (0x0080)
5655 //#define Reserved (0x0040)
5656 //#define Reserved (0x0020)
5657 
5658 #define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
5659 #define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
5660 #define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
5661 #define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
5662 #define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
5663 #define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
5664 #define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
5665 #define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
5666 
5667 /* RTCTCCTL0 Control Bits */
5668 #define TCEN (0x0001) /* RTC Enable for RTC Tamper Detection with Time Stamp */
5669 #define AUX3RST (0x0002) /* RTC Indication of power cycle on AUXVCC3 */
5670 
5671 /* RTCTCCTL1 Control Bits */
5672 #define RTCCAPIFG (0x0001) /* RTC Tamper Event Interrupt Flag */
5673 #define RTCCAPIE (0x0002) /* RTC Tamper Event Interrupt Enable */
5674 
5675 /* RTCCAPxCTL Control Bits */
5676 #define CAPEV (0x0001) /* RTC Tamper Event Flag */
5677 #define CAPES (0x0004) /* RTC Event Edge Select */
5678 #define RTCREN (0x0008) /* RTC RTCCAPx pin pullup/pulldown resistor enable */
5679 #define RTCCAPIN (0x0010) /* RTC RTCCAPx input */
5680 #define RTCCAPDIR (0x0020) /* RTC RTCCAPx Pin direction */
5681 #define RTCCAPOUT (0x0040) /* RTC RTCCAPx Output */
5682 
5683 /* RTCIV Definitions */
5684 #define RTCIV_NONE (0x0000) /* No Interrupt pending */
5685 #define RTCIV_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */
5686 #define RTCIV_RTCCAPIFG (0x0004) /* RTC RTC Tamper Event: RTCCAPIFG */
5687 #define RTCIV_RTCRDYIFG (0x0006) /* RTC ready: RTCRDYIFG */
5688 #define RTCIV_RTCTEVIFG (0x0008) /* RTC interval timer: RTCTEVIFG */
5689 #define RTCIV_RTCAIFG (0x000A) /* RTC user alarm: RTCAIFG */
5690 #define RTCIV_RT0PSIFG (0x000C) /* RTC prescaler 0: RT0PSIFG */
5691 #define RTCIV_RT1PSIFG (0x000E) /* RTC prescaler 1: RT1PSIFG */
5692 
5693 /* Legacy RTCIV Definitions */
5694 #define RTC_NONE (0x0000) /* No Interrupt pending */
5695 #define RTC_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */
5696 #define RTC_RTCRDYIFG (0x0006) /* RTC ready: RTCRDYIFG */
5697 #define RTC_RTCTEVIFG (0x0008) /* RTC interval timer: RTCTEVIFG */
5698 #define RTC_RTCAIFG (0x000A) /* RTC user alarm: RTCAIFG */
5699 #define RTC_RT0PSIFG (0x000C) /* RTC prescaler 0: RT0PSIFG */
5700 #define RTC_RT1PSIFG (0x000E) /* RTC prescaler 1: RT1PSIFG */
5701 
5702 #endif
5703 /************************************************************
5704 * SD24_B - Sigma Delta 24 Bit
5705 ************************************************************/
5706 #ifdef __MSP430_HAS_SD24_B__ /* Definition to show that Module is available */
5707 
5708 #define OFS_SD24BCTL0 (0x0000) /* SD24B Control Register 0 */
5709 #define OFS_SD24BCTL0_L OFS_SD24BCTL0
5710 #define OFS_SD24BCTL0_H OFS_SD24BCTL0+1
5711 #define OFS_SD24BCTL1 (0x0002) /* SD24B Control Register 1 */
5712 #define OFS_SD24BCTL1_L OFS_SD24BCTL1
5713 #define OFS_SD24BCTL1_H OFS_SD24BCTL1+1
5714 #define OFS_SD24BTRGCTL (0x0004) /* SD24B Trigger Control Register */
5715 #define OFS_SD24BTRGCTL_L OFS_SD24BTRGCTL
5716 #define OFS_SD24BTRGCTL_H OFS_SD24BTRGCTL+1
5717 #define OFS_SD24BTRGOSR (0x0006) /* SD24B Trigger OSR Control Register */
5718 #define OFS_SD24BTRGOSR_L OFS_SD24BTRGOSR
5719 #define OFS_SD24BTRGOSR_H OFS_SD24BTRGOSR+1
5720 #define OFS_SD24BTRGPRE (0x0008) /* SD24B Trigger Preload Register */
5721 #define OFS_SD24BTRGPRE_L OFS_SD24BTRGPRE
5722 #define OFS_SD24BTRGPRE_H OFS_SD24BTRGPRE+1
5723 #define OFS_SD24BIFG (0x000A) /* SD24B Interrupt Flag Register */
5724 #define OFS_SD24BIFG_L OFS_SD24BIFG
5725 #define OFS_SD24BIFG_H OFS_SD24BIFG+1
5726 #define OFS_SD24BIE (0x000C) /* SD24B Interrupt Enable Register */
5727 #define OFS_SD24BIE_L OFS_SD24BIE
5728 #define OFS_SD24BIE_H OFS_SD24BIE+1
5729 #define OFS_SD24BIV (0x000E) /* SD24B Interrupt Vector Register */
5730 #define OFS_SD24BIV_L OFS_SD24BIV
5731 #define OFS_SD24BIV_H OFS_SD24BIV+1
5732 
5733 #define OFS_SD24BCCTL0 (0x0010) /* SD24B Channel 0 Control Register */
5734 #define OFS_SD24BCCTL0_L OFS_SD24BCCTL0
5735 #define OFS_SD24BCCTL0_H OFS_SD24BCCTL0+1
5736 #define OFS_SD24BINCTL0 (0x0012) /* SD24B Channel 0 Input Control Register */
5737 #define OFS_SD24BINCTL0_L OFS_SD24BINCTL0
5738 #define OFS_SD24BINCTL0_H OFS_SD24BINCTL0+1
5739 #define OFS_SD24BOSR0 (0x0014) /* SD24B Channel 0 OSR Control Register */
5740 #define OFS_SD24BOSR0_L OFS_SD24BOSR0
5741 #define OFS_SD24BOSR0_H OFS_SD24BOSR0+1
5742 #define OFS_SD24BPRE0 (0x0016) /* SD24B Channel 0 Preload Register */
5743 #define OFS_SD24BPRE0_L OFS_SD24BPRE0
5744 #define OFS_SD24BPRE0_H OFS_SD24BPRE0+1
5745 
5746 #define OFS_SD24BMEML0 (0x0050) /* SD24B Channel 0 Conversion Memory Low word */
5747 #define OFS_SD24BMEML0_L OFS_SD24BMEML0
5748 #define OFS_SD24BMEML0_H OFS_SD24BMEML0+1
5749 #define OFS_SD24BMEMH0 (0x0052) /* SD24B Channel 0 Conversion Memory High Word */
5750 #define OFS_SD24BMEMH0_L OFS_SD24BMEMH0
5751 #define OFS_SD24BMEMH0_H OFS_SD24BMEMH0+1
5752 
5753 /* SD24BCTL0 */
5754 #define SD24OV32 (0x0002) /* SD24B Overflow Control */
5755 #define SD24REFS (0x0004) /* SD24B Reference Select */
5756 #define SD24SSEL0 (0x0010) /* SD24B Clock Source Select 0 */
5757 #define SD24SSEL1 (0x0020) /* SD24B Clock Source Select 1 */
5758 #define SD24M4 (0x0040) /* SD24B Modulator clock to Manchester decoder clock ratio */
5759 #define SD24CLKOS (0x0080) /* SD24B Clock Output Select */
5760 #define SD24PDIV0 (0x0100) /* SD24B Frequency pre-scaler Bit 0 */
5761 #define SD24PDIV1 (0x0200) /* SD24B Frequency pre-scaler Bit 1 */
5762 #define SD24PDIV2 (0x0400) /* SD24B Frequency pre-scaler Bit 2 */
5763 #define SD24DIV0 (0x0800) /* SD24B Frequency Divider Bit 0 */
5764 #define SD24DIV1 (0x1000) /* SD24B Frequency Divider Bit 1 */
5765 #define SD24DIV2 (0x2000) /* SD24B Frequency Divider Bit 2 */
5766 #define SD24DIV3 (0x4000) /* SD24B Frequency Divider Bit 3 */
5767 #define SD24DIV4 (0x8000) /* SD24B Frequency Divider Bit 4 */
5768 
5769 #define SD24OV32_L (0x0002) /* SD24B Overflow Control */
5770 #define SD24REFS_L (0x0004) /* SD24B Reference Select */
5771 #define SD24SSEL0_L (0x0010) /* SD24B Clock Source Select 0 */
5772 #define SD24SSEL1_L (0x0020) /* SD24B Clock Source Select 1 */
5773 #define SD24M4_L (0x0040) /* SD24B Modulator clock to Manchester decoder clock ratio */
5774 #define SD24CLKOS_L (0x0080) /* SD24B Clock Output Select */
5775 
5776 #define SD24PDIV0_H (0x0001) /* SD24B Frequency pre-scaler Bit 0 */
5777 #define SD24PDIV1_H (0x0002) /* SD24B Frequency pre-scaler Bit 1 */
5778 #define SD24PDIV2_H (0x0004) /* SD24B Frequency pre-scaler Bit 2 */
5779 #define SD24DIV0_H (0x0008) /* SD24B Frequency Divider Bit 0 */
5780 #define SD24DIV1_H (0x0010) /* SD24B Frequency Divider Bit 1 */
5781 #define SD24DIV2_H (0x0020) /* SD24B Frequency Divider Bit 2 */
5782 #define SD24DIV3_H (0x0040) /* SD24B Frequency Divider Bit 3 */
5783 #define SD24DIV4_H (0x0080) /* SD24B Frequency Divider Bit 4 */
5784 
5785 #define SD24SSEL_0 (0x0000) /* SD24B Clock Source Select MCLK */
5786 #define SD24SSEL_1 (0x0010) /* SD24B Clock Source Select SMCLK */
5787 #define SD24SSEL_2 (0x0020) /* SD24B Clock Source Select ACLK */
5788 #define SD24SSEL_3 (0x0030) /* SD24B Clock Source Select TACLK */
5789 #define SD24SSEL__MCLK (0x0000) /* SD24B Clock Source Select MCLK */
5790 #define SD24SSEL__SMCLK (0x0010) /* SD24B Clock Source Select SMCLK */
5791 #define SD24SSEL__ACLK (0x0020) /* SD24B Clock Source Select ACLK */
5792 #define SD24SSEL__SD24CLK (0x0030) /* SD24B Clock Source Select SD24CLK */
5793 
5794 #define SD24PDIV_0 (0x0000) /* SD24B Frequency pre-scaler /1 */
5795 #define SD24PDIV_1 (0x0100) /* SD24B Frequency pre-scaler /2 */
5796 #define SD24PDIV_2 (0x0200) /* SD24B Frequency pre-scaler /4 */
5797 #define SD24PDIV_3 (0x0300) /* SD24B Frequency pre-scaler /8 */
5798 #define SD24PDIV_4 (0x0400) /* SD24B Frequency pre-scaler /16 */
5799 #define SD24PDIV_5 (0x0500) /* SD24B Frequency pre-scaler /32 */
5800 #define SD24PDIV_6 (0x0600) /* SD24B Frequency pre-scaler /64 */
5801 #define SD24PDIV_7 (0x0700) /* SD24B Frequency pre-scaler /128 */
5802 
5803 /* SD24BCTL1 */
5804 #define SD24GRP0SC (0x0001) /* SD24B Group 0 Start Conversion */
5805 #define SD24GRP1SC (0x0002) /* SD24B Group 1 Start Conversion */
5806 #define SD24GRP2SC (0x0004) /* SD24B Group 2 Start Conversion */
5807 #define SD24GRP3SC (0x0008) /* SD24B Group 3 Start Conversion */
5808 #define SD24DMA0 (0x0100) /* SD24B DMA Trigger Select Bit 0 */
5809 #define SD24DMA1 (0x0200) /* SD24B DMA Trigger Select Bit 1 */
5810 #define SD24DMA2 (0x0400) /* SD24B DMA Trigger Select Bit 2 */
5811 #define SD24DMA3 (0x0800) /* SD24B DMA Trigger Select Bit 3 */
5812 
5813 #define SD24GRP0SC_L (0x0001) /* SD24B Group 0 Start Conversion */
5814 #define SD24GRP1SC_L (0x0002) /* SD24B Group 1 Start Conversion */
5815 #define SD24GRP2SC_L (0x0004) /* SD24B Group 2 Start Conversion */
5816 #define SD24GRP3SC_L (0x0008) /* SD24B Group 3 Start Conversion */
5817 
5818 #define SD24DMA0_H (0x0001) /* SD24B DMA Trigger Select Bit 0 */
5819 #define SD24DMA1_H (0x0002) /* SD24B DMA Trigger Select Bit 1 */
5820 #define SD24DMA2_H (0x0004) /* SD24B DMA Trigger Select Bit 2 */
5821 #define SD24DMA3_H (0x0008) /* SD24B DMA Trigger Select Bit 3 */
5822 
5823 #define SD24DMA_0 (0x0000) /* SD24B DMA Trigger: 0 */
5824 #define SD24DMA_1 (0x0100) /* SD24B DMA Trigger: 1 */
5825 #define SD24DMA_2 (0x0200) /* SD24B DMA Trigger: 2 */
5826 #define SD24DMA_3 (0x0300) /* SD24B DMA Trigger: 3 */
5827 #define SD24DMA_4 (0x0400) /* SD24B DMA Trigger: 4 */
5828 #define SD24DMA_5 (0x0500) /* SD24B DMA Trigger: 5 */
5829 #define SD24DMA_6 (0x0600) /* SD24B DMA Trigger: 6 */
5830 #define SD24DMA_7 (0x0700) /* SD24B DMA Trigger: 7 */
5831 #define SD24DMA_8 (0x0800) /* SD24B DMA Trigger: 8 */
5832 
5833 /* SD24BTRGCTL */
5834 #define SD24SC (0x0001) /* SD24B Start Conversion */
5835 #define SD24SCS0 (0x0002) /* SD24B Start Conversion Select Bit 0 */
5836 #define SD24SCS1 (0x0004) /* SD24B Start Conversion Select Bit 1 */
5837 #define SD24SCS2 (0x0008) /* SD24B Start Conversion Select Bit 2 */
5838 #define SD24SNGL (0x0100) /* SD24B Single Trigger Mode */
5839 #define SD24TRGIFG (0x0400) /* SD24B Trigger Interrupt Flag */
5840 #define SD24TRGIE (0x0800) /* SD24B Trigger Interrupt Enable */
5841 
5842 #define SD24SC_L (0x0001) /* SD24B Start Conversion */
5843 #define SD24SCS0_L (0x0002) /* SD24B Start Conversion Select Bit 0 */
5844 #define SD24SCS1_L (0x0004) /* SD24B Start Conversion Select Bit 1 */
5845 #define SD24SCS2_L (0x0008) /* SD24B Start Conversion Select Bit 2 */
5846 
5847 #define SD24SNGL_H (0x0001) /* SD24B Single Trigger Mode */
5848 #define SD24TRGIFG_H (0x0004) /* SD24B Trigger Interrupt Flag */
5849 #define SD24TRGIE_H (0x0008) /* SD24B Trigger Interrupt Enable */
5850 
5851 #define SD24SCS_0 (0x0000) /* SD24B Start Conversion Select: 0 */
5852 #define SD24SCS_1 (0x0002) /* SD24B Start Conversion Select: 1 */
5853 #define SD24SCS_2 (0x0004) /* SD24B Start Conversion Select: 2 */
5854 #define SD24SCS_3 (0x0006) /* SD24B Start Conversion Select: 3 */
5855 #define SD24SCS_4 (0x0008) /* SD24B Start Conversion Select: 4 */
5856 #define SD24SCS_5 (0x000A) /* SD24B Start Conversion Select: 5 */
5857 #define SD24SCS_6 (0x000C) /* SD24B Start Conversion Select: 6 */
5858 #define SD24SCS_7 (0x000E) /* SD24B Start Conversion Select: 7 */
5859 #define SD24SCS__SD24SC (0x0000) /* SD24B Start Conversion Select: SD24SC */
5860 #define SD24SCS__EXT1 (0x0002) /* SD24B Start Conversion Select: EXT1 */
5861 #define SD24SCS__EXT2 (0x0004) /* SD24B Start Conversion Select: EXT2 */
5862 #define SD24SCS__EXT3 (0x0006) /* SD24B Start Conversion Select: EXT3 */
5863 #define SD24SCS__GROUP0 (0x0008) /* SD24B Start Conversion Select: GROUP0 */
5864 #define SD24SCS__GROUP1 (0x000A) /* SD24B Start Conversion Select: GROUP1 */
5865 #define SD24SCS__GROUP2 (0x000C) /* SD24B Start Conversion Select: GROUP2 */
5866 #define SD24SCS__GROUP3 (0x000E) /* SD24B Start Conversion Select: GROUP3 */
5867 
5868 /* SD24BIFG */
5869 #define SD24IFG0 (0x0001) /* SD24B Channel 0 Interrupt Flag */
5870 #define SD24OVIFG0 (0x0100) /* SD24B Channel 0 Overflow Interrupt Flag */
5871 
5872 #define SD24IFG0_L (0x0001) /* SD24B Channel 0 Interrupt Flag */
5873 
5874 #define SD24OVIFG0_H (0x0001) /* SD24B Channel 0 Overflow Interrupt Flag */
5875 
5876 /* SD24BIE */
5877 #define SD24IE0 (0x0001) /* SD24B Channel 0 Interrupt Enable */
5878 #define SD24OVIE0 (0x0100) /* SD24B Channel 0 Overflow Interrupt Enable */
5879 
5880 #define SD24IE0_L (0x0001) /* SD24B Channel 0 Interrupt Enable */
5881 
5882 #define SD24OVIE0_H (0x0001) /* SD24B Channel 0 Overflow Interrupt Enable */
5883 
5884 /* SD24BIV Definitions */
5885 #define SD24BIV_NONE (0x0000) /* No Interrupt pending */
5886 #define SD24BIV_SD24OVIFG (0x0002) /* SD24OVIFG */
5887 #define SD24BIV_SD24TRGIFG (0x0004) /* SD24TRGIFG */
5888 #define SD24BIV_SD24IFG0 (0x0006) /* SD24IFG0 */
5889 
5890 /* SD24BCCTLx */
5891 #define SD24DF0 (0x0010) /* SD24B Data Format Bit: 0 */
5892 #define SD24DF1 (0x0020) /* SD24B Data Format Bit: 1 */
5893 #define SD24ALGN (0x0040) /* SD24B Data Alignment */
5894 #define SD24CAL (0x0200) /* SD24B Calibration */
5895 #define SD24DFS0 (0x0400) /* SD24B Digital Filter Bit: 0 */
5896 #define SD24DFS1 (0x0800) /* SD24B Digital Filter Bit: 1 */
5897 #define SD24DI (0x1000) /* SD24B Digital Bitstream Input */
5898 #define SD24MC0 (0x2000) /* SD24B Manchaster Encoding Bit: 0 */
5899 #define SD24MC1 (0x4000) /* SD24B Manchaster Encoding Bit: 1 */
5900 
5901 #define SD24DF0_L (0x0010) /* SD24B Data Format Bit: 0 */
5902 #define SD24DF1_L (0x0020) /* SD24B Data Format Bit: 1 */
5903 #define SD24ALGN_L (0x0040) /* SD24B Data Alignment */
5904 
5905 #define SD24CAL_H (0x0002) /* SD24B Calibration */
5906 #define SD24DFS0_H (0x0004) /* SD24B Digital Filter Bit: 0 */
5907 #define SD24DFS1_H (0x0008) /* SD24B Digital Filter Bit: 1 */
5908 #define SD24DI_H (0x0010) /* SD24B Digital Bitstream Input */
5909 #define SD24MC0_H (0x0020) /* SD24B Manchaster Encoding Bit: 0 */
5910 #define SD24MC1_H (0x0040) /* SD24B Manchaster Encoding Bit: 1 */
5911 
5912 #define SD24DF_0 (0x0000) /* SD24B Data Format: Offset Binary */
5913 #define SD24DF_1 (0x0010) /* SD24B Data Format: 2's complement */
5914 
5915 #define SD24DFS_0 (0x0000) /* SD24B Digital Filter 0 */
5916 #define SD24DFS_1 (0x0400) /* SD24B Digital Filter 1 */
5917 #define SD24DFS_2 (0x0800) /* SD24B Digital Filter 2 */
5918 #define SD24DFS_3 (0x0C00) /* SD24B Digital Filter 3 */
5919 
5920 #define SD24MC_0 (0x0000) /* SD24B Manchaster Encoding 0 */
5921 #define SD24MC_1 (0x2000) /* SD24B Manchaster Encoding 1 */
5922 #define SD24MC_2 (0x4000) /* SD24B Manchaster Encoding 2 */
5923 #define SD24MC_3 (0x6000) /* SD24B Manchaster Encoding 3 */
5924 
5925 /* SD24BINCTLx */
5926 #define SD24GAIN0 (0x0008) /* SD24B Input Pre-Amplifier Gain Select 0 */
5927 #define SD24GAIN1 (0x0010) /* SD24B Input Pre-Amplifier Gain Select 1 */
5928 #define SD24GAIN2 (0x0020) /* SD24B Input Pre-Amplifier Gain Select 2 */
5929 #define SD24INTDLY0 (0x0040) /* SD24B Interrupt Delay after 1.Conversion 0 */
5930 #define SD24INTDLY1 (0x0080) /* SD24B Interrupt Delay after 1.Conversion 1 */
5931 
5932 #define SD24GAIN0_L (0x0008) /* SD24B Input Pre-Amplifier Gain Select 0 */
5933 #define SD24GAIN1_L (0x0010) /* SD24B Input Pre-Amplifier Gain Select 1 */
5934 #define SD24GAIN2_L (0x0020) /* SD24B Input Pre-Amplifier Gain Select 2 */
5935 #define SD24INTDLY0_L (0x0040) /* SD24B Interrupt Delay after 1.Conversion 0 */
5936 #define SD24INTDLY1_L (0x0080) /* SD24B Interrupt Delay after 1.Conversion 1 */
5937 
5938 #define SD24GAIN_1 (0x0000) /* SD24B Input Pre-Amplifier Gain Select *1 */
5939 #define SD24GAIN_2 (0x0008) /* SD24B Input Pre-Amplifier Gain Select *2 */
5940 #define SD24GAIN_4 (0x0010) /* SD24B Input Pre-Amplifier Gain Select *4 */
5941 #define SD24GAIN_8 (0x0018) /* SD24B Input Pre-Amplifier Gain Select *8 */
5942 #define SD24GAIN_16 (0x0020) /* SD24B Input Pre-Amplifier Gain Select *16 */
5943 #define SD24GAIN_32 (0x0028) /* SD24B Input Pre-Amplifier Gain Select *32 */
5944 #define SD24GAIN_64 (0x0030) /* SD24B Input Pre-Amplifier Gain Select *64 */
5945 #define SD24GAIN_128 (0x0038) /* SD24B Input Pre-Amplifier Gain Select *128 */
5946 
5947 #define SD24INTDLY_0 (0x0000) /* SD24B Interrupt Delay: Int. after 4.Conversion */
5948 #define SD24INTDLY_1 (0x0040) /* SD24B Interrupt Delay: Int. after 3.Conversion */
5949 #define SD24INTDLY_2 (0x0080) /* SD24B Interrupt Delay: Int. after 2.Conversion */
5950 #define SD24INTDLY_3 (0x00C0) /* SD24B Interrupt Delay: Int. after 1.Conversion */
5951 
5952 /* SD24BOSRx */
5953 #define OSR0 (0x0001) /* SD24B Oversampling Rate Bit: 0 */
5954 #define OSR1 (0x0002) /* SD24B Oversampling Rate Bit: 1 */
5955 #define OSR2 (0x0004) /* SD24B Oversampling Rate Bit: 2 */
5956 #define OSR3 (0x0008) /* SD24B Oversampling Rate Bit: 3 */
5957 #define OSR4 (0x0010) /* SD24B Oversampling Rate Bit: 4 */
5958 #define OSR5 (0x0020) /* SD24B Oversampling Rate Bit: 5 */
5959 #define OSR6 (0x0040) /* SD24B Oversampling Rate Bit: 6 */
5960 #define OSR7 (0x0080) /* SD24B Oversampling Rate Bit: 7 */
5961 #define OSR8 (0x0100) /* SD24B Oversampling Rate Bit: 8 */
5962 #define OSR9 (0x0200) /* SD24B Oversampling Rate Bit: 9 */
5963 #define OSR10 (0x0400) /* SD24B Oversampling Rate Bit: 10 */
5964 
5965 #define OSR0_L (0x0001) /* SD24B Oversampling Rate Bit: 0 */
5966 #define OSR1_L (0x0002) /* SD24B Oversampling Rate Bit: 1 */
5967 #define OSR2_L (0x0004) /* SD24B Oversampling Rate Bit: 2 */
5968 #define OSR3_L (0x0008) /* SD24B Oversampling Rate Bit: 3 */
5969 #define OSR4_L (0x0010) /* SD24B Oversampling Rate Bit: 4 */
5970 #define OSR5_L (0x0020) /* SD24B Oversampling Rate Bit: 5 */
5971 #define OSR6_L (0x0040) /* SD24B Oversampling Rate Bit: 6 */
5972 #define OSR7_L (0x0080) /* SD24B Oversampling Rate Bit: 7 */
5973 
5974 #define OSR8_H (0x0001) /* SD24B Oversampling Rate Bit: 8 */
5975 #define OSR9_H (0x0002) /* SD24B Oversampling Rate Bit: 9 */
5976 #define OSR10_H (0x0004) /* SD24B Oversampling Rate Bit: 10 */
5977 
5978 /* SD24BTRGOSR */
5979 
5980 #define OSR__32 (32-1) /* SD24B Oversampling Rate: 32 */
5981 #define OSR__64 (64-1) /* SD24B Oversampling Rate: 64 */
5982 #define OSR__128 (128-1) /* SD24B Oversampling Rate: 128 */
5983 #define OSR__256 (256-1) /* SD24B Oversampling Rate: 256 */
5984 #define OSR__512 (512-1) /* SD24B Oversampling Rate: 512 */
5985 #define OSR__1024 (1024-1) /* SD24B Oversampling Rate: 1024 */
5986 
5987 
5988 #endif
5989 /************************************************************
5990 * SFR - Special Function Register Module
5991 ************************************************************/
5992 #ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */
5993 
5994 #define OFS_SFRIE1 (0x0000) /* Interrupt Enable 1 */
5995 #define OFS_SFRIE1_L OFS_SFRIE1
5996 #define OFS_SFRIE1_H OFS_SFRIE1+1
5997 
5998 /* SFRIE1 Control Bits */
5999 #define WDTIE (0x0001) /* WDT Interrupt Enable */
6000 #define OFIE (0x0002) /* Osc Fault Enable */
6001 //#define Reserved (0x0004)
6002 #define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */
6003 #define NMIIE (0x0010) /* NMI Interrupt Enable */
6004 #ifndef ACCVIE
6005 #define ACCVIE (0x0020) /* Flash Access Violation Interrupt Enable */
6006 #endif
6007 #define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */
6008 #define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */
6009 
6010 #define WDTIE_L (0x0001) /* WDT Interrupt Enable */
6011 #define OFIE_L (0x0002) /* Osc Fault Enable */
6012 //#define Reserved (0x0004)
6013 #define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */
6014 #define NMIIE_L (0x0010) /* NMI Interrupt Enable */
6015 #ifndef ACCVIE
6016 #define ACCVIE_L (0x0020) /* Flash Access Violation Interrupt Enable */
6017 #endif
6018 #define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */
6019 #define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */
6020 
6021 #define OFS_SFRIFG1 (0x0002) /* Interrupt Flag 1 */
6022 #define OFS_SFRIFG1_L OFS_SFRIFG1
6023 #define OFS_SFRIFG1_H OFS_SFRIFG1+1
6024 /* SFRIFG1 Control Bits */
6025 #define WDTIFG (0x0001) /* WDT Interrupt Flag */
6026 #define OFIFG (0x0002) /* Osc Fault Flag */
6027 //#define Reserved (0x0004)
6028 #define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */
6029 #define NMIIFG (0x0010) /* NMI Interrupt Flag */
6030 //#define Reserved (0x0020)
6031 #define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */
6032 #define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */
6033 
6034 #define WDTIFG_L (0x0001) /* WDT Interrupt Flag */
6035 #define OFIFG_L (0x0002) /* Osc Fault Flag */
6036 //#define Reserved (0x0004)
6037 #define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */
6038 #define NMIIFG_L (0x0010) /* NMI Interrupt Flag */
6039 //#define Reserved (0x0020)
6040 #define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */
6041 #define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */
6042 
6043 #define OFS_SFRRPCR (0x0004) /* RESET Pin Control Register */
6044 #define OFS_SFRRPCR_L OFS_SFRRPCR
6045 #define OFS_SFRRPCR_H OFS_SFRRPCR+1
6046 /* SFRRPCR Control Bits */
6047 #define SYSNMI (0x0001) /* NMI select */
6048 #define SYSNMIIES (0x0002) /* NMI edge select */
6049 #define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */
6050 #define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */
6051 
6052 #define SYSNMI_L (0x0001) /* NMI select */
6053 #define SYSNMIIES_L (0x0002) /* NMI edge select */
6054 #define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */
6055 #define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */
6056 
6057 #endif
6058 /************************************************************
6059 * SYS - System Module
6060 ************************************************************/
6061 #ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */
6062 
6063 #define OFS_SYSCTL (0x0000) /* System control */
6064 #define OFS_SYSCTL_L OFS_SYSCTL
6065 #define OFS_SYSCTL_H OFS_SYSCTL+1
6066 #define OFS_SYSBSLC (0x0002) /* Boot strap configuration area */
6067 #define OFS_SYSBSLC_L OFS_SYSBSLC
6068 #define OFS_SYSBSLC_H OFS_SYSBSLC+1
6069 #define OFS_SYSJMBC (0x0006) /* JTAG mailbox control */
6070 #define OFS_SYSJMBC_L OFS_SYSJMBC
6071 #define OFS_SYSJMBC_H OFS_SYSJMBC+1
6072 #define OFS_SYSJMBI0 (0x0008) /* JTAG mailbox input 0 */
6073 #define OFS_SYSJMBI0_L OFS_SYSJMBI0
6074 #define OFS_SYSJMBI0_H OFS_SYSJMBI0+1
6075 #define OFS_SYSJMBI1 (0x000A) /* JTAG mailbox input 1 */
6076 #define OFS_SYSJMBI1_L OFS_SYSJMBI1
6077 #define OFS_SYSJMBI1_H OFS_SYSJMBI1+1
6078 #define OFS_SYSJMBO0 (0x000C) /* JTAG mailbox output 0 */
6079 #define OFS_SYSJMBO0_L OFS_SYSJMBO0
6080 #define OFS_SYSJMBO0_H OFS_SYSJMBO0+1
6081 #define OFS_SYSJMBO1 (0x000E) /* JTAG mailbox output 1 */
6082 #define OFS_SYSJMBO1_L OFS_SYSJMBO1
6083 #define OFS_SYSJMBO1_H OFS_SYSJMBO1+1
6084 
6085 #define OFS_SYSBERRIV (0x0018) /* Bus Error vector generator */
6086 #define OFS_SYSBERRIV_L OFS_SYSBERRIV
6087 #define OFS_SYSBERRIV_H OFS_SYSBERRIV+1
6088 #define OFS_SYSUNIV (0x001A) /* User NMI vector generator */
6089 #define OFS_SYSUNIV_L OFS_SYSUNIV
6090 #define OFS_SYSUNIV_H OFS_SYSUNIV+1
6091 #define OFS_SYSSNIV (0x001C) /* System NMI vector generator */
6092 #define OFS_SYSSNIV_L OFS_SYSSNIV
6093 #define OFS_SYSSNIV_H OFS_SYSSNIV+1
6094 #define OFS_SYSRSTIV (0x001E) /* Reset vector generator */
6095 #define OFS_SYSRSTIV_L OFS_SYSRSTIV
6096 #define OFS_SYSRSTIV_H OFS_SYSRSTIV+1
6097 
6098 /* SYSCTL Control Bits */
6099 #define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */
6100 //#define RESERVED (0x0002) /* SYS - Reserved */
6101 #define SYSPMMPE (0x0004) /* SYS - PMM access protect */
6102 //#define RESERVED (0x0008) /* SYS - Reserved */
6103 #define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */
6104 #define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */
6105 //#define RESERVED (0x0040) /* SYS - Reserved */
6106 //#define RESERVED (0x0080) /* SYS - Reserved */
6107 //#define RESERVED (0x0100) /* SYS - Reserved */
6108 //#define RESERVED (0x0200) /* SYS - Reserved */
6109 //#define RESERVED (0x0400) /* SYS - Reserved */
6110 //#define RESERVED (0x0800) /* SYS - Reserved */
6111 //#define RESERVED (0x1000) /* SYS - Reserved */
6112 //#define RESERVED (0x2000) /* SYS - Reserved */
6113 //#define RESERVED (0x4000) /* SYS - Reserved */
6114 //#define RESERVED (0x8000) /* SYS - Reserved */
6115 
6116 /* SYSCTL Control Bits */
6117 #define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */
6118 //#define RESERVED (0x0002) /* SYS - Reserved */
6119 #define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */
6120 //#define RESERVED (0x0008) /* SYS - Reserved */
6121 #define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */
6122 #define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */
6123 //#define RESERVED (0x0040) /* SYS - Reserved */
6124 //#define RESERVED (0x0080) /* SYS - Reserved */
6125 //#define RESERVED (0x0100) /* SYS - Reserved */
6126 //#define RESERVED (0x0200) /* SYS - Reserved */
6127 //#define RESERVED (0x0400) /* SYS - Reserved */
6128 //#define RESERVED (0x0800) /* SYS - Reserved */
6129 //#define RESERVED (0x1000) /* SYS - Reserved */
6130 //#define RESERVED (0x2000) /* SYS - Reserved */
6131 //#define RESERVED (0x4000) /* SYS - Reserved */
6132 //#define RESERVED (0x8000) /* SYS - Reserved */
6133 
6134 /* SYSBSLC Control Bits */
6135 #define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */
6136 #define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */
6137 #define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */
6138 //#define RESERVED (0x0008) /* SYS - Reserved */
6139 //#define RESERVED (0x0010) /* SYS - Reserved */
6140 //#define RESERVED (0x0020) /* SYS - Reserved */
6141 //#define RESERVED (0x0040) /* SYS - Reserved */
6142 //#define RESERVED (0x0080) /* SYS - Reserved */
6143 //#define RESERVED (0x0100) /* SYS - Reserved */
6144 //#define RESERVED (0x0200) /* SYS - Reserved */
6145 //#define RESERVED (0x0400) /* SYS - Reserved */
6146 //#define RESERVED (0x0800) /* SYS - Reserved */
6147 //#define RESERVED (0x1000) /* SYS - Reserved */
6148 //#define RESERVED (0x2000) /* SYS - Reserved */
6149 #define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */
6150 #define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */
6151 
6152 /* SYSBSLC Control Bits */
6153 #define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */
6154 #define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */
6155 #define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */
6156 //#define RESERVED (0x0008) /* SYS - Reserved */
6157 //#define RESERVED (0x0010) /* SYS - Reserved */
6158 //#define RESERVED (0x0020) /* SYS - Reserved */
6159 //#define RESERVED (0x0040) /* SYS - Reserved */
6160 //#define RESERVED (0x0080) /* SYS - Reserved */
6161 //#define RESERVED (0x0100) /* SYS - Reserved */
6162 //#define RESERVED (0x0200) /* SYS - Reserved */
6163 //#define RESERVED (0x0400) /* SYS - Reserved */
6164 //#define RESERVED (0x0800) /* SYS - Reserved */
6165 //#define RESERVED (0x1000) /* SYS - Reserved */
6166 //#define RESERVED (0x2000) /* SYS - Reserved */
6167 
6168 /* SYSBSLC Control Bits */
6169 //#define RESERVED (0x0008) /* SYS - Reserved */
6170 //#define RESERVED (0x0010) /* SYS - Reserved */
6171 //#define RESERVED (0x0020) /* SYS - Reserved */
6172 //#define RESERVED (0x0040) /* SYS - Reserved */
6173 //#define RESERVED (0x0080) /* SYS - Reserved */
6174 //#define RESERVED (0x0100) /* SYS - Reserved */
6175 //#define RESERVED (0x0200) /* SYS - Reserved */
6176 //#define RESERVED (0x0400) /* SYS - Reserved */
6177 //#define RESERVED (0x0800) /* SYS - Reserved */
6178 //#define RESERVED (0x1000) /* SYS - Reserved */
6179 //#define RESERVED (0x2000) /* SYS - Reserved */
6180 #define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */
6181 #define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */
6182 
6183 /* SYSJMBC Control Bits */
6184 #define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
6185 #define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
6186 #define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
6187 #define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
6188 #define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */
6189 //#define RESERVED (0x0020) /* SYS - Reserved */
6190 #define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
6191 #define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
6192 //#define RESERVED (0x0100) /* SYS - Reserved */
6193 //#define RESERVED (0x0200) /* SYS - Reserved */
6194 //#define RESERVED (0x0400) /* SYS - Reserved */
6195 //#define RESERVED (0x0800) /* SYS - Reserved */
6196 //#define RESERVED (0x1000) /* SYS - Reserved */
6197 //#define RESERVED (0x2000) /* SYS - Reserved */
6198 //#define RESERVED (0x4000) /* SYS - Reserved */
6199 //#define RESERVED (0x8000) /* SYS - Reserved */
6200 
6201 /* SYSJMBC Control Bits */
6202 #define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
6203 #define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
6204 #define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
6205 #define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
6206 #define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */
6207 //#define RESERVED (0x0020) /* SYS - Reserved */
6208 #define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
6209 #define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
6210 //#define RESERVED (0x0100) /* SYS - Reserved */
6211 //#define RESERVED (0x0200) /* SYS - Reserved */
6212 //#define RESERVED (0x0400) /* SYS - Reserved */
6213 //#define RESERVED (0x0800) /* SYS - Reserved */
6214 //#define RESERVED (0x1000) /* SYS - Reserved */
6215 //#define RESERVED (0x2000) /* SYS - Reserved */
6216 //#define RESERVED (0x4000) /* SYS - Reserved */
6217 //#define RESERVED (0x8000) /* SYS - Reserved */
6218 
6219 
6220 #endif
6221 /************************************************************
6222 * Timerx_A7
6223 ************************************************************/
6224 #ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */
6225 
6226 #define OFS_TAxCTL (0x0000) /* Timerx_A7 Control */
6227 #define OFS_TAxCCTL0 (0x0002) /* Timerx_A7 Capture/Compare Control 0 */
6228 #define OFS_TAxCCTL1 (0x0004) /* Timerx_A7 Capture/Compare Control 1 */
6229 #define OFS_TAxCCTL2 (0x0006) /* Timerx_A7 Capture/Compare Control 2 */
6230 #define OFS_TAxCCTL3 (0x0008) /* Timerx_A7 Capture/Compare Control 3 */
6231 #define OFS_TAxCCTL4 (0x000A) /* Timerx_A7 Capture/Compare Control 4 */
6232 #define OFS_TAxCCTL5 (0x000C) /* Timerx_A7 Capture/Compare Control 5 */
6233 #define OFS_TAxCCTL6 (0x000E) /* Timerx_A7 Capture/Compare Control 6 */
6234 #define OFS_TAxR (0x0010) /* Timerx_A7 */
6235 #define OFS_TAxCCR0 (0x0012) /* Timerx_A7 Capture/Compare 0 */
6236 #define OFS_TAxCCR1 (0x0014) /* Timerx_A7 Capture/Compare 1 */
6237 #define OFS_TAxCCR2 (0x0016) /* Timerx_A7 Capture/Compare 2 */
6238 #define OFS_TAxCCR3 (0x0018) /* Timerx_A7 Capture/Compare 3 */
6239 #define OFS_TAxCCR4 (0x001A) /* Timerx_A7 Capture/Compare 4 */
6240 #define OFS_TAxCCR5 (0x001C) /* Timerx_A7 Capture/Compare 5 */
6241 #define OFS_TAxCCR6 (0x001E) /* Timerx_A7 Capture/Compare 6 */
6242 #define OFS_TAxIV (0x002E) /* Timerx_A7 Interrupt Vector Word */
6243 #define OFS_TAxEX0 (0x0020) /* Timerx_A7 Expansion Register 0 */
6244 
6245 /* Bits are already defined within the Timer0_Ax */
6246 
6247 /* TAxIV Definitions */
6248 #define TAxIV_NONE (0x0000) /* No Interrupt pending */
6249 #define TAxIV_TACCR1 (0x0002) /* TAxCCR1_CCIFG */
6250 #define TAxIV_TACCR2 (0x0004) /* TAxCCR2_CCIFG */
6251 #define TAxIV_TACCR3 (0x0006) /* TAxCCR3_CCIFG */
6252 #define TAxIV_TACCR4 (0x0008) /* TAxCCR4_CCIFG */
6253 #define TAxIV_TACCR5 (0x000A) /* TAxCCR5_CCIFG */
6254 #define TAxIV_TACCR6 (0x000C) /* TAxCCR6_CCIFG */
6255 #define TAxIV_TAIFG (0x000E) /* TAxIFG */
6256 
6257 /* Legacy Defines */
6258 #define TAxIV_TAxCCR1 (0x0002) /* TAxCCR1_CCIFG */
6259 #define TAxIV_TAxCCR2 (0x0004) /* TAxCCR2_CCIFG */
6260 #define TAxIV_TAxCCR3 (0x0006) /* TAxCCR3_CCIFG */
6261 #define TAxIV_TAxCCR4 (0x0008) /* TAxCCR4_CCIFG */
6262 #define TAxIV_TAxCCR5 (0x000A) /* TAxCCR5_CCIFG */
6263 #define TAxIV_TAxCCR6 (0x000C) /* TAxCCR6_CCIFG */
6264 #define TAxIV_TAxIFG (0x000E) /* TAxIFG */
6265 
6266 /* TAxCTL Control Bits */
6267 #define TASSEL1 (0x0200) /* Timer A clock source select 1 */
6268 #define TASSEL0 (0x0100) /* Timer A clock source select 0 */
6269 #define ID1 (0x0080) /* Timer A clock input divider 1 */
6270 #define ID0 (0x0040) /* Timer A clock input divider 0 */
6271 #define MC1 (0x0020) /* Timer A mode control 1 */
6272 #define MC0 (0x0010) /* Timer A mode control 0 */
6273 #define TACLR (0x0004) /* Timer A counter clear */
6274 #define TAIE (0x0002) /* Timer A counter interrupt enable */
6275 #define TAIFG (0x0001) /* Timer A counter interrupt flag */
6276 
6277 #define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
6278 #define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
6279 #define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */
6280 #define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
6281 #define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
6282 #define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
6283 #define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
6284 #define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
6285 #define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
6286 #define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
6287 #define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
6288 #define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
6289 #define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */
6290 #define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
6291 #define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */
6292 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
6293 #define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */
6294 #define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */
6295 #define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */
6296 #define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */
6297 #define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */
6298 #define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */
6299 #define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */
6300 #define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
6301 #define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */
6302 
6303 /* TAxCCTLx Control Bits */
6304 #define CM1 (0x8000) /* Capture mode 1 */
6305 #define CM0 (0x4000) /* Capture mode 0 */
6306 #define CCIS1 (0x2000) /* Capture input select 1 */
6307 #define CCIS0 (0x1000) /* Capture input select 0 */
6308 #define SCS (0x0800) /* Capture sychronize */
6309 #define SCCI (0x0400) /* Latched capture signal (read) */
6310 #define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
6311 #define OUTMOD2 (0x0080) /* Output mode 2 */
6312 #define OUTMOD1 (0x0040) /* Output mode 1 */
6313 #define OUTMOD0 (0x0020) /* Output mode 0 */
6314 #define CCIE (0x0010) /* Capture/compare interrupt enable */
6315 #define CCI (0x0008) /* Capture input signal (read) */
6316 #define OUT (0x0004) /* PWM Output signal if output mode 0 */
6317 #define COV (0x0002) /* Capture/compare overflow flag */
6318 #define CCIFG (0x0001) /* Capture/compare interrupt flag */
6319 
6320 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
6321 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
6322 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
6323 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
6324 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
6325 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
6326 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
6327 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
6328 #define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
6329 #define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
6330 #define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
6331 #define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
6332 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
6333 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
6334 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
6335 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
6336 
6337 /* TAxEX0 Control Bits */
6338 #define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */
6339 #define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */
6340 #define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */
6341 
6342 #define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */
6343 #define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */
6344 #define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */
6345 #define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */
6346 #define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */
6347 #define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */
6348 #define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */
6349 #define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */
6350 
6351 #endif
6352 /************************************************************
6353 * Timerx_B7
6354 ************************************************************/
6355 #ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */
6356 
6357 #define OFS_TBxCTL (0x0000) /* Timerx_B7 Control */
6358 #define OFS_TBxCCTL0 (0x0002) /* Timerx_B7 Capture/Compare Control 0 */
6359 #define OFS_TBxCCTL1 (0x0004) /* Timerx_B7 Capture/Compare Control 1 */
6360 #define OFS_TBxCCTL2 (0x0006) /* Timerx_B7 Capture/Compare Control 2 */
6361 #define OFS_TBxCCTL3 (0x0008) /* Timerx_B7 Capture/Compare Control 3 */
6362 #define OFS_TBxCCTL4 (0x000A) /* Timerx_B7 Capture/Compare Control 4 */
6363 #define OFS_TBxCCTL5 (0x000C) /* Timerx_B7 Capture/Compare Control 5 */
6364 #define OFS_TBxCCTL6 (0x000E) /* Timerx_B7 Capture/Compare Control 6 */
6365 #define OFS_TBxR (0x0010) /* Timerx_B7 */
6366 #define OFS_TBxCCR0 (0x0012) /* Timerx_B7 Capture/Compare 0 */
6367 #define OFS_TBxCCR1 (0x0014) /* Timerx_B7 Capture/Compare 1 */
6368 #define OFS_TBxCCR2 (0x0016) /* Timerx_B7 Capture/Compare 2 */
6369 #define OFS_TBxCCR3 (0x0018) /* Timerx_B7 Capture/Compare 3 */
6370 #define OFS_TBxCCR4 (0x001A) /* Timerx_B7 Capture/Compare 4 */
6371 #define OFS_TBxCCR5 (0x001C) /* Timerx_B7 Capture/Compare 5 */
6372 #define OFS_TBxCCR6 (0x001E) /* Timerx_B7 Capture/Compare 6 */
6373 #define OFS_TBxIV (0x002E) /* Timerx_B7 Interrupt Vector Word */
6374 #define OFS_TBxEX0 (0x0020) /* Timerx_B7 Expansion Register 0 */
6375 
6376 /* Bits are already defined within the Timer0_Ax */
6377 
6378 /* TBxIV Definitions */
6379 #define TBxIV_NONE (0x0000) /* No Interrupt pending */
6380 #define TBxIV_TBCCR1 (0x0002) /* TBxCCR1_CCIFG */
6381 #define TBxIV_TBCCR2 (0x0004) /* TBxCCR2_CCIFG */
6382 #define TBxIV_TBCCR3 (0x0006) /* TBxCCR3_CCIFG */
6383 #define TBxIV_TBCCR4 (0x0008) /* TBxCCR4_CCIFG */
6384 #define TBxIV_TBCCR5 (0x000A) /* TBxCCR5_CCIFG */
6385 #define TBxIV_TBCCR6 (0x000C) /* TBxCCR6_CCIFG */
6386 #define TBxIV_TBIFG (0x000E) /* TBxIFG */
6387 
6388 /* Legacy Defines */
6389 #define TBxIV_TBxCCR1 (0x0002) /* TBxCCR1_CCIFG */
6390 #define TBxIV_TBxCCR2 (0x0004) /* TBxCCR2_CCIFG */
6391 #define TBxIV_TBxCCR3 (0x0006) /* TBxCCR3_CCIFG */
6392 #define TBxIV_TBxCCR4 (0x0008) /* TBxCCR4_CCIFG */
6393 #define TBxIV_TBxCCR5 (0x000A) /* TBxCCR5_CCIFG */
6394 #define TBxIV_TBxCCR6 (0x000C) /* TBxCCR6_CCIFG */
6395 #define TBxIV_TBxIFG (0x000E) /* TBxIFG */
6396 
6397 /* TBxCTL Control Bits */
6398 #define TBCLGRP1 (0x4000) /* Timer_B7 Compare latch load group 1 */
6399 #define TBCLGRP0 (0x2000) /* Timer_B7 Compare latch load group 0 */
6400 #define CNTL1 (0x1000) /* Counter lenght 1 */
6401 #define CNTL0 (0x0800) /* Counter lenght 0 */
6402 #define TBSSEL1 (0x0200) /* Clock source 1 */
6403 #define TBSSEL0 (0x0100) /* Clock source 0 */
6404 #define TBCLR (0x0004) /* Timer_B7 counter clear */
6405 #define TBIE (0x0002) /* Timer_B7 interrupt enable */
6406 #define TBIFG (0x0001) /* Timer_B7 interrupt flag */
6407 
6408 #define SHR1 (0x4000) /* Timer_B7 Compare latch load group 1 */
6409 #define SHR0 (0x2000) /* Timer_B7 Compare latch load group 0 */
6410 
6411 #define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */
6412 #define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
6413 #define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
6414 #define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
6415 #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
6416 #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
6417 #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
6418 #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
6419 #define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */
6420 #define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
6421 #define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/
6422 #define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */
6423 #define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */
6424 #define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
6425 #define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/
6426 #define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */
6427 #define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */
6428 #define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */
6429 #define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */
6430 #define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */
6431 #define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */
6432 #define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */
6433 #define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */
6434 #define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */
6435 #define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */
6436 
6437 /* Additional Timer B Control Register bits are defined in Timer A */
6438 /* TBxCCTLx Control Bits */
6439 #define CLLD1 (0x0400) /* Compare latch load source 1 */
6440 #define CLLD0 (0x0200) /* Compare latch load source 0 */
6441 
6442 #define SLSHR1 (0x0400) /* Compare latch load source 1 */
6443 #define SLSHR0 (0x0200) /* Compare latch load source 0 */
6444 
6445 #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
6446 #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
6447 #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
6448 #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
6449 
6450 #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
6451 #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
6452 #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
6453 #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
6454 
6455 /* TBxEX0 Control Bits */
6456 #define TBIDEX0 (0x0001) /* Timer_B7 Input divider expansion Bit: 0 */
6457 #define TBIDEX1 (0x0002) /* Timer_B7 Input divider expansion Bit: 1 */
6458 #define TBIDEX2 (0x0004) /* Timer_B7 Input divider expansion Bit: 2 */
6459 
6460 #define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */
6461 #define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */
6462 #define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */
6463 #define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */
6464 #define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */
6465 #define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */
6466 #define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */
6467 #define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */
6468 #define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */
6469 #define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */
6470 #define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */
6471 #define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */
6472 #define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */
6473 #define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */
6474 #define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */
6475 #define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */
6476 
6477 
6478 #define ID1 (0x0080) /* Timer B clock input divider 1 */
6479 #define ID0 (0x0040) /* Timer B clock input divider 0 */
6480 #define MC1 (0x0020) /* Timer B mode control 1 */
6481 #define MC0 (0x0010) /* Timer B mode control 0 */
6482 #define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */
6483 #define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */
6484 #define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */
6485 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
6486 #define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */
6487 #define CM1 (0x8000) /* Capture mode 1 */
6488 #define CM0 (0x4000) /* Capture mode 0 */
6489 #define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */
6490 #define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */
6491 #define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */
6492 #define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */
6493 #define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
6494 #define CCIE (0x0010) /* Capture/compare interrupt enable */
6495 #define CCIFG (0x0001) /* Capture/compare interrupt flag */
6496 #define CCIS_0 (0*0x1000u)
6497 #define CCIS_1 (1*0x1000u)
6498 #define CCIS_2 (2*0x1000u)
6499 #define CCIS_3 (3*0x1000u)
6500 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
6501 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
6502 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
6503 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
6504 #define OUT (0x0004) /* PWM Output signal if output mode 0 */
6505 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
6506 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
6507 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
6508 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
6509 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
6510 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
6511 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
6512 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
6513 #define SCCI (0x0400) /* Latched capture signal (read) */
6514 #define SCS (0x0800) /* Capture sychronize */
6515 #define CCI (0x0008) /* Capture input signal (read) */
6516 #define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */
6517 #define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */
6518 #define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */
6519 #define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */
6520 #define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */
6521 #define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */
6522 #define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */
6523 #define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */
6524 
6525 #endif
6526 /************************************************************
6527 * Timerx_D7
6528 ************************************************************/
6529 #ifdef __MSP430_HAS_TxD7__ /* Definition to show that Module is available */
6530 
6531 #define OFS_TDxCTL0 (0x0000) /* Timerx_D7 Control 0 */
6532 #define OFS_TDxCTL1 (0x0002) /* Timerx_D7 Control 1 */
6533 #define OFS_TDxCTL2 (0x0004) /* Timerx_D7 Control 2 */
6534 #define OFS_TDxR (0x0006) /* Timerx_D7 Counter */
6535 #define OFS_TDxCCTL0 (0x0008) /* Timerx_D7 Capture/Compare Control 0 */
6536 #define OFS_TDxCCR0 (0x000A) /* Timerx_D7 Capture/Compare 0 */
6537 #define OFS_TDxCL0 (0x000C) /* Timerx_D7 Capture/Compare Latch 0 */
6538 #define OFS_TDxCCTL1 (0x000E) /* Timerx_D7 Capture/Compare Control 1 */
6539 #define OFS_TDxCCR1 (0x0010) /* Timerx_D7 Capture/Compare 1 */
6540 #define OFS_TDxCL1 (0x0012) /* Timerx_D7 Capture/Compare Latch 1 */
6541 #define OFS_TDxCCTL2 (0x0014) /* Timerx_D7 Capture/Compare Control 2 */
6542 #define OFS_TDxCCR2 (0x0016) /* Timerx_D7 Capture/Compare 2 */
6543 #define OFS_TDxCL2 (0x0018) /* Timerx_D7 Capture/Compare Latch 2 */
6544 #define OFS_TDxCCTL3 (0x001A) /* Timerx_D7 Capture/Compare Control 3 */
6545 #define OFS_TDxCCR3 (0x001C) /* Timerx_D7 Capture/Compare 3 */
6546 #define OFS_TDxCL3 (0x001E) /* Timerx_D7 Capture/Compare Latch 3 */
6547 #define OFS_TDxCCTL4 (0x0020) /* Timerx_D7 Capture/Compare Control 4 */
6548 #define OFS_TDxCCR4 (0x0022) /* Timerx_D7 Capture/Compare 4 */
6549 #define OFS_TDxCL4 (0x0024) /* Timerx_D7 Capture/Compare Latch 4 */
6550 #define OFS_TDxCCTL5 (0x0026) /* Timerx_D7 Capture/Compare Control 5 */
6551 #define OFS_TDxCCR5 (0x0028) /* Timerx_D7 Capture/Compare 5 */
6552 #define OFS_TDxCL5 (0x002A) /* Timerx_D7 Capture/Compare Latch 5 */
6553 #define OFS_TDxCCTL6 (0x002C) /* Timerx_D7 Capture/Compare Control 6 */
6554 #define OFS_TDxCCR6 (0x002E) /* Timerx_D7 Capture/Compare 6 */
6555 #define OFS_TDxCL6 (0x0030) /* Timerx_D7 Capture/Compare Latch 6 */
6556 #define OFS_TDxHCTL0 (0x0038) /* Timerx_D7 High-resolution Control Register 0 */
6557 #define OFS_TDxHCTL1 (0x003A) /* Timerx_D7 High-resolution Control Register 1 */
6558 #define OFS_TDxHINT (0x003C) /* Timerx_D7 High-resolution Interrupt Register */
6559 #define OFS_TDxIV (0x003E) /* Timerx_D7 Interrupt Vector Word */
6560 
6561 /* Bits are already defined within the Timer0_Dx */
6562 
6563 /* TDxIV Definitions */
6564 #define TDxIV_NONE (0x0000) /* No Interrupt pending */
6565 #define TDxIV_TDCCR1 (0x0002) /* TDxCCR1_CCIFG */
6566 #define TDxIV_TDCCR2 (0x0004) /* TDxCCR2_CCIFG */
6567 #define TDxIV_TDCCR3 (0x0006) /* TDxCCR3_CCIFG */
6568 #define TDxIV_TDCCR4 (0x0008) /* TDxCCR4_CCIFG */
6569 #define TDxIV_TDCCR5 (0x000A) /* TDxCCR5_CCIFG */
6570 #define TDxIV_TDCCR6 (0x000C) /* TDxCCR6_CCIFG */
6571 #define TDxIV_RES_14 (0x000E) /* Reserverd */
6572 #define TDxIV_TDIFG (0x0010) /* TDxIFG */
6573 #define TDxIV_TDHFLIFG (0x0012) /* TDHFLIFG Clock fail low */
6574 #define TDxIV_TDHFHIFG (0x0014) /* TDHFLIFG Clock fail high */
6575 #define TDxIV_TDHLKIFG (0x0016) /* TDHLKIE Clock lock*/
6576 #define TDxIV_TDHUNLKIFG (0x0018) /* TDHUNLKIE Clock unlock */
6577 
6578 /* Legacy Defines */
6579 #define TDxIV_TDxCCR1 (0x0002) /* TDxCCR1_CCIFG */
6580 #define TDxIV_TDxCCR2 (0x0004) /* TDxCCR2_CCIFG */
6581 #define TDxIV_TDxCCR3 (0x0006) /* TDxCCR3_CCIFG */
6582 #define TDxIV_TDxCCR4 (0x0008) /* TDxCCR4_CCIFG */
6583 #define TDxIV_TDxCCR5 (0x000A) /* TDxCCR5_CCIFG */
6584 #define TDxIV_TDxCCR6 (0x000C) /* TDxCCR6_CCIFG */
6585 #define TDxIV_TDxIFG (0x0010) /* TDxIFG */
6586 
6587 /* TDxCTL0 Control Bits */
6588 #define TDCLGRP1 (0x4000) /* Timer_D7 Compare latch load group 1 */
6589 #define TDCLGRP0 (0x2000) /* Timer_D7 Compare latch load group 0 */
6590 #define CNTL1 (0x1000) /* Counter lenght 1 */
6591 #define CNTL0 (0x0800) /* Counter lenght 0 */
6592 #define TDSSEL1 (0x0200) /* Clock source 1 */
6593 #define TDSSEL0 (0x0100) /* Clock source 0 */
6594 #define TDCLR (0x0004) /* Timer_D7 counter clear */
6595 #define TDIE (0x0002) /* Timer_D7 interrupt enable */
6596 #define TDIFG (0x0001) /* Timer_D7 interrupt flag */
6597 
6598 #define SHR1 (0x4000) /* Timer_D7 Compare latch load group 1 */
6599 #define SHR0 (0x2000) /* Timer_D7 Compare latch load group 0 */
6600 
6601 #define TDSSEL_0 (0*0x0100u) /* Clock Source: TDCLK */
6602 #define TDSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
6603 #define TDSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
6604 #define TDSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
6605 #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
6606 #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
6607 #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
6608 #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
6609 #define SHR_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */
6610 #define SHR_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
6611 #define SHR_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/
6612 #define SHR_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */
6613 #define TDCLGRP_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */
6614 #define TDCLGRP_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
6615 #define TDCLGRP_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/
6616 #define TDCLGRP_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */
6617 #define TDSSEL__TACLK (0*0x0100u) /* Timer_D7 clock source select: 0 - TACLK */
6618 #define TDSSEL__ACLK (1*0x0100u) /* Timer_D7 clock source select: 1 - ACLK */
6619 #define TDSSEL__SMCLK (2*0x0100u) /* Timer_D7 clock source select: 2 - SMCLK */
6620 #define TDSSEL__INCLK (3*0x0100u) /* Timer_D7 clock source select: 3 - INCLK */
6621 #define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */
6622 #define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */
6623 #define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */
6624 #define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */
6625 
6626 /* Additional Timer B Control Register bits are defined in Timer A */
6627 
6628 /* TDxCTL1 Control Bits */
6629 #define TDCLKM0 (0x0001) /* Timer_D7 Clocking Mode Bit: 0 */
6630 #define TDCLKM1 (0x0002) /* Timer_D7 Clocking Mode Bit: 1 */
6631 #define TD2CMB (0x0010) /* Timer_D7 TD0CCR Combination in TD2 */
6632 #define TD4CMB (0x0020) /* Timer_D7 TD0CCR Combination in TD4 */
6633 #define TD6CMB (0x0040) /* Timer_D7 TD0CCR Combination in TD6 */
6634 #define TDIDEX0 (0x0100) /* Timer_D7 Input divider expansion Bit: 0 */
6635 #define TDIDEX1 (0x0200) /* Timer_D7 Input divider expansion Bit: 1 */
6636 #define TDIDEX2 (0x0400) /* Timer_D7 Input divider expansion Bit: 2 */
6637 
6638 #define TDCLKM_0 (0x0000) /* Timer_D7 Clocking Mode: External */
6639 #define TDCLKM_1 (0x0001) /* Timer_D7 Clocking Mode: High-Res. local clock */
6640 #define TDCLKM_2 (0x0002) /* Timer_D7 Clocking Mode: Aux Clock */
6641 #define TDCLKM__EXT (0x0000) /* Timer_D7 Clocking Mode: External */
6642 #define TDCLKM__HIGHRES (0x0001) /* Timer_D7 Clocking Mode: High-Res. local clock */
6643 #define TDCLKM__AUX (0x0002) /* Timer_D7 Clocking Mode: Aux Clock */
6644 
6645 #define TDIDEX_0 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */
6646 #define TDIDEX_1 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */
6647 #define TDIDEX_2 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */
6648 #define TDIDEX_3 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */
6649 #define TDIDEX_4 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */
6650 #define TDIDEX_5 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */
6651 #define TDIDEX_6 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */
6652 #define TDIDEX_7 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */
6653 #define TDIDEX__1 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */
6654 #define TDIDEX__2 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */
6655 #define TDIDEX__3 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */
6656 #define TDIDEX__4 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */
6657 #define TDIDEX__5 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */
6658 #define TDIDEX__6 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */
6659 #define TDIDEX__7 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */
6660 #define TDIDEX__8 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */
6661 
6662 /* TDxCTL2 Control Bits */
6663 #define TDCAPM0 (0x0001) /* Timer_D7 Capture Mode of Channel 0 */
6664 #define TDCAPM1 (0x0002) /* Timer_D7 Capture Mode of Channel 1 */
6665 #define TDCAPM2 (0x0004) /* Timer_D7 Capture Mode of Channel 2 */
6666 #define TDCAPM3 (0x0008) /* Timer_D7 Capture Mode of Channel 3 */
6667 #define TDCAPM4 (0x0010) /* Timer_D7 Capture Mode of Channel 4 */
6668 #define TDCAPM5 (0x0020) /* Timer_D7 Capture Mode of Channel 5 */
6669 #define TDCAPM6 (0x0040) /* Timer_D7 Capture Mode of Channel 6 */
6670 
6671 /* TDxCCTLx Control Bits */
6672 #define CLLD1 (0x0400) /* Compare latch load source 1 */
6673 #define CLLD0 (0x0200) /* Compare latch load source 0 */
6674 
6675 #define SLSHR1 (0x0400) /* Compare latch load source 1 */
6676 #define SLSHR0 (0x0200) /* Compare latch load source 0 */
6677 
6678 #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
6679 #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */
6680 #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
6681 #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */
6682 
6683 #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
6684 #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */
6685 #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
6686 #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */
6687 
6688 /* TDxHCTL0 Control Bits */
6689 #define TDHEN (0x0001) /* Timer_D7 High-Resolution Enable */
6690 #define TDHREGEN (0x0002) /* Timer_D7 High-Resolution Regulatied Mode */
6691 #define TDHEAEN (0x0004) /* Timer_D7 High-Resolution clock error accum. enable */
6692 #define TDHRON (0x0008) /* Timer_D7 High-Resolution Generator forced on*/
6693 #define TDHM0 (0x0010) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 0 */
6694 #define TDHM1 (0x0020) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 1 */
6695 #define TDHD0 (0x0040) /* Timer_D7 High-Resolution clock divider Bit: 0 */
6696 #define TDHD1 (0x0080) /* Timer_D7 High-Resolution clock divider Bit: 1 */
6697 #define TDHFW (0x0100) /* Timer_D7 High-resolution generator fast wakeup enable */
6698 
6699 #define TDHCALEN TDHREGEN /* Timer_D7 Lagacy Definition */
6700 
6701 #define TDHM_0 (0x0000) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */
6702 #define TDHM_1 (0x0010) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */
6703 #define TDHM__8 (0x0000) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */
6704 #define TDHM__16 (0x0010) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */
6705 #define TDHD_0 (0x0000) /* Timer_D7 High-Resolution clock divider: /1 */
6706 #define TDHD_1 (0x0040) /* Timer_D7 High-Resolution clock divider: /2 */
6707 #define TDHD_2 (0x0080) /* Timer_D7 High-Resolution clock divider: /4 */
6708 #define TDHD_3 (0x00C0) /* Timer_D7 High-Resolution clock divider: /8 */
6709 #define TDHD__1 (0x0000) /* Timer_D7 High-Resolution clock divider: /1 */
6710 #define TDHD__2 (0x0040) /* Timer_D7 High-Resolution clock divider: /2 */
6711 #define TDHD__4 (0x0080) /* Timer_D7 High-Resolution clock divider: /4 */
6712 #define TDHD__8 (0x00C0) /* Timer_D7 High-Resolution clock divider: /8 */
6713 
6714 /* TDxHCTL1 Control Bits */
6715 #define TDHCLKTRIM0 (0x0002) /* Timer_D7 High-Resolution Clock Trim Bit: 0 */
6716 #define TDHCLKTRIM1 (0x0004) /* Timer_D7 High-Resolution Clock Trim Bit: 1 */
6717 #define TDHCLKTRIM2 (0x0008) /* Timer_D7 High-Resolution Clock Trim Bit: 2 */
6718 #define TDHCLKTRIM3 (0x0010) /* Timer_D7 High-Resolution Clock Trim Bit: 3 */
6719 #define TDHCLKTRIM4 (0x0020) /* Timer_D7 High-Resolution Clock Trim Bit: 4 */
6720 #define TDHCLKTRIM5 (0x0040) /* Timer_D7 High-Resolution Clock Trim Bit: 5 */
6721 #define TDHCLKTRIM6 (0x0080) /* Timer_D7 High-Resolution Clock Trim Bit: 6 */
6722 #define TDHCLKSR0 (0x0100) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 0 */
6723 #define TDHCLKSR1 (0x0200) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 1 */
6724 #define TDHCLKSR2 (0x0400) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 2 */
6725 #define TDHCLKSR3 (0x0800) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 3 */
6726 #define TDHCLKSR4 (0x1000) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 4 */
6727 #define TDHCLKR0 (0x2000) /* Timer_D7 High-Resolution Clock Range Bit: 0 */
6728 #define TDHCLKR1 (0x4000) /* Timer_D7 High-Resolution Clock Range Bit: 1 */
6729 #define TDHCLKCR (0x8000) /* Timer_D7 High-Resolution Coarse Clock Range */
6730 
6731 /* TDxHINT Control Bits */
6732 #define TDHFLIFG (0x0001) /* Timer_D7 High-Res. fail low Interrupt Flag */
6733 #define TDHFHIFG (0x0002) /* Timer_D7 High-Res. fail high Interrupt Flag */
6734 #define TDHLKIFG (0x0004) /* Timer_D7 High-Res. frequency lock Interrupt Flag */
6735 #define TDHUNLKIFG (0x0008) /* Timer_D7 High-Res. frequency unlock Interrupt Flag */
6736 #define TDHFLIE (0x0100) /* Timer_D7 High-Res. fail low Interrupt Enable */
6737 #define TDHFHIE (0x0200) /* Timer_D7 High-Res. fail high Interrupt Enable */
6738 #define TDHLKIE (0x0400) /* Timer_D7 High-Res. frequency lock Interrupt Enable */
6739 #define TDHUNLKIE (0x0800) /* Timer_D7 High-Res. frequency unlock Interrupt Enable */
6740 
6741 #define ID1 (0x0080) /* Timer D clock input divider 1 */
6742 #define ID0 (0x0040) /* Timer D clock input divider 0 */
6743 #define MC1 (0x0020) /* Timer D mode control 1 */
6744 #define MC0 (0x0010) /* Timer D mode control 0 */
6745 #define MC__STOP (0*0x10u) /* Timer D mode control: 0 - Stop */
6746 #define MC__UP (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */
6747 #define MC__CONTINUOUS (2*0x10u) /* Timer D mode control: 2 - Continuous up */
6748 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
6749 #define MC__UPDOWN (3*0x10u) /* Timer D mode control: 3 - Up/Down */
6750 #define CM1 (0x8000) /* Capture mode 1 */
6751 #define CM0 (0x4000) /* Capture mode 0 */
6752 #define MC_0 (0*0x10u) /* Timer D mode control: 0 - Stop */
6753 #define MC_1 (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */
6754 #define MC_2 (2*0x10u) /* Timer D mode control: 2 - Continuous up */
6755 #define MC_3 (3*0x10u) /* Timer D mode control: 3 - Up/Down */
6756 #define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
6757 #define CCIE (0x0010) /* Capture/compare interrupt enable */
6758 #define CCIFG (0x0001) /* Capture/compare interrupt flag */
6759 #define CCIS_0 (0*0x1000u)
6760 #define CCIS_1 (1*0x1000u)
6761 #define CCIS_2 (2*0x1000u)
6762 #define CCIS_3 (3*0x1000u)
6763 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
6764 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
6765 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
6766 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
6767 #define OUT (0x0004) /* PWM Output signal if output mode 0 */
6768 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
6769 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
6770 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
6771 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
6772 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
6773 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
6774 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
6775 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
6776 #define SCCI (0x0400) /* Latched capture signal (read) */
6777 #define SCS (0x0800) /* Capture sychronize */
6778 #define CCI (0x0008) /* Capture input signal (read) */
6779 #define ID__1 (0*0x40u) /* Timer D input divider: 0 - /1 */
6780 #define ID__2 (1*0x40u) /* Timer D input divider: 1 - /2 */
6781 #define ID__4 (2*0x40u) /* Timer D input divider: 2 - /4 */
6782 #define ID__8 (3*0x40u) /* Timer D input divider: 3 - /8 */
6783 #define ID_0 (0*0x40u) /* Timer D input divider: 0 - /1 */
6784 #define ID_1 (1*0x40u) /* Timer D input divider: 1 - /2 */
6785 #define ID_2 (2*0x40u) /* Timer D input divider: 2 - /4 */
6786 #define ID_3 (3*0x40u) /* Timer D input divider: 3 - /8 */
6787 
6788 #endif
6789 /************************************************************
6790 * Timer Event Control 0
6791 ************************************************************/
6792 #ifdef __MSP430_HAS_TEV0__ /* Definition to show that Module is available */
6793 
6794 #define OFS_TEC0XCTL0 (0x0000) /* Timer Event Control 0 External Control 0 */
6795 #define OFS_TEC0XCTL0_L OFS_TEC0XCTL0
6796 #define OFS_TEC0XCTL0_H OFS_TEC0XCTL0+1
6797 #define OFS_TEC0XCTL1 (0x0002) /* Timer Event Control 0 External Control 1 */
6798 #define OFS_TEC0XCTL1_L OFS_TEC0XCTL1
6799 #define OFS_TEC0XCTL1_H OFS_TEC0XCTL1+1
6800 #define OFS_TEC0XCTL2 (0x0004) /* Timer Event Control 0 External Control 2 */
6801 #define OFS_TEC0XCTL2_L OFS_TEC0XCTL2
6802 #define OFS_TEC0XCTL2_H OFS_TEC0XCTL2+1
6803 #define OFS_TEC0STA (0x0006) /* Timer Event Control 0 Status */
6804 #define OFS_TEC0STA_L OFS_TEC0STA
6805 #define OFS_TEC0STA_H OFS_TEC0STA+1
6806 #define OFS_TEC0XINT (0x0008) /* Timer Event Control 0 External Interrupt */
6807 #define OFS_TEC0XINT_L OFS_TEC0XINT
6808 #define OFS_TEC0XINT_H OFS_TEC0XINT+1
6809 #define OFS_TEC0IV (0x000A) /* Timer Event Control 0 Interrupt Vector */
6810 #define OFS_TEC0IV_L OFS_TEC0IV
6811 #define OFS_TEC0IV_H OFS_TEC0IV+1
6812 
6813 /* TECxXCTL0 Control Bits */
6814 #define TECXFLTHLD0 (0x0001) /* TEV Ext. fault signal hold for CE0 */
6815 #define TECXFLTHLD1 (0x0002) /* TEV Ext. fault signal hold for CE1 */
6816 #define TECXFLTHLD2 (0x0004) /* TEV Ext. fault signal hold for CE2 */
6817 #define TECXFLTHLD3 (0x0008) /* TEV Ext. fault signal hold for CE3 */
6818 #define TECXFLTHLD4 (0x0010) /* TEV Ext. fault signal hold for CE4 */
6819 #define TECXFLTHLD5 (0x0020) /* TEV Ext. fault signal hold for CE5 */
6820 #define TECXFLTHLD6 (0x0040) /* TEV Ext. fault signal hold for CE6 */
6821 #define TECXFLTEN0 (0x0100) /* TEV Ext. fault signal enable for CE0 */
6822 #define TECXFLTEN1 (0x0200) /* TEV Ext. fault signal enable for CE1 */
6823 #define TECXFLTEN2 (0x0400) /* TEV Ext. fault signal enable for CE2 */
6824 #define TECXFLTEN3 (0x0800) /* TEV Ext. fault signal enable for CE3 */
6825 #define TECXFLTEN4 (0x1000) /* TEV Ext. fault signal enable for CE4 */
6826 #define TECXFLTEN5 (0x2000) /* TEV Ext. fault signal enable for CE5 */
6827 #define TECXFLTEN6 (0x4000) /* TEV Ext. fault signal enable for CE6 */
6828 
6829 /* TECxXCTL0 Control Bits */
6830 #define TECXFLTHLD0_L (0x0001) /* TEV Ext. fault signal hold for CE0 */
6831 #define TECXFLTHLD1_L (0x0002) /* TEV Ext. fault signal hold for CE1 */
6832 #define TECXFLTHLD2_L (0x0004) /* TEV Ext. fault signal hold for CE2 */
6833 #define TECXFLTHLD3_L (0x0008) /* TEV Ext. fault signal hold for CE3 */
6834 #define TECXFLTHLD4_L (0x0010) /* TEV Ext. fault signal hold for CE4 */
6835 #define TECXFLTHLD5_L (0x0020) /* TEV Ext. fault signal hold for CE5 */
6836 #define TECXFLTHLD6_L (0x0040) /* TEV Ext. fault signal hold for CE6 */
6837 
6838 /* TECxXCTL0 Control Bits */
6839 #define TECXFLTEN0_H (0x0001) /* TEV Ext. fault signal enable for CE0 */
6840 #define TECXFLTEN1_H (0x0002) /* TEV Ext. fault signal enable for CE1 */
6841 #define TECXFLTEN2_H (0x0004) /* TEV Ext. fault signal enable for CE2 */
6842 #define TECXFLTEN3_H (0x0008) /* TEV Ext. fault signal enable for CE3 */
6843 #define TECXFLTEN4_H (0x0010) /* TEV Ext. fault signal enable for CE4 */
6844 #define TECXFLTEN5_H (0x0020) /* TEV Ext. fault signal enable for CE5 */
6845 #define TECXFLTEN6_H (0x0040) /* TEV Ext. fault signal enable for CE6 */
6846 
6847 /* TECxXCTL1 Control Bits */
6848 #define TECXFLTPOL0 (0x0001) /* TEV Polarity Bit of ext. fault 0 */
6849 #define TECXFLTPOL1 (0x0002) /* TEV Polarity Bit of ext. fault 1 */
6850 #define TECXFLTPOL2 (0x0004) /* TEV Polarity Bit of ext. fault 2 */
6851 #define TECXFLTPOL3 (0x0008) /* TEV Polarity Bit of ext. fault 3 */
6852 #define TECXFLTPOL4 (0x0010) /* TEV Polarity Bit of ext. fault 4 */
6853 #define TECXFLTPOL5 (0x0020) /* TEV Polarity Bit of ext. fault 5 */
6854 #define TECXFLTPOL6 (0x0040) /* TEV Polarity Bit of ext. fault 6 */
6855 #define TECXFLTLVS0 (0x0100) /* TEV Signal Type of Ext. fault 0 */
6856 #define TECXFLTLVS1 (0x0200) /* TEV Signal Type of Ext. fault 1 */
6857 #define TECXFLTLVS2 (0x0400) /* TEV Signal Type of Ext. fault 2 */
6858 #define TECXFLTLVS3 (0x0800) /* TEV Signal Type of Ext. fault 3 */
6859 #define TECXFLTLVS4 (0x1000) /* TEV Signal Type of Ext. fault 4 */
6860 #define TECXFLTLVS5 (0x2000) /* TEV Signal Type of Ext. fault 5 */
6861 #define TECXFLTLVS6 (0x4000) /* TEV Signal Type of Ext. fault 6 */
6862 
6863 /* TECxXCTL1 Control Bits */
6864 #define TECXFLTPOL0_L (0x0001) /* TEV Polarity Bit of ext. fault 0 */
6865 #define TECXFLTPOL1_L (0x0002) /* TEV Polarity Bit of ext. fault 1 */
6866 #define TECXFLTPOL2_L (0x0004) /* TEV Polarity Bit of ext. fault 2 */
6867 #define TECXFLTPOL3_L (0x0008) /* TEV Polarity Bit of ext. fault 3 */
6868 #define TECXFLTPOL4_L (0x0010) /* TEV Polarity Bit of ext. fault 4 */
6869 #define TECXFLTPOL5_L (0x0020) /* TEV Polarity Bit of ext. fault 5 */
6870 #define TECXFLTPOL6_L (0x0040) /* TEV Polarity Bit of ext. fault 6 */
6871 
6872 /* TECxXCTL1 Control Bits */
6873 #define TECXFLTLVS0_H (0x0001) /* TEV Signal Type of Ext. fault 0 */
6874 #define TECXFLTLVS1_H (0x0002) /* TEV Signal Type of Ext. fault 1 */
6875 #define TECXFLTLVS2_H (0x0004) /* TEV Signal Type of Ext. fault 2 */
6876 #define TECXFLTLVS3_H (0x0008) /* TEV Signal Type of Ext. fault 3 */
6877 #define TECXFLTLVS4_H (0x0010) /* TEV Signal Type of Ext. fault 4 */
6878 #define TECXFLTLVS5_H (0x0020) /* TEV Signal Type of Ext. fault 5 */
6879 #define TECXFLTLVS6_H (0x0040) /* TEV Signal Type of Ext. fault 6 */
6880 
6881 /* TECxXCTL2 Control Bits */
6882 #define TECCLKSEL0 (0x0001) /* TEV Aux. Clock Select Bit: 0 */
6883 #define TECCLKSEL1 (0x0002) /* TEV Aux. Clock Select Bit: 1 */
6884 #define TECAXCLREN (0x0004) /* TEV Auxilary clear signal control */
6885 #define TECEXCLREN (0x0008) /* TEV Ext. clear signal control */
6886 #define TECEXCLRHLD (0x0010) /* TEV External clear signal hold bit */
6887 #define TECEXCLRPOL (0x0020) /* TEV Polarity Bit of ext. clear */
6888 #define TECEXCLRLVS (0x0040) /* TEV Signal Type of Ext. clear */
6889 
6890 /* TECxXCTL2 Control Bits */
6891 #define TECCLKSEL0_L (0x0001) /* TEV Aux. Clock Select Bit: 0 */
6892 #define TECCLKSEL1_L (0x0002) /* TEV Aux. Clock Select Bit: 1 */
6893 #define TECAXCLREN_L (0x0004) /* TEV Auxilary clear signal control */
6894 #define TECEXCLREN_L (0x0008) /* TEV Ext. clear signal control */
6895 #define TECEXCLRHLD_L (0x0010) /* TEV External clear signal hold bit */
6896 #define TECEXCLRPOL_L (0x0020) /* TEV Polarity Bit of ext. clear */
6897 #define TECEXCLRLVS_L (0x0040) /* TEV Signal Type of Ext. clear */
6898 
6899 #define TECCLKSEL_0 (0x0000) /* TEV Aux. Clock Select: CLK0 */
6900 #define TECCLKSEL_1 (0x0001) /* TEV Aux. Clock Select: CLK1 */
6901 #define TECCLKSEL_2 (0x0002) /* TEV Aux. Clock Select: CLK2 */
6902 #define TECCLKSEL_3 (0x0003) /* TEV Aux. Clock Select: CLK3 */
6903 
6904 /* TECxSTA Control Bits */
6905 #define TECXFLT0STA (0x0001) /* TEV External fault status flag for CE0 */
6906 #define TECXFLT1STA (0x0002) /* TEV External fault status flag for CE1 */
6907 #define TECXFLT2STA (0x0004) /* TEV External fault status flag for CE2 */
6908 #define TECXFLT3STA (0x0008) /* TEV External fault status flag for CE3 */
6909 #define TECXFLT4STA (0x0010) /* TEV External fault status flag for CE4 */
6910 #define TECXFLT5STA (0x0020) /* TEV External fault status flag for CE5 */
6911 #define TECXFLT6STA (0x0040) /* TEV External fault status flag for CE6 */
6912 #define TECXCLRSTA (0x0100) /* TEC External clear status flag */
6913 
6914 /* TECxSTA Control Bits */
6915 #define TECXFLT0STA_L (0x0001) /* TEV External fault status flag for CE0 */
6916 #define TECXFLT1STA_L (0x0002) /* TEV External fault status flag for CE1 */
6917 #define TECXFLT2STA_L (0x0004) /* TEV External fault status flag for CE2 */
6918 #define TECXFLT3STA_L (0x0008) /* TEV External fault status flag for CE3 */
6919 #define TECXFLT4STA_L (0x0010) /* TEV External fault status flag for CE4 */
6920 #define TECXFLT5STA_L (0x0020) /* TEV External fault status flag for CE5 */
6921 #define TECXFLT6STA_L (0x0040) /* TEV External fault status flag for CE6 */
6922 
6923 /* TECxSTA Control Bits */
6924 #define TECXCLRSTA_H (0x0001) /* TEC External clear status flag */
6925 
6926 /* TECxXINT Control Bits */
6927 #define TECAXCLRIFG (0x0001) /* TEC Aux. Clear Interrupt Flag */
6928 #define TECEXCLRIFG (0x0002) /* TEC External Clear Interrupt Flag */
6929 #define TECXFLTIFG (0x0004) /* TEC External Fault Interrupt Flag */
6930 #define TECAXCLRIE (0x0100) /* TEC Aux. Clear Interrupt Enable */
6931 #define TECEXCLRIE (0x0200) /* TEC External Clear Interrupt Enable */
6932 #define TECXFLTIE (0x0400) /* TEC External Fault Interrupt Enable */
6933 
6934 /* TECxXINT Control Bits */
6935 #define TECAXCLRIFG_L (0x0001) /* TEC Aux. Clear Interrupt Flag */
6936 #define TECEXCLRIFG_L (0x0002) /* TEC External Clear Interrupt Flag */
6937 #define TECXFLTIFG_L (0x0004) /* TEC External Fault Interrupt Flag */
6938 
6939 /* TECxXINT Control Bits */
6940 #define TECAXCLRIE_H (0x0001) /* TEC Aux. Clear Interrupt Enable */
6941 #define TECEXCLRIE_H (0x0002) /* TEC External Clear Interrupt Enable */
6942 #define TECXFLTIE_H (0x0004) /* TEC External Fault Interrupt Enable */
6943 
6944 /* TEC0IV Definitions */
6945 #define TEC0IV_NONE (0x0000) /* No Interrupt pending */
6946 #define TEC0IV_TECXFLTIFG (0x0002) /* TEC0XFLTIFG */
6947 #define TEC0IV_TECEXCLRIFG (0x0004) /* TEC0EXCLRIFG */
6948 #define TEC0IV_TECAXCLRIFG (0x0006) /* TEC0AXCLRIFG */
6949 
6950 #endif
6951 /************************************************************
6952 * Timer Event Control x
6953 ************************************************************/
6954 #ifdef __MSP430_HAS_TEVx__ /* Definition to show that Module is available */
6955 
6956 #define OFS_TECxXCTL0 (0x0000) /* Timer Event Control x External Control 0 */
6957 #define OFS_TECxXCTL0_L OFS_TECxXCTL0
6958 #define OFS_TECxXCTL0_H OFS_TECxXCTL0+1
6959 #define OFS_TECxXCTL1 (0x0002) /* Timer Event Control x External Control 1 */
6960 #define OFS_TECxXCTL1_L OFS_TECxXCTL1
6961 #define OFS_TECxXCTL1_H OFS_TECxXCTL1+1
6962 #define OFS_TECxXCTL2 (0x0004) /* Timer Event Control x External Control 2 */
6963 #define OFS_TECxXCTL2_L OFS_TECxXCTL2
6964 #define OFS_TECxXCTL2_H OFS_TECxXCTL2+1
6965 #define OFS_TECxSTA (0x0006) /* Timer Event Control x Status */
6966 #define OFS_TECxSTA_L OFS_TECxSTA
6967 #define OFS_TECxSTA_H OFS_TECxSTA+1
6968 #define OFS_TECxXINT (0x0008) /* Timer Event Control x External Interrupt */
6969 #define OFS_TECxXINT_L OFS_TECxXINT
6970 #define OFS_TECxXINT_H OFS_TECxXINT+1
6971 #define OFS_TECxIV (0x000A) /* Timer Event Control x Interrupt Vector */
6972 #define OFS_TECxIV_L OFS_TECxIV
6973 #define OFS_TECxIV_H OFS_TECxIV+1
6974 
6975 /* TECIV Definitions */
6976 #define TECxIV_NONE (0x0000) /* No Interrupt pending */
6977 #define TECxIV_TECXFLTIFG (0x0002) /* TECxXFLTIFG */
6978 #define TECxIV_TECEXCLRIFG (0x0004) /* TECxEXCLRIFG */
6979 #define TECxIV_TECAXCLRIFG (0x0006) /* TECxAXCLRIFG */
6980 
6981 
6982 #endif
6983 
6984 /************************************************************
6985 * UNIFIED CLOCK SYSTEM
6986 ************************************************************/
6987 #ifdef __MSP430_HAS_UCS__ /* Definition to show that Module is available */
6988 
6989 #define OFS_UCSCTL0 (0x0000) /* UCS Control Register 0 */
6990 #define OFS_UCSCTL0_L OFS_UCSCTL0
6991 #define OFS_UCSCTL0_H OFS_UCSCTL0+1
6992 #define OFS_UCSCTL1 (0x0002) /* UCS Control Register 1 */
6993 #define OFS_UCSCTL1_L OFS_UCSCTL1
6994 #define OFS_UCSCTL1_H OFS_UCSCTL1+1
6995 #define OFS_UCSCTL2 (0x0004) /* UCS Control Register 2 */
6996 #define OFS_UCSCTL2_L OFS_UCSCTL2
6997 #define OFS_UCSCTL2_H OFS_UCSCTL2+1
6998 #define OFS_UCSCTL3 (0x0006) /* UCS Control Register 3 */
6999 #define OFS_UCSCTL3_L OFS_UCSCTL3
7000 #define OFS_UCSCTL3_H OFS_UCSCTL3+1
7001 #define OFS_UCSCTL4 (0x0008) /* UCS Control Register 4 */
7002 #define OFS_UCSCTL4_L OFS_UCSCTL4
7003 #define OFS_UCSCTL4_H OFS_UCSCTL4+1
7004 #define OFS_UCSCTL5 (0x000A) /* UCS Control Register 5 */
7005 #define OFS_UCSCTL5_L OFS_UCSCTL5
7006 #define OFS_UCSCTL5_H OFS_UCSCTL5+1
7007 #define OFS_UCSCTL6 (0x000C) /* UCS Control Register 6 */
7008 #define OFS_UCSCTL6_L OFS_UCSCTL6
7009 #define OFS_UCSCTL6_H OFS_UCSCTL6+1
7010 #define OFS_UCSCTL7 (0x000E) /* UCS Control Register 7 */
7011 #define OFS_UCSCTL7_L OFS_UCSCTL7
7012 #define OFS_UCSCTL7_H OFS_UCSCTL7+1
7013 #define OFS_UCSCTL8 (0x0010) /* UCS Control Register 8 */
7014 #define OFS_UCSCTL8_L OFS_UCSCTL8
7015 #define OFS_UCSCTL8_H OFS_UCSCTL8+1
7016 
7017 /* UCSCTL0 Control Bits */
7018 //#define RESERVED (0x0001) /* RESERVED */
7019 //#define RESERVED (0x0002) /* RESERVED */
7020 //#define RESERVED (0x0004) /* RESERVED */
7021 #define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */
7022 #define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */
7023 #define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */
7024 #define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */
7025 #define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */
7026 #define DCO0 (0x0100) /* DCO TAP Bit : 0 */
7027 #define DCO1 (0x0200) /* DCO TAP Bit : 1 */
7028 #define DCO2 (0x0400) /* DCO TAP Bit : 2 */
7029 #define DCO3 (0x0800) /* DCO TAP Bit : 3 */
7030 #define DCO4 (0x1000) /* DCO TAP Bit : 4 */
7031 //#define RESERVED (0x2000) /* RESERVED */
7032 //#define RESERVED (0x4000) /* RESERVED */
7033 //#define RESERVED (0x8000) /* RESERVED */
7034 
7035 /* UCSCTL0 Control Bits */
7036 //#define RESERVED (0x0001) /* RESERVED */
7037 //#define RESERVED (0x0002) /* RESERVED */
7038 //#define RESERVED (0x0004) /* RESERVED */
7039 #define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */
7040 #define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */
7041 #define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */
7042 #define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */
7043 #define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */
7044 //#define RESERVED (0x2000) /* RESERVED */
7045 //#define RESERVED (0x4000) /* RESERVED */
7046 //#define RESERVED (0x8000) /* RESERVED */
7047 
7048 /* UCSCTL0 Control Bits */
7049 //#define RESERVED (0x0001) /* RESERVED */
7050 //#define RESERVED (0x0002) /* RESERVED */
7051 //#define RESERVED (0x0004) /* RESERVED */
7052 #define DCO0_H (0x0001) /* DCO TAP Bit : 0 */
7053 #define DCO1_H (0x0002) /* DCO TAP Bit : 1 */
7054 #define DCO2_H (0x0004) /* DCO TAP Bit : 2 */
7055 #define DCO3_H (0x0008) /* DCO TAP Bit : 3 */
7056 #define DCO4_H (0x0010) /* DCO TAP Bit : 4 */
7057 //#define RESERVED (0x2000) /* RESERVED */
7058 //#define RESERVED (0x4000) /* RESERVED */
7059 //#define RESERVED (0x8000) /* RESERVED */
7060 
7061 /* UCSCTL1 Control Bits */
7062 #define DISMOD (0x0001) /* Disable Modulation */
7063 //#define RESERVED (0x0002) /* RESERVED */
7064 //#define RESERVED (0x0004) /* RESERVED */
7065 //#define RESERVED (0x0008) /* RESERVED */
7066 #define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */
7067 #define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */
7068 #define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */
7069 //#define RESERVED (0x0080) /* RESERVED */
7070 //#define RESERVED (0x0100) /* RESERVED */
7071 //#define RESERVED (0x0200) /* RESERVED */
7072 //#define RESERVED (0x0400) /* RESERVED */
7073 //#define RESERVED (0x0800) /* RESERVED */
7074 //#define RESERVED (0x1000) /* RESERVED */
7075 //#define RESERVED (0x2000) /* RESERVED */
7076 //#define RESERVED (0x4000) /* RESERVED */
7077 //#define RESERVED (0x8000) /* RESERVED */
7078 
7079 /* UCSCTL1 Control Bits */
7080 #define DISMOD_L (0x0001) /* Disable Modulation */
7081 //#define RESERVED (0x0002) /* RESERVED */
7082 //#define RESERVED (0x0004) /* RESERVED */
7083 //#define RESERVED (0x0008) /* RESERVED */
7084 #define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */
7085 #define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */
7086 #define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */
7087 //#define RESERVED (0x0080) /* RESERVED */
7088 //#define RESERVED (0x0100) /* RESERVED */
7089 //#define RESERVED (0x0200) /* RESERVED */
7090 //#define RESERVED (0x0400) /* RESERVED */
7091 //#define RESERVED (0x0800) /* RESERVED */
7092 //#define RESERVED (0x1000) /* RESERVED */
7093 //#define RESERVED (0x2000) /* RESERVED */
7094 //#define RESERVED (0x4000) /* RESERVED */
7095 //#define RESERVED (0x8000) /* RESERVED */
7096 
7097 #define DCORSEL_0 (0x0000) /* DCO RSEL 0 */
7098 #define DCORSEL_1 (0x0010) /* DCO RSEL 1 */
7099 #define DCORSEL_2 (0x0020) /* DCO RSEL 2 */
7100 #define DCORSEL_3 (0x0030) /* DCO RSEL 3 */
7101 #define DCORSEL_4 (0x0040) /* DCO RSEL 4 */
7102 #define DCORSEL_5 (0x0050) /* DCO RSEL 5 */
7103 #define DCORSEL_6 (0x0060) /* DCO RSEL 6 */
7104 #define DCORSEL_7 (0x0070) /* DCO RSEL 7 */
7105 
7106 /* UCSCTL2 Control Bits */
7107 #define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */
7108 #define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */
7109 #define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */
7110 #define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */
7111 #define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */
7112 #define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */
7113 #define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */
7114 #define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */
7115 #define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */
7116 #define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */
7117 //#define RESERVED (0x0400) /* RESERVED */
7118 //#define RESERVED (0x0800) /* RESERVED */
7119 #define FLLD0 (0x1000) /* Loop Divider Bit : 0 */
7120 #define FLLD1 (0x2000) /* Loop Divider Bit : 1 */
7121 #define FLLD2 (0x4000) /* Loop Divider Bit : 1 */
7122 //#define RESERVED (0x8000) /* RESERVED */
7123 
7124 /* UCSCTL2 Control Bits */
7125 #define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */
7126 #define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */
7127 #define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */
7128 #define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */
7129 #define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */
7130 #define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */
7131 #define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */
7132 #define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */
7133 //#define RESERVED (0x0400) /* RESERVED */
7134 //#define RESERVED (0x0800) /* RESERVED */
7135 //#define RESERVED (0x8000) /* RESERVED */
7136 
7137 /* UCSCTL2 Control Bits */
7138 #define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */
7139 #define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */
7140 //#define RESERVED (0x0400) /* RESERVED */
7141 //#define RESERVED (0x0800) /* RESERVED */
7142 #define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */
7143 #define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */
7144 #define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */
7145 //#define RESERVED (0x8000) /* RESERVED */
7146 
7147 #define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */
7148 #define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */
7149 #define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */
7150 #define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */
7151 #define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */
7152 #define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */
7153 #define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */
7154 #define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */
7155 #define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */
7156 #define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */
7157 #define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */
7158 #define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */
7159 #define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */
7160 #define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */
7161 
7162 /* UCSCTL3 Control Bits */
7163 #define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */
7164 #define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */
7165 #define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */
7166 //#define RESERVED (0x0008) /* RESERVED */
7167 #define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */
7168 #define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */
7169 #define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */
7170 //#define RESERVED (0x0080) /* RESERVED */
7171 //#define RESERVED (0x0100) /* RESERVED */
7172 //#define RESERVED (0x0200) /* RESERVED */
7173 //#define RESERVED (0x0400) /* RESERVED */
7174 //#define RESERVED (0x0800) /* RESERVED */
7175 //#define RESERVED (0x1000) /* RESERVED */
7176 //#define RESERVED (0x2000) /* RESERVED */
7177 //#define RESERVED (0x4000) /* RESERVED */
7178 //#define RESERVED (0x8000) /* RESERVED */
7179 
7180 /* UCSCTL3 Control Bits */
7181 #define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */
7182 #define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */
7183 #define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */
7184 //#define RESERVED (0x0008) /* RESERVED */
7185 #define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */
7186 #define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */
7187 #define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */
7188 //#define RESERVED (0x0080) /* RESERVED */
7189 //#define RESERVED (0x0100) /* RESERVED */
7190 //#define RESERVED (0x0200) /* RESERVED */
7191 //#define RESERVED (0x0400) /* RESERVED */
7192 //#define RESERVED (0x0800) /* RESERVED */
7193 //#define RESERVED (0x1000) /* RESERVED */
7194 //#define RESERVED (0x2000) /* RESERVED */
7195 //#define RESERVED (0x4000) /* RESERVED */
7196 //#define RESERVED (0x8000) /* RESERVED */
7197 
7198 #define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */
7199 #define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */
7200 #define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */
7201 #define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */
7202 #define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */
7203 #define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */
7204 #define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */
7205 #define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */
7206 #define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */
7207 #define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */
7208 #define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */
7209 #define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */
7210 #define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */
7211 #define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */
7212 #define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */
7213 #define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */
7214 #define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */
7215 #define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */
7216 #define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */
7217 #define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */
7218 #define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */
7219 #define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */
7220 #define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */
7221 #define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */
7222 #define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */
7223 
7224 /* UCSCTL4 Control Bits */
7225 #define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
7226 #define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
7227 #define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
7228 //#define RESERVED (0x0008) /* RESERVED */
7229 #define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
7230 #define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
7231 #define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
7232 //#define RESERVED (0x0080) /* RESERVED */
7233 #define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
7234 #define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
7235 #define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
7236 //#define RESERVED (0x0800) /* RESERVED */
7237 //#define RESERVED (0x1000) /* RESERVED */
7238 //#define RESERVED (0x2000) /* RESERVED */
7239 //#define RESERVED (0x4000) /* RESERVED */
7240 //#define RESERVED (0x8000) /* RESERVED */
7241 
7242 /* UCSCTL4 Control Bits */
7243 #define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
7244 #define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
7245 #define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
7246 //#define RESERVED (0x0008) /* RESERVED */
7247 #define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
7248 #define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
7249 #define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
7250 //#define RESERVED (0x0080) /* RESERVED */
7251 //#define RESERVED (0x0800) /* RESERVED */
7252 //#define RESERVED (0x1000) /* RESERVED */
7253 //#define RESERVED (0x2000) /* RESERVED */
7254 //#define RESERVED (0x4000) /* RESERVED */
7255 //#define RESERVED (0x8000) /* RESERVED */
7256 
7257 /* UCSCTL4 Control Bits */
7258 //#define RESERVED (0x0008) /* RESERVED */
7259 //#define RESERVED (0x0080) /* RESERVED */
7260 #define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
7261 #define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
7262 #define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
7263 //#define RESERVED (0x0800) /* RESERVED */
7264 //#define RESERVED (0x1000) /* RESERVED */
7265 //#define RESERVED (0x2000) /* RESERVED */
7266 //#define RESERVED (0x4000) /* RESERVED */
7267 //#define RESERVED (0x8000) /* RESERVED */
7268 
7269 #define SELM_0 (0x0000) /* MCLK Source Select 0 */
7270 #define SELM_1 (0x0001) /* MCLK Source Select 1 */
7271 #define SELM_2 (0x0002) /* MCLK Source Select 2 */
7272 #define SELM_3 (0x0003) /* MCLK Source Select 3 */
7273 #define SELM_4 (0x0004) /* MCLK Source Select 4 */
7274 #define SELM_5 (0x0005) /* MCLK Source Select 5 */
7275 #define SELM_6 (0x0006) /* MCLK Source Select 6 */
7276 #define SELM_7 (0x0007) /* MCLK Source Select 7 */
7277 #define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */
7278 #define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
7279 #define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */
7280 #define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
7281 #define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */
7282 #define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */
7283 
7284 #define SELS_0 (0x0000) /* SMCLK Source Select 0 */
7285 #define SELS_1 (0x0010) /* SMCLK Source Select 1 */
7286 #define SELS_2 (0x0020) /* SMCLK Source Select 2 */
7287 #define SELS_3 (0x0030) /* SMCLK Source Select 3 */
7288 #define SELS_4 (0x0040) /* SMCLK Source Select 4 */
7289 #define SELS_5 (0x0050) /* SMCLK Source Select 5 */
7290 #define SELS_6 (0x0060) /* SMCLK Source Select 6 */
7291 #define SELS_7 (0x0070) /* SMCLK Source Select 7 */
7292 #define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */
7293 #define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
7294 #define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */
7295 #define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
7296 #define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */
7297 #define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */
7298 
7299 #define SELA_0 (0x0000) /* ACLK Source Select 0 */
7300 #define SELA_1 (0x0100) /* ACLK Source Select 1 */
7301 #define SELA_2 (0x0200) /* ACLK Source Select 2 */
7302 #define SELA_3 (0x0300) /* ACLK Source Select 3 */
7303 #define SELA_4 (0x0400) /* ACLK Source Select 4 */
7304 #define SELA_5 (0x0500) /* ACLK Source Select 5 */
7305 #define SELA_6 (0x0600) /* ACLK Source Select 6 */
7306 #define SELA_7 (0x0700) /* ACLK Source Select 7 */
7307 #define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */
7308 #define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
7309 #define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */
7310 #define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */
7311 #define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */
7312 #define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */
7313 
7314 /* UCSCTL5 Control Bits */
7315 #define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
7316 #define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
7317 #define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
7318 //#define RESERVED (0x0008) /* RESERVED */
7319 #define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
7320 #define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
7321 #define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
7322 //#define RESERVED (0x0080) /* RESERVED */
7323 #define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
7324 #define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
7325 #define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
7326 //#define RESERVED (0x0800) /* RESERVED */
7327 #define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */
7328 #define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */
7329 #define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */
7330 //#define RESERVED (0x8000) /* RESERVED */
7331 
7332 /* UCSCTL5 Control Bits */
7333 #define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
7334 #define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
7335 #define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
7336 //#define RESERVED (0x0008) /* RESERVED */
7337 #define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
7338 #define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
7339 #define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
7340 //#define RESERVED (0x0080) /* RESERVED */
7341 //#define RESERVED (0x0800) /* RESERVED */
7342 //#define RESERVED (0x8000) /* RESERVED */
7343 
7344 /* UCSCTL5 Control Bits */
7345 //#define RESERVED (0x0008) /* RESERVED */
7346 //#define RESERVED (0x0080) /* RESERVED */
7347 #define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
7348 #define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
7349 #define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
7350 //#define RESERVED (0x0800) /* RESERVED */
7351 #define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */
7352 #define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */
7353 #define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */
7354 //#define RESERVED (0x8000) /* RESERVED */
7355 
7356 #define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
7357 #define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
7358 #define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
7359 #define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
7360 #define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
7361 #define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
7362 #define DIVM_6 (0x0006) /* MCLK Source Divider 6 */
7363 #define DIVM_7 (0x0007) /* MCLK Source Divider 7 */
7364 #define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
7365 #define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
7366 #define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
7367 #define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
7368 #define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
7369 #define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
7370 
7371 #define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
7372 #define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
7373 #define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
7374 #define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
7375 #define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
7376 #define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
7377 #define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */
7378 #define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */
7379 #define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
7380 #define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
7381 #define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
7382 #define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
7383 #define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
7384 #define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
7385 
7386 #define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
7387 #define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
7388 #define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
7389 #define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
7390 #define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
7391 #define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
7392 #define DIVA_6 (0x0600) /* ACLK Source Divider 6 */
7393 #define DIVA_7 (0x0700) /* ACLK Source Divider 7 */
7394 #define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
7395 #define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
7396 #define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
7397 #define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
7398 #define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
7399 #define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
7400 
7401 #define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */
7402 #define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */
7403 #define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */
7404 #define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */
7405 #define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */
7406 #define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */
7407 #define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */
7408 #define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */
7409 #define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */
7410 #define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */
7411 #define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */
7412 #define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */
7413 #define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */
7414 #define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */
7415 
7416 /* UCSCTL6 Control Bits */
7417 #define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
7418 #define SMCLKOFF (0x0002) /* SMCLK Off */
7419 #define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */
7420 #define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */
7421 #define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
7422 #define XTS (0x0020) /* 1: Selects high-freq. oscillator */
7423 #define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */
7424 #define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */
7425 #define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */
7426 //#define RESERVED (0x0200) /* RESERVED */
7427 //#define RESERVED (0x0400) /* RESERVED */
7428 //#define RESERVED (0x0800) /* RESERVED */
7429 #define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
7430 //#define RESERVED (0x2000) /* RESERVED */
7431 #define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */
7432 #define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */
7433 
7434 /* UCSCTL6 Control Bits */
7435 #define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
7436 #define SMCLKOFF_L (0x0002) /* SMCLK Off */
7437 #define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */
7438 #define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */
7439 #define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
7440 #define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */
7441 #define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */
7442 #define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */
7443 //#define RESERVED (0x0200) /* RESERVED */
7444 //#define RESERVED (0x0400) /* RESERVED */
7445 //#define RESERVED (0x0800) /* RESERVED */
7446 //#define RESERVED (0x2000) /* RESERVED */
7447 
7448 /* UCSCTL6 Control Bits */
7449 #define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */
7450 //#define RESERVED (0x0200) /* RESERVED */
7451 //#define RESERVED (0x0400) /* RESERVED */
7452 //#define RESERVED (0x0800) /* RESERVED */
7453 #define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
7454 //#define RESERVED (0x2000) /* RESERVED */
7455 #define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */
7456 #define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */
7457 
7458 #define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */
7459 #define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */
7460 #define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */
7461 #define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */
7462 #define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */
7463 #define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */
7464 #define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */
7465 #define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */
7466 #define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */
7467 #define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */
7468 #define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */
7469 #define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */
7470 
7471 /* UCSCTL7 Control Bits */
7472 #define DCOFFG (0x0001) /* DCO Fault Flag */
7473 #define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
7474 #define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
7475 #define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */
7476 //#define RESERVED (0x0010) /* RESERVED */
7477 //#define RESERVED (0x0020) /* RESERVED */
7478 //#define RESERVED (0x0040) /* RESERVED */
7479 //#define RESERVED (0x0080) /* RESERVED */
7480 //#define RESERVED (0x0100) /* RESERVED */
7481 //#define RESERVED (0x0200) /* RESERVED */
7482 //#define RESERVED (0x0400) /* RESERVED */
7483 //#define RESERVED (0x0800) /* RESERVED */
7484 //#define RESERVED (0x1000) /* RESERVED */
7485 //#define RESERVED (0x2000) /* RESERVED */
7486 //#define RESERVED (0x4000) /* RESERVED */
7487 //#define RESERVED (0x8000) /* RESERVED */
7488 
7489 /* UCSCTL7 Control Bits */
7490 #define DCOFFG_L (0x0001) /* DCO Fault Flag */
7491 #define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
7492 #define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
7493 #define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */
7494 //#define RESERVED (0x0010) /* RESERVED */
7495 //#define RESERVED (0x0020) /* RESERVED */
7496 //#define RESERVED (0x0040) /* RESERVED */
7497 //#define RESERVED (0x0080) /* RESERVED */
7498 //#define RESERVED (0x0100) /* RESERVED */
7499 //#define RESERVED (0x0200) /* RESERVED */
7500 //#define RESERVED (0x0400) /* RESERVED */
7501 //#define RESERVED (0x0800) /* RESERVED */
7502 //#define RESERVED (0x1000) /* RESERVED */
7503 //#define RESERVED (0x2000) /* RESERVED */
7504 //#define RESERVED (0x4000) /* RESERVED */
7505 //#define RESERVED (0x8000) /* RESERVED */
7506 
7507 /* UCSCTL8 Control Bits */
7508 #define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
7509 #define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
7510 #define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
7511 #define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */
7512 //#define RESERVED (0x0010) /* RESERVED */
7513 //#define RESERVED (0x0020) /* RESERVED */
7514 //#define RESERVED (0x0040) /* RESERVED */
7515 //#define RESERVED (0x0080) /* RESERVED */
7516 //#define RESERVED (0x0100) /* RESERVED */
7517 //#define RESERVED (0x0200) /* RESERVED */
7518 //#define RESERVED (0x0400) /* RESERVED */
7519 //#define RESERVED (0x0800) /* RESERVED */
7520 //#define RESERVED (0x1000) /* RESERVED */
7521 //#define RESERVED (0x2000) /* RESERVED */
7522 //#define RESERVED (0x4000) /* RESERVED */
7523 //#define RESERVED (0x8000) /* RESERVED */
7524 
7525 /* UCSCTL8 Control Bits */
7526 #define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
7527 #define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
7528 #define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
7529 #define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */
7530 //#define RESERVED (0x0010) /* RESERVED */
7531 //#define RESERVED (0x0020) /* RESERVED */
7532 //#define RESERVED (0x0040) /* RESERVED */
7533 //#define RESERVED (0x0080) /* RESERVED */
7534 //#define RESERVED (0x0100) /* RESERVED */
7535 //#define RESERVED (0x0200) /* RESERVED */
7536 //#define RESERVED (0x0400) /* RESERVED */
7537 //#define RESERVED (0x0800) /* RESERVED */
7538 //#define RESERVED (0x1000) /* RESERVED */
7539 //#define RESERVED (0x2000) /* RESERVED */
7540 //#define RESERVED (0x4000) /* RESERVED */
7541 //#define RESERVED (0x8000) /* RESERVED */
7542 
7543 #endif
7544 /************************************************************
7545 * UNIFIED CLOCK SYSTEM FOR Radio Devices
7546 ************************************************************/
7547 #ifdef __MSP430_HAS_UCS_RF__ /* Definition to show that Module is available */
7548 
7549 #define OFS_UCSCTL0 (0x0000) /* UCS Control Register 0 */
7550 #define OFS_UCSCTL0_L OFS_UCSCTL0
7551 #define OFS_UCSCTL0_H OFS_UCSCTL0+1
7552 #define OFS_UCSCTL1 (0x0002) /* UCS Control Register 1 */
7553 #define OFS_UCSCTL1_L OFS_UCSCTL1
7554 #define OFS_UCSCTL1_H OFS_UCSCTL1+1
7555 #define OFS_UCSCTL2 (0x0004) /* UCS Control Register 2 */
7556 #define OFS_UCSCTL2_L OFS_UCSCTL2
7557 #define OFS_UCSCTL2_H OFS_UCSCTL2+1
7558 #define OFS_UCSCTL3 (0x0006) /* UCS Control Register 3 */
7559 #define OFS_UCSCTL3_L OFS_UCSCTL3
7560 #define OFS_UCSCTL3_H OFS_UCSCTL3+1
7561 #define OFS_UCSCTL4 (0x0008) /* UCS Control Register 4 */
7562 #define OFS_UCSCTL4_L OFS_UCSCTL4
7563 #define OFS_UCSCTL4_H OFS_UCSCTL4+1
7564 #define OFS_UCSCTL5 (0x000A) /* UCS Control Register 5 */
7565 #define OFS_UCSCTL5_L OFS_UCSCTL5
7566 #define OFS_UCSCTL5_H OFS_UCSCTL5+1
7567 #define OFS_UCSCTL6 (0x000C) /* UCS Control Register 6 */
7568 #define OFS_UCSCTL6_L OFS_UCSCTL6
7569 #define OFS_UCSCTL6_H OFS_UCSCTL6+1
7570 #define OFS_UCSCTL7 (0x000E) /* UCS Control Register 7 */
7571 #define OFS_UCSCTL7_L OFS_UCSCTL7
7572 #define OFS_UCSCTL7_H OFS_UCSCTL7+1
7573 #define OFS_UCSCTL8 (0x0010) /* UCS Control Register 8 */
7574 #define OFS_UCSCTL8_L OFS_UCSCTL8
7575 #define OFS_UCSCTL8_H OFS_UCSCTL8+1
7576 
7577 /* UCSCTL0 Control Bits */
7578 //#define RESERVED (0x0001) /* RESERVED */
7579 //#define RESERVED (0x0002) /* RESERVED */
7580 //#define RESERVED (0x0004) /* RESERVED */
7581 #define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */
7582 #define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */
7583 #define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */
7584 #define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */
7585 #define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */
7586 #define DCO0 (0x0100) /* DCO TAP Bit : 0 */
7587 #define DCO1 (0x0200) /* DCO TAP Bit : 1 */
7588 #define DCO2 (0x0400) /* DCO TAP Bit : 2 */
7589 #define DCO3 (0x0800) /* DCO TAP Bit : 3 */
7590 #define DCO4 (0x1000) /* DCO TAP Bit : 4 */
7591 //#define RESERVED (0x2000) /* RESERVED */
7592 //#define RESERVED (0x4000) /* RESERVED */
7593 //#define RESERVED (0x8000) /* RESERVED */
7594 
7595 /* UCSCTL0 Control Bits */
7596 //#define RESERVED (0x0001) /* RESERVED */
7597 //#define RESERVED (0x0002) /* RESERVED */
7598 //#define RESERVED (0x0004) /* RESERVED */
7599 #define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */
7600 #define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */
7601 #define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */
7602 #define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */
7603 #define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */
7604 //#define RESERVED (0x2000) /* RESERVED */
7605 //#define RESERVED (0x4000) /* RESERVED */
7606 //#define RESERVED (0x8000) /* RESERVED */
7607 
7608 /* UCSCTL0 Control Bits */
7609 //#define RESERVED (0x0001) /* RESERVED */
7610 //#define RESERVED (0x0002) /* RESERVED */
7611 //#define RESERVED (0x0004) /* RESERVED */
7612 #define DCO0_H (0x0001) /* DCO TAP Bit : 0 */
7613 #define DCO1_H (0x0002) /* DCO TAP Bit : 1 */
7614 #define DCO2_H (0x0004) /* DCO TAP Bit : 2 */
7615 #define DCO3_H (0x0008) /* DCO TAP Bit : 3 */
7616 #define DCO4_H (0x0010) /* DCO TAP Bit : 4 */
7617 //#define RESERVED (0x2000) /* RESERVED */
7618 //#define RESERVED (0x4000) /* RESERVED */
7619 //#define RESERVED (0x8000) /* RESERVED */
7620 
7621 /* UCSCTL1 Control Bits */
7622 #define DISMOD (0x0001) /* Disable Modulation */
7623 //#define RESERVED (0x0002) /* RESERVED */
7624 //#define RESERVED (0x0004) /* RESERVED */
7625 //#define RESERVED (0x0008) /* RESERVED */
7626 #define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */
7627 #define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */
7628 #define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */
7629 //#define RESERVED (0x0080) /* RESERVED */
7630 //#define RESERVED (0x0100) /* RESERVED */
7631 //#define RESERVED (0x0200) /* RESERVED */
7632 //#define RESERVED (0x0400) /* RESERVED */
7633 //#define RESERVED (0x0800) /* RESERVED */
7634 //#define RESERVED (0x1000) /* RESERVED */
7635 //#define RESERVED (0x2000) /* RESERVED */
7636 //#define RESERVED (0x4000) /* RESERVED */
7637 //#define RESERVED (0x8000) /* RESERVED */
7638 
7639 /* UCSCTL1 Control Bits */
7640 #define DISMOD_L (0x0001) /* Disable Modulation */
7641 //#define RESERVED (0x0002) /* RESERVED */
7642 //#define RESERVED (0x0004) /* RESERVED */
7643 //#define RESERVED (0x0008) /* RESERVED */
7644 #define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */
7645 #define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */
7646 #define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */
7647 //#define RESERVED (0x0080) /* RESERVED */
7648 //#define RESERVED (0x0100) /* RESERVED */
7649 //#define RESERVED (0x0200) /* RESERVED */
7650 //#define RESERVED (0x0400) /* RESERVED */
7651 //#define RESERVED (0x0800) /* RESERVED */
7652 //#define RESERVED (0x1000) /* RESERVED */
7653 //#define RESERVED (0x2000) /* RESERVED */
7654 //#define RESERVED (0x4000) /* RESERVED */
7655 //#define RESERVED (0x8000) /* RESERVED */
7656 
7657 #define DCORSEL_0 (0x0000) /* DCO RSEL 0 */
7658 #define DCORSEL_1 (0x0010) /* DCO RSEL 1 */
7659 #define DCORSEL_2 (0x0020) /* DCO RSEL 2 */
7660 #define DCORSEL_3 (0x0030) /* DCO RSEL 3 */
7661 #define DCORSEL_4 (0x0040) /* DCO RSEL 4 */
7662 #define DCORSEL_5 (0x0050) /* DCO RSEL 5 */
7663 #define DCORSEL_6 (0x0060) /* DCO RSEL 6 */
7664 #define DCORSEL_7 (0x0070) /* DCO RSEL 7 */
7665 
7666 /* UCSCTL2 Control Bits */
7667 #define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */
7668 #define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */
7669 #define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */
7670 #define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */
7671 #define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */
7672 #define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */
7673 #define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */
7674 #define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */
7675 #define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */
7676 #define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */
7677 //#define RESERVED (0x0400) /* RESERVED */
7678 //#define RESERVED (0x0800) /* RESERVED */
7679 #define FLLD0 (0x1000) /* Loop Divider Bit : 0 */
7680 #define FLLD1 (0x2000) /* Loop Divider Bit : 1 */
7681 #define FLLD2 (0x4000) /* Loop Divider Bit : 1 */
7682 //#define RESERVED (0x8000) /* RESERVED */
7683 
7684 /* UCSCTL2 Control Bits */
7685 #define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */
7686 #define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */
7687 #define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */
7688 #define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */
7689 #define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */
7690 #define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */
7691 #define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */
7692 #define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */
7693 //#define RESERVED (0x0400) /* RESERVED */
7694 //#define RESERVED (0x0800) /* RESERVED */
7695 //#define RESERVED (0x8000) /* RESERVED */
7696 
7697 /* UCSCTL2 Control Bits */
7698 #define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */
7699 #define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */
7700 //#define RESERVED (0x0400) /* RESERVED */
7701 //#define RESERVED (0x0800) /* RESERVED */
7702 #define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */
7703 #define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */
7704 #define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */
7705 //#define RESERVED (0x8000) /* RESERVED */
7706 
7707 #define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */
7708 #define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */
7709 #define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */
7710 #define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */
7711 #define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */
7712 #define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */
7713 #define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */
7714 #define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */
7715 #define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */
7716 #define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */
7717 #define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */
7718 #define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */
7719 #define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */
7720 #define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */
7721 
7722 /* UCSCTL3 Control Bits */
7723 #define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */
7724 #define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */
7725 #define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */
7726 //#define RESERVED (0x0008) /* RESERVED */
7727 #define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */
7728 #define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */
7729 #define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */
7730 //#define RESERVED (0x0080) /* RESERVED */
7731 //#define RESERVED (0x0100) /* RESERVED */
7732 //#define RESERVED (0x0200) /* RESERVED */
7733 //#define RESERVED (0x0400) /* RESERVED */
7734 //#define RESERVED (0x0800) /* RESERVED */
7735 //#define RESERVED (0x1000) /* RESERVED */
7736 //#define RESERVED (0x2000) /* RESERVED */
7737 //#define RESERVED (0x4000) /* RESERVED */
7738 //#define RESERVED (0x8000) /* RESERVED */
7739 
7740 /* UCSCTL3 Control Bits */
7741 #define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */
7742 #define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */
7743 #define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */
7744 //#define RESERVED (0x0008) /* RESERVED */
7745 #define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */
7746 #define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */
7747 #define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */
7748 //#define RESERVED (0x0080) /* RESERVED */
7749 //#define RESERVED (0x0100) /* RESERVED */
7750 //#define RESERVED (0x0200) /* RESERVED */
7751 //#define RESERVED (0x0400) /* RESERVED */
7752 //#define RESERVED (0x0800) /* RESERVED */
7753 //#define RESERVED (0x1000) /* RESERVED */
7754 //#define RESERVED (0x2000) /* RESERVED */
7755 //#define RESERVED (0x4000) /* RESERVED */
7756 //#define RESERVED (0x8000) /* RESERVED */
7757 
7758 #define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */
7759 #define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */
7760 #define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */
7761 #define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */
7762 #define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */
7763 #define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */
7764 #define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */
7765 #define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */
7766 #define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */
7767 #define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */
7768 #define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */
7769 #define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */
7770 #define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */
7771 #define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */
7772 #define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */
7773 #define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */
7774 #define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */
7775 #define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */
7776 #define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */
7777 #define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */
7778 #define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */
7779 #define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */
7780 #define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */
7781 #define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */
7782 #define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */
7783 
7784 /* UCSCTL4 Control Bits */
7785 #define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
7786 #define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
7787 #define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
7788 //#define RESERVED (0x0008) /* RESERVED */
7789 #define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
7790 #define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
7791 #define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
7792 //#define RESERVED (0x0080) /* RESERVED */
7793 #define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
7794 #define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
7795 #define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
7796 //#define RESERVED (0x0800) /* RESERVED */
7797 //#define RESERVED (0x1000) /* RESERVED */
7798 //#define RESERVED (0x2000) /* RESERVED */
7799 //#define RESERVED (0x4000) /* RESERVED */
7800 //#define RESERVED (0x8000) /* RESERVED */
7801 
7802 /* UCSCTL4 Control Bits */
7803 #define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
7804 #define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
7805 #define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
7806 //#define RESERVED (0x0008) /* RESERVED */
7807 #define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
7808 #define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
7809 #define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
7810 //#define RESERVED (0x0080) /* RESERVED */
7811 //#define RESERVED (0x0800) /* RESERVED */
7812 //#define RESERVED (0x1000) /* RESERVED */
7813 //#define RESERVED (0x2000) /* RESERVED */
7814 //#define RESERVED (0x4000) /* RESERVED */
7815 //#define RESERVED (0x8000) /* RESERVED */
7816 
7817 /* UCSCTL4 Control Bits */
7818 //#define RESERVED (0x0008) /* RESERVED */
7819 //#define RESERVED (0x0080) /* RESERVED */
7820 #define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
7821 #define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
7822 #define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
7823 //#define RESERVED (0x0800) /* RESERVED */
7824 //#define RESERVED (0x1000) /* RESERVED */
7825 //#define RESERVED (0x2000) /* RESERVED */
7826 //#define RESERVED (0x4000) /* RESERVED */
7827 //#define RESERVED (0x8000) /* RESERVED */
7828 
7829 #define SELM_0 (0x0000) /* MCLK Source Select 0 */
7830 #define SELM_1 (0x0001) /* MCLK Source Select 1 */
7831 #define SELM_2 (0x0002) /* MCLK Source Select 2 */
7832 #define SELM_3 (0x0003) /* MCLK Source Select 3 */
7833 #define SELM_4 (0x0004) /* MCLK Source Select 4 */
7834 #define SELM_5 (0x0005) /* MCLK Source Select 5 */
7835 #define SELM_6 (0x0006) /* MCLK Source Select 6 */
7836 #define SELM_7 (0x0007) /* MCLK Source Select 7 */
7837 #define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */
7838 #define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
7839 #define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */
7840 #define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
7841 #define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */
7842 #define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */
7843 
7844 #define SELS_0 (0x0000) /* SMCLK Source Select 0 */
7845 #define SELS_1 (0x0010) /* SMCLK Source Select 1 */
7846 #define SELS_2 (0x0020) /* SMCLK Source Select 2 */
7847 #define SELS_3 (0x0030) /* SMCLK Source Select 3 */
7848 #define SELS_4 (0x0040) /* SMCLK Source Select 4 */
7849 #define SELS_5 (0x0050) /* SMCLK Source Select 5 */
7850 #define SELS_6 (0x0060) /* SMCLK Source Select 6 */
7851 #define SELS_7 (0x0070) /* SMCLK Source Select 7 */
7852 #define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */
7853 #define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
7854 #define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */
7855 #define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
7856 #define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */
7857 #define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */
7858 
7859 #define SELA_0 (0x0000) /* ACLK Source Select 0 */
7860 #define SELA_1 (0x0100) /* ACLK Source Select 1 */
7861 #define SELA_2 (0x0200) /* ACLK Source Select 2 */
7862 #define SELA_3 (0x0300) /* ACLK Source Select 3 */
7863 #define SELA_4 (0x0400) /* ACLK Source Select 4 */
7864 #define SELA_5 (0x0500) /* ACLK Source Select 5 */
7865 #define SELA_6 (0x0600) /* ACLK Source Select 6 */
7866 #define SELA_7 (0x0700) /* ACLK Source Select 7 */
7867 #define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */
7868 #define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
7869 #define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */
7870 #define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */
7871 #define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */
7872 #define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */
7873 
7874 /* UCSCTL5 Control Bits */
7875 #define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
7876 #define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
7877 #define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
7878 //#define RESERVED (0x0008) /* RESERVED */
7879 #define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
7880 #define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
7881 #define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
7882 //#define RESERVED (0x0080) /* RESERVED */
7883 #define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
7884 #define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
7885 #define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
7886 //#define RESERVED (0x0800) /* RESERVED */
7887 #define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */
7888 #define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */
7889 #define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */
7890 //#define RESERVED (0x8000) /* RESERVED */
7891 
7892 /* UCSCTL5 Control Bits */
7893 #define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
7894 #define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
7895 #define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
7896 //#define RESERVED (0x0008) /* RESERVED */
7897 #define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
7898 #define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
7899 #define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
7900 //#define RESERVED (0x0080) /* RESERVED */
7901 //#define RESERVED (0x0800) /* RESERVED */
7902 //#define RESERVED (0x8000) /* RESERVED */
7903 
7904 /* UCSCTL5 Control Bits */
7905 //#define RESERVED (0x0008) /* RESERVED */
7906 //#define RESERVED (0x0080) /* RESERVED */
7907 #define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
7908 #define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
7909 #define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
7910 //#define RESERVED (0x0800) /* RESERVED */
7911 #define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */
7912 #define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */
7913 #define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */
7914 //#define RESERVED (0x8000) /* RESERVED */
7915 
7916 #define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
7917 #define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
7918 #define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
7919 #define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
7920 #define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
7921 #define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
7922 #define DIVM_6 (0x0006) /* MCLK Source Divider 6 */
7923 #define DIVM_7 (0x0007) /* MCLK Source Divider 7 */
7924 #define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
7925 #define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
7926 #define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
7927 #define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
7928 #define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
7929 #define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
7930 
7931 #define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
7932 #define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
7933 #define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
7934 #define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
7935 #define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
7936 #define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
7937 #define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */
7938 #define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */
7939 #define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
7940 #define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
7941 #define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
7942 #define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
7943 #define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
7944 #define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
7945 
7946 #define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
7947 #define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
7948 #define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
7949 #define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
7950 #define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
7951 #define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
7952 #define DIVA_6 (0x0600) /* ACLK Source Divider 6 */
7953 #define DIVA_7 (0x0700) /* ACLK Source Divider 7 */
7954 #define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
7955 #define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
7956 #define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
7957 #define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
7958 #define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
7959 #define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
7960 
7961 #define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */
7962 #define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */
7963 #define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */
7964 #define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */
7965 #define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */
7966 #define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */
7967 #define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */
7968 #define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */
7969 #define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */
7970 #define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */
7971 #define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */
7972 #define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */
7973 #define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */
7974 #define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */
7975 
7976 /* UCSCTL6 Control Bits */
7977 #define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
7978 #define SMCLKOFF (0x0002) /* SMCLK Off */
7979 #define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */
7980 #define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */
7981 #define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
7982 #define XTS (0x0020) /* 1: Selects high-freq. oscillator */
7983 #define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */
7984 #define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */
7985 #define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */
7986 //#define RESERVED (0x0200) /* RESERVED */
7987 //#define RESERVED (0x0400) /* RESERVED */
7988 //#define RESERVED (0x0800) /* RESERVED */
7989 //#define RESERVED (0x1000) /* RESERVED */
7990 //#define RESERVED (0x2000) /* RESERVED */
7991 //#define RESERVED (0x4000) /* RESERVED */
7992 //#define RESERVED (0x8000) /* RESERVED */
7993 
7994 /* UCSCTL6 Control Bits */
7995 #define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
7996 #define SMCLKOFF_L (0x0002) /* SMCLK Off */
7997 #define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */
7998 #define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */
7999 #define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
8000 #define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */
8001 #define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */
8002 #define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */
8003 //#define RESERVED (0x0200) /* RESERVED */
8004 //#define RESERVED (0x0400) /* RESERVED */
8005 //#define RESERVED (0x0800) /* RESERVED */
8006 //#define RESERVED (0x1000) /* RESERVED */
8007 //#define RESERVED (0x2000) /* RESERVED */
8008 //#define RESERVED (0x4000) /* RESERVED */
8009 //#define RESERVED (0x8000) /* RESERVED */
8010 
8011 /* UCSCTL6 Control Bits */
8012 #define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */
8013 //#define RESERVED (0x0200) /* RESERVED */
8014 //#define RESERVED (0x0400) /* RESERVED */
8015 //#define RESERVED (0x0800) /* RESERVED */
8016 //#define RESERVED (0x1000) /* RESERVED */
8017 //#define RESERVED (0x2000) /* RESERVED */
8018 //#define RESERVED (0x4000) /* RESERVED */
8019 //#define RESERVED (0x8000) /* RESERVED */
8020 
8021 #define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */
8022 #define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */
8023 #define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */
8024 #define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */
8025 #define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */
8026 #define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */
8027 #define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */
8028 #define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */
8029 
8030 /* UCSCTL7 Control Bits */
8031 #define DCOFFG (0x0001) /* DCO Fault Flag */
8032 #define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
8033 #define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
8034 #define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */
8035 //#define RESERVED (0x0010) /* RESERVED */
8036 //#define RESERVED (0x0020) /* RESERVED */
8037 //#define RESERVED (0x0040) /* RESERVED */
8038 //#define RESERVED (0x0080) /* RESERVED */
8039 //#define RESERVED (0x0100) /* RESERVED */
8040 //#define RESERVED (0x0200) /* RESERVED */
8041 //#define RESERVED (0x0400) /* RESERVED */
8042 //#define RESERVED (0x0800) /* RESERVED */
8043 //#define RESERVED (0x1000) /* RESERVED */
8044 //#define RESERVED (0x2000) /* RESERVED */
8045 //#define RESERVED (0x4000) /* RESERVED */
8046 //#define RESERVED (0x8000) /* RESERVED */
8047 
8048 /* UCSCTL7 Control Bits */
8049 #define DCOFFG_L (0x0001) /* DCO Fault Flag */
8050 #define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
8051 #define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
8052 #define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */
8053 //#define RESERVED (0x0010) /* RESERVED */
8054 //#define RESERVED (0x0020) /* RESERVED */
8055 //#define RESERVED (0x0040) /* RESERVED */
8056 //#define RESERVED (0x0080) /* RESERVED */
8057 //#define RESERVED (0x0100) /* RESERVED */
8058 //#define RESERVED (0x0200) /* RESERVED */
8059 //#define RESERVED (0x0400) /* RESERVED */
8060 //#define RESERVED (0x0800) /* RESERVED */
8061 //#define RESERVED (0x1000) /* RESERVED */
8062 //#define RESERVED (0x2000) /* RESERVED */
8063 //#define RESERVED (0x4000) /* RESERVED */
8064 //#define RESERVED (0x8000) /* RESERVED */
8065 
8066 /* UCSCTL8 Control Bits */
8067 #define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
8068 #define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
8069 #define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
8070 #define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */
8071 //#define RESERVED (0x0010) /* RESERVED */
8072 //#define RESERVED (0x0020) /* RESERVED */
8073 //#define RESERVED (0x0040) /* RESERVED */
8074 //#define RESERVED (0x0080) /* RESERVED */
8075 //#define RESERVED (0x0100) /* RESERVED */
8076 //#define RESERVED (0x0200) /* RESERVED */
8077 //#define RESERVED (0x0400) /* RESERVED */
8078 //#define RESERVED (0x0800) /* RESERVED */
8079 //#define RESERVED (0x1000) /* RESERVED */
8080 //#define RESERVED (0x2000) /* RESERVED */
8081 //#define RESERVED (0x4000) /* RESERVED */
8082 //#define RESERVED (0x8000) /* RESERVED */
8083 
8084 /* UCSCTL8 Control Bits */
8085 #define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
8086 #define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
8087 #define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
8088 #define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */
8089 //#define RESERVED (0x0010) /* RESERVED */
8090 //#define RESERVED (0x0020) /* RESERVED */
8091 //#define RESERVED (0x0040) /* RESERVED */
8092 //#define RESERVED (0x0080) /* RESERVED */
8093 //#define RESERVED (0x0100) /* RESERVED */
8094 //#define RESERVED (0x0200) /* RESERVED */
8095 //#define RESERVED (0x0400) /* RESERVED */
8096 //#define RESERVED (0x0800) /* RESERVED */
8097 //#define RESERVED (0x1000) /* RESERVED */
8098 //#define RESERVED (0x2000) /* RESERVED */
8099 //#define RESERVED (0x4000) /* RESERVED */
8100 //#define RESERVED (0x8000) /* RESERVED */
8101 
8102 #endif
8103 /************************************************************
8104 * USB
8105 ************************************************************/
8106 #ifdef __MSP430_HAS_USB__ /* Definition to show that Module is available */
8107 
8108 /* ========================================================================= */
8109 /* USB Configuration Registers */
8110 /* ========================================================================= */
8111 #define OFS_USBKEYID (0x0000) /* USB Controller key register */
8112 #define OFS_USBKEYID_L OFS_USBKEYID
8113 #define OFS_USBKEYID_H OFS_USBKEYID+1
8114 #define OFS_USBCNF (0x0002) /* USB Module configuration register */
8115 #define OFS_USBCNF_L OFS_USBCNF
8116 #define OFS_USBCNF_H OFS_USBCNF+1
8117 #define OFS_USBPHYCTL (0x0004) /* USB PHY control register */
8118 #define OFS_USBPHYCTL_L OFS_USBPHYCTL
8119 #define OFS_USBPHYCTL_H OFS_USBPHYCTL+1
8120 #define OFS_USBPWRCTL (0x0008) /* USB Power control register */
8121 #define OFS_USBPWRCTL_L OFS_USBPWRCTL
8122 #define OFS_USBPWRCTL_H OFS_USBPWRCTL+1
8123 #define OFS_USBPLLCTL (0x0010) /* USB PLL control register */
8124 #define OFS_USBPLLCTL_L OFS_USBPLLCTL
8125 #define OFS_USBPLLCTL_H OFS_USBPLLCTL+1
8126 #define OFS_USBPLLDIVB (0x0012) /* USB PLL Clock Divider Buffer control register */
8127 #define OFS_USBPLLDIVB_L OFS_USBPLLDIVB
8128 #define OFS_USBPLLDIVB_H OFS_USBPLLDIVB+1
8129 #define OFS_USBPLLIR (0x0014) /* USB PLL Interrupt control register */
8130 #define OFS_USBPLLIR_L OFS_USBPLLIR
8131 #define OFS_USBPLLIR_H OFS_USBPLLIR+1
8132 
8133 #define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */
8134 #define USBKEY (0x9628) /* USB Control Register key */
8135 
8136 /* USBCNF Control Bits */
8137 #define USB_EN (0x0001) /* USB - Module enable */
8138 #define PUR_EN (0x0002) /* USB - PUR pin enable */
8139 #define PUR_IN (0x0004) /* USB - PUR pin input value */
8140 #define BLKRDY (0x0008) /* USB - Block ready signal for DMA */
8141 #define FNTEN (0x0010) /* USB - Frame Number receive Trigger enable for DMA */
8142 //#define RESERVED (0x0020) /* USB - */
8143 //#define RESERVED (0x0040) /* USB - */
8144 //#define RESERVED (0x0080) /* USB - */
8145 //#define RESERVED (0x0100) /* USB - */
8146 //#define RESERVED (0x0200) /* USB - */
8147 //#define RESERVED (0x0400) /* USB - */
8148 //#define RESERVED (0x0800) /* USB - */
8149 //#define RESERVED (0x1000) /* USB - */
8150 //#define RESERVED (0x2000) /* USB - */
8151 //#define RESERVED (0x4000) /* USB - */
8152 //#define RESERVED (0x8000) /* USB - */
8153 
8154 /* USBCNF Control Bits */
8155 #define USB_EN_L (0x0001) /* USB - Module enable */
8156 #define PUR_EN_L (0x0002) /* USB - PUR pin enable */
8157 #define PUR_IN_L (0x0004) /* USB - PUR pin input value */
8158 #define BLKRDY_L (0x0008) /* USB - Block ready signal for DMA */
8159 #define FNTEN_L (0x0010) /* USB - Frame Number receive Trigger enable for DMA */
8160 //#define RESERVED (0x0020) /* USB - */
8161 //#define RESERVED (0x0040) /* USB - */
8162 //#define RESERVED (0x0080) /* USB - */
8163 //#define RESERVED (0x0100) /* USB - */
8164 //#define RESERVED (0x0200) /* USB - */
8165 //#define RESERVED (0x0400) /* USB - */
8166 //#define RESERVED (0x0800) /* USB - */
8167 //#define RESERVED (0x1000) /* USB - */
8168 //#define RESERVED (0x2000) /* USB - */
8169 //#define RESERVED (0x4000) /* USB - */
8170 //#define RESERVED (0x8000) /* USB - */
8171 
8172 /* USBPHYCTL Control Bits */
8173 #define PUOUT0 (0x0001) /* USB - USB Port Output Signal Bit 0 */
8174 #define PUOUT1 (0x0002) /* USB - USB Port Output Signal Bit 1 */
8175 #define PUIN0 (0x0004) /* USB - PU0/DP Input Data */
8176 #define PUIN1 (0x0008) /* USB - PU1/DM Input Data */
8177 //#define RESERVED (0x0010) /* USB - */
8178 #define PUOPE (0x0020) /* USB - USB Port Output Enable */
8179 //#define RESERVED (0x0040) /* USB - */
8180 #define PUSEL (0x0080) /* USB - USB Port Function Select */
8181 #define PUIPE (0x0100) /* USB - PHY Single Ended Input enable */
8182 //#define RESERVED (0x0200) /* USB - */
8183 //#define RESERVED (0x0100) /* USB - */
8184 //#define RESERVED (0x0200) /* USB - */
8185 //#define RESERVED (0x0400) /* USB - */
8186 //#define RESERVED (0x0800) /* USB - */
8187 //#define RESERVED (0x1000) /* USB - */
8188 //#define RESERVED (0x2000) /* USB - */
8189 //#define RESERVED (0x4000) /* USB - */
8190 //#define RESERVED (0x8000) /* USB - */
8191 
8192 /* USBPHYCTL Control Bits */
8193 #define PUOUT0_L (0x0001) /* USB - USB Port Output Signal Bit 0 */
8194 #define PUOUT1_L (0x0002) /* USB - USB Port Output Signal Bit 1 */
8195 #define PUIN0_L (0x0004) /* USB - PU0/DP Input Data */
8196 #define PUIN1_L (0x0008) /* USB - PU1/DM Input Data */
8197 //#define RESERVED (0x0010) /* USB - */
8198 #define PUOPE_L (0x0020) /* USB - USB Port Output Enable */
8199 //#define RESERVED (0x0040) /* USB - */
8200 #define PUSEL_L (0x0080) /* USB - USB Port Function Select */
8201 //#define RESERVED (0x0200) /* USB - */
8202 //#define RESERVED (0x0100) /* USB - */
8203 //#define RESERVED (0x0200) /* USB - */
8204 //#define RESERVED (0x0400) /* USB - */
8205 //#define RESERVED (0x0800) /* USB - */
8206 //#define RESERVED (0x1000) /* USB - */
8207 //#define RESERVED (0x2000) /* USB - */
8208 //#define RESERVED (0x4000) /* USB - */
8209 //#define RESERVED (0x8000) /* USB - */
8210 
8211 /* USBPHYCTL Control Bits */
8212 //#define RESERVED (0x0010) /* USB - */
8213 //#define RESERVED (0x0040) /* USB - */
8214 #define PUIPE_H (0x0001) /* USB - PHY Single Ended Input enable */
8215 //#define RESERVED (0x0200) /* USB - */
8216 //#define RESERVED (0x0100) /* USB - */
8217 //#define RESERVED (0x0200) /* USB - */
8218 //#define RESERVED (0x0400) /* USB - */
8219 //#define RESERVED (0x0800) /* USB - */
8220 //#define RESERVED (0x1000) /* USB - */
8221 //#define RESERVED (0x2000) /* USB - */
8222 //#define RESERVED (0x4000) /* USB - */
8223 //#define RESERVED (0x8000) /* USB - */
8224 
8225 #define PUDIR (0x0020) /* USB - Legacy Definition: USB Port Output Enable */
8226 #define PSEIEN (0x0100) /* USB - Legacy Definition: PHY Single Ended Input enable */
8227 
8228 /* USBPWRCTL Control Bits */
8229 #define VUOVLIFG (0x0001) /* USB - VUSB Overload Interrupt Flag */
8230 #define VBONIFG (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */
8231 #define VBOFFIFG (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */
8232 #define USBBGVBV (0x0008) /* USB - USB Bandgap and VBUS valid */
8233 #define USBDETEN (0x0010) /* USB - VBUS on/off events enable */
8234 #define OVLAOFF (0x0020) /* USB - LDO overload auto off enable */
8235 #define SLDOAON (0x0040) /* USB - Secondary LDO auto on enable */
8236 //#define RESERVED (0x0080) /* USB - */
8237 #define VUOVLIE (0x0100) /* USB - Overload indication Interrupt Enable */
8238 #define VBONIE (0x0200) /* USB - VBUS "Coming ON" Interrupt Enable */
8239 #define VBOFFIE (0x0400) /* USB - VBUS "Going OFF" Interrupt Enable */
8240 #define VUSBEN (0x0800) /* USB - LDO Enable (3.3V) */
8241 #define SLDOEN (0x1000) /* USB - Secondary LDO Enable (1.8V) */
8242 //#define RESERVED (0x2000) /* USB - */
8243 //#define RESERVED (0x4000) /* USB - */
8244 //#define RESERVED (0x8000) /* USB - */
8245 
8246 /* USBPWRCTL Control Bits */
8247 #define VUOVLIFG_L (0x0001) /* USB - VUSB Overload Interrupt Flag */
8248 #define VBONIFG_L (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */
8249 #define VBOFFIFG_L (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */
8250 #define USBBGVBV_L (0x0008) /* USB - USB Bandgap and VBUS valid */
8251 #define USBDETEN_L (0x0010) /* USB - VBUS on/off events enable */
8252 #define OVLAOFF_L (0x0020) /* USB - LDO overload auto off enable */
8253 #define SLDOAON_L (0x0040) /* USB - Secondary LDO auto on enable */
8254 //#define RESERVED (0x0080) /* USB - */
8255 //#define RESERVED (0x2000) /* USB - */
8256 //#define RESERVED (0x4000) /* USB - */
8257 //#define RESERVED (0x8000) /* USB - */
8258 
8259 /* USBPWRCTL Control Bits */
8260 //#define RESERVED (0x0080) /* USB - */
8261 #define VUOVLIE_H (0x0001) /* USB - Overload indication Interrupt Enable */
8262 #define VBONIE_H (0x0002) /* USB - VBUS "Coming ON" Interrupt Enable */
8263 #define VBOFFIE_H (0x0004) /* USB - VBUS "Going OFF" Interrupt Enable */
8264 #define VUSBEN_H (0x0008) /* USB - LDO Enable (3.3V) */
8265 #define SLDOEN_H (0x0010) /* USB - Secondary LDO Enable (1.8V) */
8266 //#define RESERVED (0x2000) /* USB - */
8267 //#define RESERVED (0x4000) /* USB - */
8268 //#define RESERVED (0x8000) /* USB - */
8269 
8270 /* USBPLLCTL Control Bits */
8271 //#define RESERVED (0x0001) /* USB - */
8272 //#define RESERVED (0x0002) /* USB - */
8273 //#define RESERVED (0x0004) /* USB - */
8274 //#define RESERVED (0x0008) /* USB - */
8275 //#define RESERVED (0x0010) /* USB - */
8276 //#define RESERVED (0x0020) /* USB - */
8277 #define UCLKSEL0 (0x0040) /* USB - Module Clock Select Bit 0 */
8278 #define UCLKSEL1 (0x0080) /* USB - Module Clock Select Bit 1 */
8279 #define UPLLEN (0x0100) /* USB - PLL enable */
8280 #define UPFDEN (0x0200) /* USB - Phase Freq. Discriminator enable */
8281 //#define RESERVED (0x0400) /* USB - */
8282 //#define RESERVED (0x0800) /* USB - */
8283 //#define RESERVED (0x1000) /* USB - */
8284 //#define RESERVED (0x2000) /* USB - */
8285 //#define RESERVED (0x4000) /* USB - */
8286 //#define RESERVED (0x8000) /* USB - */
8287 
8288 /* USBPLLCTL Control Bits */
8289 //#define RESERVED (0x0001) /* USB - */
8290 //#define RESERVED (0x0002) /* USB - */
8291 //#define RESERVED (0x0004) /* USB - */
8292 //#define RESERVED (0x0008) /* USB - */
8293 //#define RESERVED (0x0010) /* USB - */
8294 //#define RESERVED (0x0020) /* USB - */
8295 #define UCLKSEL0_L (0x0040) /* USB - Module Clock Select Bit 0 */
8296 #define UCLKSEL1_L (0x0080) /* USB - Module Clock Select Bit 1 */
8297 //#define RESERVED (0x0400) /* USB - */
8298 //#define RESERVED (0x0800) /* USB - */
8299 //#define RESERVED (0x1000) /* USB - */
8300 //#define RESERVED (0x2000) /* USB - */
8301 //#define RESERVED (0x4000) /* USB - */
8302 //#define RESERVED (0x8000) /* USB - */
8303 
8304 /* USBPLLCTL Control Bits */
8305 //#define RESERVED (0x0001) /* USB - */
8306 //#define RESERVED (0x0002) /* USB - */
8307 //#define RESERVED (0x0004) /* USB - */
8308 //#define RESERVED (0x0008) /* USB - */
8309 //#define RESERVED (0x0010) /* USB - */
8310 //#define RESERVED (0x0020) /* USB - */
8311 #define UPLLEN_H (0x0001) /* USB - PLL enable */
8312 #define UPFDEN_H (0x0002) /* USB - Phase Freq. Discriminator enable */
8313 //#define RESERVED (0x0400) /* USB - */
8314 //#define RESERVED (0x0800) /* USB - */
8315 //#define RESERVED (0x1000) /* USB - */
8316 //#define RESERVED (0x2000) /* USB - */
8317 //#define RESERVED (0x4000) /* USB - */
8318 //#define RESERVED (0x8000) /* USB - */
8319 
8320 #define UCLKSEL_0 (0x0000) /* USB - Module Clock Select: 0 */
8321 #define UCLKSEL_1 (0x0040) /* USB - Module Clock Select: 1 */
8322 #define UCLKSEL_2 (0x0080) /* USB - Module Clock Select: 2 */
8323 #define UCLKSEL_3 (0x00C0) /* USB - Module Clock Select: 3 (Reserved) */
8324 
8325 #define UCLKSEL__PLLCLK (0x0000) /* USB - Module Clock Select: PLLCLK */
8326 #define UCLKSEL__XT1CLK (0x0040) /* USB - Module Clock Select: XT1CLK */
8327 #define UCLKSEL__XT2CLK (0x0080) /* USB - Module Clock Select: XT2CLK */
8328 
8329 /* USBPLLDIVB Control Bits */
8330 #define UPMB0 (0x0001) /* USB - PLL feedback divider buffer Bit 0 */
8331 #define UPMB1 (0x0002) /* USB - PLL feedback divider buffer Bit 1 */
8332 #define UPMB2 (0x0004) /* USB - PLL feedback divider buffer Bit 2 */
8333 #define UPMB3 (0x0008) /* USB - PLL feedback divider buffer Bit 3 */
8334 #define UPMB4 (0x0010) /* USB - PLL feedback divider buffer Bit 4 */
8335 #define UPMB5 (0x0020) /* USB - PLL feedback divider buffer Bit 5 */
8336 //#define RESERVED (0x0040) /* USB - */
8337 //#define RESERVED (0x0080) /* USB - */
8338 #define UPQB0 (0x0100) /* USB - PLL prescale divider buffer Bit 0 */
8339 #define UPQB1 (0x0200) /* USB - PLL prescale divider buffer Bit 1 */
8340 #define UPQB2 (0x0400) /* USB - PLL prescale divider buffer Bit 2 */
8341 //#define RESERVED (0x0800) /* USB - */
8342 //#define RESERVED (0x1000) /* USB - */
8343 //#define RESERVED (0x2000) /* USB - */
8344 //#define RESERVED (0x4000) /* USB - */
8345 //#define RESERVED (0x8000) /* USB - */
8346 
8347 /* USBPLLDIVB Control Bits */
8348 #define UPMB0_L (0x0001) /* USB - PLL feedback divider buffer Bit 0 */
8349 #define UPMB1_L (0x0002) /* USB - PLL feedback divider buffer Bit 1 */
8350 #define UPMB2_L (0x0004) /* USB - PLL feedback divider buffer Bit 2 */
8351 #define UPMB3_L (0x0008) /* USB - PLL feedback divider buffer Bit 3 */
8352 #define UPMB4_L (0x0010) /* USB - PLL feedback divider buffer Bit 4 */
8353 #define UPMB5_L (0x0020) /* USB - PLL feedback divider buffer Bit 5 */
8354 //#define RESERVED (0x0040) /* USB - */
8355 //#define RESERVED (0x0080) /* USB - */
8356 //#define RESERVED (0x0800) /* USB - */
8357 //#define RESERVED (0x1000) /* USB - */
8358 //#define RESERVED (0x2000) /* USB - */
8359 //#define RESERVED (0x4000) /* USB - */
8360 //#define RESERVED (0x8000) /* USB - */
8361 
8362 /* USBPLLDIVB Control Bits */
8363 //#define RESERVED (0x0040) /* USB - */
8364 //#define RESERVED (0x0080) /* USB - */
8365 #define UPQB0_H (0x0001) /* USB - PLL prescale divider buffer Bit 0 */
8366 #define UPQB1_H (0x0002) /* USB - PLL prescale divider buffer Bit 1 */
8367 #define UPQB2_H (0x0004) /* USB - PLL prescale divider buffer Bit 2 */
8368 //#define RESERVED (0x0800) /* USB - */
8369 //#define RESERVED (0x1000) /* USB - */
8370 //#define RESERVED (0x2000) /* USB - */
8371 //#define RESERVED (0x4000) /* USB - */
8372 //#define RESERVED (0x8000) /* USB - */
8373 
8374 #define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */
8375 #define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */
8376 #define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */
8377 #define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */
8378 #define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */
8379 #define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */
8380 #define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */
8381 #define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */
8382 #define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */
8383 #define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */
8384 #define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */
8385 #define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */
8386 #define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */
8387 #define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */
8388 #define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */
8389 #define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */
8390 #define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */
8391 #define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */
8392 #define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */
8393 #define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */
8394 #define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */
8395 #define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */
8396 #define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */
8397 #define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */
8398 #define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */
8399 #define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */
8400 #define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */
8401 #define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */
8402 #define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */
8403 #define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */
8404 #define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */
8405 #define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */
8406 #define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */
8407 #define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */
8408 #define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */
8409 #define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */
8410 #define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */
8411 #define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */
8412 #define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */
8413 #define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */
8414 #define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */
8415 #define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */
8416 #define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */
8417 
8418 /* USBPLLIR Control Bits */
8419 #define USBOOLIFG (0x0001) /* USB - PLL out of lock Interrupt Flag */
8420 #define USBLOSIFG (0x0002) /* USB - PLL loss of signal Interrupt Flag */
8421 #define USBOORIFG (0x0004) /* USB - PLL out of range Interrupt Flag */
8422 //#define RESERVED (0x0008) /* USB - */
8423 //#define RESERVED (0x0010) /* USB - */
8424 //#define RESERVED (0x0020) /* USB - */
8425 //#define RESERVED (0x0040) /* USB - */
8426 //#define RESERVED (0x0080) /* USB - */
8427 #define USBOOLIE (0x0100) /* USB - PLL out of lock Interrupt enable */
8428 #define USBLOSIE (0x0200) /* USB - PLL loss of signal Interrupt enable */
8429 #define USBOORIE (0x0400) /* USB - PLL out of range Interrupt enable */
8430 //#define RESERVED (0x0800) /* USB - */
8431 //#define RESERVED (0x1000) /* USB - */
8432 //#define RESERVED (0x2000) /* USB - */
8433 //#define RESERVED (0x4000) /* USB - */
8434 //#define RESERVED (0x8000) /* USB - */
8435 
8436 /* USBPLLIR Control Bits */
8437 #define USBOOLIFG_L (0x0001) /* USB - PLL out of lock Interrupt Flag */
8438 #define USBLOSIFG_L (0x0002) /* USB - PLL loss of signal Interrupt Flag */
8439 #define USBOORIFG_L (0x0004) /* USB - PLL out of range Interrupt Flag */
8440 //#define RESERVED (0x0008) /* USB - */
8441 //#define RESERVED (0x0010) /* USB - */
8442 //#define RESERVED (0x0020) /* USB - */
8443 //#define RESERVED (0x0040) /* USB - */
8444 //#define RESERVED (0x0080) /* USB - */
8445 //#define RESERVED (0x0800) /* USB - */
8446 //#define RESERVED (0x1000) /* USB - */
8447 //#define RESERVED (0x2000) /* USB - */
8448 //#define RESERVED (0x4000) /* USB - */
8449 //#define RESERVED (0x8000) /* USB - */
8450 
8451 /* USBPLLIR Control Bits */
8452 //#define RESERVED (0x0008) /* USB - */
8453 //#define RESERVED (0x0010) /* USB - */
8454 //#define RESERVED (0x0020) /* USB - */
8455 //#define RESERVED (0x0040) /* USB - */
8456 //#define RESERVED (0x0080) /* USB - */
8457 #define USBOOLIE_H (0x0001) /* USB - PLL out of lock Interrupt enable */
8458 #define USBLOSIE_H (0x0002) /* USB - PLL loss of signal Interrupt enable */
8459 #define USBOORIE_H (0x0004) /* USB - PLL out of range Interrupt enable */
8460 //#define RESERVED (0x0800) /* USB - */
8461 //#define RESERVED (0x1000) /* USB - */
8462 //#define RESERVED (0x2000) /* USB - */
8463 //#define RESERVED (0x4000) /* USB - */
8464 //#define RESERVED (0x8000) /* USB - */
8465 
8466 /* ========================================================================= */
8467 /* USB Control Registers */
8468 /* ========================================================================= */
8469 #define OFS_USBIEPCNF_0 (0x0020) /* USB Input endpoint_0: Configuration */
8470 #define OFS_USBIEPCNT_0 (0x0021) /* USB Input endpoint_0: Byte Count */
8471 #define OFS_USBOEPCNF_0 (0x0022) /* USB Output endpoint_0: Configuration */
8472 #define OFS_USBOEPCNT_0 (0x0023) /* USB Output endpoint_0: byte count */
8473 #define OFS_USBIEPIE (0x002E) /* USB Input endpoint interrupt enable flags */
8474 #define OFS_USBOEPIE (0x002F) /* USB Output endpoint interrupt enable flags */
8475 #define OFS_USBIEPIFG (0x0030) /* USB Input endpoint interrupt flags */
8476 #define OFS_USBOEPIFG (0x0031) /* USB Output endpoint interrupt flags */
8477 #define OFS_USBVECINT (0x0032) /* USB Vector interrupt register */
8478 #define OFS_USBVECINT_L OFS_USBVECINT
8479 #define OFS_USBVECINT_H OFS_USBVECINT+1
8480 #define OFS_USBMAINT (0x0036) /* USB maintenance register */
8481 #define OFS_USBMAINT_L OFS_USBMAINT
8482 #define OFS_USBMAINT_H OFS_USBMAINT+1
8483 #define OFS_USBTSREG (0x0038) /* USB Time Stamp register */
8484 #define OFS_USBTSREG_L OFS_USBTSREG
8485 #define OFS_USBTSREG_H OFS_USBTSREG+1
8486 #define OFS_USBFN (0x003A) /* USB Frame number */
8487 #define OFS_USBFN_L OFS_USBFN
8488 #define OFS_USBFN_H OFS_USBFN+1
8489 #define OFS_USBCTL (0x003C) /* USB control register */
8490 #define OFS_USBIE (0x003D) /* USB interrupt enable register */
8491 #define OFS_USBIFG (0x003E) /* USB interrupt flag register */
8492 #define OFS_USBFUNADR (0x003F) /* USB Function address register */
8493 
8494 #define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */
8495 
8496 /* USBIEPCNF_0 Control Bits */
8497 /* USBOEPCNF_0 Control Bits */
8498 //#define RESERVED (0x0001) /* USB - */
8499 //#define RESERVED (0x0001) /* USB - */
8500 #define USBIIE (0x0004) /* USB - Transaction Interrupt indication enable */
8501 #define STALL (0x0008) /* USB - Stall Condition */
8502 //#define RESERVED (0x0010) /* USB - */
8503 #define TOGGLE (0x0020) /* USB - Toggle Bit */
8504 //#define RESERVED (0x0040) /* USB - */
8505 #define UBME (0x0080) /* USB - UBM In-Endpoint Enable */
8506 
8507 /* USBIEPBCNT_0 Control Bits */
8508 /* USBOEPBCNT_0 Control Bits */
8509 #define CNT0 (0x0001) /* USB - Byte Count Bit 0 */
8510 #define CNT1 (0x0001) /* USB - Byte Count Bit 1 */
8511 #define CNT2 (0x0004) /* USB - Byte Count Bit 2 */
8512 #define CNT3 (0x0008) /* USB - Byte Count Bit 3 */
8513 //#define RESERVED (0x0010) /* USB - */
8514 //#define RESERVED (0x0020) /* USB - */
8515 //#define RESERVED (0x0040) /* USB - */
8516 #define NAK (0x0080) /* USB - No Acknowledge Status Bit */
8517 
8518 /* USBMAINT Control Bits */
8519 #define UTIFG (0x0001) /* USB - Timer Interrupt Flag */
8520 #define UTIE (0x0002) /* USB - Timer Interrupt Enable */
8521 //#define RESERVED (0x0004) /* USB - */
8522 //#define RESERVED (0x0008) /* USB - */
8523 //#define RESERVED (0x0010) /* USB - */
8524 //#define RESERVED (0x0020) /* USB - */
8525 //#define RESERVED (0x0040) /* USB - */
8526 //#define RESERVED (0x0080) /* USB - */
8527 #define TSGEN (0x0100) /* USB - Time Stamp Generator Enable */
8528 #define TSESEL0 (0x0200) /* USB - Time Stamp Event Select Bit 0 */
8529 #define TSESEL1 (0x0400) /* USB - Time Stamp Event Select Bit 1 */
8530 #define TSE3 (0x0800) /* USB - Time Stamp Event #3 Bit */
8531 //#define RESERVED (0x1000) /* USB - */
8532 #define UTSEL0 (0x2000) /* USB - Timer Select Bit 0 */
8533 #define UTSEL1 (0x4000) /* USB - Timer Select Bit 1 */
8534 #define UTSEL2 (0x8000) /* USB - Timer Select Bit 2 */
8535 
8536 /* USBMAINT Control Bits */
8537 #define UTIFG_L (0x0001) /* USB - Timer Interrupt Flag */
8538 #define UTIE_L (0x0002) /* USB - Timer Interrupt Enable */
8539 //#define RESERVED (0x0004) /* USB - */
8540 //#define RESERVED (0x0008) /* USB - */
8541 //#define RESERVED (0x0010) /* USB - */
8542 //#define RESERVED (0x0020) /* USB - */
8543 //#define RESERVED (0x0040) /* USB - */
8544 //#define RESERVED (0x0080) /* USB - */
8545 //#define RESERVED (0x1000) /* USB - */
8546 
8547 /* USBMAINT Control Bits */
8548 //#define RESERVED (0x0004) /* USB - */
8549 //#define RESERVED (0x0008) /* USB - */
8550 //#define RESERVED (0x0010) /* USB - */
8551 //#define RESERVED (0x0020) /* USB - */
8552 //#define RESERVED (0x0040) /* USB - */
8553 //#define RESERVED (0x0080) /* USB - */
8554 #define TSGEN_H (0x0001) /* USB - Time Stamp Generator Enable */
8555 #define TSESEL0_H (0x0002) /* USB - Time Stamp Event Select Bit 0 */
8556 #define TSESEL1_H (0x0004) /* USB - Time Stamp Event Select Bit 1 */
8557 #define TSE3_H (0x0008) /* USB - Time Stamp Event #3 Bit */
8558 //#define RESERVED (0x1000) /* USB - */
8559 #define UTSEL0_H (0x0020) /* USB - Timer Select Bit 0 */
8560 #define UTSEL1_H (0x0040) /* USB - Timer Select Bit 1 */
8561 #define UTSEL2_H (0x0080) /* USB - Timer Select Bit 2 */
8562 
8563 #define TSESEL_0 (0x0000) /* USB - Time Stamp Event Select: 0 */
8564 #define TSESEL_1 (0x0200) /* USB - Time Stamp Event Select: 1 */
8565 #define TSESEL_2 (0x0400) /* USB - Time Stamp Event Select: 2 */
8566 #define TSESEL_3 (0x0600) /* USB - Time Stamp Event Select: 3 */
8567 
8568 #define UTSEL_0 (0x0000) /* USB - Timer Select: 0 */
8569 #define UTSEL_1 (0x2000) /* USB - Timer Select: 1 */
8570 #define UTSEL_2 (0x4000) /* USB - Timer Select: 2 */
8571 #define UTSEL_3 (0x6000) /* USB - Timer Select: 3 */
8572 #define UTSEL_4 (0x8000) /* USB - Timer Select: 4 */
8573 #define UTSEL_5 (0xA000) /* USB - Timer Select: 5 */
8574 #define UTSEL_6 (0xC000) /* USB - Timer Select: 6 */
8575 #define UTSEL_7 (0xE000) /* USB - Timer Select: 7 */
8576 
8577 /* USBCTL Control Bits */
8578 #define DIR (0x0001) /* USB - Data Response Bit */
8579 //#define RESERVED (0x0002) /* USB - */
8580 //#define RESERVED (0x0004) /* USB - */
8581 //#define RESERVED (0x0008) /* USB - */
8582 #define FRSTE (0x0010) /* USB - Function Reset Connection Enable */
8583 #define RWUP (0x0020) /* USB - Device Remote Wakeup Request */
8584 #define FEN (0x0040) /* USB - Function Enable Bit */
8585 //#define RESERVED (0x0080) /* USB - */
8586 
8587 /* USBIE Control Bits */
8588 #define STPOWIE (0x0001) /* USB - Setup Overwrite Interrupt Enable */
8589 //#define RESERVED (0x0002) /* USB - */
8590 #define SETUPIE (0x0004) /* USB - Setup Interrupt Enable */
8591 //#define RESERVED (0x0008) /* USB - */
8592 //#define RESERVED (0x0010) /* USB - */
8593 #define RESRIE (0x0020) /* USB - Function Resume Request Interrupt Enable */
8594 #define SUSRIE (0x0040) /* USB - Function Suspend Request Interrupt Enable */
8595 #define RSTRIE (0x0080) /* USB - Function Reset Request Interrupt Enable */
8596 
8597 /* USBIFG Control Bits */
8598 #define STPOWIFG (0x0001) /* USB - Setup Overwrite Interrupt Flag */
8599 //#define RESERVED (0x0002) /* USB - */
8600 #define SETUPIFG (0x0004) /* USB - Setup Interrupt Flag */
8601 //#define RESERVED (0x0008) /* USB - */
8602 //#define RESERVED (0x0010) /* USB - */
8603 #define RESRIFG (0x0020) /* USB - Function Resume Request Interrupt Flag */
8604 #define SUSRIFG (0x0040) /* USB - Function Suspend Request Interrupt Flag */
8605 #define RSTRIFG (0x0080) /* USB - Function Reset Request Interrupt Flag */
8606 
8607 //values of USBVECINT when USB-interrupt occured
8608 #define USBVECINT_NONE 0x00
8609 #define USBVECINT_PWR_DROP 0x02
8610 #define USBVECINT_PLL_LOCK 0x04
8611 #define USBVECINT_PLL_SIGNAL 0x06
8612 #define USBVECINT_PLL_RANGE 0x08
8613 #define USBVECINT_PWR_VBUSOn 0x0A
8614 #define USBVECINT_PWR_VBUSOff 0x0C
8615 #define USBVECINT_USB_TIMESTAMP 0x10
8616 #define USBVECINT_INPUT_ENDPOINT0 0x12
8617 #define USBVECINT_OUTPUT_ENDPOINT0 0x14
8618 #define USBVECINT_RSTR 0x16
8619 #define USBVECINT_SUSR 0x18
8620 #define USBVECINT_RESR 0x1A
8621 #define USBVECINT_SETUP_PACKET_RECEIVED 0x20
8622 #define USBVECINT_STPOW_PACKET_RECEIVED 0x22
8623 #define USBVECINT_INPUT_ENDPOINT1 0x24
8624 #define USBVECINT_INPUT_ENDPOINT2 0x26
8625 #define USBVECINT_INPUT_ENDPOINT3 0x28
8626 #define USBVECINT_INPUT_ENDPOINT4 0x2A
8627 #define USBVECINT_INPUT_ENDPOINT5 0x2C
8628 #define USBVECINT_INPUT_ENDPOINT6 0x2E
8629 #define USBVECINT_INPUT_ENDPOINT7 0x30
8630 #define USBVECINT_OUTPUT_ENDPOINT1 0x32
8631 #define USBVECINT_OUTPUT_ENDPOINT2 0x34
8632 #define USBVECINT_OUTPUT_ENDPOINT3 0x36
8633 #define USBVECINT_OUTPUT_ENDPOINT4 0x38
8634 #define USBVECINT_OUTPUT_ENDPOINT5 0x3A
8635 #define USBVECINT_OUTPUT_ENDPOINT6 0x3C
8636 #define USBVECINT_OUTPUT_ENDPOINT7 0x3E
8637 
8638 
8639 /* ========================================================================= */
8640 /* USB Operation Registers */
8641 /* ========================================================================= */
8642 
8643 #define OFS_USBIEPSIZXY_7 (0x23FF) /* Input Endpoint_7: X/Y-buffer size */
8644 #define OFS_USBIEPBCTY_7 (0x23FE) /* Input Endpoint_7: Y-byte count */
8645 #define OFS_USBIEPBBAY_7 (0x23FD) /* Input Endpoint_7: Y-buffer base addr. */
8646 //#define Spare_O (0x23FC) /* Not used */
8647 //#define Spare_O (0x23FB) /* Not used */
8648 #define OFS_USBIEPBCTX_7 (0x23FA) /* Input Endpoint_7: X-byte count */
8649 #define OFS_USBIEPBBAX_7 (0x23F9) /* Input Endpoint_7: X-buffer base addr. */
8650 #define OFS_USBIEPCNF_7 (0x23F8) /* Input Endpoint_7: Configuration */
8651 #define OFS_USBIEPSIZXY_6 (0x23F7) /* Input Endpoint_6: X/Y-buffer size */
8652 #define OFS_USBIEPBCTY_6 (0x23F6) /* Input Endpoint_6: Y-byte count */
8653 #define OFS_USBIEPBBAY_6 (0x23F5) /* Input Endpoint_6: Y-buffer base addr. */
8654 //#define Spare_O (0x23F4) /* Not used */
8655 //#define Spare_O (0x23F3) /* Not used */
8656 #define OFS_USBIEPBCTX_6 (0x23F2) /* Input Endpoint_6: X-byte count */
8657 #define OFS_USBIEPBBAX_6 (0x23F1) /* Input Endpoint_6: X-buffer base addr. */
8658 #define OFS_USBIEPCNF_6 (0x23F0) /* Input Endpoint_6: Configuration */
8659 #define OFS_USBIEPSIZXY_5 (0x23EF) /* Input Endpoint_5: X/Y-buffer size */
8660 #define OFS_USBIEPBCTY_5 (0x23EE) /* Input Endpoint_5: Y-byte count */
8661 #define OFS_USBIEPBBAY_5 (0x23ED) /* Input Endpoint_5: Y-buffer base addr. */
8662 //#define Spare_O (0x23EC) /* Not used */
8663 //#define Spare_O (0x23EB) /* Not used */
8664 #define OFS_USBIEPBCTX_5 (0x23EA) /* Input Endpoint_5: X-byte count */
8665 #define OFS_USBIEPBBAX_5 (0x23E9) /* Input Endpoint_5: X-buffer base addr. */
8666 #define OFS_USBIEPCNF_5 (0x23E8) /* Input Endpoint_5: Configuration */
8667 #define OFS_USBIEPSIZXY_4 (0x23E7) /* Input Endpoint_4: X/Y-buffer size */
8668 #define OFS_USBIEPBCTY_4 (0x23E6) /* Input Endpoint_4: Y-byte count */
8669 #define OFS_USBIEPBBAY_4 (0x23E5) /* Input Endpoint_4: Y-buffer base addr. */
8670 //#define Spare_O (0x23E4) /* Not used */
8671 //#define Spare_O (0x23E3) /* Not used */
8672 #define OFS_USBIEPBCTX_4 (0x23E2) /* Input Endpoint_4: X-byte count */
8673 #define OFS_USBIEPBBAX_4 (0x23E1) /* Input Endpoint_4: X-buffer base addr. */
8674 #define OFS_USBIEPCNF_4 (0x23E0) /* Input Endpoint_4: Configuration */
8675 #define OFS_USBIEPSIZXY_3 (0x23DF) /* Input Endpoint_3: X/Y-buffer size */
8676 #define OFS_USBIEPBCTY_3 (0x23DE) /* Input Endpoint_3: Y-byte count */
8677 #define OFS_USBIEPBBAY_3 (0x23DD) /* Input Endpoint_3: Y-buffer base addr. */
8678 //#define Spare_O (0x23DC) /* Not used */
8679 //#define Spare_O (0x23DB) /* Not used */
8680 #define OFS_USBIEPBCTX_3 (0x23DA) /* Input Endpoint_3: X-byte count */
8681 #define OFS_USBIEPBBAX_3 (0x23D9) /* Input Endpoint_3: X-buffer base addr. */
8682 #define OFS_USBIEPCNF_3 (0x23D8) /* Input Endpoint_3: Configuration */
8683 #define OFS_USBIEPSIZXY_2 (0x23D7) /* Input Endpoint_2: X/Y-buffer size */
8684 #define OFS_USBIEPBCTY_2 (0x23D6) /* Input Endpoint_2: Y-byte count */
8685 #define OFS_USBIEPBBAY_2 (0x23D5) /* Input Endpoint_2: Y-buffer base addr. */
8686 //#define Spare_O (0x23D4) /* Not used */
8687 //#define Spare_O (0x23D3) /* Not used */
8688 #define OFS_USBIEPBCTX_2 (0x23D2) /* Input Endpoint_2: X-byte count */
8689 #define OFS_USBIEPBBAX_2 (0x23D1) /* Input Endpoint_2: X-buffer base addr. */
8690 #define OFS_USBIEPCNF_2 (0x23D0) /* Input Endpoint_2: Configuration */
8691 #define OFS_USBIEPSIZXY_1 (0x23CF) /* Input Endpoint_1: X/Y-buffer size */
8692 #define OFS_USBIEPBCTY_1 (0x23CE) /* Input Endpoint_1: Y-byte count */
8693 #define OFS_USBIEPBBAY_1 (0x23CD) /* Input Endpoint_1: Y-buffer base addr. */
8694 //#define Spare_O (0x23CC) /* Not used */
8695 //#define Spare_O (0x23CB) /* Not used */
8696 #define OFS_USBIEPBCTX_1 (0x23CA) /* Input Endpoint_1: X-byte count */
8697 #define OFS_USBIEPBBAX_1 (0x23C9) /* Input Endpoint_1: X-buffer base addr. */
8698 #define OFS_USBIEPCNF_1 (0x23C8) /* Input Endpoint_1: Configuration */
8699 //#define (0x23C7)_O /* */
8700 //#define RESERVED_O (0x1C00) /* */
8701 //#define (0x23C0)_O /* */
8702 #define OFS_USBOEPSIZXY_7 (0x23BF) /* Output Endpoint_7: X/Y-buffer size */
8703 #define OFS_USBOEPBCTY_7 (0x23BE) /* Output Endpoint_7: Y-byte count */
8704 #define OFS_USBOEPBBAY_7 (0x23BD) /* Output Endpoint_7: Y-buffer base addr. */
8705 //#define Spare_O (0x23BC) /* Not used */
8706 //#define Spare_O (0x23BB) /* Not used */
8707 #define OFS_USBOEPBCTX_7 (0x23BA) /* Output Endpoint_7: X-byte count */
8708 #define OFS_USBOEPBBAX_7 (0x23B9) /* Output Endpoint_7: X-buffer base addr. */
8709 #define OFS_USBOEPCNF_7 (0x23B8) /* Output Endpoint_7: Configuration */
8710 #define OFS_USBOEPSIZXY_6 (0x23B7) /* Output Endpoint_6: X/Y-buffer size */
8711 #define OFS_USBOEPBCTY_6 (0x23B6) /* Output Endpoint_6: Y-byte count */
8712 #define OFS_USBOEPBBAY_6 (0x23B5) /* Output Endpoint_6: Y-buffer base addr. */
8713 //#define Spare_O (0x23B4) /* Not used */
8714 //#define Spare_O (0x23B3) /* Not used */
8715 #define OFS_USBOEPBCTX_6 (0x23B2) /* Output Endpoint_6: X-byte count */
8716 #define OFS_USBOEPBBAX_6 (0x23B1) /* Output Endpoint_6: X-buffer base addr. */
8717 #define OFS_USBOEPCNF_6 (0x23B0) /* Output Endpoint_6: Configuration */
8718 #define OFS_USBOEPSIZXY_5 (0x23AF) /* Output Endpoint_5: X/Y-buffer size */
8719 #define OFS_USBOEPBCTY_5 (0x23AE) /* Output Endpoint_5: Y-byte count */
8720 #define OFS_USBOEPBBAY_5 (0x23AD) /* Output Endpoint_5: Y-buffer base addr. */
8721 //#define Spare_O (0x23AC) /* Not used */
8722 //#define Spare_O (0x23AB) /* Not used */
8723 #define OFS_USBOEPBCTX_5 (0x23AA) /* Output Endpoint_5: X-byte count */
8724 #define OFS_USBOEPBBAX_5 (0x23A9) /* Output Endpoint_5: X-buffer base addr. */
8725 #define OFS_USBOEPCNF_5 (0x23A8) /* Output Endpoint_5: Configuration */
8726 #define OFS_USBOEPSIZXY_4 (0x23A7) /* Output Endpoint_4: X/Y-buffer size */
8727 #define OFS_USBOEPBCTY_4 (0x23A6) /* Output Endpoint_4: Y-byte count */
8728 #define OFS_USBOEPBBAY_4 (0x23A5) /* Output Endpoint_4: Y-buffer base addr. */
8729 //#define Spare_O (0x23A4) /* Not used */
8730 //#define Spare_O (0x23A3) /* Not used */
8731 #define OFS_USBOEPBCTX_4 (0x23A2) /* Output Endpoint_4: X-byte count */
8732 #define OFS_USBOEPBBAX_4 (0x23A1) /* Output Endpoint_4: X-buffer base addr. */
8733 #define OFS_USBOEPCNF_4 (0x23A0) /* Output Endpoint_4: Configuration */
8734 #define OFS_USBOEPSIZXY_3 (0x239F) /* Output Endpoint_3: X/Y-buffer size */
8735 #define OFS_USBOEPBCTY_3 (0x239E) /* Output Endpoint_3: Y-byte count */
8736 #define OFS_USBOEPBBAY_3 (0x239D) /* Output Endpoint_3: Y-buffer base addr. */
8737 //#define Spare_O (0x239C) /* Not used */
8738 //#define Spare_O (0x239B) /* Not used */
8739 #define OFS_USBOEPBCTX_3 (0x239A) /* Output Endpoint_3: X-byte count */
8740 #define OFS_USBOEPBBAX_3 (0x2399) /* Output Endpoint_3: X-buffer base addr. */
8741 #define OFS_USBOEPCNF_3 (0x2398) /* Output Endpoint_3: Configuration */
8742 #define OFS_USBOEPSIZXY_2 (0x2397) /* Output Endpoint_2: X/Y-buffer size */
8743 #define OFS_USBOEPBCTY_2 (0x2396) /* Output Endpoint_2: Y-byte count */
8744 #define OFS_USBOEPBBAY_2 (0x2395) /* Output Endpoint_2: Y-buffer base addr. */
8745 //#define Spare_O (0x2394) /* Not used */
8746 //#define Spare_O (0x2393) /* Not used */
8747 #define OFS_USBOEPBCTX_2 (0x2392) /* Output Endpoint_2: X-byte count */
8748 #define OFS_USBOEPBBAX_2 (0x2391) /* Output Endpoint_2: X-buffer base addr. */
8749 #define OFS_USBOEPCNF_2 (0x2390) /* Output Endpoint_2: Configuration */
8750 #define OFS_USBOEPSIZXY_1 (0x238F) /* Output Endpoint_1: X/Y-buffer size */
8751 #define OFS_USBOEPBCTY_1 (0x238E) /* Output Endpoint_1: Y-byte count */
8752 #define OFS_USBOEPBBAY_1 (0x238D) /* Output Endpoint_1: Y-buffer base addr. */
8753 //#define Spare_O (0x238C) /* Not used */
8754 //#define Spare_O (0x238B) /* Not used */
8755 #define OFS_USBOEPBCTX_1 (0x238A) /* Output Endpoint_1: X-byte count */
8756 #define OFS_USBOEPBBAX_1 (0x2389) /* Output Endpoint_1: X-buffer base addr. */
8757 #define OFS_USBOEPCNF_1 (0x2388) /* Output Endpoint_1: Configuration */
8758 #define OFS_USBSUBLK (0x2380) /* Setup Packet Block */
8759 #define OFS_USBIEP0BUF (0x2378) /* Input endpoint_0 buffer */
8760 #define OFS_USBOEP0BUF (0x2370) /* Output endpoint_0 buffer */
8761 #define OFS_USBTOPBUFF (0x236F) /* Top of buffer space */
8762 // (1904 Bytes) /* Buffer space */
8763 #define OFS_USBSTABUFF (0x1C00) /* Start of buffer space */
8764 
8765 /* USBIEPCNF_n Control Bits */
8766 /* USBOEPCNF_n Control Bits */
8767 //#define RESERVED (0x0001) /* USB - */
8768 //#define RESERVED (0x0001) /* USB - */
8769 #define DBUF (0x0010) /* USB - Double Buffer Enable */
8770 //#define RESERVED (0x0040) /* USB - */
8771 
8772 /* USBIEPBCNT_n Control Bits */
8773 /* USBOEPBCNT_n Control Bits */
8774 #define CNT4 (0x0010) /* USB - Byte Count Bit 3 */
8775 #define CNT5 (0x0020) /* USB - Byte Count Bit 3 */
8776 #define CNT6 (0x0040) /* USB - Byte Count Bit 3 */
8777 #endif
8778 /************************************************************
8779 * USCI Ax
8780 ************************************************************/
8781 #ifdef __MSP430_HAS_USCI_Ax__ /* Definition to show that Module is available */
8782 
8783 #define OFS_UCAxCTLW0 (0x0000) /* USCI Ax Control Word Register 0 */
8784 #define OFS_UCAxCTLW0_L OFS_UCAxCTLW0
8785 #define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1
8786 #define OFS_UCAxCTL0 (0x0001)
8787 #define OFS_UCAxCTL1 (0x0000)
8788 #define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */
8789 #define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */
8790 #define OFS_UCAxBRW (0x0006) /* USCI Ax Baud Word Rate 0 */
8791 #define OFS_UCAxBRW_L OFS_UCAxBRW
8792 #define OFS_UCAxBRW_H OFS_UCAxBRW+1
8793 #define OFS_UCAxBR0 (0x0006)
8794 #define OFS_UCAxBR1 (0x0007)
8795 #define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */
8796 #define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */
8797 #define OFS_UCAxMCTL (0x0008) /* USCI Ax Modulation Control */
8798 #define OFS_UCAxSTAT (0x000A) /* USCI Ax Status Register */
8799 #define OFS_UCAxRXBUF (0x000C) /* USCI Ax Receive Buffer */
8800 #define OFS_UCAxTXBUF (0x000E) /* USCI Ax Transmit Buffer */
8801 #define OFS_UCAxABCTL (0x0010) /* USCI Ax LIN Control */
8802 #define OFS_UCAxIRCTL (0x0012) /* USCI Ax IrDA Transmit Control */
8803 #define OFS_UCAxIRCTL_L OFS_UCAxIRCTL
8804 #define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1
8805 #define OFS_UCAxIRTCTL (0x0012)
8806 #define OFS_UCAxIRRCTL (0x0013)
8807 #define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */
8808 #define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */
8809 #define OFS_UCAxICTL (0x001C) /* USCI Ax Interrupt Enable Register */
8810 #define OFS_UCAxICTL_L OFS_UCAxICTL
8811 #define OFS_UCAxICTL_H OFS_UCAxICTL+1
8812 #define OFS_UCAxIE (0x001C)
8813 #define OFS_UCAxIFG (0x001D)
8814 #define UCAxIE UCAxICTL_L /* USCI Ax Interrupt Enable Register */
8815 #define UCAxIFG UCAxICTL_H /* USCI Ax Interrupt Flags Register */
8816 #define OFS_UCAxIV (0x001E) /* USCI Ax Interrupt Vector Register */
8817 
8818 #define OFS_UCAxCTLW0__SPI (0x0000)
8819 #define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI
8820 #define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1
8821 #define OFS_UCAxCTL0__SPI (0x0001)
8822 #define OFS_UCAxCTL1__SPI (0x0000)
8823 #define OFS_UCAxBRW__SPI (0x0006)
8824 #define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI
8825 #define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1
8826 #define OFS_UCAxBR0__SPI (0x0006)
8827 #define OFS_UCAxBR1__SPI (0x0007)
8828 #define OFS_UCAxMCTL__SPI (0x0008)
8829 #define OFS_UCAxSTAT__SPI (0x000A)
8830 #define OFS_UCAxRXBUF__SPI (0x000C)
8831 #define OFS_UCAxTXBUF__SPI (0x000E)
8832 #define OFS_UCAxICTL__SPI (0x001C)
8833 #define OFS_UCAxICTL__SPI_L OFS_UCAxICTL__SPI
8834 #define OFS_UCAxICTL__SPI_H OFS_UCAxICTL__SPI+1
8835 #define OFS_UCAxIE__SPI (0x001C)
8836 #define OFS_UCAxIFG__SPI (0x001D)
8837 #define OFS_UCAxIV__SPI (0x001E)
8838 
8839 #endif
8840 /************************************************************
8841 * USCI Bx
8842 ************************************************************/
8843 #ifdef __MSP430_HAS_USCI_Bx__ /* Definition to show that Module is available */
8844 
8845 #define OFS_UCBxCTLW0__SPI (0x0000)
8846 #define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI
8847 #define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1
8848 #define OFS_UCBxCTL0__SPI (0x0001)
8849 #define OFS_UCBxCTL1__SPI (0x0000)
8850 #define OFS_UCBxBRW__SPI (0x0006)
8851 #define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI
8852 #define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1
8853 #define OFS_UCBxBR0__SPI (0x0006)
8854 #define OFS_UCBxBR1__SPI (0x0007)
8855 #define OFS_UCBxSTAT__SPI (0x000A)
8856 #define OFS_UCBxRXBUF__SPI (0x000C)
8857 #define OFS_UCBxTXBUF__SPI (0x000E)
8858 #define OFS_UCBxICTL__SPI (0x001C)
8859 #define OFS_UCBxICTL__SPI_L OFS_UCBxICTL__SPI
8860 #define OFS_UCBxICTL__SPI_H OFS_UCBxICTL__SPI+1
8861 #define OFS_UCBxIE__SPI (0x001C)
8862 #define OFS_UCBxIFG__SPI (0x001D)
8863 #define OFS_UCBxIV__SPI (0x001E)
8864 
8865 #define OFS_UCBxCTLW0 (0x0000) /* USCI Bx Control Word Register 0 */
8866 #define OFS_UCBxCTLW0_L OFS_UCBxCTLW0
8867 #define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1
8868 #define OFS_UCBxCTL0 (0x0001)
8869 #define OFS_UCBxCTL1 (0x0000)
8870 #define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */
8871 #define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */
8872 #define OFS_UCBxBRW (0x0006) /* USCI Bx Baud Word Rate 0 */
8873 #define OFS_UCBxBRW_L OFS_UCBxBRW
8874 #define OFS_UCBxBRW_H OFS_UCBxBRW+1
8875 #define OFS_UCBxBR0 (0x0006)
8876 #define OFS_UCBxBR1 (0x0007)
8877 #define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */
8878 #define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */
8879 #define OFS_UCBxSTAT (0x000A) /* USCI Bx Status Register */
8880 #define OFS_UCBxRXBUF (0x000C) /* USCI Bx Receive Buffer */
8881 #define OFS_UCBxTXBUF (0x000E) /* USCI Bx Transmit Buffer */
8882 #define OFS_UCBxI2COA (0x0010) /* USCI Bx I2C Own Address */
8883 #define OFS_UCBxI2COA_L OFS_UCBxI2COA
8884 #define OFS_UCBxI2COA_H OFS_UCBxI2COA+1
8885 #define OFS_UCBxI2CSA (0x0012) /* USCI Bx I2C Slave Address */
8886 #define OFS_UCBxI2CSA_L OFS_UCBxI2CSA
8887 #define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1
8888 #define OFS_UCBxICTL (0x001C) /* USCI Bx Interrupt Enable Register */
8889 #define OFS_UCBxICTL_L OFS_UCBxICTL
8890 #define OFS_UCBxICTL_H OFS_UCBxICTL+1
8891 #define OFS_UCBxIE (0x001C)
8892 #define OFS_UCBxIFG (0x001D)
8893 #define UCBxIE UCBxICTL_L /* USCI Bx Interrupt Enable Register */
8894 #define UCBxIFG UCBxICTL_H /* USCI Bx Interrupt Flags Register */
8895 #define OFS_UCBxIV (0x001E) /* USCI Bx Interrupt Vector Register */
8896 
8897 #endif
8898 #if (defined(__MSP430_HAS_USCI_Ax__) || defined(__MSP430_HAS_USCI_Bx__))
8899 
8900 // UCAxCTL0 UART-Mode Control Bits
8901 #define UCPEN (0x80) /* Async. Mode: Parity enable */
8902 #define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
8903 #define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
8904 #define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
8905 #define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
8906 #define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
8907 #define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
8908 #define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
8909 
8910 // UCxxCTL0 SPI-Mode Control Bits
8911 #define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
8912 #define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
8913 #define UCMST (0x08) /* Sync. Mode: Master Select */
8914 
8915 // UCBxCTL0 I2C-Mode Control Bits
8916 #define UCA10 (0x80) /* 10-bit Address Mode */
8917 #define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
8918 #define UCMM (0x20) /* Multi-Master Environment */
8919 //#define res (0x10) /* reserved */
8920 #define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
8921 #define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
8922 #define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
8923 #define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
8924 
8925 // UCAxCTL1 UART-Mode Control Bits
8926 #define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
8927 #define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
8928 #define UCRXEIE (0x20) /* RX Error interrupt enable */
8929 #define UCBRKIE (0x10) /* Break interrupt enable */
8930 #define UCDORM (0x08) /* Dormant (Sleep) Mode */
8931 #define UCTXADDR (0x04) /* Send next Data as Address */
8932 #define UCTXBRK (0x02) /* Send next Data as Break */
8933 #define UCSWRST (0x01) /* USCI Software Reset */
8934 
8935 // UCxxCTL1 SPI-Mode Control Bits
8936 //#define res (0x20) /* reserved */
8937 //#define res (0x10) /* reserved */
8938 //#define res (0x08) /* reserved */
8939 //#define res (0x04) /* reserved */
8940 //#define res (0x02) /* reserved */
8941 
8942 // UCBxCTL1 I2C-Mode Control Bits
8943 //#define res (0x20) /* reserved */
8944 #define UCTR (0x10) /* Transmit/Receive Select/Flag */
8945 #define UCTXNACK (0x08) /* Transmit NACK */
8946 #define UCTXSTP (0x04) /* Transmit STOP */
8947 #define UCTXSTT (0x02) /* Transmit START */
8948 #define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
8949 #define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
8950 #define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
8951 #define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
8952 #define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */
8953 #define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */
8954 #define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */
8955 
8956 /* UCAxMCTL Control Bits */
8957 #define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
8958 #define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
8959 #define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
8960 #define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
8961 #define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
8962 #define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
8963 #define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
8964 #define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
8965 
8966 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
8967 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
8968 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
8969 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
8970 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
8971 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
8972 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
8973 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
8974 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
8975 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
8976 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
8977 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
8978 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
8979 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
8980 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
8981 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
8982 
8983 #define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
8984 #define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
8985 #define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
8986 #define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
8987 #define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
8988 #define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
8989 #define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
8990 #define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
8991 
8992 /* UCAxSTAT Control Bits */
8993 #define UCLISTEN (0x80) /* USCI Listen mode */
8994 #define UCFE (0x40) /* USCI Frame Error Flag */
8995 #define UCOE (0x20) /* USCI Overrun Error Flag */
8996 #define UCPE (0x10) /* USCI Parity Error Flag */
8997 #define UCBRK (0x08) /* USCI Break received */
8998 #define UCRXERR (0x04) /* USCI RX Error Flag */
8999 #define UCADDR (0x02) /* USCI Address received Flag */
9000 #define UCBUSY (0x01) /* USCI Busy Flag */
9001 #define UCIDLE (0x02) /* USCI Idle line detected Flag */
9002 
9003 /* UCBxSTAT Control Bits */
9004 #define UCSCLLOW (0x40) /* SCL low */
9005 #define UCGC (0x20) /* General Call address received Flag */
9006 #define UCBBUSY (0x10) /* Bus Busy Flag */
9007 
9008 /* UCAxIRTCTL Control Bits */
9009 #define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
9010 #define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
9011 #define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
9012 #define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
9013 #define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
9014 #define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
9015 #define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
9016 #define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
9017 
9018 /* UCAxIRRCTL Control Bits */
9019 #define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
9020 #define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
9021 #define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
9022 #define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
9023 #define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
9024 #define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
9025 #define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
9026 #define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
9027 
9028 /* UCAxABCTL Control Bits */
9029 //#define res (0x80) /* reserved */
9030 //#define res (0x40) /* reserved */
9031 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
9032 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
9033 #define UCSTOE (0x08) /* Sync-Field Timeout error */
9034 #define UCBTOE (0x04) /* Break Timeout error */
9035 //#define res (0x02) /* reserved */
9036 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */
9037 
9038 /* UCBxI2COA Control Bits */
9039 #define UCGCEN (0x8000) /* I2C General Call enable */
9040 #define UCOA9 (0x0200) /* I2C Own Address 9 */
9041 #define UCOA8 (0x0100) /* I2C Own Address 8 */
9042 #define UCOA7 (0x0080) /* I2C Own Address 7 */
9043 #define UCOA6 (0x0040) /* I2C Own Address 6 */
9044 #define UCOA5 (0x0020) /* I2C Own Address 5 */
9045 #define UCOA4 (0x0010) /* I2C Own Address 4 */
9046 #define UCOA3 (0x0008) /* I2C Own Address 3 */
9047 #define UCOA2 (0x0004) /* I2C Own Address 2 */
9048 #define UCOA1 (0x0002) /* I2C Own Address 1 */
9049 #define UCOA0 (0x0001) /* I2C Own Address 0 */
9050 
9051 /* UCBxI2COA Control Bits */
9052 #define UCOA7_L (0x0080) /* I2C Own Address 7 */
9053 #define UCOA6_L (0x0040) /* I2C Own Address 6 */
9054 #define UCOA5_L (0x0020) /* I2C Own Address 5 */
9055 #define UCOA4_L (0x0010) /* I2C Own Address 4 */
9056 #define UCOA3_L (0x0008) /* I2C Own Address 3 */
9057 #define UCOA2_L (0x0004) /* I2C Own Address 2 */
9058 #define UCOA1_L (0x0002) /* I2C Own Address 1 */
9059 #define UCOA0_L (0x0001) /* I2C Own Address 0 */
9060 
9061 /* UCBxI2COA Control Bits */
9062 #define UCGCEN_H (0x0080) /* I2C General Call enable */
9063 #define UCOA9_H (0x0002) /* I2C Own Address 9 */
9064 #define UCOA8_H (0x0001) /* I2C Own Address 8 */
9065 
9066 /* UCBxI2CSA Control Bits */
9067 #define UCSA9 (0x0200) /* I2C Slave Address 9 */
9068 #define UCSA8 (0x0100) /* I2C Slave Address 8 */
9069 #define UCSA7 (0x0080) /* I2C Slave Address 7 */
9070 #define UCSA6 (0x0040) /* I2C Slave Address 6 */
9071 #define UCSA5 (0x0020) /* I2C Slave Address 5 */
9072 #define UCSA4 (0x0010) /* I2C Slave Address 4 */
9073 #define UCSA3 (0x0008) /* I2C Slave Address 3 */
9074 #define UCSA2 (0x0004) /* I2C Slave Address 2 */
9075 #define UCSA1 (0x0002) /* I2C Slave Address 1 */
9076 #define UCSA0 (0x0001) /* I2C Slave Address 0 */
9077 
9078 /* UCBxI2CSA Control Bits */
9079 #define UCSA7_L (0x0080) /* I2C Slave Address 7 */
9080 #define UCSA6_L (0x0040) /* I2C Slave Address 6 */
9081 #define UCSA5_L (0x0020) /* I2C Slave Address 5 */
9082 #define UCSA4_L (0x0010) /* I2C Slave Address 4 */
9083 #define UCSA3_L (0x0008) /* I2C Slave Address 3 */
9084 #define UCSA2_L (0x0004) /* I2C Slave Address 2 */
9085 #define UCSA1_L (0x0002) /* I2C Slave Address 1 */
9086 #define UCSA0_L (0x0001) /* I2C Slave Address 0 */
9087 
9088 /* UCBxI2CSA Control Bits */
9089 #define UCSA9_H (0x0002) /* I2C Slave Address 9 */
9090 #define UCSA8_H (0x0001) /* I2C Slave Address 8 */
9091 
9092 /* UCAxIE Control Bits */
9093 #define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */
9094 #define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */
9095 
9096 /* UCAxIE Control Bits */
9097 #define UCTXIE_L (0x0002) /* USCI Transmit Interrupt Enable */
9098 #define UCRXIE_L (0x0001) /* USCI Receive Interrupt Enable */
9099 
9100 /* UCBxIE Control Bits */
9101 #define UCNACKIE (0x0020) /* NACK Condition interrupt enable */
9102 #define UCALIE (0x0010) /* Arbitration Lost interrupt enable */
9103 #define UCSTPIE (0x0008) /* STOP Condition interrupt enable */
9104 #define UCSTTIE (0x0004) /* START Condition interrupt enable */
9105 #define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */
9106 #define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */
9107 
9108 /* UCBxIE Control Bits */
9109 #define UCNACKIE_L (0x0020) /* NACK Condition interrupt enable */
9110 #define UCALIE_L (0x0010) /* Arbitration Lost interrupt enable */
9111 #define UCSTPIE_L (0x0008) /* STOP Condition interrupt enable */
9112 #define UCSTTIE_L (0x0004) /* START Condition interrupt enable */
9113 #define UCTXIE_L (0x0002) /* USCI Transmit Interrupt Enable */
9114 #define UCRXIE_L (0x0001) /* USCI Receive Interrupt Enable */
9115 
9116 /* UCAxIFG Control Bits */
9117 #define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */
9118 #define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */
9119 
9120 /* UCAxIFG Control Bits */
9121 #define UCTXIFG_L (0x0002) /* USCI Transmit Interrupt Flag */
9122 #define UCRXIFG_L (0x0001) /* USCI Receive Interrupt Flag */
9123 
9124 /* UCBxIFG Control Bits */
9125 #define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */
9126 #define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */
9127 #define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */
9128 #define UCSTTIFG (0x0004) /* START Condition interrupt Flag */
9129 #define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */
9130 #define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */
9131 
9132 /* UCBxIFG Control Bits */
9133 #define UCNACKIFG_L (0x0020) /* NAK Condition interrupt Flag */
9134 #define UCALIFG_L (0x0010) /* Arbitration Lost interrupt Flag */
9135 #define UCSTPIFG_L (0x0008) /* STOP Condition interrupt Flag */
9136 #define UCSTTIFG_L (0x0004) /* START Condition interrupt Flag */
9137 #define UCTXIFG_L (0x0002) /* USCI Transmit Interrupt Flag */
9138 #define UCRXIFG_L (0x0001) /* USCI Receive Interrupt Flag */
9139 
9140 /* USCI Definitions */
9141 #define USCI_NONE (0x0000) /* No Interrupt pending */
9142 #define USCI_UCRXIFG (0x0002) /* USCI UCRXIFG */
9143 #define USCI_UCTXIFG (0x0004) /* USCI UCTXIFG */
9144 #define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */
9145 #define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */
9146 #define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/
9147 #define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/
9148 #define USCI_I2C_UCRXIFG (0x000A) /* USCI I2C Mode: UCRXIFG */
9149 #define USCI_I2C_UCTXIFG (0x000C) /* USCI I2C Mode: UCTXIFG */
9150 
9151 #endif
9152 /************************************************************
9153 * USCI Ax
9154 ************************************************************/
9155 #ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */
9156 
9157 #define OFS_UCAxCTLW0 (0x0000) /* USCI Ax Control Word Register 0 */
9158 #define OFS_UCAxCTLW0_L OFS_UCAxCTLW0
9159 #define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1
9160 #define OFS_UCAxCTL0 (0x0001)
9161 #define OFS_UCAxCTL1 (0x0000)
9162 #define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */
9163 #define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */
9164 #define OFS_UCAxCTLW1 (0x0002) /* USCI Ax Control Word Register 1 */
9165 #define OFS_UCAxCTLW1_L OFS_UCAxCTLW1
9166 #define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1
9167 #define OFS_UCAxBRW (0x0006) /* USCI Ax Baud Word Rate 0 */
9168 #define OFS_UCAxBRW_L OFS_UCAxBRW
9169 #define OFS_UCAxBRW_H OFS_UCAxBRW+1
9170 #define OFS_UCAxBR0 (0x0006)
9171 #define OFS_UCAxBR1 (0x0007)
9172 #define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */
9173 #define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */
9174 #define OFS_UCAxMCTLW (0x0008) /* USCI Ax Modulation Control */
9175 #define OFS_UCAxMCTLW_L OFS_UCAxMCTLW
9176 #define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1
9177 #define OFS_UCAxSTATW (0x000A) /* USCI Ax Status Register */
9178 #define OFS_UCAxRXBUF (0x000C) /* USCI Ax Receive Buffer */
9179 #define OFS_UCAxRXBUF_L OFS_UCAxRXBUF
9180 #define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1
9181 #define OFS_UCAxTXBUF (0x000E) /* USCI Ax Transmit Buffer */
9182 #define OFS_UCAxTXBUF_L OFS_UCAxTXBUF
9183 #define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1
9184 #define OFS_UCAxABCTL (0x0010) /* USCI Ax LIN Control */
9185 #define OFS_UCAxIRCTL (0x0012) /* USCI Ax IrDA Transmit Control */
9186 #define OFS_UCAxIRCTL_L OFS_UCAxIRCTL
9187 #define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1
9188 #define OFS_UCAxIRTCTL (0x0012)
9189 #define OFS_UCAxIRRCTL (0x0013)
9190 #define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */
9191 #define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */
9192 #define OFS_UCAxIE (0x001A) /* USCI Ax Interrupt Enable Register */
9193 #define OFS_UCAxIE_L OFS_UCAxIE
9194 #define OFS_UCAxIE_H OFS_UCAxIE+1
9195 #define OFS_UCAxIFG (0x001C) /* USCI Ax Interrupt Flags Register */
9196 #define OFS_UCAxIFG_L OFS_UCAxIFG
9197 #define OFS_UCAxIFG_H OFS_UCAxIFG+1
9198 #define OFS_UCAxIE__UART (0x001A)
9199 #define OFS_UCAxIE__UART_L OFS_UCAxIE__UART
9200 #define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1
9201 #define OFS_UCAxIFG__UART (0x001C)
9202 #define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART
9203 #define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1
9204 #define OFS_UCAxIV (0x001E) /* USCI Ax Interrupt Vector Register */
9205 
9206 #define OFS_UCAxCTLW0__SPI (0x0000)
9207 #define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI
9208 #define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1
9209 #define OFS_UCAxCTL0__SPI (0x0001)
9210 #define OFS_UCAxCTL1__SPI (0x0000)
9211 #define OFS_UCAxBRW__SPI (0x0006)
9212 #define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI
9213 #define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1
9214 #define OFS_UCAxBR0__SPI (0x0006)
9215 #define OFS_UCAxBR1__SPI (0x0007)
9216 #define OFS_UCAxSTATW__SPI (0x000A)
9217 #define OFS_UCAxRXBUF__SPI (0x000C)
9218 #define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI
9219 #define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1
9220 #define OFS_UCAxTXBUF__SPI (0x000E)
9221 #define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI
9222 #define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1
9223 #define OFS_UCAxIE__SPI (0x001A)
9224 #define OFS_UCAxIFG__SPI (0x001C)
9225 #define OFS_UCAxIV__SPI (0x001E)
9226 
9227 #endif
9228 /************************************************************
9229 * USCI Bx
9230 ************************************************************/
9231 #ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */
9232 
9233 #define OFS_UCBxCTLW0__SPI (0x0000)
9234 #define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI
9235 #define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1
9236 #define OFS_UCBxCTL0__SPI (0x0001)
9237 #define OFS_UCBxCTL1__SPI (0x0000)
9238 #define OFS_UCBxBRW__SPI (0x0006)
9239 #define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI
9240 #define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1
9241 #define OFS_UCBxBR0__SPI (0x0006)
9242 #define OFS_UCBxBR1__SPI (0x0007)
9243 #define OFS_UCBxSTATW__SPI (0x0008)
9244 #define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI
9245 #define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1
9246 #define OFS_UCBxRXBUF__SPI (0x000C)
9247 #define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI
9248 #define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1
9249 #define OFS_UCBxTXBUF__SPI (0x000E)
9250 #define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI
9251 #define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1
9252 #define OFS_UCBxIE__SPI (0x002A)
9253 #define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI
9254 #define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1
9255 #define OFS_UCBxIFG__SPI (0x002C)
9256 #define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI
9257 #define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1
9258 #define OFS_UCBxIV__SPI (0x002E)
9259 
9260 #define OFS_UCBxCTLW0 (0x0000) /* USCI Bx Control Word Register 0 */
9261 #define OFS_UCBxCTLW0_L OFS_UCBxCTLW0
9262 #define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1
9263 #define OFS_UCBxCTL0 (0x0001)
9264 #define OFS_UCBxCTL1 (0x0000)
9265 #define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */
9266 #define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */
9267 #define OFS_UCBxCTLW1 (0x0002) /* USCI Bx Control Word Register 1 */
9268 #define OFS_UCBxCTLW1_L OFS_UCBxCTLW1
9269 #define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1
9270 #define OFS_UCBxBRW (0x0006) /* USCI Bx Baud Word Rate 0 */
9271 #define OFS_UCBxBRW_L OFS_UCBxBRW
9272 #define OFS_UCBxBRW_H OFS_UCBxBRW+1
9273 #define OFS_UCBxBR0 (0x0006)
9274 #define OFS_UCBxBR1 (0x0007)
9275 #define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */
9276 #define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */
9277 #define OFS_UCBxSTATW (0x0008) /* USCI Bx Status Word Register */
9278 #define OFS_UCBxSTATW_L OFS_UCBxSTATW
9279 #define OFS_UCBxSTATW_H OFS_UCBxSTATW+1
9280 #define OFS_UCBxSTATW__I2C (0x0008)
9281 #define OFS_UCBxSTAT__I2C (0x0008)
9282 #define OFS_UCBxBCNT__I2C (0x0009)
9283 #define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */
9284 #define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */
9285 #define OFS_UCBxTBCNT (0x000A) /* USCI Bx Byte Counter Threshold Register */
9286 #define OFS_UCBxTBCNT_L OFS_UCBxTBCNT
9287 #define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1
9288 #define OFS_UCBxRXBUF (0x000C) /* USCI Bx Receive Buffer */
9289 #define OFS_UCBxRXBUF_L OFS_UCBxRXBUF
9290 #define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1
9291 #define OFS_UCBxTXBUF (0x000E) /* USCI Bx Transmit Buffer */
9292 #define OFS_UCBxTXBUF_L OFS_UCBxTXBUF
9293 #define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1
9294 #define OFS_UCBxI2COA0 (0x0014) /* USCI Bx I2C Own Address 0 */
9295 #define OFS_UCBxI2COA0_L OFS_UCBxI2COA0
9296 #define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1
9297 #define OFS_UCBxI2COA1 (0x0016) /* USCI Bx I2C Own Address 1 */
9298 #define OFS_UCBxI2COA1_L OFS_UCBxI2COA1
9299 #define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1
9300 #define OFS_UCBxI2COA2 (0x0018) /* USCI Bx I2C Own Address 2 */
9301 #define OFS_UCBxI2COA2_L OFS_UCBxI2COA2
9302 #define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1
9303 #define OFS_UCBxI2COA3 (0x001A) /* USCI Bx I2C Own Address 3 */
9304 #define OFS_UCBxI2COA3_L OFS_UCBxI2COA3
9305 #define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1
9306 #define OFS_UCBxADDRX (0x001C) /* USCI Bx Received Address Register */
9307 #define OFS_UCBxADDRX_L OFS_UCBxADDRX
9308 #define OFS_UCBxADDRX_H OFS_UCBxADDRX+1
9309 #define OFS_UCBxADDMASK (0x001E) /* USCI Bx Address Mask Register */
9310 #define OFS_UCBxADDMASK_L OFS_UCBxADDMASK
9311 #define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1
9312 #define OFS_UCBxI2CSA (0x0020) /* USCI Bx I2C Slave Address */
9313 #define OFS_UCBxI2CSA_L OFS_UCBxI2CSA
9314 #define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1
9315 #define OFS_UCBxIE (0x002A) /* USCI Bx Interrupt Enable Register */
9316 #define OFS_UCBxIE_L OFS_UCBxIE
9317 #define OFS_UCBxIE_H OFS_UCBxIE+1
9318 #define OFS_UCBxIFG (0x002C) /* USCI Bx Interrupt Flags Register */
9319 #define OFS_UCBxIFG_L OFS_UCBxIFG
9320 #define OFS_UCBxIFG_H OFS_UCBxIFG+1
9321 #define OFS_UCBxIE__I2C (0x002A)
9322 #define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C
9323 #define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1
9324 #define OFS_UCBxIFG__I2C (0x002C)
9325 #define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C
9326 #define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1
9327 #define OFS_UCBxIV (0x002E) /* USCI Bx Interrupt Vector Register */
9328 
9329 #endif
9330 #if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__))
9331 
9332 // UCAxCTLW0 UART-Mode Control Bits
9333 #define UCPEN (0x8000) /* Async. Mode: Parity enable */
9334 #define UCPAR (0x4000) /* Async. Mode: Parity 0:odd / 1:even */
9335 #define UCMSB (0x2000) /* Async. Mode: MSB first 0:LSB / 1:MSB */
9336 #define UC7BIT (0x1000) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
9337 #define UCSPB (0x0800) /* Async. Mode: Stop Bits 0:one / 1: two */
9338 #define UCMODE1 (0x0400) /* Async. Mode: USCI Mode 1 */
9339 #define UCMODE0 (0x0200) /* Async. Mode: USCI Mode 0 */
9340 #define UCSYNC (0x0100) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
9341 #define UCSSEL1 (0x0080) /* USCI 0 Clock Source Select 1 */
9342 #define UCSSEL0 (0x0040) /* USCI 0 Clock Source Select 0 */
9343 #define UCRXEIE (0x0020) /* RX Error interrupt enable */
9344 #define UCBRKIE (0x0010) /* Break interrupt enable */
9345 #define UCDORM (0x0008) /* Dormant (Sleep) Mode */
9346 #define UCTXADDR (0x0004) /* Send next Data as Address */
9347 #define UCTXBRK (0x0002) /* Send next Data as Break */
9348 #define UCSWRST (0x0001) /* USCI Software Reset */
9349 
9350 // UCAxCTLW0 UART-Mode Control Bits
9351 #define UCSSEL1_L (0x0080) /* USCI 0 Clock Source Select 1 */
9352 #define UCSSEL0_L (0x0040) /* USCI 0 Clock Source Select 0 */
9353 #define UCRXEIE_L (0x0020) /* RX Error interrupt enable */
9354 #define UCBRKIE_L (0x0010) /* Break interrupt enable */
9355 #define UCDORM_L (0x0008) /* Dormant (Sleep) Mode */
9356 #define UCTXADDR_L (0x0004) /* Send next Data as Address */
9357 #define UCTXBRK_L (0x0002) /* Send next Data as Break */
9358 #define UCSWRST_L (0x0001) /* USCI Software Reset */
9359 
9360 // UCAxCTLW0 UART-Mode Control Bits
9361 #define UCPEN_H (0x0080) /* Async. Mode: Parity enable */
9362 #define UCPAR_H (0x0040) /* Async. Mode: Parity 0:odd / 1:even */
9363 #define UCMSB_H (0x0020) /* Async. Mode: MSB first 0:LSB / 1:MSB */
9364 #define UC7BIT_H (0x0010) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
9365 #define UCSPB_H (0x0008) /* Async. Mode: Stop Bits 0:one / 1: two */
9366 #define UCMODE1_H (0x0004) /* Async. Mode: USCI Mode 1 */
9367 #define UCMODE0_H (0x0002) /* Async. Mode: USCI Mode 0 */
9368 #define UCSYNC_H (0x0001) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
9369 
9370 // UCxxCTLW0 SPI-Mode Control Bits
9371 #define UCCKPH (0x8000) /* Sync. Mode: Clock Phase */
9372 #define UCCKPL (0x4000) /* Sync. Mode: Clock Polarity */
9373 #define UCMST (0x0800) /* Sync. Mode: Master Select */
9374 //#define res (0x0020) /* reserved */
9375 //#define res (0x0010) /* reserved */
9376 //#define res (0x0008) /* reserved */
9377 //#define res (0x0004) /* reserved */
9378 #define UCSTEM (0x0002) /* USCI STE Mode */
9379 
9380 // UCBxCTLW0 I2C-Mode Control Bits
9381 #define UCA10 (0x8000) /* 10-bit Address Mode */
9382 #define UCSLA10 (0x4000) /* 10-bit Slave Address Mode */
9383 #define UCMM (0x2000) /* Multi-Master Environment */
9384 //#define res (0x1000) /* reserved */
9385 //#define res (0x0100) /* reserved */
9386 #define UCTXACK (0x0020) /* Transmit ACK */
9387 #define UCTR (0x0010) /* Transmit/Receive Select/Flag */
9388 #define UCTXNACK (0x0008) /* Transmit NACK */
9389 #define UCTXSTP (0x0004) /* Transmit STOP */
9390 #define UCTXSTT (0x0002) /* Transmit START */
9391 
9392 // UCBxCTLW0 I2C-Mode Control Bits
9393 //#define res (0x1000) /* reserved */
9394 //#define res (0x0100) /* reserved */
9395 #define UCTXACK_L (0x0020) /* Transmit ACK */
9396 #define UCTR_L (0x0010) /* Transmit/Receive Select/Flag */
9397 #define UCTXNACK_L (0x0008) /* Transmit NACK */
9398 #define UCTXSTP_L (0x0004) /* Transmit STOP */
9399 #define UCTXSTT_L (0x0002) /* Transmit START */
9400 
9401 // UCBxCTLW0 I2C-Mode Control Bits
9402 #define UCA10_H (0x0080) /* 10-bit Address Mode */
9403 #define UCSLA10_H (0x0040) /* 10-bit Slave Address Mode */
9404 #define UCMM_H (0x0020) /* Multi-Master Environment */
9405 //#define res (0x1000) /* reserved */
9406 //#define res (0x0100) /* reserved */
9407 
9408 #define UCMODE_0 (0x0000) /* Sync. Mode: USCI Mode: 0 */
9409 #define UCMODE_1 (0x0200) /* Sync. Mode: USCI Mode: 1 */
9410 #define UCMODE_2 (0x0400) /* Sync. Mode: USCI Mode: 2 */
9411 #define UCMODE_3 (0x0600) /* Sync. Mode: USCI Mode: 3 */
9412 
9413 #define UCSSEL_0 (0x0000) /* USCI 0 Clock Source: 0 */
9414 #define UCSSEL_1 (0x0040) /* USCI 0 Clock Source: 1 */
9415 #define UCSSEL_2 (0x0080) /* USCI 0 Clock Source: 2 */
9416 #define UCSSEL_3 (0x00C0) /* USCI 0 Clock Source: 3 */
9417 #define UCSSEL__UCLK (0x0000) /* USCI 0 Clock Source: UCLK */
9418 #define UCSSEL__ACLK (0x0040) /* USCI 0 Clock Source: ACLK */
9419 #define UCSSEL__SMCLK (0x0080) /* USCI 0 Clock Source: SMCLK */
9420 
9421 // UCAxCTLW1 UART-Mode Control Bits
9422 #define UCGLIT1 (0x0002) /* USCI Deglitch Time Bit 1 */
9423 #define UCGLIT0 (0x0001) /* USCI Deglitch Time Bit 0 */
9424 
9425 // UCAxCTLW1 UART-Mode Control Bits
9426 #define UCGLIT1_L (0x0002) /* USCI Deglitch Time Bit 1 */
9427 #define UCGLIT0_L (0x0001) /* USCI Deglitch Time Bit 0 */
9428 
9429 // UCBxCTLW1 I2C-Mode Control Bits
9430 #define UCETXINT (0x0100) /* USCI Early UCTXIFG0 */
9431 #define UCCLTO1 (0x0080) /* USCI Clock low timeout Bit: 1 */
9432 #define UCCLTO0 (0x0040) /* USCI Clock low timeout Bit: 0 */
9433 #define UCSTPNACK (0x0020) /* USCI Acknowledge Stop last byte */
9434 #define UCSWACK (0x0010) /* USCI Software controlled ACK */
9435 #define UCASTP1 (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
9436 #define UCASTP0 (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
9437 #define UCGLIT1 (0x0002) /* USCI Deglitch time Bit: 1 */
9438 #define UCGLIT0 (0x0001) /* USCI Deglitch time Bit: 0 */
9439 
9440 // UCBxCTLW1 I2C-Mode Control Bits
9441 #define UCCLTO1_L (0x0080) /* USCI Clock low timeout Bit: 1 */
9442 #define UCCLTO0_L (0x0040) /* USCI Clock low timeout Bit: 0 */
9443 #define UCSTPNACK_L (0x0020) /* USCI Acknowledge Stop last byte */
9444 #define UCSWACK_L (0x0010) /* USCI Software controlled ACK */
9445 #define UCASTP1_L (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
9446 #define UCASTP0_L (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
9447 #define UCGLIT1_L (0x0002) /* USCI Deglitch time Bit: 1 */
9448 #define UCGLIT0_L (0x0001) /* USCI Deglitch time Bit: 0 */
9449 
9450 // UCBxCTLW1 I2C-Mode Control Bits
9451 #define UCETXINT_H (0x0001) /* USCI Early UCTXIFG0 */
9452 
9453 #define UCGLIT_0 (0x0000) /* USCI Deglitch time: 0 */
9454 #define UCGLIT_1 (0x0001) /* USCI Deglitch time: 1 */
9455 #define UCGLIT_2 (0x0002) /* USCI Deglitch time: 2 */
9456 #define UCGLIT_3 (0x0003) /* USCI Deglitch time: 3 */
9457 
9458 #define UCASTP_0 (0x0000) /* USCI Automatic Stop condition generation: 0 */
9459 #define UCASTP_1 (0x0004) /* USCI Automatic Stop condition generation: 1 */
9460 #define UCASTP_2 (0x0008) /* USCI Automatic Stop condition generation: 2 */
9461 #define UCASTP_3 (0x000C) /* USCI Automatic Stop condition generation: 3 */
9462 
9463 #define UCCLTO_0 (0x0000) /* USCI Clock low timeout: 0 */
9464 #define UCCLTO_1 (0x0040) /* USCI Clock low timeout: 1 */
9465 #define UCCLTO_2 (0x0080) /* USCI Clock low timeout: 2 */
9466 #define UCCLTO_3 (0x00C0) /* USCI Clock low timeout: 3 */
9467 
9468 /* UCAxMCTLW Control Bits */
9469 #define UCBRS7 (0x8000) /* USCI Second Stage Modulation Select 7 */
9470 #define UCBRS6 (0x4000) /* USCI Second Stage Modulation Select 6 */
9471 #define UCBRS5 (0x2000) /* USCI Second Stage Modulation Select 5 */
9472 #define UCBRS4 (0x1000) /* USCI Second Stage Modulation Select 4 */
9473 #define UCBRS3 (0x0800) /* USCI Second Stage Modulation Select 3 */
9474 #define UCBRS2 (0x0400) /* USCI Second Stage Modulation Select 2 */
9475 #define UCBRS1 (0x0200) /* USCI Second Stage Modulation Select 1 */
9476 #define UCBRS0 (0x0100) /* USCI Second Stage Modulation Select 0 */
9477 #define UCBRF3 (0x0080) /* USCI First Stage Modulation Select 3 */
9478 #define UCBRF2 (0x0040) /* USCI First Stage Modulation Select 2 */
9479 #define UCBRF1 (0x0020) /* USCI First Stage Modulation Select 1 */
9480 #define UCBRF0 (0x0010) /* USCI First Stage Modulation Select 0 */
9481 #define UCOS16 (0x0001) /* USCI 16-times Oversampling enable */
9482 
9483 /* UCAxMCTLW Control Bits */
9484 #define UCBRF3_L (0x0080) /* USCI First Stage Modulation Select 3 */
9485 #define UCBRF2_L (0x0040) /* USCI First Stage Modulation Select 2 */
9486 #define UCBRF1_L (0x0020) /* USCI First Stage Modulation Select 1 */
9487 #define UCBRF0_L (0x0010) /* USCI First Stage Modulation Select 0 */
9488 #define UCOS16_L (0x0001) /* USCI 16-times Oversampling enable */
9489 
9490 /* UCAxMCTLW Control Bits */
9491 #define UCBRS7_H (0x0080) /* USCI Second Stage Modulation Select 7 */
9492 #define UCBRS6_H (0x0040) /* USCI Second Stage Modulation Select 6 */
9493 #define UCBRS5_H (0x0020) /* USCI Second Stage Modulation Select 5 */
9494 #define UCBRS4_H (0x0010) /* USCI Second Stage Modulation Select 4 */
9495 #define UCBRS3_H (0x0008) /* USCI Second Stage Modulation Select 3 */
9496 #define UCBRS2_H (0x0004) /* USCI Second Stage Modulation Select 2 */
9497 #define UCBRS1_H (0x0002) /* USCI Second Stage Modulation Select 1 */
9498 #define UCBRS0_H (0x0001) /* USCI Second Stage Modulation Select 0 */
9499 
9500 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
9501 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
9502 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
9503 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
9504 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
9505 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
9506 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
9507 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
9508 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
9509 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
9510 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
9511 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
9512 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
9513 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
9514 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
9515 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
9516 
9517 /* UCAxSTATW Control Bits */
9518 #define UCLISTEN (0x0080) /* USCI Listen mode */
9519 #define UCFE (0x0040) /* USCI Frame Error Flag */
9520 #define UCOE (0x0020) /* USCI Overrun Error Flag */
9521 #define UCPE (0x0010) /* USCI Parity Error Flag */
9522 #define UCBRK (0x0008) /* USCI Break received */
9523 #define UCRXERR (0x0004) /* USCI RX Error Flag */
9524 #define UCADDR (0x0002) /* USCI Address received Flag */
9525 #define UCBUSY (0x0001) /* USCI Busy Flag */
9526 #define UCIDLE (0x0002) /* USCI Idle line detected Flag */
9527 
9528 /* UCBxSTATW I2C Control Bits */
9529 #define UCBCNT7 (0x8000) /* USCI Byte Counter Bit 7 */
9530 #define UCBCNT6 (0x4000) /* USCI Byte Counter Bit 6 */
9531 #define UCBCNT5 (0x2000) /* USCI Byte Counter Bit 5 */
9532 #define UCBCNT4 (0x1000) /* USCI Byte Counter Bit 4 */
9533 #define UCBCNT3 (0x0800) /* USCI Byte Counter Bit 3 */
9534 #define UCBCNT2 (0x0400) /* USCI Byte Counter Bit 2 */
9535 #define UCBCNT1 (0x0200) /* USCI Byte Counter Bit 1 */
9536 #define UCBCNT0 (0x0100) /* USCI Byte Counter Bit 0 */
9537 #define UCSCLLOW (0x0040) /* SCL low */
9538 #define UCGC (0x0020) /* General Call address received Flag */
9539 #define UCBBUSY (0x0010) /* Bus Busy Flag */
9540 
9541 /* UCBxTBCNT I2C Control Bits */
9542 #define UCTBCNT7 (0x0080) /* USCI Byte Counter Bit 7 */
9543 #define UCTBCNT6 (0x0040) /* USCI Byte Counter Bit 6 */
9544 #define UCTBCNT5 (0x0020) /* USCI Byte Counter Bit 5 */
9545 #define UCTBCNT4 (0x0010) /* USCI Byte Counter Bit 4 */
9546 #define UCTBCNT3 (0x0008) /* USCI Byte Counter Bit 3 */
9547 #define UCTBCNT2 (0x0004) /* USCI Byte Counter Bit 2 */
9548 #define UCTBCNT1 (0x0002) /* USCI Byte Counter Bit 1 */
9549 #define UCTBCNT0 (0x0001) /* USCI Byte Counter Bit 0 */
9550 
9551 /* UCAxIRCTL Control Bits */
9552 #define UCIRRXFL5 (0x8000) /* IRDA Receive Filter Length 5 */
9553 #define UCIRRXFL4 (0x4000) /* IRDA Receive Filter Length 4 */
9554 #define UCIRRXFL3 (0x2000) /* IRDA Receive Filter Length 3 */
9555 #define UCIRRXFL2 (0x1000) /* IRDA Receive Filter Length 2 */
9556 #define UCIRRXFL1 (0x0800) /* IRDA Receive Filter Length 1 */
9557 #define UCIRRXFL0 (0x0400) /* IRDA Receive Filter Length 0 */
9558 #define UCIRRXPL (0x0200) /* IRDA Receive Input Polarity */
9559 #define UCIRRXFE (0x0100) /* IRDA Receive Filter enable */
9560 #define UCIRTXPL5 (0x0080) /* IRDA Transmit Pulse Length 5 */
9561 #define UCIRTXPL4 (0x0040) /* IRDA Transmit Pulse Length 4 */
9562 #define UCIRTXPL3 (0x0020) /* IRDA Transmit Pulse Length 3 */
9563 #define UCIRTXPL2 (0x0010) /* IRDA Transmit Pulse Length 2 */
9564 #define UCIRTXPL1 (0x0008) /* IRDA Transmit Pulse Length 1 */
9565 #define UCIRTXPL0 (0x0004) /* IRDA Transmit Pulse Length 0 */
9566 #define UCIRTXCLK (0x0002) /* IRDA Transmit Pulse Clock Select */
9567 #define UCIREN (0x0001) /* IRDA Encoder/Decoder enable */
9568 
9569 /* UCAxIRCTL Control Bits */
9570 #define UCIRTXPL5_L (0x0080) /* IRDA Transmit Pulse Length 5 */
9571 #define UCIRTXPL4_L (0x0040) /* IRDA Transmit Pulse Length 4 */
9572 #define UCIRTXPL3_L (0x0020) /* IRDA Transmit Pulse Length 3 */
9573 #define UCIRTXPL2_L (0x0010) /* IRDA Transmit Pulse Length 2 */
9574 #define UCIRTXPL1_L (0x0008) /* IRDA Transmit Pulse Length 1 */
9575 #define UCIRTXPL0_L (0x0004) /* IRDA Transmit Pulse Length 0 */
9576 #define UCIRTXCLK_L (0x0002) /* IRDA Transmit Pulse Clock Select */
9577 #define UCIREN_L (0x0001) /* IRDA Encoder/Decoder enable */
9578 
9579 /* UCAxIRCTL Control Bits */
9580 #define UCIRRXFL5_H (0x0080) /* IRDA Receive Filter Length 5 */
9581 #define UCIRRXFL4_H (0x0040) /* IRDA Receive Filter Length 4 */
9582 #define UCIRRXFL3_H (0x0020) /* IRDA Receive Filter Length 3 */
9583 #define UCIRRXFL2_H (0x0010) /* IRDA Receive Filter Length 2 */
9584 #define UCIRRXFL1_H (0x0008) /* IRDA Receive Filter Length 1 */
9585 #define UCIRRXFL0_H (0x0004) /* IRDA Receive Filter Length 0 */
9586 #define UCIRRXPL_H (0x0002) /* IRDA Receive Input Polarity */
9587 #define UCIRRXFE_H (0x0001) /* IRDA Receive Filter enable */
9588 
9589 /* UCAxABCTL Control Bits */
9590 //#define res (0x80) /* reserved */
9591 //#define res (0x40) /* reserved */
9592 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
9593 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
9594 #define UCSTOE (0x08) /* Sync-Field Timeout error */
9595 #define UCBTOE (0x04) /* Break Timeout error */
9596 //#define res (0x02) /* reserved */
9597 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */
9598 
9599 /* UCBxI2COA0 Control Bits */
9600 #define UCGCEN (0x8000) /* I2C General Call enable */
9601 #define UCOAEN (0x0400) /* I2C Own Address enable */
9602 #define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
9603 #define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
9604 #define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
9605 #define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
9606 #define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
9607 #define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
9608 #define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
9609 #define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
9610 #define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
9611 #define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
9612 
9613 /* UCBxI2COA0 Control Bits */
9614 #define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
9615 #define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
9616 #define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
9617 #define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
9618 #define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
9619 #define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
9620 #define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
9621 #define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
9622 
9623 /* UCBxI2COA0 Control Bits */
9624 #define UCGCEN_H (0x0080) /* I2C General Call enable */
9625 #define UCOAEN_H (0x0004) /* I2C Own Address enable */
9626 #define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
9627 #define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
9628 
9629 /* UCBxI2COAx Control Bits */
9630 #define UCOAEN (0x0400) /* I2C Own Address enable */
9631 #define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
9632 #define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
9633 #define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
9634 #define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
9635 #define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
9636 #define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
9637 #define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
9638 #define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
9639 #define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
9640 #define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
9641 
9642 /* UCBxI2COAx Control Bits */
9643 #define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
9644 #define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
9645 #define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
9646 #define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
9647 #define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
9648 #define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
9649 #define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
9650 #define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
9651 
9652 /* UCBxI2COAx Control Bits */
9653 #define UCOAEN_H (0x0004) /* I2C Own Address enable */
9654 #define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
9655 #define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
9656 
9657 /* UCBxADDRX Control Bits */
9658 #define UCADDRX9 (0x0200) /* I2C Receive Address Bit 9 */
9659 #define UCADDRX8 (0x0100) /* I2C Receive Address Bit 8 */
9660 #define UCADDRX7 (0x0080) /* I2C Receive Address Bit 7 */
9661 #define UCADDRX6 (0x0040) /* I2C Receive Address Bit 6 */
9662 #define UCADDRX5 (0x0020) /* I2C Receive Address Bit 5 */
9663 #define UCADDRX4 (0x0010) /* I2C Receive Address Bit 4 */
9664 #define UCADDRX3 (0x0008) /* I2C Receive Address Bit 3 */
9665 #define UCADDRX2 (0x0004) /* I2C Receive Address Bit 2 */
9666 #define UCADDRX1 (0x0002) /* I2C Receive Address Bit 1 */
9667 #define UCADDRX0 (0x0001) /* I2C Receive Address Bit 0 */
9668 
9669 /* UCBxADDRX Control Bits */
9670 #define UCADDRX7_L (0x0080) /* I2C Receive Address Bit 7 */
9671 #define UCADDRX6_L (0x0040) /* I2C Receive Address Bit 6 */
9672 #define UCADDRX5_L (0x0020) /* I2C Receive Address Bit 5 */
9673 #define UCADDRX4_L (0x0010) /* I2C Receive Address Bit 4 */
9674 #define UCADDRX3_L (0x0008) /* I2C Receive Address Bit 3 */
9675 #define UCADDRX2_L (0x0004) /* I2C Receive Address Bit 2 */
9676 #define UCADDRX1_L (0x0002) /* I2C Receive Address Bit 1 */
9677 #define UCADDRX0_L (0x0001) /* I2C Receive Address Bit 0 */
9678 
9679 /* UCBxADDRX Control Bits */
9680 #define UCADDRX9_H (0x0002) /* I2C Receive Address Bit 9 */
9681 #define UCADDRX8_H (0x0001) /* I2C Receive Address Bit 8 */
9682 
9683 /* UCBxADDMASK Control Bits */
9684 #define UCADDMASK9 (0x0200) /* I2C Address Mask Bit 9 */
9685 #define UCADDMASK8 (0x0100) /* I2C Address Mask Bit 8 */
9686 #define UCADDMASK7 (0x0080) /* I2C Address Mask Bit 7 */
9687 #define UCADDMASK6 (0x0040) /* I2C Address Mask Bit 6 */
9688 #define UCADDMASK5 (0x0020) /* I2C Address Mask Bit 5 */
9689 #define UCADDMASK4 (0x0010) /* I2C Address Mask Bit 4 */
9690 #define UCADDMASK3 (0x0008) /* I2C Address Mask Bit 3 */
9691 #define UCADDMASK2 (0x0004) /* I2C Address Mask Bit 2 */
9692 #define UCADDMASK1 (0x0002) /* I2C Address Mask Bit 1 */
9693 #define UCADDMASK0 (0x0001) /* I2C Address Mask Bit 0 */
9694 
9695 /* UCBxADDMASK Control Bits */
9696 #define UCADDMASK7_L (0x0080) /* I2C Address Mask Bit 7 */
9697 #define UCADDMASK6_L (0x0040) /* I2C Address Mask Bit 6 */
9698 #define UCADDMASK5_L (0x0020) /* I2C Address Mask Bit 5 */
9699 #define UCADDMASK4_L (0x0010) /* I2C Address Mask Bit 4 */
9700 #define UCADDMASK3_L (0x0008) /* I2C Address Mask Bit 3 */
9701 #define UCADDMASK2_L (0x0004) /* I2C Address Mask Bit 2 */
9702 #define UCADDMASK1_L (0x0002) /* I2C Address Mask Bit 1 */
9703 #define UCADDMASK0_L (0x0001) /* I2C Address Mask Bit 0 */
9704 
9705 /* UCBxADDMASK Control Bits */
9706 #define UCADDMASK9_H (0x0002) /* I2C Address Mask Bit 9 */
9707 #define UCADDMASK8_H (0x0001) /* I2C Address Mask Bit 8 */
9708 
9709 /* UCBxI2CSA Control Bits */
9710 #define UCSA9 (0x0200) /* I2C Slave Address Bit 9 */
9711 #define UCSA8 (0x0100) /* I2C Slave Address Bit 8 */
9712 #define UCSA7 (0x0080) /* I2C Slave Address Bit 7 */
9713 #define UCSA6 (0x0040) /* I2C Slave Address Bit 6 */
9714 #define UCSA5 (0x0020) /* I2C Slave Address Bit 5 */
9715 #define UCSA4 (0x0010) /* I2C Slave Address Bit 4 */
9716 #define UCSA3 (0x0008) /* I2C Slave Address Bit 3 */
9717 #define UCSA2 (0x0004) /* I2C Slave Address Bit 2 */
9718 #define UCSA1 (0x0002) /* I2C Slave Address Bit 1 */
9719 #define UCSA0 (0x0001) /* I2C Slave Address Bit 0 */
9720 
9721 /* UCBxI2CSA Control Bits */
9722 #define UCSA7_L (0x0080) /* I2C Slave Address Bit 7 */
9723 #define UCSA6_L (0x0040) /* I2C Slave Address Bit 6 */
9724 #define UCSA5_L (0x0020) /* I2C Slave Address Bit 5 */
9725 #define UCSA4_L (0x0010) /* I2C Slave Address Bit 4 */
9726 #define UCSA3_L (0x0008) /* I2C Slave Address Bit 3 */
9727 #define UCSA2_L (0x0004) /* I2C Slave Address Bit 2 */
9728 #define UCSA1_L (0x0002) /* I2C Slave Address Bit 1 */
9729 #define UCSA0_L (0x0001) /* I2C Slave Address Bit 0 */
9730 
9731 /* UCBxI2CSA Control Bits */
9732 #define UCSA9_H (0x0002) /* I2C Slave Address Bit 9 */
9733 #define UCSA8_H (0x0001) /* I2C Slave Address Bit 8 */
9734 
9735 /* UCAxIE UART Control Bits */
9736 #define UCTXCPTIE (0x0008) /* UART Transmit Complete Interrupt Enable */
9737 #define UCSTTIE (0x0004) /* UART Start Bit Interrupt Enalble */
9738 #define UCTXIE (0x0002) /* UART Transmit Interrupt Enable */
9739 #define UCRXIE (0x0001) /* UART Receive Interrupt Enable */
9740 
9741 /* UCAxIE/UCBxIE SPI Control Bits */
9742 
9743 /* UCBxIE I2C Control Bits */
9744 #define UCBIT9IE (0x4000) /* I2C Bit 9 Position Interrupt Enable 3 */
9745 #define UCTXIE3 (0x2000) /* I2C Transmit Interrupt Enable 3 */
9746 #define UCRXIE3 (0x1000) /* I2C Receive Interrupt Enable 3 */
9747 #define UCTXIE2 (0x0800) /* I2C Transmit Interrupt Enable 2 */
9748 #define UCRXIE2 (0x0400) /* I2C Receive Interrupt Enable 2 */
9749 #define UCTXIE1 (0x0200) /* I2C Transmit Interrupt Enable 1 */
9750 #define UCRXIE1 (0x0100) /* I2C Receive Interrupt Enable 1 */
9751 #define UCCLTOIE (0x0080) /* I2C Clock Low Timeout interrupt enable */
9752 #define UCBCNTIE (0x0040) /* I2C Automatic stop assertion interrupt enable */
9753 #define UCNACKIE (0x0020) /* I2C NACK Condition interrupt enable */
9754 #define UCALIE (0x0010) /* I2C Arbitration Lost interrupt enable */
9755 #define UCSTPIE (0x0008) /* I2C STOP Condition interrupt enable */
9756 #define UCSTTIE (0x0004) /* I2C START Condition interrupt enable */
9757 #define UCTXIE0 (0x0002) /* I2C Transmit Interrupt Enable 0 */
9758 #define UCRXIE0 (0x0001) /* I2C Receive Interrupt Enable 0 */
9759 
9760 /* UCAxIFG UART Control Bits */
9761 #define UCTXCPTIFG (0x0008) /* UART Transmit Complete Interrupt Flag */
9762 #define UCSTTIFG (0x0004) /* UART Start Bit Interrupt Flag */
9763 #define UCTXIFG (0x0002) /* UART Transmit Interrupt Flag */
9764 #define UCRXIFG (0x0001) /* UART Receive Interrupt Flag */
9765 
9766 /* UCAxIFG/UCBxIFG SPI Control Bits */
9767 #define UCTXIFG (0x0002) /* SPI Transmit Interrupt Flag */
9768 #define UCRXIFG (0x0001) /* SPI Receive Interrupt Flag */
9769 
9770 /* UCBxIFG Control Bits */
9771 #define UCBIT9IFG (0x4000) /* I2C Bit 9 Possition Interrupt Flag 3 */
9772 #define UCTXIFG3 (0x2000) /* I2C Transmit Interrupt Flag 3 */
9773 #define UCRXIFG3 (0x1000) /* I2C Receive Interrupt Flag 3 */
9774 #define UCTXIFG2 (0x0800) /* I2C Transmit Interrupt Flag 2 */
9775 #define UCRXIFG2 (0x0400) /* I2C Receive Interrupt Flag 2 */
9776 #define UCTXIFG1 (0x0200) /* I2C Transmit Interrupt Flag 1 */
9777 #define UCRXIFG1 (0x0100) /* I2C Receive Interrupt Flag 1 */
9778 #define UCCLTOIFG (0x0080) /* I2C Clock low Timeout interrupt Flag */
9779 #define UCBCNTIFG (0x0040) /* I2C Byte counter interrupt flag */
9780 #define UCNACKIFG (0x0020) /* I2C NACK Condition interrupt Flag */
9781 #define UCALIFG (0x0010) /* I2C Arbitration Lost interrupt Flag */
9782 #define UCSTPIFG (0x0008) /* I2C STOP Condition interrupt Flag */
9783 #define UCSTTIFG (0x0004) /* I2C START Condition interrupt Flag */
9784 #define UCTXIFG0 (0x0002) /* I2C Transmit Interrupt Flag 0 */
9785 #define UCRXIFG0 (0x0001) /* I2C Receive Interrupt Flag 0 */
9786 
9787 /* USCI UART Definitions */
9788 #define USCI_NONE (0x0000) /* No Interrupt pending */
9789 #define USCI_UART_UCRXIFG (0x0002) /* USCI UCRXIFG */
9790 #define USCI_UART_UCTXIFG (0x0004) /* USCI UCTXIFG */
9791 #define USCI_UART_UCSTTIFG (0x0006) /* USCI UCSTTIFG */
9792 #define USCI_UART_UCTXCPTIFG (0x0008) /* USCI UCTXCPTIFG */
9793 
9794 /* USCI SPI Definitions */
9795 #define USCI_SPI_UCRXIFG (0x0002) /* USCI UCRXIFG */
9796 #define USCI_SPI_UCTXIFG (0x0004) /* USCI UCTXIFG */
9797 
9798 /* USCI I2C Definitions */
9799 #define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */
9800 #define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */
9801 #define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/
9802 #define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/
9803 #define USCI_I2C_UCRXIFG3 (0x000A) /* USCI I2C Mode: UCRXIFG3 */
9804 #define USCI_I2C_UCTXIFG3 (0x000C) /* USCI I2C Mode: UCTXIFG3 */
9805 #define USCI_I2C_UCRXIFG2 (0x000E) /* USCI I2C Mode: UCRXIFG2 */
9806 #define USCI_I2C_UCTXIFG2 (0x0010) /* USCI I2C Mode: UCTXIFG2 */
9807 #define USCI_I2C_UCRXIFG1 (0x0012) /* USCI I2C Mode: UCRXIFG1 */
9808 #define USCI_I2C_UCTXIFG1 (0x0014) /* USCI I2C Mode: UCTXIFG1 */
9809 #define USCI_I2C_UCRXIFG0 (0x0016) /* USCI I2C Mode: UCRXIFG0 */
9810 #define USCI_I2C_UCTXIFG0 (0x0018) /* USCI I2C Mode: UCTXIFG0 */
9811 #define USCI_I2C_UCBCNTIFG (0x001A) /* USCI I2C Mode: UCBCNTIFG */
9812 #define USCI_I2C_UCCLTOIFG (0x001C) /* USCI I2C Mode: UCCLTOIFG */
9813 #define USCI_I2C_UCBIT9IFG (0x001E) /* USCI I2C Mode: UCBIT9IFG */
9814 
9815 #endif
9816 /************************************************************
9817 * WATCHDOG TIMER A
9818 ************************************************************/
9819 #ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */
9820 
9821 #define OFS_WDTCTL (0x000C) /* Watchdog Timer Control */
9822 #define OFS_WDTCTL_L OFS_WDTCTL
9823 #define OFS_WDTCTL_H OFS_WDTCTL+1
9824 /* The bit names have been prefixed with "WDT" */
9825 /* WDTCTL Control Bits */
9826 #define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */
9827 #define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */
9828 #define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */
9829 #define WDTCNTCL (0x0008) /* WDT - Timer Clear */
9830 #define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */
9831 #define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */
9832 #define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */
9833 #define WDTHOLD (0x0080) /* WDT - Timer hold */
9834 
9835 /* WDTCTL Control Bits */
9836 #define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */
9837 #define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */
9838 #define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */
9839 #define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */
9840 #define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */
9841 #define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */
9842 #define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */
9843 #define WDTHOLD_L (0x0080) /* WDT - Timer hold */
9844 
9845 #define WDTPW (0x5A00)
9846 
9847 #define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */
9848 #define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */
9849 #define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
9850 #define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */
9851 #define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */
9852 #define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
9853 #define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
9854 #define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
9855 #define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */
9856 #define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */
9857 #define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
9858 #define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */
9859 #define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */
9860 #define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
9861 #define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
9862 #define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
9863 
9864 #define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
9865 #define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
9866 #define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
9867 #define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */
9868 #define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
9869 #define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
9870 #define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
9871 
9872 /* WDT-interval times [1ms] coded with Bits 0-2 */
9873 /* WDT is clocked by fSMCLK (assumed 1MHz) */
9874 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
9875 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
9876 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
9877 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
9878 /* WDT is clocked by fACLK (assumed 32KHz) */
9879 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
9880 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
9881 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
9882 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
9883 /* Watchdog mode -> reset after expired time */
9884 /* WDT is clocked by fSMCLK (assumed 1MHz) */
9885 #define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
9886 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
9887 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
9888 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
9889 /* WDT is clocked by fACLK (assumed 32KHz) */
9890 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
9891 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
9892 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
9893 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */
9894 
9895 #endif
9896 
9897 /************************************************************
9898 * TLV Descriptors
9899 ************************************************************/
9900 #define __MSP430_HAS_TLV__ /* Definition to show that Module is available */
9901 #define TLV_BASE __MSP430_BASEADDRESS_TLV__
9902 
9903 #define TLV_START (0x1A08) /* Start Address of the TLV structure */
9904 #define TLV_END (0x1AFF) /* End Address of the TLV structure */
9905 
9906 #define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */
9907 #define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
9908 #define TLV_Reserved3 (0x03) /* Future usage */
9909 #define TLV_Reserved4 (0x04) /* Future usage */
9910 #define TLV_BLANK (0x05) /* Blank descriptor */
9911 #define TLV_Reserved6 (0x06) /* Future usage */
9912 #define TLV_Reserved7 (0x07) /* Serial Number */
9913 #define TLV_DIERECORD (0x08) /* Die Record */
9914 #define TLV_ADCCAL (0x11) /* ADC12 calibration */
9915 #define TLV_ADC12CAL (0x11) /* ADC12 calibration */
9916 #define TLV_REFCAL (0x12) /* REF calibration */
9917 #define TLV_ADC10CAL (0x13) /* ADC10 calibration */
9918 #define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */
9919 #define TLV_TAGEXT (0xFE) /* Tag extender */
9920 #define TLV_TAGEND (0xFF) /* Tag End of Table */
9921 
9922 /************************************************************
9923 * Interrupt Vectors (offset from 0xFF80)
9924 ************************************************************/
9925 
9926 #pragma diag_suppress 1107
9927 #define VECTOR_NAME(name) name##_ptr
9928 #define EMIT_PRAGMA(x) _Pragma(#x)
9929 #define CREATE_VECTOR(name) void * const VECTOR_NAME(name) = (void *)(long)&name
9930 #define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
9931 #define PLACE_INTERRUPT(func) EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
9932 #define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
9933  PLACE_VECTOR(VECTOR_NAME(func), offset) \
9934  PLACE_INTERRUPT(func)
9935 
9936 
9937 /************************************************************
9938 * End of Modules
9939 ************************************************************/
9940 
9941 #ifdef __cplusplus
9942 }
9943 #endif /* extern "C" */
9944 
9945 #endif /* #ifndef __msp430F5XX_F6XXGENERIC */
9946 
__SFR_FARPTR
void(* __SFR_FARPTR)()
Definition: CCS/msp430f5xx_6xxgeneric.h:67
Copyright 2014, Texas Instruments Incorporated