IAR/msp430f5xx_6xxgeneric.h
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1 /********************************************************************
2 *
3 * Standard register and bit definitions for the Texas Instruments
4 * MSP430 microcontroller.
5 *
6 * This file supports assembler and C development for
7 * MSP430F5XX_F6XXGENERIC device.
8 *
9 * Texas Instruments, Version 1.0
10 *
11 * Rev. 1.0, Setup
12 *
13 *
14 ********************************************************************/
15 
16 #ifndef __msp430F5XX_F6XXGENERIC
17 #define __msp430F5XX_F6XXGENERIC
18 
19 //#define __MSP430_HEADER_VERSION__ 1093
20 
21 #ifdef __IAR_SYSTEMS_ICC__
22 #ifndef _SYSTEM_BUILD
23 #pragma system_include
24 #endif
25 #endif
26 
27 #if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */
28 #error msp430f5xx_6xxgeneric.h file for use with ICC430/A430 only
29 #endif
30 
31 
32 #ifdef __IAR_SYSTEMS_ICC__
33 #include "in430.h"
34 #pragma language=extended
35 
36 #define DEFC(name, address) __no_init volatile unsigned char name @ address;
37 #define DEFW(name, address) __no_init volatile unsigned short name @ address;
38 
39 #define DEFCW(name, address) __no_init union \
40 { \
41  struct \
42  { \
43  volatile unsigned char name##_L; \
44  volatile unsigned char name##_H; \
45  }; \
46  volatile unsigned short name; \
47 } @ address;
48 
49 #define READ_ONLY_DEFCW(name, address) __no_init union \
50 { \
51  struct \
52  { \
53  volatile READ_ONLY unsigned char name##_L; \
54  volatile READ_ONLY unsigned char name##_H; \
55  }; \
56  volatile READ_ONLY unsigned short name; \
57 } @ address;
58 
59 
60 #if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__
61 #define __ACCESS_20BIT_REG__ void __data20 * volatile
62 #else
63 #define __ACCESS_20BIT_REG__ volatile unsigned short /* only short access from C is allowed in small memory model */
64 #endif
65 
66 #define DEFA(name, address) __no_init union \
67 { \
68  struct \
69  { \
70  volatile unsigned char name##_L; \
71  volatile unsigned char name##_H; \
72  }; \
73  struct \
74  { \
75  volatile unsigned short name##L; \
76  volatile unsigned short name##H; \
77  }; \
78  __ACCESS_20BIT_REG__ name; \
79 } @ address;
80 
81 #endif /* __IAR_SYSTEMS_ICC__ */
82 
83 
84 #ifdef __IAR_SYSTEMS_ASM__
85 #define DEFC(name, address) sfrb name = address;
86 #define DEFW(name, address) sfrw name = address;
87 
88 #define DEFCW(name, address) sfrbw name, name##_L, name##_H, address;
89 sfrbw macro name, name_L, name_H, address;
90 sfrb name_L = address;
91 sfrb name_H = address+1;
92 sfrw name = address;
93  endm
94 
95 #define READ_ONLY_DEFCW(name, address) const_sfrbw name, name##_L, name##_H, address;
96 const_sfrbw macro name, name_L, name_H, address;
97 const sfrb name_L = address;
98 const sfrb name_H = address+1;
99 const sfrw name = address;
100  endm
101 
102 #define DEFA(name, address) sfrba name, name##L, name##H, name##_L, name##_H, address;
103 sfrba macro name, nameL, nameH, name_L, name_H, address;
104 sfrb name_L = address;
105 sfrb name_H = address+1;
106 sfrw nameL = address;
107 sfrw nameH = address+2;
108 sfrl name = address;
109  endm
110 
111 #endif /* __IAR_SYSTEMS_ASM__*/
112 
113 #ifdef __cplusplus
114 #define READ_ONLY
115 #else
116 #define READ_ONLY const
117 #endif
118 
119 /************************************************************
120 * STANDARD BITS
121 ************************************************************/
122 
123 #define BIT0 (0x0001u)
124 #define BIT1 (0x0002u)
125 #define BIT2 (0x0004u)
126 #define BIT3 (0x0008u)
127 #define BIT4 (0x0010u)
128 #define BIT5 (0x0020u)
129 #define BIT6 (0x0040u)
130 #define BIT7 (0x0080u)
131 #define BIT8 (0x0100u)
132 #define BIT9 (0x0200u)
133 #define BITA (0x0400u)
134 #define BITB (0x0800u)
135 #define BITC (0x1000u)
136 #define BITD (0x2000u)
137 #define BITE (0x4000u)
138 #define BITF (0x8000u)
139 
140 /************************************************************
141 * STATUS REGISTER BITS
142 ************************************************************/
143 
144 #define C (0x0001u)
145 #define Z (0x0002u)
146 #define N (0x0004u)
147 #define V (0x0100u)
148 #define GIE (0x0008u)
149 #define CPUOFF (0x0010u)
150 #define OSCOFF (0x0020u)
151 #define SCG0 (0x0040u)
152 #define SCG1 (0x0080u)
153 
154 /* Low Power Modes coded with Bits 4-7 in SR */
155 
156 #ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */
157 #define LPM0 (CPUOFF)
158 #define LPM1 (SCG0+CPUOFF)
159 #define LPM2 (SCG1+CPUOFF)
160 #define LPM3 (SCG1+SCG0+CPUOFF)
161 #define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
162 /* End #defines for assembler */
163 
164 #else /* Begin #defines for C */
165 #define LPM0_bits (CPUOFF)
166 #define LPM1_bits (SCG0+CPUOFF)
167 #define LPM2_bits (SCG1+CPUOFF)
168 #define LPM3_bits (SCG1+SCG0+CPUOFF)
169 #define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
170 
171 #include "in430.h"
172 
173 #define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */
174 #define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
175 #define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */
176 #define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
177 #define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */
178 #define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
179 #define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */
180 #define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
181 #define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */
182 #define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
183 #endif /* End #defines for C */
184 
185 /************************************************************
186 * CPU
187 ************************************************************/
188 #define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */
189 
190 #if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \
191  || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \
192  || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \
193  || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__)
194  #define __MSP430_HAS_TxA7__
195 #endif
196 #if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \
197  || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__)
198  #define __MSP430_HAS_TxB7__
199 #endif
200 #if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \
201  || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__)
202  #define __MSP430_HAS_TxD7__
203 #endif
204 #if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__)
205  #define __MSP430_HAS_USCI_Ax__
206 #endif
207 #if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__)
208  #define __MSP430_HAS_USCI_Bx__
209 #endif
210 #if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__)
211  #define __MSP430_HAS_EUSCI_Ax__
212 #endif
213 #if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__)
214  #define __MSP430_HAS_EUSCI_Bx__
215 #endif
216 #ifdef __MSP430_HAS_EUSCI_B0__
217  #define __MSP430_HAS_EUSCI_Bx__
218 #endif
219 
220 /************************************************************
221 * ADC10_A
222 ************************************************************/
223 #ifdef __MSP430_HAS_ADC10_A__ /* Definition to show that Module is available */
224 
225 #define OFS_ADC10CTL0 (0x0000u) /* ADC10 Control 0 */
226 #define OFS_ADC10CTL0_L OFS_ADC10CTL0
227 #define OFS_ADC10CTL0_H OFS_ADC10CTL0+1
228 #define OFS_ADC10CTL1 (0x0002u) /* ADC10 Control 1 */
229 #define OFS_ADC10CTL1_L OFS_ADC10CTL1
230 #define OFS_ADC10CTL1_H OFS_ADC10CTL1+1
231 #define OFS_ADC10CTL2 (0x0004u) /* ADC10 Control 2 */
232 #define OFS_ADC10CTL2_L OFS_ADC10CTL2
233 #define OFS_ADC10CTL2_H OFS_ADC10CTL2+1
234 #define OFS_ADC10LO (0x0006u) /* ADC10 Window Comparator High Threshold */
235 #define OFS_ADC10LO_L OFS_ADC10LO
236 #define OFS_ADC10LO_H OFS_ADC10LO+1
237 #define OFS_ADC10HI (0x0008u) /* ADC10 Window Comparator High Threshold */
238 #define OFS_ADC10HI_L OFS_ADC10HI
239 #define OFS_ADC10HI_H OFS_ADC10HI+1
240 #define OFS_ADC10MCTL0 (0x000Au) /* ADC10 Memory Control 0 */
241 #define OFS_ADC10MCTL0_L OFS_ADC10MCTL0
242 #define OFS_ADC10MCTL0_H OFS_ADC10MCTL0+1
243 #define OFS_ADC10MEM0 (0x0012u) /* ADC10 Conversion Memory 0 */
244 #define OFS_ADC10MEM0_L OFS_ADC10MEM0
245 #define OFS_ADC10MEM0_H OFS_ADC10MEM0+1
246 #define OFS_ADC10IE (0x001Au) /* ADC10 Interrupt Enable */
247 #define OFS_ADC10IE_L OFS_ADC10IE
248 #define OFS_ADC10IE_H OFS_ADC10IE+1
249 #define OFS_ADC10IFG (0x001Cu) /* ADC10 Interrupt Flag */
250 #define OFS_ADC10IFG_L OFS_ADC10IFG
251 #define OFS_ADC10IFG_H OFS_ADC10IFG+1
252 #define OFS_ADC10IV (0x001Eu) /* ADC10 Interrupt Vector Word */
253 #define OFS_ADC10IV_L OFS_ADC10IV
254 #define OFS_ADC10IV_H OFS_ADC10IV+1
255 
256 /* ADC10CTL0 Control Bits */
257 #define ADC10SC (0x0001u) /* ADC10 Start Conversion */
258 #define ADC10ENC (0x0002u) /* ADC10 Enable Conversion */
259 #define ADC10ON (0x0010u) /* ADC10 On/enable */
260 #define ADC10MSC (0x0080u) /* ADC10 Multiple SampleConversion */
261 #define ADC10SHT0 (0x0100u) /* ADC10 Sample Hold Select Bit: 0 */
262 #define ADC10SHT1 (0x0200u) /* ADC10 Sample Hold Select Bit: 1 */
263 #define ADC10SHT2 (0x0400u) /* ADC10 Sample Hold Select Bit: 2 */
264 #define ADC10SHT3 (0x0800u) /* ADC10 Sample Hold Select Bit: 3 */
265 
266 /* ADC10CTL0 Control Bits */
267 #define ADC10SC_L (0x0001u) /* ADC10 Start Conversion */
268 #define ADC10ENC_L (0x0002u) /* ADC10 Enable Conversion */
269 #define ADC10ON_L (0x0010u) /* ADC10 On/enable */
270 #define ADC10MSC_L (0x0080u) /* ADC10 Multiple SampleConversion */
271 
272 /* ADC10CTL0 Control Bits */
273 #define ADC10SHT0_H (0x0001u) /* ADC10 Sample Hold Select Bit: 0 */
274 #define ADC10SHT1_H (0x0002u) /* ADC10 Sample Hold Select Bit: 1 */
275 #define ADC10SHT2_H (0x0004u) /* ADC10 Sample Hold Select Bit: 2 */
276 #define ADC10SHT3_H (0x0008u) /* ADC10 Sample Hold Select Bit: 3 */
277 
278 #define ADC10SHT_0 (0*0x100u) /* ADC10 Sample Hold Select 0 */
279 #define ADC10SHT_1 (1*0x100u) /* ADC10 Sample Hold Select 1 */
280 #define ADC10SHT_2 (2*0x100u) /* ADC10 Sample Hold Select 2 */
281 #define ADC10SHT_3 (3*0x100u) /* ADC10 Sample Hold Select 3 */
282 #define ADC10SHT_4 (4*0x100u) /* ADC10 Sample Hold Select 4 */
283 #define ADC10SHT_5 (5*0x100u) /* ADC10 Sample Hold Select 5 */
284 #define ADC10SHT_6 (6*0x100u) /* ADC10 Sample Hold Select 6 */
285 #define ADC10SHT_7 (7*0x100u) /* ADC10 Sample Hold Select 7 */
286 #define ADC10SHT_8 (8*0x100u) /* ADC10 Sample Hold Select 8 */
287 #define ADC10SHT_9 (9*0x100u) /* ADC10 Sample Hold Select 9 */
288 #define ADC10SHT_10 (10*0x100u) /* ADC10 Sample Hold Select 10 */
289 #define ADC10SHT_11 (11*0x100u) /* ADC10 Sample Hold Select 11 */
290 #define ADC10SHT_12 (12*0x100u) /* ADC10 Sample Hold Select 12 */
291 #define ADC10SHT_13 (13*0x100u) /* ADC10 Sample Hold Select 13 */
292 #define ADC10SHT_14 (14*0x100u) /* ADC10 Sample Hold Select 14 */
293 #define ADC10SHT_15 (15*0x100u) /* ADC10 Sample Hold Select 15 */
294 
295 /* ADC10CTL1 Control Bits */
296 #define ADC10BUSY (0x0001u) /* ADC10 Busy */
297 #define ADC10CONSEQ0 (0x0002u) /* ADC10 Conversion Sequence Select 0 */
298 #define ADC10CONSEQ1 (0x0004u) /* ADC10 Conversion Sequence Select 1 */
299 #define ADC10SSEL0 (0x0008u) /* ADC10 Clock Source Select 0 */
300 #define ADC10SSEL1 (0x0010u) /* ADC10 Clock Source Select 1 */
301 #define ADC10DIV0 (0x0020u) /* ADC10 Clock Divider Select 0 */
302 #define ADC10DIV1 (0x0040u) /* ADC10 Clock Divider Select 1 */
303 #define ADC10DIV2 (0x0080u) /* ADC10 Clock Divider Select 2 */
304 #define ADC10ISSH (0x0100u) /* ADC10 Invert Sample Hold Signal */
305 #define ADC10SHP (0x0200u) /* ADC10 Sample/Hold Pulse Mode */
306 #define ADC10SHS0 (0x0400u) /* ADC10 Sample/Hold Source 0 */
307 #define ADC10SHS1 (0x0800u) /* ADC10 Sample/Hold Source 1 */
308 
309 /* ADC10CTL1 Control Bits */
310 #define ADC10BUSY_L (0x0001u) /* ADC10 Busy */
311 #define ADC10CONSEQ0_L (0x0002u) /* ADC10 Conversion Sequence Select 0 */
312 #define ADC10CONSEQ1_L (0x0004u) /* ADC10 Conversion Sequence Select 1 */
313 #define ADC10SSEL0_L (0x0008u) /* ADC10 Clock Source Select 0 */
314 #define ADC10SSEL1_L (0x0010u) /* ADC10 Clock Source Select 1 */
315 #define ADC10DIV0_L (0x0020u) /* ADC10 Clock Divider Select 0 */
316 #define ADC10DIV1_L (0x0040u) /* ADC10 Clock Divider Select 1 */
317 #define ADC10DIV2_L (0x0080u) /* ADC10 Clock Divider Select 2 */
318 
319 /* ADC10CTL1 Control Bits */
320 #define ADC10ISSH_H (0x0001u) /* ADC10 Invert Sample Hold Signal */
321 #define ADC10SHP_H (0x0002u) /* ADC10 Sample/Hold Pulse Mode */
322 #define ADC10SHS0_H (0x0004u) /* ADC10 Sample/Hold Source 0 */
323 #define ADC10SHS1_H (0x0008u) /* ADC10 Sample/Hold Source 1 */
324 
325 #define ADC10CONSEQ_0 (0*2u) /* ADC10 Conversion Sequence Select: 0 */
326 #define ADC10CONSEQ_1 (1*2u) /* ADC10 Conversion Sequence Select: 1 */
327 #define ADC10CONSEQ_2 (2*2u) /* ADC10 Conversion Sequence Select: 2 */
328 #define ADC10CONSEQ_3 (3*2u) /* ADC10 Conversion Sequence Select: 3 */
329 
330 #define ADC10SSEL_0 (0*8u) /* ADC10 Clock Source Select: 0 */
331 #define ADC10SSEL_1 (1*8u) /* ADC10 Clock Source Select: 1 */
332 #define ADC10SSEL_2 (2*8u) /* ADC10 Clock Source Select: 2 */
333 #define ADC10SSEL_3 (3*8u) /* ADC10 Clock Source Select: 3 */
334 
335 #define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select: 0 */
336 #define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select: 1 */
337 #define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select: 2 */
338 #define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select: 3 */
339 #define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select: 4 */
340 #define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select: 5 */
341 #define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select: 6 */
342 #define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select: 7 */
343 
344 #define ADC10SHS_0 (0*0x400u) /* ADC10 Sample/Hold Source: 0 */
345 #define ADC10SHS_1 (1*0x400u) /* ADC10 Sample/Hold Source: 1 */
346 #define ADC10SHS_2 (2*0x400u) /* ADC10 Sample/Hold Source: 2 */
347 #define ADC10SHS_3 (3*0x400u) /* ADC10 Sample/Hold Source: 3 */
348 
349 /* ADC10CTL2 Control Bits */
350 #define ADC10REFBURST (0x0001u) /* ADC10 Reference Burst */
351 #define ADC10SR (0x0004u) /* ADC10 Sampling Rate */
352 #define ADC10DF (0x0008u) /* ADC10 Data Format */
353 #define ADC10RES (0x0010u) /* ADC10 Resolution Bit */
354 #define ADC10PDIV0 (0x0100u) /* ADC10 predivider Bit: 0 */
355 #define ADC10PDIV1 (0x0200u) /* ADC10 predivider Bit: 1 */
356 
357 /* ADC10CTL2 Control Bits */
358 #define ADC10REFBURST_L (0x0001u) /* ADC10 Reference Burst */
359 #define ADC10SR_L (0x0004u) /* ADC10 Sampling Rate */
360 #define ADC10DF_L (0x0008u) /* ADC10 Data Format */
361 #define ADC10RES_L (0x0010u) /* ADC10 Resolution Bit */
362 
363 /* ADC10CTL2 Control Bits */
364 #define ADC10PDIV0_H (0x0001u) /* ADC10 predivider Bit: 0 */
365 #define ADC10PDIV1_H (0x0002u) /* ADC10 predivider Bit: 1 */
366 
367 #define ADC10PDIV_0 (0x0000u) /* ADC10 predivider /1 */
368 #define ADC10PDIV_1 (0x0100u) /* ADC10 predivider /2 */
369 #define ADC10PDIV_2 (0x0200u) /* ADC10 predivider /64 */
370 #define ADC10PDIV_3 (0x0300u) /* ADC10 predivider reserved */
371 
372 #define ADC10PDIV__1 (0x0000u) /* ADC10 predivider /1 */
373 #define ADC10PDIV__4 (0x0100u) /* ADC10 predivider /2 */
374 #define ADC10PDIV__64 (0x0200u) /* ADC10 predivider /64 */
375 
376 /* ADC10MCTL0 Control Bits */
377 #define ADC10INCH0 (0x0001u) /* ADC10 Input Channel Select Bit 0 */
378 #define ADC10INCH1 (0x0002u) /* ADC10 Input Channel Select Bit 1 */
379 #define ADC10INCH2 (0x0004u) /* ADC10 Input Channel Select Bit 2 */
380 #define ADC10INCH3 (0x0008u) /* ADC10 Input Channel Select Bit 3 */
381 #define ADC10SREF0 (0x0010u) /* ADC10 Select Reference Bit 0 */
382 #define ADC10SREF1 (0x0020u) /* ADC10 Select Reference Bit 1 */
383 #define ADC10SREF2 (0x0040u) /* ADC10 Select Reference Bit 2 */
384 
385 /* ADC10MCTL0 Control Bits */
386 #define ADC10INCH0_L (0x0001u) /* ADC10 Input Channel Select Bit 0 */
387 #define ADC10INCH1_L (0x0002u) /* ADC10 Input Channel Select Bit 1 */
388 #define ADC10INCH2_L (0x0004u) /* ADC10 Input Channel Select Bit 2 */
389 #define ADC10INCH3_L (0x0008u) /* ADC10 Input Channel Select Bit 3 */
390 #define ADC10SREF0_L (0x0010u) /* ADC10 Select Reference Bit 0 */
391 #define ADC10SREF1_L (0x0020u) /* ADC10 Select Reference Bit 1 */
392 #define ADC10SREF2_L (0x0040u) /* ADC10 Select Reference Bit 2 */
393 
394 #define ADC10INCH_0 (0) /* ADC10 Input Channel 0 */
395 #define ADC10INCH_1 (1) /* ADC10 Input Channel 1 */
396 #define ADC10INCH_2 (2) /* ADC10 Input Channel 2 */
397 #define ADC10INCH_3 (3) /* ADC10 Input Channel 3 */
398 #define ADC10INCH_4 (4) /* ADC10 Input Channel 4 */
399 #define ADC10INCH_5 (5) /* ADC10 Input Channel 5 */
400 #define ADC10INCH_6 (6) /* ADC10 Input Channel 6 */
401 #define ADC10INCH_7 (7) /* ADC10 Input Channel 7 */
402 #define ADC10INCH_8 (8) /* ADC10 Input Channel 8 */
403 #define ADC10INCH_9 (9) /* ADC10 Input Channel 9 */
404 #define ADC10INCH_10 (10) /* ADC10 Input Channel 10 */
405 #define ADC10INCH_11 (11) /* ADC10 Input Channel 11 */
406 #define ADC10INCH_12 (12) /* ADC10 Input Channel 12 */
407 #define ADC10INCH_13 (13) /* ADC10 Input Channel 13 */
408 #define ADC10INCH_14 (14) /* ADC10 Input Channel 14 */
409 #define ADC10INCH_15 (15) /* ADC10 Input Channel 15 */
410 
411 #define ADC10SREF_0 (0*0x10u) /* ADC10 Select Reference 0 */
412 #define ADC10SREF_1 (1*0x10u) /* ADC10 Select Reference 1 */
413 #define ADC10SREF_2 (2*0x10u) /* ADC10 Select Reference 2 */
414 #define ADC10SREF_3 (3*0x10u) /* ADC10 Select Reference 3 */
415 #define ADC10SREF_4 (4*0x10u) /* ADC10 Select Reference 4 */
416 #define ADC10SREF_5 (5*0x10u) /* ADC10 Select Reference 5 */
417 #define ADC10SREF_6 (6*0x10u) /* ADC10 Select Reference 6 */
418 #define ADC10SREF_7 (7*0x10u) /* ADC10 Select Reference 7 */
419 
420 /* ADC10IE Interrupt Enable Bits */
421 #define ADC10IE0 (0x0001u) /* ADC10_A Interrupt enable */
422 #define ADC10INIE (0x0002u) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */
423 #define ADC10LOIE (0x0004u) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */
424 #define ADC10HIIE (0x0008u) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */
425 #define ADC10OVIE (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt enable */
426 #define ADC10TOVIE (0x0020u) /* ADC10_A conversion-time-overflow Interrupt enable */
427 
428 /* ADC10IE Interrupt Enable Bits */
429 #define ADC10IE0_L (0x0001u) /* ADC10_A Interrupt enable */
430 #define ADC10INIE_L (0x0002u) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */
431 #define ADC10LOIE_L (0x0004u) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */
432 #define ADC10HIIE_L (0x0008u) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */
433 #define ADC10OVIE_L (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt enable */
434 #define ADC10TOVIE_L (0x0020u) /* ADC10_A conversion-time-overflow Interrupt enable */
435 
436 /* ADC10IFG Interrupt Flag Bits */
437 #define ADC10IFG0 (0x0001u) /* ADC10_A Interrupt Flag */
438 #define ADC10INIFG (0x0002u) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */
439 #define ADC10LOIFG (0x0004u) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */
440 #define ADC10HIIFG (0x0008u) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */
441 #define ADC10OVIFG (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt Flag */
442 #define ADC10TOVIFG (0x0020u) /* ADC10_A conversion-time-overflow Interrupt Flag */
443 
444 /* ADC10IFG Interrupt Flag Bits */
445 #define ADC10IFG0_L (0x0001u) /* ADC10_A Interrupt Flag */
446 #define ADC10INIFG_L (0x0002u) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */
447 #define ADC10LOIFG_L (0x0004u) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */
448 #define ADC10HIIFG_L (0x0008u) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */
449 #define ADC10OVIFG_L (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt Flag */
450 #define ADC10TOVIFG_L (0x0020u) /* ADC10_A conversion-time-overflow Interrupt Flag */
451 
452 /* ADC10IV Definitions */
453 #define ADC10IV_NONE (0x0000u) /* No Interrupt pending */
454 #define ADC10IV_ADC10OVIFG (0x0002u) /* ADC10OVIFG */
455 #define ADC10IV_ADC10TOVIFG (0x0004u) /* ADC10TOVIFG */
456 #define ADC10IV_ADC10HIIFG (0x0006u) /* ADC10HIIFG */
457 #define ADC10IV_ADC10LOIFG (0x0008u) /* ADC10LOIFG */
458 #define ADC10IV_ADC10INIFG (0x000Au) /* ADC10INIFG */
459 #define ADC10IV_ADC10IFG (0x000Cu) /* ADC10IFG */
460 
461 #endif
462 /************************************************************
463 * ADC12 PLUS
464 ************************************************************/
465 #ifdef __MSP430_HAS_ADC12_PLUS__ /* Definition to show that Module is available */
466 
467 #define OFS_ADC12CTL0 (0x0000u) /* ADC12+ Control 0 */
468 #define OFS_ADC12CTL0_L OFS_ADC12CTL0
469 #define OFS_ADC12CTL0_H OFS_ADC12CTL0+1
470 #define OFS_ADC12CTL1 (0x0002u) /* ADC12+ Control 1 */
471 #define OFS_ADC12CTL1_L OFS_ADC12CTL1
472 #define OFS_ADC12CTL1_H OFS_ADC12CTL1+1
473 #define OFS_ADC12CTL2 (0x0004u) /* ADC12+ Control 2 */
474 #define OFS_ADC12CTL2_L OFS_ADC12CTL2
475 #define OFS_ADC12CTL2_H OFS_ADC12CTL2+1
476 #define OFS_ADC12IFG (0x000Au) /* ADC12+ Interrupt Flag */
477 #define OFS_ADC12IFG_L OFS_ADC12IFG
478 #define OFS_ADC12IFG_H OFS_ADC12IFG+1
479 #define OFS_ADC12IE (0x000Cu) /* ADC12+ Interrupt Enable */
480 #define OFS_ADC12IE_L OFS_ADC12IE
481 #define OFS_ADC12IE_H OFS_ADC12IE+1
482 #define OFS_ADC12IV (0x000Eu) /* ADC12+ Interrupt Vector Word */
483 #define OFS_ADC12IV_L OFS_ADC12IV
484 #define OFS_ADC12IV_H OFS_ADC12IV+1
485 
486 #define OFS_ADC12MEM0 (0x0020u) /* ADC12 Conversion Memory 0 */
487 #define OFS_ADC12MEM0_L OFS_ADC12MEM0
488 #define OFS_ADC12MEM0_H OFS_ADC12MEM0+1
489 #define OFS_ADC12MEM1 (0x0022u) /* ADC12 Conversion Memory 1 */
490 #define OFS_ADC12MEM1_L OFS_ADC12MEM1
491 #define OFS_ADC12MEM1_H OFS_ADC12MEM1+1
492 #define OFS_ADC12MEM2 (0x0024u) /* ADC12 Conversion Memory 2 */
493 #define OFS_ADC12MEM2_L OFS_ADC12MEM2
494 #define OFS_ADC12MEM2_H OFS_ADC12MEM2+1
495 #define OFS_ADC12MEM3 (0x0026u) /* ADC12 Conversion Memory 3 */
496 #define OFS_ADC12MEM3_L OFS_ADC12MEM3
497 #define OFS_ADC12MEM3_H OFS_ADC12MEM3+1
498 #define OFS_ADC12MEM4 (0x0028u) /* ADC12 Conversion Memory 4 */
499 #define OFS_ADC12MEM4_L OFS_ADC12MEM4
500 #define OFS_ADC12MEM4_H OFS_ADC12MEM4+1
501 #define OFS_ADC12MEM5 (0x002Au) /* ADC12 Conversion Memory 5 */
502 #define OFS_ADC12MEM5_L OFS_ADC12MEM5
503 #define OFS_ADC12MEM5_H OFS_ADC12MEM5+1
504 #define OFS_ADC12MEM6 (0x002Cu) /* ADC12 Conversion Memory 6 */
505 #define OFS_ADC12MEM6_L OFS_ADC12MEM6
506 #define OFS_ADC12MEM6_H OFS_ADC12MEM6+1
507 #define OFS_ADC12MEM7 (0x002Eu) /* ADC12 Conversion Memory 7 */
508 #define OFS_ADC12MEM7_L OFS_ADC12MEM7
509 #define OFS_ADC12MEM7_H OFS_ADC12MEM7+1
510 #define OFS_ADC12MEM8 (0x0030u) /* ADC12 Conversion Memory 8 */
511 #define OFS_ADC12MEM8_L OFS_ADC12MEM8
512 #define OFS_ADC12MEM8_H OFS_ADC12MEM8+1
513 #define OFS_ADC12MEM9 (0x0032u) /* ADC12 Conversion Memory 9 */
514 #define OFS_ADC12MEM9_L OFS_ADC12MEM9
515 #define OFS_ADC12MEM9_H OFS_ADC12MEM9+1
516 #define OFS_ADC12MEM10 (0x0034u) /* ADC12 Conversion Memory 10 */
517 #define OFS_ADC12MEM10_L OFS_ADC12MEM10
518 #define OFS_ADC12MEM10_H OFS_ADC12MEM10+1
519 #define OFS_ADC12MEM11 (0x0036u) /* ADC12 Conversion Memory 11 */
520 #define OFS_ADC12MEM11_L OFS_ADC12MEM11
521 #define OFS_ADC12MEM11_H OFS_ADC12MEM11+1
522 #define OFS_ADC12MEM12 (0x0038u) /* ADC12 Conversion Memory 12 */
523 #define OFS_ADC12MEM12_L OFS_ADC12MEM12
524 #define OFS_ADC12MEM12_H OFS_ADC12MEM12+1
525 #define OFS_ADC12MEM13 (0x003Au) /* ADC12 Conversion Memory 13 */
526 #define OFS_ADC12MEM13_L OFS_ADC12MEM13
527 #define OFS_ADC12MEM13_H OFS_ADC12MEM13+1
528 #define OFS_ADC12MEM14 (0x003Cu) /* ADC12 Conversion Memory 14 */
529 #define OFS_ADC12MEM14_L OFS_ADC12MEM14
530 #define OFS_ADC12MEM14_H OFS_ADC12MEM14+1
531 #define OFS_ADC12MEM15 (0x003Eu) /* ADC12 Conversion Memory 15 */
532 #define OFS_ADC12MEM15_L OFS_ADC12MEM15
533 #define OFS_ADC12MEM15_H OFS_ADC12MEM15+1
534 #define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */
535 #ifndef __IAR_SYSTEMS_ICC__
536 #define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */
537 #else
538 #define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
539 #endif
540 
541 #define OFS_ADC12MCTL0 (0x0010u) /* ADC12 Memory Control 0 */
542 #define OFS_ADC12MCTL1 (0x0011u) /* ADC12 Memory Control 1 */
543 #define OFS_ADC12MCTL2 (0x0012u) /* ADC12 Memory Control 2 */
544 #define OFS_ADC12MCTL3 (0x0013u) /* ADC12 Memory Control 3 */
545 #define OFS_ADC12MCTL4 (0x0014u) /* ADC12 Memory Control 4 */
546 #define OFS_ADC12MCTL5 (0x0015u) /* ADC12 Memory Control 5 */
547 #define OFS_ADC12MCTL6 (0x0016u) /* ADC12 Memory Control 6 */
548 #define OFS_ADC12MCTL7 (0x0017u) /* ADC12 Memory Control 7 */
549 #define OFS_ADC12MCTL8 (0x0018u) /* ADC12 Memory Control 8 */
550 #define OFS_ADC12MCTL9 (0x0019u) /* ADC12 Memory Control 9 */
551 #define OFS_ADC12MCTL10 (0x001Au) /* ADC12 Memory Control 10 */
552 #define OFS_ADC12MCTL11 (0x001Bu) /* ADC12 Memory Control 11 */
553 #define OFS_ADC12MCTL12 (0x001Cu) /* ADC12 Memory Control 12 */
554 #define OFS_ADC12MCTL13 (0x001Du) /* ADC12 Memory Control 13 */
555 #define OFS_ADC12MCTL14 (0x001Eu) /* ADC12 Memory Control 14 */
556 #define OFS_ADC12MCTL15 (0x001Fu) /* ADC12 Memory Control 15 */
557 #define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */
558 #ifndef __IAR_SYSTEMS_ICC__
559 #define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */
560 #else
561 #define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */
562 #endif
563 
564 /* ADC12CTL0 Control Bits */
565 #define ADC12SC (0x0001u) /* ADC12 Start Conversion */
566 #define ADC12ENC (0x0002u) /* ADC12 Enable Conversion */
567 #define ADC12TOVIE (0x0004u) /* ADC12 Timer Overflow interrupt enable */
568 #define ADC12OVIE (0x0008u) /* ADC12 Overflow interrupt enable */
569 #define ADC12ON (0x0010u) /* ADC12 On/enable */
570 #define ADC12REFON (0x0020u) /* ADC12 Reference on */
571 #define ADC12REF2_5V (0x0040u) /* ADC12 Ref 0:1.5V / 1:2.5V */
572 #define ADC12MSC (0x0080u) /* ADC12 Multiple SampleConversion */
573 #define ADC12SHT00 (0x0100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
574 #define ADC12SHT01 (0x0200u) /* ADC12 Sample Hold 0 Select Bit: 1 */
575 #define ADC12SHT02 (0x0400u) /* ADC12 Sample Hold 0 Select Bit: 2 */
576 #define ADC12SHT03 (0x0800u) /* ADC12 Sample Hold 0 Select Bit: 3 */
577 #define ADC12SHT10 (0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
578 #define ADC12SHT11 (0x2000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
579 #define ADC12SHT12 (0x4000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
580 #define ADC12SHT13 (0x8000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
581 
582 /* ADC12CTL0 Control Bits */
583 #define ADC12SC_L (0x0001u) /* ADC12 Start Conversion */
584 #define ADC12ENC_L (0x0002u) /* ADC12 Enable Conversion */
585 #define ADC12TOVIE_L (0x0004u) /* ADC12 Timer Overflow interrupt enable */
586 #define ADC12OVIE_L (0x0008u) /* ADC12 Overflow interrupt enable */
587 #define ADC12ON_L (0x0010u) /* ADC12 On/enable */
588 #define ADC12REFON_L (0x0020u) /* ADC12 Reference on */
589 #define ADC12REF2_5V_L (0x0040u) /* ADC12 Ref 0:1.5V / 1:2.5V */
590 #define ADC12MSC_L (0x0080u) /* ADC12 Multiple SampleConversion */
591 
592 /* ADC12CTL0 Control Bits */
593 #define ADC12SHT00_H (0x0001u) /* ADC12 Sample Hold 0 Select Bit: 0 */
594 #define ADC12SHT01_H (0x0002u) /* ADC12 Sample Hold 0 Select Bit: 1 */
595 #define ADC12SHT02_H (0x0004u) /* ADC12 Sample Hold 0 Select Bit: 2 */
596 #define ADC12SHT03_H (0x0008u) /* ADC12 Sample Hold 0 Select Bit: 3 */
597 #define ADC12SHT10_H (0x0010u) /* ADC12 Sample Hold 1 Select Bit: 0 */
598 #define ADC12SHT11_H (0x0020u) /* ADC12 Sample Hold 1 Select Bit: 1 */
599 #define ADC12SHT12_H (0x0040u) /* ADC12 Sample Hold 1 Select Bit: 2 */
600 #define ADC12SHT13_H (0x0080u) /* ADC12 Sample Hold 1 Select Bit: 3 */
601 
602 #define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
603 #define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */
604 #define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */
605 #define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */
606 #define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */
607 #define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */
608 #define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */
609 #define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */
610 #define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */
611 #define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */
612 #define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */
613 #define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */
614 #define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */
615 #define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */
616 #define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */
617 #define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */
618 
619 #define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
620 #define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
621 #define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
622 #define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
623 #define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */
624 #define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */
625 #define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */
626 #define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */
627 #define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */
628 #define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */
629 #define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */
630 #define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */
631 #define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */
632 #define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */
633 #define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */
634 #define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */
635 
636 /* ADC12CTL1 Control Bits */
637 #define ADC12BUSY (0x0001u) /* ADC12 Busy */
638 #define ADC12CONSEQ0 (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */
639 #define ADC12CONSEQ1 (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */
640 #define ADC12SSEL0 (0x0008u) /* ADC12 Clock Source Select Bit: 0 */
641 #define ADC12SSEL1 (0x0010u) /* ADC12 Clock Source Select Bit: 1 */
642 #define ADC12DIV0 (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */
643 #define ADC12DIV1 (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */
644 #define ADC12DIV2 (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */
645 #define ADC12ISSH (0x0100u) /* ADC12 Invert Sample Hold Signal */
646 #define ADC12SHP (0x0200u) /* ADC12 Sample/Hold Pulse Mode */
647 #define ADC12SHS0 (0x0400u) /* ADC12 Sample/Hold Source Bit: 0 */
648 #define ADC12SHS1 (0x0800u) /* ADC12 Sample/Hold Source Bit: 1 */
649 #define ADC12CSTARTADD0 (0x1000u) /* ADC12 Conversion Start Address Bit: 0 */
650 #define ADC12CSTARTADD1 (0x2000u) /* ADC12 Conversion Start Address Bit: 1 */
651 #define ADC12CSTARTADD2 (0x4000u) /* ADC12 Conversion Start Address Bit: 2 */
652 #define ADC12CSTARTADD3 (0x8000u) /* ADC12 Conversion Start Address Bit: 3 */
653 
654 /* ADC12CTL1 Control Bits */
655 #define ADC12BUSY_L (0x0001u) /* ADC12 Busy */
656 #define ADC12CONSEQ0_L (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */
657 #define ADC12CONSEQ1_L (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */
658 #define ADC12SSEL0_L (0x0008u) /* ADC12 Clock Source Select Bit: 0 */
659 #define ADC12SSEL1_L (0x0010u) /* ADC12 Clock Source Select Bit: 1 */
660 #define ADC12DIV0_L (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */
661 #define ADC12DIV1_L (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */
662 #define ADC12DIV2_L (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */
663 
664 /* ADC12CTL1 Control Bits */
665 #define ADC12ISSH_H (0x0001u) /* ADC12 Invert Sample Hold Signal */
666 #define ADC12SHP_H (0x0002u) /* ADC12 Sample/Hold Pulse Mode */
667 #define ADC12SHS0_H (0x0004u) /* ADC12 Sample/Hold Source Bit: 0 */
668 #define ADC12SHS1_H (0x0008u) /* ADC12 Sample/Hold Source Bit: 1 */
669 #define ADC12CSTARTADD0_H (0x0010u) /* ADC12 Conversion Start Address Bit: 0 */
670 #define ADC12CSTARTADD1_H (0x0020u) /* ADC12 Conversion Start Address Bit: 1 */
671 #define ADC12CSTARTADD2_H (0x0040u) /* ADC12 Conversion Start Address Bit: 2 */
672 #define ADC12CSTARTADD3_H (0x0080u) /* ADC12 Conversion Start Address Bit: 3 */
673 
674 #define ADC12CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */
675 #define ADC12CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */
676 #define ADC12CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */
677 #define ADC12CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */
678 
679 #define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */
680 #define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */
681 #define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */
682 #define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */
683 
684 #define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */
685 #define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */
686 #define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */
687 #define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */
688 #define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */
689 #define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */
690 #define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */
691 #define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */
692 
693 #define ADC12SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */
694 #define ADC12SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */
695 #define ADC12SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */
696 #define ADC12SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */
697 
698 #define ADC12CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */
699 #define ADC12CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */
700 #define ADC12CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */
701 #define ADC12CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */
702 #define ADC12CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */
703 #define ADC12CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */
704 #define ADC12CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */
705 #define ADC12CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */
706 #define ADC12CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */
707 #define ADC12CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */
708 #define ADC12CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */
709 #define ADC12CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */
710 #define ADC12CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */
711 #define ADC12CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */
712 #define ADC12CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */
713 #define ADC12CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 */
714 
715 /* ADC12CTL2 Control Bits */
716 #define ADC12REFBURST (0x0001u) /* ADC12+ Reference Burst */
717 #define ADC12REFOUT (0x0002u) /* ADC12+ Reference Out */
718 #define ADC12SR (0x0004u) /* ADC12+ Sampling Rate */
719 #define ADC12DF (0x0008u) /* ADC12+ Data Format */
720 #define ADC12RES0 (0x0010u) /* ADC12+ Resolution Bit: 0 */
721 #define ADC12RES1 (0x0020u) /* ADC12+ Resolution Bit: 1 */
722 #define ADC12TCOFF (0x0080u) /* ADC12+ Temperature Sensor Off */
723 #define ADC12PDIV (0x0100u) /* ADC12+ predivider 0:/1 1:/4 */
724 
725 /* ADC12CTL2 Control Bits */
726 #define ADC12REFBURST_L (0x0001u) /* ADC12+ Reference Burst */
727 #define ADC12REFOUT_L (0x0002u) /* ADC12+ Reference Out */
728 #define ADC12SR_L (0x0004u) /* ADC12+ Sampling Rate */
729 #define ADC12DF_L (0x0008u) /* ADC12+ Data Format */
730 #define ADC12RES0_L (0x0010u) /* ADC12+ Resolution Bit: 0 */
731 #define ADC12RES1_L (0x0020u) /* ADC12+ Resolution Bit: 1 */
732 #define ADC12TCOFF_L (0x0080u) /* ADC12+ Temperature Sensor Off */
733 
734 /* ADC12CTL2 Control Bits */
735 #define ADC12PDIV_H (0x0001u) /* ADC12+ predivider 0:/1 1:/4 */
736 
737 #define ADC12RES_0 (0x0000u) /* ADC12+ Resolution : 8 Bit */
738 #define ADC12RES_1 (0x0010u) /* ADC12+ Resolution : 10 Bit */
739 #define ADC12RES_2 (0x0020u) /* ADC12+ Resolution : 12 Bit */
740 #define ADC12RES_3 (0x0030u) /* ADC12+ Resolution : reserved */
741 
742 /* ADC12MCTLx Control Bits */
743 #define ADC12INCH0 (0x0001u) /* ADC12 Input Channel Select Bit 0 */
744 #define ADC12INCH1 (0x0002u) /* ADC12 Input Channel Select Bit 1 */
745 #define ADC12INCH2 (0x0004u) /* ADC12 Input Channel Select Bit 2 */
746 #define ADC12INCH3 (0x0008u) /* ADC12 Input Channel Select Bit 3 */
747 #define ADC12SREF0 (0x0010u) /* ADC12 Select Reference Bit 0 */
748 #define ADC12SREF1 (0x0020u) /* ADC12 Select Reference Bit 1 */
749 #define ADC12SREF2 (0x0040u) /* ADC12 Select Reference Bit 2 */
750 #define ADC12EOS (0x0080u) /* ADC12 End of Sequence */
751 
752 #define ADC12INCH_0 (0x0000u) /* ADC12 Input Channel 0 */
753 #define ADC12INCH_1 (0x0001u) /* ADC12 Input Channel 1 */
754 #define ADC12INCH_2 (0x0002u) /* ADC12 Input Channel 2 */
755 #define ADC12INCH_3 (0x0003u) /* ADC12 Input Channel 3 */
756 #define ADC12INCH_4 (0x0004u) /* ADC12 Input Channel 4 */
757 #define ADC12INCH_5 (0x0005u) /* ADC12 Input Channel 5 */
758 #define ADC12INCH_6 (0x0006u) /* ADC12 Input Channel 6 */
759 #define ADC12INCH_7 (0x0007u) /* ADC12 Input Channel 7 */
760 #define ADC12INCH_8 (0x0008u) /* ADC12 Input Channel 8 */
761 #define ADC12INCH_9 (0x0009u) /* ADC12 Input Channel 9 */
762 #define ADC12INCH_10 (0x000Au) /* ADC12 Input Channel 10 */
763 #define ADC12INCH_11 (0x000Bu) /* ADC12 Input Channel 11 */
764 #define ADC12INCH_12 (0x000Cu) /* ADC12 Input Channel 12 */
765 #define ADC12INCH_13 (0x000Du) /* ADC12 Input Channel 13 */
766 #define ADC12INCH_14 (0x000Eu) /* ADC12 Input Channel 14 */
767 #define ADC12INCH_15 (0x000Fu) /* ADC12 Input Channel 15 */
768 
769 #define ADC12SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */
770 #define ADC12SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */
771 #define ADC12SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */
772 #define ADC12SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */
773 #define ADC12SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */
774 #define ADC12SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */
775 #define ADC12SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */
776 #define ADC12SREF_7 (7*0x10u) /* ADC12 Select Reference 7 */
777 
778 #define ADC12IE0 (0x0001u) /* ADC12 Memory 0 Interrupt Enable */
779 #define ADC12IE1 (0x0002u) /* ADC12 Memory 1 Interrupt Enable */
780 #define ADC12IE2 (0x0004u) /* ADC12 Memory 2 Interrupt Enable */
781 #define ADC12IE3 (0x0008u) /* ADC12 Memory 3 Interrupt Enable */
782 #define ADC12IE4 (0x0010u) /* ADC12 Memory 4 Interrupt Enable */
783 #define ADC12IE5 (0x0020u) /* ADC12 Memory 5 Interrupt Enable */
784 #define ADC12IE6 (0x0040u) /* ADC12 Memory 6 Interrupt Enable */
785 #define ADC12IE7 (0x0080u) /* ADC12 Memory 7 Interrupt Enable */
786 #define ADC12IE8 (0x0100u) /* ADC12 Memory 8 Interrupt Enable */
787 #define ADC12IE9 (0x0200u) /* ADC12 Memory 9 Interrupt Enable */
788 #define ADC12IE10 (0x0400u) /* ADC12 Memory 10 Interrupt Enable */
789 #define ADC12IE11 (0x0800u) /* ADC12 Memory 11 Interrupt Enable */
790 #define ADC12IE12 (0x1000u) /* ADC12 Memory 12 Interrupt Enable */
791 #define ADC12IE13 (0x2000u) /* ADC12 Memory 13 Interrupt Enable */
792 #define ADC12IE14 (0x4000u) /* ADC12 Memory 14 Interrupt Enable */
793 #define ADC12IE15 (0x8000u) /* ADC12 Memory 15 Interrupt Enable */
794 
795 #define ADC12IE0_L (0x0001u) /* ADC12 Memory 0 Interrupt Enable */
796 #define ADC12IE1_L (0x0002u) /* ADC12 Memory 1 Interrupt Enable */
797 #define ADC12IE2_L (0x0004u) /* ADC12 Memory 2 Interrupt Enable */
798 #define ADC12IE3_L (0x0008u) /* ADC12 Memory 3 Interrupt Enable */
799 #define ADC12IE4_L (0x0010u) /* ADC12 Memory 4 Interrupt Enable */
800 #define ADC12IE5_L (0x0020u) /* ADC12 Memory 5 Interrupt Enable */
801 #define ADC12IE6_L (0x0040u) /* ADC12 Memory 6 Interrupt Enable */
802 #define ADC12IE7_L (0x0080u) /* ADC12 Memory 7 Interrupt Enable */
803 
804 #define ADC12IE8_H (0x0001u) /* ADC12 Memory 8 Interrupt Enable */
805 #define ADC12IE9_H (0x0002u) /* ADC12 Memory 9 Interrupt Enable */
806 #define ADC12IE10_H (0x0004u) /* ADC12 Memory 10 Interrupt Enable */
807 #define ADC12IE11_H (0x0008u) /* ADC12 Memory 11 Interrupt Enable */
808 #define ADC12IE12_H (0x0010u) /* ADC12 Memory 12 Interrupt Enable */
809 #define ADC12IE13_H (0x0020u) /* ADC12 Memory 13 Interrupt Enable */
810 #define ADC12IE14_H (0x0040u) /* ADC12 Memory 14 Interrupt Enable */
811 #define ADC12IE15_H (0x0080u) /* ADC12 Memory 15 Interrupt Enable */
812 
813 #define ADC12IFG0 (0x0001u) /* ADC12 Memory 0 Interrupt Flag */
814 #define ADC12IFG1 (0x0002u) /* ADC12 Memory 1 Interrupt Flag */
815 #define ADC12IFG2 (0x0004u) /* ADC12 Memory 2 Interrupt Flag */
816 #define ADC12IFG3 (0x0008u) /* ADC12 Memory 3 Interrupt Flag */
817 #define ADC12IFG4 (0x0010u) /* ADC12 Memory 4 Interrupt Flag */
818 #define ADC12IFG5 (0x0020u) /* ADC12 Memory 5 Interrupt Flag */
819 #define ADC12IFG6 (0x0040u) /* ADC12 Memory 6 Interrupt Flag */
820 #define ADC12IFG7 (0x0080u) /* ADC12 Memory 7 Interrupt Flag */
821 #define ADC12IFG8 (0x0100u) /* ADC12 Memory 8 Interrupt Flag */
822 #define ADC12IFG9 (0x0200u) /* ADC12 Memory 9 Interrupt Flag */
823 #define ADC12IFG10 (0x0400u) /* ADC12 Memory 10 Interrupt Flag */
824 #define ADC12IFG11 (0x0800u) /* ADC12 Memory 11 Interrupt Flag */
825 #define ADC12IFG12 (0x1000u) /* ADC12 Memory 12 Interrupt Flag */
826 #define ADC12IFG13 (0x2000u) /* ADC12 Memory 13 Interrupt Flag */
827 #define ADC12IFG14 (0x4000u) /* ADC12 Memory 14 Interrupt Flag */
828 #define ADC12IFG15 (0x8000u) /* ADC12 Memory 15 Interrupt Flag */
829 
830 #define ADC12IFG0_L (0x0001u) /* ADC12 Memory 0 Interrupt Flag */
831 #define ADC12IFG1_L (0x0002u) /* ADC12 Memory 1 Interrupt Flag */
832 #define ADC12IFG2_L (0x0004u) /* ADC12 Memory 2 Interrupt Flag */
833 #define ADC12IFG3_L (0x0008u) /* ADC12 Memory 3 Interrupt Flag */
834 #define ADC12IFG4_L (0x0010u) /* ADC12 Memory 4 Interrupt Flag */
835 #define ADC12IFG5_L (0x0020u) /* ADC12 Memory 5 Interrupt Flag */
836 #define ADC12IFG6_L (0x0040u) /* ADC12 Memory 6 Interrupt Flag */
837 #define ADC12IFG7_L (0x0080u) /* ADC12 Memory 7 Interrupt Flag */
838 
839 #define ADC12IFG8_H (0x0001u) /* ADC12 Memory 8 Interrupt Flag */
840 #define ADC12IFG9_H (0x0002u) /* ADC12 Memory 9 Interrupt Flag */
841 #define ADC12IFG10_H (0x0004u) /* ADC12 Memory 10 Interrupt Flag */
842 #define ADC12IFG11_H (0x0008u) /* ADC12 Memory 11 Interrupt Flag */
843 #define ADC12IFG12_H (0x0010u) /* ADC12 Memory 12 Interrupt Flag */
844 #define ADC12IFG13_H (0x0020u) /* ADC12 Memory 13 Interrupt Flag */
845 #define ADC12IFG14_H (0x0040u) /* ADC12 Memory 14 Interrupt Flag */
846 #define ADC12IFG15_H (0x0080u) /* ADC12 Memory 15 Interrupt Flag */
847 
848 /* ADC12IV Definitions */
849 #define ADC12IV_NONE (0x0000u) /* No Interrupt pending */
850 #define ADC12IV_ADC12OVIFG (0x0002u) /* ADC12OVIFG */
851 #define ADC12IV_ADC12TOVIFG (0x0004u) /* ADC12TOVIFG */
852 #define ADC12IV_ADC12IFG0 (0x0006u) /* ADC12IFG0 */
853 #define ADC12IV_ADC12IFG1 (0x0008u) /* ADC12IFG1 */
854 #define ADC12IV_ADC12IFG2 (0x000Au) /* ADC12IFG2 */
855 #define ADC12IV_ADC12IFG3 (0x000Cu) /* ADC12IFG3 */
856 #define ADC12IV_ADC12IFG4 (0x000Eu) /* ADC12IFG4 */
857 #define ADC12IV_ADC12IFG5 (0x0010u) /* ADC12IFG5 */
858 #define ADC12IV_ADC12IFG6 (0x0012u) /* ADC12IFG6 */
859 #define ADC12IV_ADC12IFG7 (0x0014u) /* ADC12IFG7 */
860 #define ADC12IV_ADC12IFG8 (0x0016u) /* ADC12IFG8 */
861 #define ADC12IV_ADC12IFG9 (0x0018u) /* ADC12IFG9 */
862 #define ADC12IV_ADC12IFG10 (0x001Au) /* ADC12IFG10 */
863 #define ADC12IV_ADC12IFG11 (0x001Cu) /* ADC12IFG11 */
864 #define ADC12IV_ADC12IFG12 (0x001Eu) /* ADC12IFG12 */
865 #define ADC12IV_ADC12IFG13 (0x0020u) /* ADC12IFG13 */
866 #define ADC12IV_ADC12IFG14 (0x0022u) /* ADC12IFG14 */
867 #define ADC12IV_ADC12IFG15 (0x0024u) /* ADC12IFG15 */
868 
869 #endif
870 /************************************************************
871 * AES Accelerator
872 ************************************************************/
873 #ifdef __MSP430_HAS_AES__ /* Definition to show that Module is available */
874 
875 #define OFS_AESACTL0 (0x0000u) /* AES accelerator control register 0 */
876 #define OFS_AESACTL0_L OFS_AESACTL0
877 #define OFS_AESACTL0_H OFS_AESACTL0+1
878 #define OFS_AESASTAT (0x0004u) /* AES accelerator status register */
879 #define OFS_AESASTAT_L OFS_AESASTAT
880 #define OFS_AESASTAT_H OFS_AESASTAT+1
881 #define OFS_AESAKEY (0x0006u) /* AES accelerator key register */
882 #define OFS_AESAKEY_L OFS_AESAKEY
883 #define OFS_AESAKEY_H OFS_AESAKEY+1
884 #define OFS_AESADIN (0x0008u) /* AES accelerator data in register */
885 #define OFS_AESADIN_L OFS_AESADIN
886 #define OFS_AESADIN_H OFS_AESADIN+1
887 #define OFS_AESADOUT (0x000Au) /* AES accelerator data out register */
888 #define OFS_AESADOUT_L OFS_AESADOUT
889 #define OFS_AESADOUT_H OFS_AESADOUT+1
890 
891 /* AESACTL0 Control Bits */
892 #define AESOP0 (0x0001u) /* AES Operation Bit: 0 */
893 #define AESOP1 (0x0002u) /* AES Operation Bit: 1 */
894 #define AESSWRST (0x0080u) /* AES Software Reset */
895 #define AESRDYIFG (0x0100u) /* AES ready interrupt flag */
896 #define AESERRFG (0x0800u) /* AES Error Flag */
897 #define AESRDYIE (0x1000u) /* AES ready interrupt enable*/
898 
899 /* AESACTL0 Control Bits */
900 #define AESOP0_L (0x0001u) /* AES Operation Bit: 0 */
901 #define AESOP1_L (0x0002u) /* AES Operation Bit: 1 */
902 #define AESSWRST_L (0x0080u) /* AES Software Reset */
903 
904 /* AESACTL0 Control Bits */
905 #define AESRDYIFG_H (0x0001u) /* AES ready interrupt flag */
906 #define AESERRFG_H (0x0008u) /* AES Error Flag */
907 #define AESRDYIE_H (0x0010u) /* AES ready interrupt enable*/
908 
909 #define AESOP_0 (0x0000u) /* AES Operation: Encrypt */
910 #define AESOP_1 (0x0001u) /* AES Operation: Decrypt (same Key) */
911 #define AESOP_2 (0x0002u) /* AES Operation: Decrypt (frist round Key) */
912 #define AESOP_3 (0x0003u) /* AES Operation: Generate first round Key */
913 
914 /* AESASTAT Control Bits */
915 #define AESBUSY (0x0001u) /* AES Busy */
916 #define AESKEYWR (0x0002u) /* AES All 16 bytes written to AESAKEY */
917 #define AESDINWR (0x0004u) /* AES All 16 bytes written to AESADIN */
918 #define AESDOUTRD (0x0008u) /* AES All 16 bytes read from AESADOUT */
919 #define AESKEYCNT0 (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */
920 #define AESKEYCNT1 (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */
921 #define AESKEYCNT2 (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */
922 #define AESKEYCNT3 (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */
923 #define AESDINCNT0 (0x0100u) /* AES Bytes written via AESADIN Bit: 0 */
924 #define AESDINCNT1 (0x0200u) /* AES Bytes written via AESADIN Bit: 1 */
925 #define AESDINCNT2 (0x0400u) /* AES Bytes written via AESADIN Bit: 2 */
926 #define AESDINCNT3 (0x0800u) /* AES Bytes written via AESADIN Bit: 3 */
927 #define AESDOUTCNT0 (0x1000u) /* AES Bytes read via AESADOUT Bit: 0 */
928 #define AESDOUTCNT1 (0x2000u) /* AES Bytes read via AESADOUT Bit: 1 */
929 #define AESDOUTCNT2 (0x4000u) /* AES Bytes read via AESADOUT Bit: 2 */
930 #define AESDOUTCNT3 (0x8000u) /* AES Bytes read via AESADOUT Bit: 3 */
931 
932 /* AESASTAT Control Bits */
933 #define AESBUSY_L (0x0001u) /* AES Busy */
934 #define AESKEYWR_L (0x0002u) /* AES All 16 bytes written to AESAKEY */
935 #define AESDINWR_L (0x0004u) /* AES All 16 bytes written to AESADIN */
936 #define AESDOUTRD_L (0x0008u) /* AES All 16 bytes read from AESADOUT */
937 #define AESKEYCNT0_L (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */
938 #define AESKEYCNT1_L (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */
939 #define AESKEYCNT2_L (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */
940 #define AESKEYCNT3_L (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */
941 
942 /* AESASTAT Control Bits */
943 #define AESDINCNT0_H (0x0001u) /* AES Bytes written via AESADIN Bit: 0 */
944 #define AESDINCNT1_H (0x0002u) /* AES Bytes written via AESADIN Bit: 1 */
945 #define AESDINCNT2_H (0x0004u) /* AES Bytes written via AESADIN Bit: 2 */
946 #define AESDINCNT3_H (0x0008u) /* AES Bytes written via AESADIN Bit: 3 */
947 #define AESDOUTCNT0_H (0x0010u) /* AES Bytes read via AESADOUT Bit: 0 */
948 #define AESDOUTCNT1_H (0x0020u) /* AES Bytes read via AESADOUT Bit: 1 */
949 #define AESDOUTCNT2_H (0x0040u) /* AES Bytes read via AESADOUT Bit: 2 */
950 #define AESDOUTCNT3_H (0x0080u) /* AES Bytes read via AESADOUT Bit: 3 */
951 
952 #endif
953 /*************************************************************
954 * Backup RAM Module
955 *************************************************************/
956 #ifdef __MSP430_HAS_BACKUP_RAM__ /* Definition to show that Module is available */
957 
958 #define OFS_BAKMEM0 (0x0000u) /* Battery Backup Memory 0 */
959 #define OFS_BAKMEM0_L OFS_BAKMEM0
960 #define OFS_BAKMEM0_H OFS_BAKMEM0+1
961 #define OFS_BAKMEM1 (0x0002u) /* Battery Backup Memory 0 */
962 #define OFS_BAKMEM1_L OFS_BAKMEM1
963 #define OFS_BAKMEM1_H OFS_BAKMEM1+1
964 #define OFS_BAKMEM2 (0x0004u) /* Battery Backup Memory 0 */
965 #define OFS_BAKMEM2_L OFS_BAKMEM2
966 #define OFS_BAKMEM2_H OFS_BAKMEM2+1
967 #define OFS_BAKMEM3 (0x0006u) /* Battery Backup Memory 0 */
968 #define OFS_BAKMEM3_L OFS_BAKMEM3
969 #define OFS_BAKMEM3_H OFS_BAKMEM3+1
970 
971 #endif
972 /*************************************************************
973 * Battery Charger Module
974 *************************************************************/
975 #ifdef __MSP430_HAS_BATTERY_CHARGER__ /* Definition to show that Module is available */
976 
977 #define OFS_BAKCTL (0x0000u) /* Battery Backup Control */
978 #define OFS_BAKCTL_L OFS_BAKCTL
979 #define OFS_BAKCTL_H OFS_BAKCTL+1
980 #define OFS_BAKCHCTL (0x0002u) /* Battery Charger Control */
981 #define OFS_BAKCHCTL_L OFS_BAKCHCTL
982 #define OFS_BAKCHCTL_H OFS_BAKCHCTL+1
983 
984 /* BAKCTL Control Bits */
985 #define LOCKBAK (0x0001u) /* Lock backup sub-system */
986 #define BAKSW (0x0002u) /* Manual switch to battery backup supply */
987 #define BAKADC (0x0004u) /* Battery backup supply to ADC. */
988 #define BAKDIS (0x0008u) /* Disable backup supply switching. */
989 
990 /* BAKCTL Control Bits */
991 #define LOCKBAK_L (0x0001u) /* Lock backup sub-system */
992 #define BAKSW_L (0x0002u) /* Manual switch to battery backup supply */
993 #define BAKADC_L (0x0004u) /* Battery backup supply to ADC. */
994 #define BAKDIS_L (0x0008u) /* Disable backup supply switching. */
995 
996 /* BAKCHCTL Control Bits */
997 #define CHEN (0x0001u) /* Charger enable */
998 #define CHC0 (0x0002u) /* Charger charge current Bit 0 */
999 #define CHC1 (0x0004u) /* Charger charge current Bit 1 */
1000 #define CHV0 (0x0010u) /* Charger end voltage Bit 0 */
1001 #define CHV1 (0x0020u) /* Charger end voltage Bit 1 */
1002 
1003 /* BAKCHCTL Control Bits */
1004 #define CHEN_L (0x0001u) /* Charger enable */
1005 #define CHC0_L (0x0002u) /* Charger charge current Bit 0 */
1006 #define CHC1_L (0x0004u) /* Charger charge current Bit 1 */
1007 #define CHV0_L (0x0010u) /* Charger end voltage Bit 0 */
1008 #define CHV1_L (0x0020u) /* Charger end voltage Bit 1 */
1009 
1010 #define CHPWD (0x6900u) /* Charger write password. */
1011 
1012 #endif
1013 /************************************************************
1014 * Comparator B
1015 ************************************************************/
1016 #ifdef __MSP430_HAS_COMPB__ /* Definition to show that Module is available */
1017 
1018 #define OFS_CBCTL0 (0x0000u) /* Comparator B Control Register 0 */
1019 #define OFS_CBCTL0_L OFS_CBCTL0
1020 #define OFS_CBCTL0_H OFS_CBCTL0+1
1021 #define OFS_CBCTL1 (0x0002u) /* Comparator B Control Register 1 */
1022 #define OFS_CBCTL1_L OFS_CBCTL1
1023 #define OFS_CBCTL1_H OFS_CBCTL1+1
1024 #define OFS_CBCTL2 (0x0004u) /* Comparator B Control Register 2 */
1025 #define OFS_CBCTL2_L OFS_CBCTL2
1026 #define OFS_CBCTL2_H OFS_CBCTL2+1
1027 #define OFS_CBCTL3 (0x0006u) /* Comparator B Control Register 3 */
1028 #define OFS_CBCTL3_L OFS_CBCTL3
1029 #define OFS_CBCTL3_H OFS_CBCTL3+1
1030 #define OFS_CBINT (0x000Cu) /* Comparator B Interrupt Register */
1031 #define OFS_CBINT_L OFS_CBINT
1032 #define OFS_CBINT_H OFS_CBINT+1
1033 #define OFS_CBIV (0x000Eu) /* Comparator B Interrupt Vector Word */
1034 
1035 /* CBCTL0 Control Bits */
1036 #define CBIPSEL0 (0x0001u) /* Comp. B Pos. Channel Input Select 0 */
1037 #define CBIPSEL1 (0x0002u) /* Comp. B Pos. Channel Input Select 1 */
1038 #define CBIPSEL2 (0x0004u) /* Comp. B Pos. Channel Input Select 2 */
1039 #define CBIPSEL3 (0x0008u) /* Comp. B Pos. Channel Input Select 3 */
1040 //#define RESERVED (0x0010u) /* Comp. B */
1041 //#define RESERVED (0x0020u) /* Comp. B */
1042 //#define RESERVED (0x0040u) /* Comp. B */
1043 #define CBIPEN (0x0080u) /* Comp. B Pos. Channel Input Enable */
1044 #define CBIMSEL0 (0x0100u) /* Comp. B Neg. Channel Input Select 0 */
1045 #define CBIMSEL1 (0x0200u) /* Comp. B Neg. Channel Input Select 1 */
1046 #define CBIMSEL2 (0x0400u) /* Comp. B Neg. Channel Input Select 2 */
1047 #define CBIMSEL3 (0x0800u) /* Comp. B Neg. Channel Input Select 3 */
1048 //#define RESERVED (0x1000u) /* Comp. B */
1049 //#define RESERVED (0x2000u) /* Comp. B */
1050 //#define RESERVED (0x4000u) /* Comp. B */
1051 #define CBIMEN (0x8000u) /* Comp. B Neg. Channel Input Enable */
1052 
1053 /* CBCTL0 Control Bits */
1054 #define CBIPSEL0_L (0x0001u) /* Comp. B Pos. Channel Input Select 0 */
1055 #define CBIPSEL1_L (0x0002u) /* Comp. B Pos. Channel Input Select 1 */
1056 #define CBIPSEL2_L (0x0004u) /* Comp. B Pos. Channel Input Select 2 */
1057 #define CBIPSEL3_L (0x0008u) /* Comp. B Pos. Channel Input Select 3 */
1058 //#define RESERVED (0x0010u) /* Comp. B */
1059 //#define RESERVED (0x0020u) /* Comp. B */
1060 //#define RESERVED (0x0040u) /* Comp. B */
1061 #define CBIPEN_L (0x0080u) /* Comp. B Pos. Channel Input Enable */
1062 //#define RESERVED (0x1000u) /* Comp. B */
1063 //#define RESERVED (0x2000u) /* Comp. B */
1064 //#define RESERVED (0x4000u) /* Comp. B */
1065 
1066 /* CBCTL0 Control Bits */
1067 //#define RESERVED (0x0010u) /* Comp. B */
1068 //#define RESERVED (0x0020u) /* Comp. B */
1069 //#define RESERVED (0x0040u) /* Comp. B */
1070 #define CBIMSEL0_H (0x0001u) /* Comp. B Neg. Channel Input Select 0 */
1071 #define CBIMSEL1_H (0x0002u) /* Comp. B Neg. Channel Input Select 1 */
1072 #define CBIMSEL2_H (0x0004u) /* Comp. B Neg. Channel Input Select 2 */
1073 #define CBIMSEL3_H (0x0008u) /* Comp. B Neg. Channel Input Select 3 */
1074 //#define RESERVED (0x1000u) /* Comp. B */
1075 //#define RESERVED (0x2000u) /* Comp. B */
1076 //#define RESERVED (0x4000u) /* Comp. B */
1077 #define CBIMEN_H (0x0080u) /* Comp. B Neg. Channel Input Enable */
1078 
1079 #define CBIPSEL_0 (0x0000u) /* Comp. B V+ terminal Input Select: Channel 0 */
1080 #define CBIPSEL_1 (0x0001u) /* Comp. B V+ terminal Input Select: Channel 1 */
1081 #define CBIPSEL_2 (0x0002u) /* Comp. B V+ terminal Input Select: Channel 2 */
1082 #define CBIPSEL_3 (0x0003u) /* Comp. B V+ terminal Input Select: Channel 3 */
1083 #define CBIPSEL_4 (0x0004u) /* Comp. B V+ terminal Input Select: Channel 4 */
1084 #define CBIPSEL_5 (0x0005u) /* Comp. B V+ terminal Input Select: Channel 5 */
1085 #define CBIPSEL_6 (0x0006u) /* Comp. B V+ terminal Input Select: Channel 6 */
1086 #define CBIPSEL_7 (0x0007u) /* Comp. B V+ terminal Input Select: Channel 7 */
1087 #define CBIPSEL_8 (0x0008u) /* Comp. B V+ terminal Input Select: Channel 8 */
1088 #define CBIPSEL_9 (0x0009u) /* Comp. B V+ terminal Input Select: Channel 9 */
1089 #define CBIPSEL_10 (0x000Au) /* Comp. B V+ terminal Input Select: Channel 10 */
1090 #define CBIPSEL_11 (0x000Bu) /* Comp. B V+ terminal Input Select: Channel 11 */
1091 #define CBIPSEL_12 (0x000Cu) /* Comp. B V+ terminal Input Select: Channel 12 */
1092 #define CBIPSEL_13 (0x000Du) /* Comp. B V+ terminal Input Select: Channel 13 */
1093 #define CBIPSEL_14 (0x000Eu) /* Comp. B V+ terminal Input Select: Channel 14 */
1094 #define CBIPSEL_15 (0x000Fu) /* Comp. B V+ terminal Input Select: Channel 15 */
1095 
1096 #define CBIMSEL_0 (0x0000u) /* Comp. B V- Terminal Input Select: Channel 0 */
1097 #define CBIMSEL_1 (0x0100u) /* Comp. B V- Terminal Input Select: Channel 1 */
1098 #define CBIMSEL_2 (0x0200u) /* Comp. B V- Terminal Input Select: Channel 2 */
1099 #define CBIMSEL_3 (0x0300u) /* Comp. B V- Terminal Input Select: Channel 3 */
1100 #define CBIMSEL_4 (0x0400u) /* Comp. B V- Terminal Input Select: Channel 4 */
1101 #define CBIMSEL_5 (0x0500u) /* Comp. B V- Terminal Input Select: Channel 5 */
1102 #define CBIMSEL_6 (0x0600u) /* Comp. B V- Terminal Input Select: Channel 6 */
1103 #define CBIMSEL_7 (0x0700u) /* Comp. B V- Terminal Input Select: Channel 7 */
1104 #define CBIMSEL_8 (0x0800u) /* Comp. B V- terminal Input Select: Channel 8 */
1105 #define CBIMSEL_9 (0x0900u) /* Comp. B V- terminal Input Select: Channel 9 */
1106 #define CBIMSEL_10 (0x0A00u) /* Comp. B V- terminal Input Select: Channel 10 */
1107 #define CBIMSEL_11 (0x0B00u) /* Comp. B V- terminal Input Select: Channel 11 */
1108 #define CBIMSEL_12 (0x0C00u) /* Comp. B V- terminal Input Select: Channel 12 */
1109 #define CBIMSEL_13 (0x0D00u) /* Comp. B V- terminal Input Select: Channel 13 */
1110 #define CBIMSEL_14 (0x0E00u) /* Comp. B V- terminal Input Select: Channel 14 */
1111 #define CBIMSEL_15 (0x0F00u) /* Comp. B V- terminal Input Select: Channel 15 */
1112 
1113 /* CBCTL1 Control Bits */
1114 #define CBOUT (0x0001u) /* Comp. B Output */
1115 #define CBOUTPOL (0x0002u) /* Comp. B Output Polarity */
1116 #define CBF (0x0004u) /* Comp. B Enable Output Filter */
1117 #define CBIES (0x0008u) /* Comp. B Interrupt Edge Select */
1118 #define CBSHORT (0x0010u) /* Comp. B Input Short */
1119 #define CBEX (0x0020u) /* Comp. B Exchange Inputs */
1120 #define CBFDLY0 (0x0040u) /* Comp. B Filter delay Bit 0 */
1121 #define CBFDLY1 (0x0080u) /* Comp. B Filter delay Bit 1 */
1122 #define CBPWRMD0 (0x0100u) /* Comp. B Power Mode Bit 0 */
1123 #define CBPWRMD1 (0x0200u) /* Comp. B Power Mode Bit 1 */
1124 #define CBON (0x0400u) /* Comp. B enable */
1125 #define CBMRVL (0x0800u) /* Comp. B CBMRV Level */
1126 #define CBMRVS (0x1000u) /* Comp. B Output selects between VREF0 or VREF1*/
1127 //#define RESERVED (0x2000u) /* Comp. B */
1128 //#define RESERVED (0x4000u) /* Comp. B */
1129 //#define RESERVED (0x8000u) /* Comp. B */
1130 
1131 /* CBCTL1 Control Bits */
1132 #define CBOUT_L (0x0001u) /* Comp. B Output */
1133 #define CBOUTPOL_L (0x0002u) /* Comp. B Output Polarity */
1134 #define CBF_L (0x0004u) /* Comp. B Enable Output Filter */
1135 #define CBIES_L (0x0008u) /* Comp. B Interrupt Edge Select */
1136 #define CBSHORT_L (0x0010u) /* Comp. B Input Short */
1137 #define CBEX_L (0x0020u) /* Comp. B Exchange Inputs */
1138 #define CBFDLY0_L (0x0040u) /* Comp. B Filter delay Bit 0 */
1139 #define CBFDLY1_L (0x0080u) /* Comp. B Filter delay Bit 1 */
1140 //#define RESERVED (0x2000u) /* Comp. B */
1141 //#define RESERVED (0x4000u) /* Comp. B */
1142 //#define RESERVED (0x8000u) /* Comp. B */
1143 
1144 /* CBCTL1 Control Bits */
1145 #define CBPWRMD0_H (0x0001u) /* Comp. B Power Mode Bit 0 */
1146 #define CBPWRMD1_H (0x0002u) /* Comp. B Power Mode Bit 1 */
1147 #define CBON_H (0x0004u) /* Comp. B enable */
1148 #define CBMRVL_H (0x0008u) /* Comp. B CBMRV Level */
1149 #define CBMRVS_H (0x0010u) /* Comp. B Output selects between VREF0 or VREF1*/
1150 //#define RESERVED (0x2000u) /* Comp. B */
1151 //#define RESERVED (0x4000u) /* Comp. B */
1152 //#define RESERVED (0x8000u) /* Comp. B */
1153 
1154 #define CBFDLY_0 (0x0000u) /* Comp. B Filter delay 0 : 450ns */
1155 #define CBFDLY_1 (0x0040u) /* Comp. B Filter delay 1 : 900ns */
1156 #define CBFDLY_2 (0x0080u) /* Comp. B Filter delay 2 : 1800ns */
1157 #define CBFDLY_3 (0x00C0u) /* Comp. B Filter delay 3 : 3600ns */
1158 
1159 #define CBPWRMD_0 (0x0000u) /* Comp. B Power Mode 0 : High speed */
1160 #define CBPWRMD_1 (0x0100u) /* Comp. B Power Mode 1 : Normal */
1161 #define CBPWRMD_2 (0x0200u) /* Comp. B Power Mode 2 : Ultra-Low*/
1162 #define CBPWRMD_3 (0x0300u) /* Comp. B Power Mode 3 : Reserved */
1163 
1164 /* CBCTL2 Control Bits */
1165 #define CBREF00 (0x0001u) /* Comp. B Reference 0 Resistor Select Bit : 0 */
1166 #define CBREF01 (0x0002u) /* Comp. B Reference 0 Resistor Select Bit : 1 */
1167 #define CBREF02 (0x0004u) /* Comp. B Reference 0 Resistor Select Bit : 2 */
1168 #define CBREF03 (0x0008u) /* Comp. B Reference 0 Resistor Select Bit : 3 */
1169 #define CBREF04 (0x0010u) /* Comp. B Reference 0 Resistor Select Bit : 4 */
1170 #define CBRSEL (0x0020u) /* Comp. B Reference select */
1171 #define CBRS0 (0x0040u) /* Comp. B Reference Source Bit : 0 */
1172 #define CBRS1 (0x0080u) /* Comp. B Reference Source Bit : 1 */
1173 #define CBREF10 (0x0100u) /* Comp. B Reference 1 Resistor Select Bit : 0 */
1174 #define CBREF11 (0x0200u) /* Comp. B Reference 1 Resistor Select Bit : 1 */
1175 #define CBREF12 (0x0400u) /* Comp. B Reference 1 Resistor Select Bit : 2 */
1176 #define CBREF13 (0x0800u) /* Comp. B Reference 1 Resistor Select Bit : 3 */
1177 #define CBREF14 (0x1000u) /* Comp. B Reference 1 Resistor Select Bit : 4 */
1178 #define CBREFL0 (0x2000u) /* Comp. B Reference voltage level Bit : 0 */
1179 #define CBREFL1 (0x4000u) /* Comp. B Reference voltage level Bit : 1 */
1180 #define CBREFACC (0x8000u) /* Comp. B Reference Accuracy */
1181 
1182 /* CBCTL2 Control Bits */
1183 #define CBREF00_L (0x0001u) /* Comp. B Reference 0 Resistor Select Bit : 0 */
1184 #define CBREF01_L (0x0002u) /* Comp. B Reference 0 Resistor Select Bit : 1 */
1185 #define CBREF02_L (0x0004u) /* Comp. B Reference 0 Resistor Select Bit : 2 */
1186 #define CBREF03_L (0x0008u) /* Comp. B Reference 0 Resistor Select Bit : 3 */
1187 #define CBREF04_L (0x0010u) /* Comp. B Reference 0 Resistor Select Bit : 4 */
1188 #define CBRSEL_L (0x0020u) /* Comp. B Reference select */
1189 #define CBRS0_L (0x0040u) /* Comp. B Reference Source Bit : 0 */
1190 #define CBRS1_L (0x0080u) /* Comp. B Reference Source Bit : 1 */
1191 
1192 /* CBCTL2 Control Bits */
1193 #define CBREF10_H (0x0001u) /* Comp. B Reference 1 Resistor Select Bit : 0 */
1194 #define CBREF11_H (0x0002u) /* Comp. B Reference 1 Resistor Select Bit : 1 */
1195 #define CBREF12_H (0x0004u) /* Comp. B Reference 1 Resistor Select Bit : 2 */
1196 #define CBREF13_H (0x0008u) /* Comp. B Reference 1 Resistor Select Bit : 3 */
1197 #define CBREF14_H (0x0010u) /* Comp. B Reference 1 Resistor Select Bit : 4 */
1198 #define CBREFL0_H (0x0020u) /* Comp. B Reference voltage level Bit : 0 */
1199 #define CBREFL1_H (0x0040u) /* Comp. B Reference voltage level Bit : 1 */
1200 #define CBREFACC_H (0x0080u) /* Comp. B Reference Accuracy */
1201 
1202 #define CBREF0_0 (0x0000u) /* Comp. B Int. Ref.0 Select 0 : 1/32 */
1203 #define CBREF0_1 (0x0001u) /* Comp. B Int. Ref.0 Select 1 : 2/32 */
1204 #define CBREF0_2 (0x0002u) /* Comp. B Int. Ref.0 Select 2 : 3/32 */
1205 #define CBREF0_3 (0x0003u) /* Comp. B Int. Ref.0 Select 3 : 4/32 */
1206 #define CBREF0_4 (0x0004u) /* Comp. B Int. Ref.0 Select 4 : 5/32 */
1207 #define CBREF0_5 (0x0005u) /* Comp. B Int. Ref.0 Select 5 : 6/32 */
1208 #define CBREF0_6 (0x0006u) /* Comp. B Int. Ref.0 Select 6 : 7/32 */
1209 #define CBREF0_7 (0x0007u) /* Comp. B Int. Ref.0 Select 7 : 8/32 */
1210 #define CBREF0_8 (0x0008u) /* Comp. B Int. Ref.0 Select 0 : 9/32 */
1211 #define CBREF0_9 (0x0009u) /* Comp. B Int. Ref.0 Select 1 : 10/32 */
1212 #define CBREF0_10 (0x000Au) /* Comp. B Int. Ref.0 Select 2 : 11/32 */
1213 #define CBREF0_11 (0x000Bu) /* Comp. B Int. Ref.0 Select 3 : 12/32 */
1214 #define CBREF0_12 (0x000Cu) /* Comp. B Int. Ref.0 Select 4 : 13/32 */
1215 #define CBREF0_13 (0x000Du) /* Comp. B Int. Ref.0 Select 5 : 14/32 */
1216 #define CBREF0_14 (0x000Eu) /* Comp. B Int. Ref.0 Select 6 : 15/32 */
1217 #define CBREF0_15 (0x000Fu) /* Comp. B Int. Ref.0 Select 7 : 16/32 */
1218 #define CBREF0_16 (0x0010u) /* Comp. B Int. Ref.0 Select 0 : 17/32 */
1219 #define CBREF0_17 (0x0011u) /* Comp. B Int. Ref.0 Select 1 : 18/32 */
1220 #define CBREF0_18 (0x0012u) /* Comp. B Int. Ref.0 Select 2 : 19/32 */
1221 #define CBREF0_19 (0x0013u) /* Comp. B Int. Ref.0 Select 3 : 20/32 */
1222 #define CBREF0_20 (0x0014u) /* Comp. B Int. Ref.0 Select 4 : 21/32 */
1223 #define CBREF0_21 (0x0015u) /* Comp. B Int. Ref.0 Select 5 : 22/32 */
1224 #define CBREF0_22 (0x0016u) /* Comp. B Int. Ref.0 Select 6 : 23/32 */
1225 #define CBREF0_23 (0x0017u) /* Comp. B Int. Ref.0 Select 7 : 24/32 */
1226 #define CBREF0_24 (0x0018u) /* Comp. B Int. Ref.0 Select 0 : 25/32 */
1227 #define CBREF0_25 (0x0019u) /* Comp. B Int. Ref.0 Select 1 : 26/32 */
1228 #define CBREF0_26 (0x001Au) /* Comp. B Int. Ref.0 Select 2 : 27/32 */
1229 #define CBREF0_27 (0x001Bu) /* Comp. B Int. Ref.0 Select 3 : 28/32 */
1230 #define CBREF0_28 (0x001Cu) /* Comp. B Int. Ref.0 Select 4 : 29/32 */
1231 #define CBREF0_29 (0x001Du) /* Comp. B Int. Ref.0 Select 5 : 30/32 */
1232 #define CBREF0_30 (0x001Eu) /* Comp. B Int. Ref.0 Select 6 : 31/32 */
1233 #define CBREF0_31 (0x001Fu) /* Comp. B Int. Ref.0 Select 7 : 32/32 */
1234 
1235 #define CBRS_0 (0x0000u) /* Comp. B Reference Source 0 : Off */
1236 #define CBRS_1 (0x0040u) /* Comp. B Reference Source 1 : Vcc */
1237 #define CBRS_2 (0x0080u) /* Comp. B Reference Source 2 : Shared Ref. */
1238 #define CBRS_3 (0x00C0u) /* Comp. B Reference Source 3 : Shared Ref. / Off */
1239 
1240 #define CBREF1_0 (0x0000u) /* Comp. B Int. Ref.1 Select 0 : 1/32 */
1241 #define CBREF1_1 (0x0100u) /* Comp. B Int. Ref.1 Select 1 : 2/32 */
1242 #define CBREF1_2 (0x0200u) /* Comp. B Int. Ref.1 Select 2 : 3/32 */
1243 #define CBREF1_3 (0x0300u) /* Comp. B Int. Ref.1 Select 3 : 4/32 */
1244 #define CBREF1_4 (0x0400u) /* Comp. B Int. Ref.1 Select 4 : 5/32 */
1245 #define CBREF1_5 (0x0500u) /* Comp. B Int. Ref.1 Select 5 : 6/32 */
1246 #define CBREF1_6 (0x0600u) /* Comp. B Int. Ref.1 Select 6 : 7/32 */
1247 #define CBREF1_7 (0x0700u) /* Comp. B Int. Ref.1 Select 7 : 8/32 */
1248 #define CBREF1_8 (0x0800u) /* Comp. B Int. Ref.1 Select 0 : 9/32 */
1249 #define CBREF1_9 (0x0900u) /* Comp. B Int. Ref.1 Select 1 : 10/32 */
1250 #define CBREF1_10 (0x0A00u) /* Comp. B Int. Ref.1 Select 2 : 11/32 */
1251 #define CBREF1_11 (0x0B00u) /* Comp. B Int. Ref.1 Select 3 : 12/32 */
1252 #define CBREF1_12 (0x0C00u) /* Comp. B Int. Ref.1 Select 4 : 13/32 */
1253 #define CBREF1_13 (0x0D00u) /* Comp. B Int. Ref.1 Select 5 : 14/32 */
1254 #define CBREF1_14 (0x0E00u) /* Comp. B Int. Ref.1 Select 6 : 15/32 */
1255 #define CBREF1_15 (0x0F00u) /* Comp. B Int. Ref.1 Select 7 : 16/32 */
1256 #define CBREF1_16 (0x1000u) /* Comp. B Int. Ref.1 Select 0 : 17/32 */
1257 #define CBREF1_17 (0x1100u) /* Comp. B Int. Ref.1 Select 1 : 18/32 */
1258 #define CBREF1_18 (0x1200u) /* Comp. B Int. Ref.1 Select 2 : 19/32 */
1259 #define CBREF1_19 (0x1300u) /* Comp. B Int. Ref.1 Select 3 : 20/32 */
1260 #define CBREF1_20 (0x1400u) /* Comp. B Int. Ref.1 Select 4 : 21/32 */
1261 #define CBREF1_21 (0x1500u) /* Comp. B Int. Ref.1 Select 5 : 22/32 */
1262 #define CBREF1_22 (0x1600u) /* Comp. B Int. Ref.1 Select 6 : 23/32 */
1263 #define CBREF1_23 (0x1700u) /* Comp. B Int. Ref.1 Select 7 : 24/32 */
1264 #define CBREF1_24 (0x1800u) /* Comp. B Int. Ref.1 Select 0 : 25/32 */
1265 #define CBREF1_25 (0x1900u) /* Comp. B Int. Ref.1 Select 1 : 26/32 */
1266 #define CBREF1_26 (0x1A00u) /* Comp. B Int. Ref.1 Select 2 : 27/32 */
1267 #define CBREF1_27 (0x1B00u) /* Comp. B Int. Ref.1 Select 3 : 28/32 */
1268 #define CBREF1_28 (0x1C00u) /* Comp. B Int. Ref.1 Select 4 : 29/32 */
1269 #define CBREF1_29 (0x1D00u) /* Comp. B Int. Ref.1 Select 5 : 30/32 */
1270 #define CBREF1_30 (0x1E00u) /* Comp. B Int. Ref.1 Select 6 : 31/32 */
1271 #define CBREF1_31 (0x1F00u) /* Comp. B Int. Ref.1 Select 7 : 32/32 */
1272 
1273 #define CBREFL_0 (0x0000u) /* Comp. B Reference voltage level 0 : None */
1274 #define CBREFL_1 (0x2000u) /* Comp. B Reference voltage level 1 : 1.5V */
1275 #define CBREFL_2 (0x4000u) /* Comp. B Reference voltage level 2 : 2.0V */
1276 #define CBREFL_3 (0x6000u) /* Comp. B Reference voltage level 3 : 2.5V */
1277 
1278 #define CBPD0 (0x0001u) /* Comp. B Disable Input Buffer of Port Register .0 */
1279 #define CBPD1 (0x0002u) /* Comp. B Disable Input Buffer of Port Register .1 */
1280 #define CBPD2 (0x0004u) /* Comp. B Disable Input Buffer of Port Register .2 */
1281 #define CBPD3 (0x0008u) /* Comp. B Disable Input Buffer of Port Register .3 */
1282 #define CBPD4 (0x0010u) /* Comp. B Disable Input Buffer of Port Register .4 */
1283 #define CBPD5 (0x0020u) /* Comp. B Disable Input Buffer of Port Register .5 */
1284 #define CBPD6 (0x0040u) /* Comp. B Disable Input Buffer of Port Register .6 */
1285 #define CBPD7 (0x0080u) /* Comp. B Disable Input Buffer of Port Register .7 */
1286 #define CBPD8 (0x0100u) /* Comp. B Disable Input Buffer of Port Register .8 */
1287 #define CBPD9 (0x0200u) /* Comp. B Disable Input Buffer of Port Register .9 */
1288 #define CBPD10 (0x0400u) /* Comp. B Disable Input Buffer of Port Register .10 */
1289 #define CBPD11 (0x0800u) /* Comp. B Disable Input Buffer of Port Register .11 */
1290 #define CBPD12 (0x1000u) /* Comp. B Disable Input Buffer of Port Register .12 */
1291 #define CBPD13 (0x2000u) /* Comp. B Disable Input Buffer of Port Register .13 */
1292 #define CBPD14 (0x4000u) /* Comp. B Disable Input Buffer of Port Register .14 */
1293 #define CBPD15 (0x8000u) /* Comp. B Disable Input Buffer of Port Register .15 */
1294 
1295 #define CBPD0_L (0x0001u) /* Comp. B Disable Input Buffer of Port Register .0 */
1296 #define CBPD1_L (0x0002u) /* Comp. B Disable Input Buffer of Port Register .1 */
1297 #define CBPD2_L (0x0004u) /* Comp. B Disable Input Buffer of Port Register .2 */
1298 #define CBPD3_L (0x0008u) /* Comp. B Disable Input Buffer of Port Register .3 */
1299 #define CBPD4_L (0x0010u) /* Comp. B Disable Input Buffer of Port Register .4 */
1300 #define CBPD5_L (0x0020u) /* Comp. B Disable Input Buffer of Port Register .5 */
1301 #define CBPD6_L (0x0040u) /* Comp. B Disable Input Buffer of Port Register .6 */
1302 #define CBPD7_L (0x0080u) /* Comp. B Disable Input Buffer of Port Register .7 */
1303 
1304 #define CBPD8_H (0x0001u) /* Comp. B Disable Input Buffer of Port Register .8 */
1305 #define CBPD9_H (0x0002u) /* Comp. B Disable Input Buffer of Port Register .9 */
1306 #define CBPD10_H (0x0004u) /* Comp. B Disable Input Buffer of Port Register .10 */
1307 #define CBPD11_H (0x0008u) /* Comp. B Disable Input Buffer of Port Register .11 */
1308 #define CBPD12_H (0x0010u) /* Comp. B Disable Input Buffer of Port Register .12 */
1309 #define CBPD13_H (0x0020u) /* Comp. B Disable Input Buffer of Port Register .13 */
1310 #define CBPD14_H (0x0040u) /* Comp. B Disable Input Buffer of Port Register .14 */
1311 #define CBPD15_H (0x0080u) /* Comp. B Disable Input Buffer of Port Register .15 */
1312 
1313 /* CBINT Control Bits */
1314 #define CBIFG (0x0001u) /* Comp. B Interrupt Flag */
1315 #define CBIIFG (0x0002u) /* Comp. B Interrupt Flag Inverted Polarity */
1316 //#define RESERVED (0x0004u) /* Comp. B */
1317 //#define RESERVED (0x0008u) /* Comp. B */
1318 //#define RESERVED (0x0010u) /* Comp. B */
1319 //#define RESERVED (0x0020u) /* Comp. B */
1320 //#define RESERVED (0x0040u) /* Comp. B */
1321 //#define RESERVED (0x0080u) /* Comp. B */
1322 #define CBIE (0x0100u) /* Comp. B Interrupt Enable */
1323 #define CBIIE (0x0200u) /* Comp. B Interrupt Enable Inverted Polarity */
1324 //#define RESERVED (0x0400u) /* Comp. B */
1325 //#define RESERVED (0x0800u) /* Comp. B */
1326 //#define RESERVED (0x1000u) /* Comp. B */
1327 //#define RESERVED (0x2000u) /* Comp. B */
1328 //#define RESERVED (0x4000u) /* Comp. B */
1329 //#define RESERVED (0x8000u) /* Comp. B */
1330 
1331 /* CBINT Control Bits */
1332 #define CBIFG_L (0x0001u) /* Comp. B Interrupt Flag */
1333 #define CBIIFG_L (0x0002u) /* Comp. B Interrupt Flag Inverted Polarity */
1334 //#define RESERVED (0x0004u) /* Comp. B */
1335 //#define RESERVED (0x0008u) /* Comp. B */
1336 //#define RESERVED (0x0010u) /* Comp. B */
1337 //#define RESERVED (0x0020u) /* Comp. B */
1338 //#define RESERVED (0x0040u) /* Comp. B */
1339 //#define RESERVED (0x0080u) /* Comp. B */
1340 //#define RESERVED (0x0400u) /* Comp. B */
1341 //#define RESERVED (0x0800u) /* Comp. B */
1342 //#define RESERVED (0x1000u) /* Comp. B */
1343 //#define RESERVED (0x2000u) /* Comp. B */
1344 //#define RESERVED (0x4000u) /* Comp. B */
1345 //#define RESERVED (0x8000u) /* Comp. B */
1346 
1347 /* CBINT Control Bits */
1348 //#define RESERVED (0x0004u) /* Comp. B */
1349 //#define RESERVED (0x0008u) /* Comp. B */
1350 //#define RESERVED (0x0010u) /* Comp. B */
1351 //#define RESERVED (0x0020u) /* Comp. B */
1352 //#define RESERVED (0x0040u) /* Comp. B */
1353 //#define RESERVED (0x0080u) /* Comp. B */
1354 #define CBIE_H (0x0001u) /* Comp. B Interrupt Enable */
1355 #define CBIIE_H (0x0002u) /* Comp. B Interrupt Enable Inverted Polarity */
1356 //#define RESERVED (0x0400u) /* Comp. B */
1357 //#define RESERVED (0x0800u) /* Comp. B */
1358 //#define RESERVED (0x1000u) /* Comp. B */
1359 //#define RESERVED (0x2000u) /* Comp. B */
1360 //#define RESERVED (0x4000u) /* Comp. B */
1361 //#define RESERVED (0x8000u) /* Comp. B */
1362 
1363 /* CBIV Definitions */
1364 #define CBIV_NONE (0x0000u) /* No Interrupt pending */
1365 #define CBIV_CBIFG (0x0002u) /* CBIFG */
1366 #define CBIV_CBIIFG (0x0004u) /* CBIIFG */
1367 
1368 #endif
1369 /************************************************************
1370 * CC1101 Radio Interface
1371 ************************************************************/
1372 #ifdef __MSP430_HAS_CC1101__ /* Definition to show that Module is available */
1373 
1374 #define OFS_RF1AIFCTL0 (0x0000u) /* Radio interface control register 0 */
1375 #define OFS_RF1AIFCTL0_L OFS_RF1AIFCTL0
1376 #define OFS_RF1AIFCTL0_H OFS_RF1AIFCTL0+1
1377 #define OFS_RF1AIFCTL1 (0x0002u) /* Radio interface control register 1 */
1378 #define OFS_RF1AIFCTL1_L OFS_RF1AIFCTL1
1379 #define OFS_RF1AIFCTL1_H OFS_RF1AIFCTL1+1
1380 #define RF1AIFIFG RF1AIFCTL1_L /* Radio interface interrupt flag register */
1381 #define RF1AIFIE RF1AIFCTL1_H /* Radio interface interrupt enable register */
1382 #define OFS_RF1AIFCTL2 (0x0004u) /* (Radio interface control register 2) */
1383 #define OFS_RF1AIFCTL2_L OFS_RF1AIFCTL2
1384 #define OFS_RF1AIFCTL2_H OFS_RF1AIFCTL2+1
1385 #define OFS_RF1AIFERR (0x0006u) /* Radio interface error flag register */
1386 #define OFS_RF1AIFERR_L OFS_RF1AIFERR
1387 #define OFS_RF1AIFERR_H OFS_RF1AIFERR+1
1388 #define OFS_RF1AIFERRV (0x000Cu) /* Radio interface error vector word register */
1389 #define OFS_RF1AIFERRV_L OFS_RF1AIFERRV
1390 #define OFS_RF1AIFERRV_H OFS_RF1AIFERRV+1
1391 #define OFS_RF1AIFIV (0x000Eu) /* Radio interface interrupt vector word register */
1392 #define OFS_RF1AIFIV_L OFS_RF1AIFIV
1393 #define OFS_RF1AIFIV_H OFS_RF1AIFIV+1
1394 #define OFS_RF1AINSTRW (0x0010u) /* Radio instruction word register */
1395 #define OFS_RF1AINSTRW_L OFS_RF1AINSTRW
1396 #define OFS_RF1AINSTRW_H OFS_RF1AINSTRW+1
1397 #define RF1ADINB RF1AINSTRW_L /* Radio instruction byte register */
1398 #define RF1AINSTRB RF1AINSTRW_H /* Radio byte data in register */
1399 #define OFS_RF1AINSTR1W (0x0012u) /* Radio instruction 1-byte register with autoread */
1400 #define OFS_RF1AINSTR1W_L OFS_RF1AINSTR1W
1401 #define OFS_RF1AINSTR1W_H OFS_RF1AINSTR1W+1
1402 #define RF1AINSTR1B RF1AINSTR1W_H /* Radio instruction 1-byte register with autoread */
1403 #define OFS_RF1AINSTR2W (0x0014u) /* Radio instruction 2-byte register with autoread */
1404 #define OFS_RF1AINSTR2W_L OFS_RF1AINSTR2W
1405 #define OFS_RF1AINSTR2W_H OFS_RF1AINSTR2W+1
1406 #define RF1AINSTR2B RF1AINSTR1W_H /* Radio instruction 2-byte register with autoread */
1407 #define OFS_RF1ADINW (0x0016u) /* Radio word data in register */
1408 #define OFS_RF1ADINW_L OFS_RF1ADINW
1409 #define OFS_RF1ADINW_H OFS_RF1ADINW+1
1410 
1411 #define OFS_RF1ASTAT0W (0x0020u) /* Radio status word register without auto-read */
1412 #define OFS_RF1ASTAT0W_L OFS_RF1ASTAT0W
1413 #define OFS_RF1ASTAT0W_H OFS_RF1ASTAT0W+1
1414 #define RF1ADOUT0B RF1ASTAT0W_L /* Radio byte data out register without auto-read */
1415 #define RF1ASTAT0B RF1ASTAT0W_H /* Radio status byte register without auto-read */
1416 #define RF1ASTATW RF1ASTAT0W /* Radio status word register without auto-read */
1417 #define RF1ADOUTB RF1ASTAT0W_L /* Radio byte data out register without auto-read */
1418 #define RF1ASTATB RF1ASTAT0W_H /* Radio status byte register without auto-read */
1419 #define OFS_RF1ASTAT1W (0x0022u) /* Radio status word register with 1-byte auto-read */
1420 #define OFS_RF1ASTAT1W_L OFS_RF1ASTAT1W
1421 #define OFS_RF1ASTAT1W_H OFS_RF1ASTAT1W+1
1422 #define RF1ADOUT1B RF1ASTAT1W_L /* Radio byte data out register with 1-byte auto-read */
1423 #define RF1ASTAT1B RF1ASTAT1W_H /* Radio status byte register with 1-byte auto-read */
1424 #define OFS_RF1ASTAT2W (0x0024u) /* Radio status word register with 2-byte auto-read */
1425 #define OFS_RF1ASTAT2W_L OFS_RF1ASTAT2W
1426 #define OFS_RF1ASTAT2W_H OFS_RF1ASTAT2W+1
1427 #define RF1ADOUT2B RF1ASTAT2W_L /* Radio byte data out register with 2-byte auto-read */
1428 #define RF1ASTAT2B RF1ASTAT2W_H /* Radio status byte register with 2-byte auto-read */
1429 #define OFS_RF1ADOUT0W (0x0028u) /* Radio core word data out register without auto-read */
1430 #define OFS_RF1ADOUT0W_L OFS_RF1ADOUT0W
1431 #define OFS_RF1ADOUT0W_H OFS_RF1ADOUT0W+1
1432 #define RF1ADOUTW RF1ADOUT0W /* Radio core word data out register without auto-read */
1433 #define RF1ADOUTW_L RF1ADOUT0W_L /* Radio core word data out register without auto-read */
1434 #define RF1ADOUTW_H RF1ADOUT0W_H /* Radio core word data out register without auto-read */
1435 #define OFS_RF1ADOUT1W (0x002Au) /* Radio core word data out register with 1-byte auto-read */
1436 #define OFS_RF1ADOUT1W_L OFS_RF1ADOUT1W
1437 #define OFS_RF1ADOUT1W_H OFS_RF1ADOUT1W+1
1438 #define OFS_RF1ADOUT2W (0x002Cu) /* Radio core word data out register with 2-byte auto-read */
1439 #define OFS_RF1ADOUT2W_L OFS_RF1ADOUT2W
1440 #define OFS_RF1ADOUT2W_H OFS_RF1ADOUT2W+1
1441 #define OFS_RF1AIN (0x0030u) /* Radio core signal input register */
1442 #define OFS_RF1AIN_L OFS_RF1AIN
1443 #define OFS_RF1AIN_H OFS_RF1AIN+1
1444 #define OFS_RF1AIFG (0x0032u) /* Radio core interrupt flag register */
1445 #define OFS_RF1AIFG_L OFS_RF1AIFG
1446 #define OFS_RF1AIFG_H OFS_RF1AIFG+1
1447 #define OFS_RF1AIES (0x0034u) /* Radio core interrupt edge select register */
1448 #define OFS_RF1AIES_L OFS_RF1AIES
1449 #define OFS_RF1AIES_H OFS_RF1AIES+1
1450 #define OFS_RF1AIE (0x0036u) /* Radio core interrupt enable register */
1451 #define OFS_RF1AIE_L OFS_RF1AIE
1452 #define OFS_RF1AIE_H OFS_RF1AIE+1
1453 #define OFS_RF1AIV (0x0038u) /* Radio core interrupt vector word register */
1454 #define OFS_RF1AIV_L OFS_RF1AIV
1455 #define OFS_RF1AIV_H OFS_RF1AIV+1
1456 #define OFS_RF1ARXFIFO (0x003Cu) /* Direct receive FIFO access register */
1457 #define OFS_RF1ARXFIFO_L OFS_RF1ARXFIFO
1458 #define OFS_RF1ARXFIFO_H OFS_RF1ARXFIFO+1
1459 #define OFS_RF1ATXFIFO (0x003Eu) /* Direct transmit FIFO access register */
1460 #define OFS_RF1ATXFIFO_L OFS_RF1ATXFIFO
1461 #define OFS_RF1ATXFIFO_H OFS_RF1ATXFIFO+1
1462 
1463 /* RF1AIFCTL0 Control Bits */
1464 #define RFFIFOEN (0x0001u) /* CC1101 Direct FIFO access enable */
1465 #define RFENDIAN (0x0002u) /* CC1101 Disable endianness conversion */
1466 
1467 /* RF1AIFCTL0 Control Bits */
1468 #define RFFIFOEN_L (0x0001u) /* CC1101 Direct FIFO access enable */
1469 #define RFENDIAN_L (0x0002u) /* CC1101 Disable endianness conversion */
1470 
1471 /* RF1AIFCTL1 Control Bits */
1472 #define RFRXIFG (0x0001u) /* Radio interface direct FIFO access receive interrupt flag */
1473 #define RFTXIFG (0x0002u) /* Radio interface direct FIFO access transmit interrupt flag */
1474 #define RFERRIFG (0x0004u) /* Radio interface error interrupt flag */
1475 #define RFINSTRIFG (0x0010u) /* Radio interface instruction interrupt flag */
1476 #define RFDINIFG (0x0020u) /* Radio interface data in interrupt flag */
1477 #define RFSTATIFG (0x0040u) /* Radio interface status interrupt flag */
1478 #define RFDOUTIFG (0x0080u) /* Radio interface data out interrupt flag */
1479 #define RFRXIE (0x0100u) /* Radio interface direct FIFO access receive interrupt enable */
1480 #define RFTXIE (0x0200u) /* Radio interface direct FIFO access transmit interrupt enable */
1481 #define RFERRIE (0x0400u) /* Radio interface error interrupt enable */
1482 #define RFINSTRIE (0x1000u) /* Radio interface instruction interrupt enable */
1483 #define RFDINIE (0x2000u) /* Radio interface data in interrupt enable */
1484 #define RFSTATIE (0x4000u) /* Radio interface status interrupt enable */
1485 #define RFDOUTIE (0x8000u) /* Radio interface data out interrupt enable */
1486 
1487 /* RF1AIFCTL1 Control Bits */
1488 #define RFRXIFG_L (0x0001u) /* Radio interface direct FIFO access receive interrupt flag */
1489 #define RFTXIFG_L (0x0002u) /* Radio interface direct FIFO access transmit interrupt flag */
1490 #define RFERRIFG_L (0x0004u) /* Radio interface error interrupt flag */
1491 #define RFINSTRIFG_L (0x0010u) /* Radio interface instruction interrupt flag */
1492 #define RFDINIFG_L (0x0020u) /* Radio interface data in interrupt flag */
1493 #define RFSTATIFG_L (0x0040u) /* Radio interface status interrupt flag */
1494 #define RFDOUTIFG_L (0x0080u) /* Radio interface data out interrupt flag */
1495 
1496 /* RF1AIFCTL1 Control Bits */
1497 #define RFRXIE_H (0x0001u) /* Radio interface direct FIFO access receive interrupt enable */
1498 #define RFTXIE_H (0x0002u) /* Radio interface direct FIFO access transmit interrupt enable */
1499 #define RFERRIE_H (0x0004u) /* Radio interface error interrupt enable */
1500 #define RFINSTRIE_H (0x0010u) /* Radio interface instruction interrupt enable */
1501 #define RFDINIE_H (0x0020u) /* Radio interface data in interrupt enable */
1502 #define RFSTATIE_H (0x0040u) /* Radio interface status interrupt enable */
1503 #define RFDOUTIE_H (0x0080u) /* Radio interface data out interrupt enable */
1504 
1505 /* RF1AIFERR Control Bits */
1506 #define LVERR (0x0001u) /* Low Core Voltage Error Flag */
1507 #define OPERR (0x0002u) /* Operand Error Flag */
1508 #define OUTERR (0x0004u) /* Output data not available Error Flag */
1509 #define OPOVERR (0x0008u) /* Operand Overwrite Error Flag */
1510 
1511 /* RF1AIFERR Control Bits */
1512 #define LVERR_L (0x0001u) /* Low Core Voltage Error Flag */
1513 #define OPERR_L (0x0002u) /* Operand Error Flag */
1514 #define OUTERR_L (0x0004u) /* Output data not available Error Flag */
1515 #define OPOVERR_L (0x0008u) /* Operand Overwrite Error Flag */
1516 
1517 /* RF1AIFERRV Definitions */
1518 #define RF1AIFERRV_NONE (0x0000u) /* No Error pending */
1519 #define RF1AIFERRV_LVERR (0x0002u) /* Low core voltage error */
1520 #define RF1AIFERRV_OPERR (0x0004u) /* Operand Error */
1521 #define RF1AIFERRV_OUTERR (0x0006u) /* Output data not available Error */
1522 #define RF1AIFERRV_OPOVERR (0x0008u) /* Operand Overwrite Error */
1523 
1524 /* RF1AIFIV Definitions */
1525 #define RF1AIFIV_NONE (0x0000u) /* No Interrupt pending */
1526 #define RF1AIFIV_RFERRIFG (0x0002u) /* Radio interface error */
1527 #define RF1AIFIV_RFDOUTIFG (0x0004u) /* Radio i/f data out */
1528 #define RF1AIFIV_RFSTATIFG (0x0006u) /* Radio i/f status out */
1529 #define RF1AIFIV_RFDINIFG (0x0008u) /* Radio i/f data in */
1530 #define RF1AIFIV_RFINSTRIFG (0x000Au) /* Radio i/f instruction in */
1531 
1532 /* RF1AIV Definitions */
1533 #define RF1AIV_NONE (0x0000u) /* No Interrupt pending */
1534 #define RF1AIV_RFIFG0 (0x0002u) /* RFIFG0 */
1535 #define RF1AIV_RFIFG1 (0x0004u) /* RFIFG1 */
1536 #define RF1AIV_RFIFG2 (0x0006u) /* RFIFG2 */
1537 #define RF1AIV_RFIFG3 (0x0008u) /* RFIFG3 */
1538 #define RF1AIV_RFIFG4 (0x000Au) /* RFIFG4 */
1539 #define RF1AIV_RFIFG5 (0x000Cu) /* RFIFG5 */
1540 #define RF1AIV_RFIFG6 (0x000Eu) /* RFIFG6 */
1541 #define RF1AIV_RFIFG7 (0x0010u) /* RFIFG7 */
1542 #define RF1AIV_RFIFG8 (0x0012u) /* RFIFG8 */
1543 #define RF1AIV_RFIFG9 (0x0014u) /* RFIFG9 */
1544 #define RF1AIV_RFIFG10 (0x0016u) /* RFIFG10 */
1545 #define RF1AIV_RFIFG11 (0x0018u) /* RFIFG11 */
1546 #define RF1AIV_RFIFG12 (0x001Au) /* RFIFG12 */
1547 #define RF1AIV_RFIFG13 (0x001Cu) /* RFIFG13 */
1548 #define RF1AIV_RFIFG14 (0x001Eu) /* RFIFG14 */
1549 #define RF1AIV_RFIFG15 (0x0020u) /* RFIFG15 */
1550 
1551 // Radio Core Registers
1552 #define IOCFG2 0x00 /* IOCFG2 - GDO2 output pin configuration */
1553 #define IOCFG1 0x01 /* IOCFG1 - GDO1 output pin configuration */
1554 #define IOCFG0 0x02 /* IOCFG1 - GDO0 output pin configuration */
1555 #define FIFOTHR 0x03 /* FIFOTHR - RX FIFO and TX FIFO thresholds */
1556 #define SYNC1 0x04 /* SYNC1 - Sync word, high byte */
1557 #define SYNC0 0x05 /* SYNC0 - Sync word, low byte */
1558 #define PKTLEN 0x06 /* PKTLEN - Packet length */
1559 #define PKTCTRL1 0x07 /* PKTCTRL1 - Packet automation control */
1560 #define PKTCTRL0 0x08 /* PKTCTRL0 - Packet automation control */
1561 #define ADDR 0x09 /* ADDR - Device address */
1562 #define CHANNR 0x0A /* CHANNR - Channel number */
1563 #define FSCTRL1 0x0B /* FSCTRL1 - Frequency synthesizer control */
1564 #define FSCTRL0 0x0C /* FSCTRL0 - Frequency synthesizer control */
1565 #define FREQ2 0x0D /* FREQ2 - Frequency control word, high byte */
1566 #define FREQ1 0x0E /* FREQ1 - Frequency control word, middle byte */
1567 #define FREQ0 0x0F /* FREQ0 - Frequency control word, low byte */
1568 #define MDMCFG4 0x10 /* MDMCFG4 - Modem configuration */
1569 #define MDMCFG3 0x11 /* MDMCFG3 - Modem configuration */
1570 #define MDMCFG2 0x12 /* MDMCFG2 - Modem configuration */
1571 #define MDMCFG1 0x13 /* MDMCFG1 - Modem configuration */
1572 #define MDMCFG0 0x14 /* MDMCFG0 - Modem configuration */
1573 #define DEVIATN 0x15 /* DEVIATN - Modem deviation setting */
1574 #define MCSM2 0x16 /* MCSM2 - Main Radio Control State Machine configuration */
1575 #define MCSM1 0x17 /* MCSM1 - Main Radio Control State Machine configuration */
1576 #define MCSM0 0x18 /* MCSM0 - Main Radio Control State Machine configuration */
1577 #define FOCCFG 0x19 /* FOCCFG - Frequency Offset Compensation configuration */
1578 #define BSCFG 0x1A /* BSCFG - Bit Synchronization configuration */
1579 #define AGCCTRL2 0x1B /* AGCCTRL2 - AGC control */
1580 #define AGCCTRL1 0x1C /* AGCCTRL1 - AGC control */
1581 #define AGCCTRL0 0x1D /* AGCCTRL0 - AGC control */
1582 #define WOREVT1 0x1E /* WOREVT1 - High byte Event0 timeout */
1583 #define WOREVT0 0x1F /* WOREVT0 - Low byte Event0 timeout */
1584 #define WORCTRL 0x20 /* WORCTRL - Wake On Radio control */
1585 #define FREND1 0x21 /* FREND1 - Front end RX configuration */
1586 #define FREND0 0x22 /* FREDN0 - Front end TX configuration */
1587 #define FSCAL3 0x23 /* FSCAL3 - Frequency synthesizer calibration */
1588 #define FSCAL2 0x24 /* FSCAL2 - Frequency synthesizer calibration */
1589 #define FSCAL1 0x25 /* FSCAL1 - Frequency synthesizer calibration */
1590 #define FSCAL0 0x26 /* FSCAL0 - Frequency synthesizer calibration */
1591 //#define RCCTRL1 0x27 /* RCCTRL1 - RC oscillator configuration */
1592 //#define RCCTRL0 0x28 /* RCCTRL0 - RC oscillator configuration */
1593 #define FSTEST 0x29 /* FSTEST - Frequency synthesizer calibration control */
1594 #define PTEST 0x2A /* PTEST - Production test */
1595 #define AGCTEST 0x2B /* AGCTEST - AGC test */
1596 #define TEST2 0x2C /* TEST2 - Various test settings */
1597 #define TEST1 0x2D /* TEST1 - Various test settings */
1598 #define TEST0 0x2E /* TEST0 - Various test settings */
1599 
1600 /* status registers */
1601 #define PARTNUM 0x30 /* PARTNUM - Chip ID */
1602 #define VERSION 0x31 /* VERSION - Chip ID */
1603 #define FREQEST 0x32 /* FREQEST – Frequency Offset Estimate from demodulator */
1604 #define LQI 0x33 /* LQI – Demodulator estimate for Link Quality */
1605 #define RSSI 0x34 /* RSSI – Received signal strength indication */
1606 #define MARCSTATE 0x35 /* MARCSTATE – Main Radio Control State Machine state */
1607 #define WORTIME1 0x36 /* WORTIME1 – High byte of WOR time */
1608 #define WORTIME0 0x37 /* WORTIME0 – Low byte of WOR time */
1609 #define PKTSTATUS 0x38 /* PKTSTATUS – Current GDOx status and packet status */
1610 #define VCO_VC_DAC 0x39 /* VCO_VC_DAC – Current setting from PLL calibration module */
1611 #define TXBYTES 0x3A /* TXBYTES – Underflow and number of bytes */
1612 #define RXBYTES 0x3B /* RXBYTES – Overflow and number of bytes */
1613 
1614 /* burst write registers */
1615 #define PATABLE 0x3E /* PATABLE - PA control settings table */
1616 #define TXFIFO 0x3F /* TXFIFO - Transmit FIFO */
1617 #define RXFIFO 0x3F /* RXFIFO - Receive FIFO */
1618 
1619 /* Radio Core Instructions */
1620 /* command strobes */
1621 #define RF_SRES 0x30 /* SRES - Reset chip. */
1622 #define RF_SFSTXON 0x31 /* SFSTXON - Enable and calibrate frequency synthesizer. */
1623 #define RF_SXOFF 0x32 /* SXOFF - Turn off crystal oscillator. */
1624 #define RF_SCAL 0x33 /* SCAL - Calibrate frequency synthesizer and turn it off. */
1625 #define RF_SRX 0x34 /* SRX - Enable RX. Perform calibration if enabled. */
1626 #define RF_STX 0x35 /* STX - Enable TX. If in RX state, only enable TX if CCA passes. */
1627 #define RF_SIDLE 0x36 /* SIDLE - Exit RX / TX, turn off frequency synthesizer. */
1628 //#define RF_SRSVD 0x37 /* SRVSD - Reserved. Do not use. */
1629 #define RF_SWOR 0x38 /* SWOR - Start automatic RX polling sequence (Wake-on-Radio) */
1630 #define RF_SPWD 0x39 /* SPWD - Enter power down mode when CSn goes high. */
1631 #define RF_SFRX 0x3A /* SFRX - Flush the RX FIFO buffer. */
1632 #define RF_SFTX 0x3B /* SFTX - Flush the TX FIFO buffer. */
1633 #define RF_SWORRST 0x3C /* SWORRST - Reset real time clock. */
1634 #define RF_SNOP 0x3D /* SNOP - No operation. Returns status byte. */
1635 
1636 #define RF_RXSTAT 0x80 /* Used in combination with strobe commands delivers number of availabe bytes in RX FIFO with return status */
1637 #define RF_TXSTAT 0x00 /* Used in combination with strobe commands delivers number of availabe bytes in TX FIFO with return status */
1638 
1639 /* other radio instr */
1640 #define RF_SNGLREGRD 0x80
1641 #define RF_SNGLREGWR 0x00
1642 #define RF_REGRD 0xC0
1643 #define RF_REGWR 0x40
1644 #define RF_STATREGRD 0xC0 /* Read single radio core status register */
1645 #define RF_SNGLPATABRD (RF_SNGLREGRD+PATABLE)
1646 #define RF_SNGLPATABWR (RF_SNGLREGWR+PATABLE)
1647 #define RF_PATABRD (RF_REGRD+PATABLE)
1648 #define RF_PATABWR (RF_REGWR+PATABLE)
1649 #define RF_SNGLRXRD (RF_SNGLREGRD+RXFIFO)
1650 #define RF_SNGLTXWR (RF_SNGLREGWR+TXFIFO)
1651 #define RF_RXFIFORD (RF_REGRD+RXFIFO)
1652 #define RF_TXFIFOWR (RF_REGWR+TXFIFO)
1653 
1654 #endif
1655 /*************************************************************
1656 * CRC Module
1657 *************************************************************/
1658 #ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */
1659 
1660 #define OFS_CRCDI (0x0000u) /* CRC Data In Register */
1661 #define OFS_CRCDI_L OFS_CRCDI
1662 #define OFS_CRCDI_H OFS_CRCDI+1
1663 #define OFS_CRCDIRB (0x0002u) /* CRC data in reverse byte Register */
1664 #define OFS_CRCDIRB_L OFS_CRCDIRB
1665 #define OFS_CRCDIRB_H OFS_CRCDIRB+1
1666 #define OFS_CRCINIRES (0x0004u) /* CRC Initialisation Register and Result Register */
1667 #define OFS_CRCINIRES_L OFS_CRCINIRES
1668 #define OFS_CRCINIRES_H OFS_CRCINIRES+1
1669 #define OFS_CRCRESR (0x0006u) /* CRC reverse result Register */
1670 #define OFS_CRCRESR_L OFS_CRCRESR
1671 #define OFS_CRCRESR_H OFS_CRCRESR+1
1672 
1673 #endif
1674 /************************************************************
1675 * DAC12
1676 ************************************************************/
1677 #ifdef __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */
1678 
1679 #define OFS_DAC12_0CTL0 (0x0000u) /* DAC12_0 Control Register 0 */
1680 #define OFS_DAC12_0CTL1 (0x0002u) /* DAC12_0 Control Register 1 */
1681 #define OFS_DAC12_0DAT (0x0004u) /* DAC12_0 Data */
1682 #define OFS_DAC12_0CALCTL (0x0006u) /* DAC12_0 Calibration Control Register */
1683 #define OFS_DAC12_0CALDAT (0x0008u) /* DAC12_0 Calibration Data Register */
1684 #define OFS_DAC12_1CTL0 (0x0010u) /* DAC12_1 Control Register 0 */
1685 #define OFS_DAC12_1CTL1 (0x0012u) /* DAC12_1 Control Register 1 */
1686 #define OFS_DAC12_1DAT (0x0014u) /* DAC12_1 Data */
1687 #define OFS_DAC12_1CALCTL (0x0016u) /* DAC12_1 Calibration Control Register */
1688 #define OFS_DAC12_1CALDAT (0x0018u) /* DAC12_1 Calibration Data Register */
1689 #define OFS_DAC12_IV (0x001Eu) /* DAC12 Interrupt Vector Word */
1690 
1691 /* DAC12_xCTL0 Control Bits */
1692 #define DAC12GRP (0x0001u) /* DAC12 group */
1693 #define DAC12ENC (0x0002u) /* DAC12 enable conversion */
1694 #define DAC12IFG (0x0004u) /* DAC12 interrupt flag */
1695 #define DAC12IE (0x0008u) /* DAC12 interrupt enable */
1696 #define DAC12DF (0x0010u) /* DAC12 data format */
1697 #define DAC12AMP0 (0x0020u) /* DAC12 amplifier bit 0 */
1698 #define DAC12AMP1 (0x0040u) /* DAC12 amplifier bit 1 */
1699 #define DAC12AMP2 (0x0080u) /* DAC12 amplifier bit 2 */
1700 #define DAC12IR (0x0100u) /* DAC12 input reference and output range */
1701 #define DAC12CALON (0x0200u) /* DAC12 calibration */
1702 #define DAC12LSEL0 (0x0400u) /* DAC12 load select bit 0 */
1703 #define DAC12LSEL1 (0x0800u) /* DAC12 load select bit 1 */
1704 #define DAC12RES (0x1000u) /* DAC12 resolution */
1705 #define DAC12SREF0 (0x2000u) /* DAC12 reference bit 0 */
1706 #define DAC12SREF1 (0x4000u) /* DAC12 reference bit 1 */
1707 #define DAC12OPS (0x8000u) /* DAC12 Operation Amp. */
1708 
1709 #define DAC12AMP_0 (0*0x0020u) /* DAC12 amplifier 0: off, 3-state */
1710 #define DAC12AMP_1 (1*0x0020u) /* DAC12 amplifier 1: off, off */
1711 #define DAC12AMP_2 (2*0x0020u) /* DAC12 amplifier 2: low, low */
1712 #define DAC12AMP_3 (3*0x0020u) /* DAC12 amplifier 3: low, medium */
1713 #define DAC12AMP_4 (4*0x0020u) /* DAC12 amplifier 4: low, high */
1714 #define DAC12AMP_5 (5*0x0020u) /* DAC12 amplifier 5: medium, medium */
1715 #define DAC12AMP_6 (6*0x0020u) /* DAC12 amplifier 6: medium, high */
1716 #define DAC12AMP_7 (7*0x0020u) /* DAC12 amplifier 7: high, high */
1717 
1718 #define DAC12LSEL_0 (0*0x0400u) /* DAC12 load select 0: direct */
1719 #define DAC12LSEL_1 (1*0x0400u) /* DAC12 load select 1: latched with DAT */
1720 #define DAC12LSEL_2 (2*0x0400u) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */
1721 #define DAC12LSEL_3 (3*0x0400u) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */
1722 
1723 #define DAC12SREF_0 (0*0x2000u) /* DAC12 reference 0: Vref+ */
1724 #define DAC12SREF_1 (1*0x2000u) /* DAC12 reference 1: Vref+ */
1725 #define DAC12SREF_2 (2*0x2000u) /* DAC12 reference 2: Veref+ */
1726 #define DAC12SREF_3 (3*0x2000u) /* DAC12 reference 3: Veref+ */
1727 
1728 /* DAC12_xCTL1 Control Bits */
1729 #define DAC12DFJ (0x0001u) /* DAC12 Data Format Justification */
1730 #define DAC12OG (0x0002u) /* DAC12 output buffer gain: 0: 3x gain / 1: 2x gain */
1731 
1732 /* DAC12_xCALCTL Control Bits */
1733 #define DAC12LOCK (0x0001u) /* DAC12 Calibration Lock */
1734 
1735 #define DAC12PW (0xA500u) /* DAC12 Calibration Register write Password */
1736 
1737 /* DACIV Definitions */
1738 #define DACIV_NONE (0x0000u) /* No Interrupt pending */
1739 #define DACIV_DAC12IFG_0 (0x0002u) /* DAC12IFG_0 */
1740 #define DACIV_DAC12IFG_1 (0x0004u) /* DAC12IFG_1 */
1741 
1742 #endif
1743 /************************************************************
1744 * DMA_X
1745 ************************************************************/
1746 #ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
1747 
1748 #define OFS_DMACTL0 (0x0000u) /* DMA Module Control 0 */
1749 #define OFS_DMACTL0_L OFS_DMACTL0
1750 #define OFS_DMACTL0_H OFS_DMACTL0+1
1751 #define OFS_DMACTL1 (0x0002u) /* DMA Module Control 1 */
1752 #define OFS_DMACTL1_L OFS_DMACTL1
1753 #define OFS_DMACTL1_H OFS_DMACTL1+1
1754 #define OFS_DMACTL2 (0x0004u) /* DMA Module Control 2 */
1755 #define OFS_DMACTL2_L OFS_DMACTL2
1756 #define OFS_DMACTL2_H OFS_DMACTL2+1
1757 #define OFS_DMACTL3 (0x0006u) /* DMA Module Control 3 */
1758 #define OFS_DMACTL3_L OFS_DMACTL3
1759 #define OFS_DMACTL3_H OFS_DMACTL3+1
1760 #define OFS_DMACTL4 (0x0008u) /* DMA Module Control 4 */
1761 #define OFS_DMACTL4_L OFS_DMACTL4
1762 #define OFS_DMACTL4_H OFS_DMACTL4+1
1763 #define OFS_DMAIV (0x000Eu) /* DMA Interrupt Vector Word */
1764 #define OFS_DMAIV_L OFS_DMAIV
1765 #define OFS_DMAIV_H OFS_DMAIV+1
1766 
1767 #define OFS_DMA0CTL (0x0010u) /* DMA Channel 0 Control */
1768 #define OFS_DMA0CTL_L OFS_DMA0CTL
1769 #define OFS_DMA0CTL_H OFS_DMA0CTL+1
1770 #define OFS_DMA0SA (0x0012u) /* DMA Channel 0 Source Address */
1771 #define OFS_DMA0DA (0x0016u) /* DMA Channel 0 Destination Address */
1772 #define OFS_DMA0SZ (0x001Au) /* DMA Channel 0 Transfer Size */
1773 
1774 #define OFS_DMA1CTL (0x0020u) /* DMA Channel 1 Control */
1775 #define OFS_DMA1CTL_L OFS_DMA1CTL
1776 #define OFS_DMA1CTL_H OFS_DMA1CTL+1
1777 #define OFS_DMA1SA (0x0022u) /* DMA Channel 1 Source Address */
1778 #define OFS_DMA1DA (0x0026u) /* DMA Channel 1 Destination Address */
1779 #define OFS_DMA1SZ (0x002Au) /* DMA Channel 1 Transfer Size */
1780 
1781 #define OFS_DMA2CTL (0x0030u) /* DMA Channel 2 Control */
1782 #define OFS_DMA2CTL_L OFS_DMA2CTL
1783 #define OFS_DMA2CTL_H OFS_DMA2CTL+1
1784 #define OFS_DMA2SA (0x0032u) /* DMA Channel 2 Source Address */
1785 #define OFS_DMA2DA (0x0036u) /* DMA Channel 2 Destination Address */
1786 #define OFS_DMA2SZ (0x003Au) /* DMA Channel 2 Transfer Size */
1787 
1788 /* DMACTL0 Control Bits */
1789 #define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */
1790 #define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */
1791 #define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */
1792 #define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */
1793 #define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */
1794 #define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */
1795 #define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */
1796 #define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */
1797 #define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */
1798 #define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */
1799 
1800 /* DMACTL0 Control Bits */
1801 #define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */
1802 #define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */
1803 #define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */
1804 #define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */
1805 #define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */
1806 
1807 /* DMACTL0 Control Bits */
1808 #define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */
1809 #define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */
1810 #define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */
1811 #define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */
1812 #define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */
1813 
1814 /* DMACTL01 Control Bits */
1815 #define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */
1816 #define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */
1817 #define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */
1818 #define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */
1819 #define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */
1820 
1821 /* DMACTL01 Control Bits */
1822 #define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */
1823 #define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */
1824 #define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */
1825 #define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */
1826 #define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */
1827 
1828 /* DMACTL4 Control Bits */
1829 #define ENNMI (0x0001u) /* Enable NMI interruption of DMA */
1830 #define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */
1831 #define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */
1832 
1833 /* DMACTL4 Control Bits */
1834 #define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */
1835 #define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */
1836 #define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */
1837 
1838 /* DMAxCTL Control Bits */
1839 #define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */
1840 #define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */
1841 #define DMAIE (0x0004u) /* DMA interrupt enable */
1842 #define DMAIFG (0x0008u) /* DMA interrupt flag */
1843 #define DMAEN (0x0010u) /* DMA enable */
1844 #define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */
1845 #define DMASRCBYTE (0x0040u) /* DMA source byte */
1846 #define DMADSTBYTE (0x0080u) /* DMA destination byte */
1847 #define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */
1848 #define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */
1849 #define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */
1850 #define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */
1851 #define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */
1852 #define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */
1853 #define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */
1854 
1855 /* DMAxCTL Control Bits */
1856 #define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */
1857 #define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */
1858 #define DMAIE_L (0x0004u) /* DMA interrupt enable */
1859 #define DMAIFG_L (0x0008u) /* DMA interrupt flag */
1860 #define DMAEN_L (0x0010u) /* DMA enable */
1861 #define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */
1862 #define DMASRCBYTE_L (0x0040u) /* DMA source byte */
1863 #define DMADSTBYTE_L (0x0080u) /* DMA destination byte */
1864 
1865 /* DMAxCTL Control Bits */
1866 #define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */
1867 #define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */
1868 #define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */
1869 #define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */
1870 #define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */
1871 #define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */
1872 #define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */
1873 
1874 #define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
1875 #define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
1876 #define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
1877 #define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
1878 
1879 #define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
1880 #define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
1881 #define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
1882 #define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
1883 
1884 #define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
1885 #define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
1886 #define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
1887 #define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
1888 
1889 #define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
1890 #define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
1891 #define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
1892 #define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
1893 #define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
1894 #define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
1895 #define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
1896 #define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
1897 
1898 /* DMAIV Definitions */
1899 #define DMAIV_NONE (0x0000u) /* No Interrupt pending */
1900 #define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/
1901 #define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/
1902 #define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/
1903 
1904 #endif
1905 /************************************************************
1906 * DMA_X
1907 ************************************************************/
1908 #ifdef __MSP430_HAS_DMAX_6__ /* Definition to show that Module is available */
1909 
1910 #define OFS_DMACTL0 (0x0000u) /* DMA Module Control 0 */
1911 #define OFS_DMACTL0_L OFS_DMACTL0
1912 #define OFS_DMACTL0_H OFS_DMACTL0+1
1913 #define OFS_DMACTL1 (0x0002u) /* DMA Module Control 1 */
1914 #define OFS_DMACTL1_L OFS_DMACTL1
1915 #define OFS_DMACTL1_H OFS_DMACTL1+1
1916 #define OFS_DMACTL2 (0x0004u) /* DMA Module Control 2 */
1917 #define OFS_DMACTL2_L OFS_DMACTL2
1918 #define OFS_DMACTL2_H OFS_DMACTL2+1
1919 #define OFS_DMACTL3 (0x0006u) /* DMA Module Control 3 */
1920 #define OFS_DMACTL3_L OFS_DMACTL3
1921 #define OFS_DMACTL3_H OFS_DMACTL3+1
1922 #define OFS_DMACTL4 (0x0008u) /* DMA Module Control 4 */
1923 #define OFS_DMACTL4_L OFS_DMACTL4
1924 #define OFS_DMACTL4_H OFS_DMACTL4+1
1925 #define OFS_DMAIV (0x000Eu) /* DMA Interrupt Vector Word */
1926 #define OFS_DMAIV_L OFS_DMAIV
1927 #define OFS_DMAIV_H OFS_DMAIV+1
1928 
1929 #define OFS_DMA0CTL (0x0010u) /* DMA Channel 0 Control */
1930 #define OFS_DMA0CTL_L OFS_DMA0CTL
1931 #define OFS_DMA0CTL_H OFS_DMA0CTL+1
1932 #define OFS_DMA0SA (0x0012u) /* DMA Channel 0 Source Address */
1933 #define OFS_DMA0DA (0x0016u) /* DMA Channel 0 Destination Address */
1934 #define OFS_DMA0SZ (0x001Au) /* DMA Channel 0 Transfer Size */
1935 
1936 #define OFS_DMA1CTL (0x0020u) /* DMA Channel 1 Control */
1937 #define OFS_DMA1CTL_L OFS_DMA1CTL
1938 #define OFS_DMA1CTL_H OFS_DMA1CTL+1
1939 #define OFS_DMA1SA (0x0022u) /* DMA Channel 1 Source Address */
1940 #define OFS_DMA1DA (0x0026u) /* DMA Channel 1 Destination Address */
1941 #define OFS_DMA1SZ (0x002Au) /* DMA Channel 1 Transfer Size */
1942 
1943 #define OFS_DMA2CTL (0x0030u) /* DMA Channel 2 Control */
1944 #define OFS_DMA2CTL_L OFS_DMA2CTL
1945 #define OFS_DMA2CTL_H OFS_DMA2CTL+1
1946 #define OFS_DMA2SA (0x0032u) /* DMA Channel 2 Source Address */
1947 #define OFS_DMA2DA (0x0036u) /* DMA Channel 2 Destination Address */
1948 #define OFS_DMA2SZ (0x003Au) /* DMA Channel 2 Transfer Size */
1949 
1950 #define OFS_DMA3CTL (0x0040u) /* DMA Channel 3 Control */
1951 #define OFS_DMA3CTL_L OFS_DMA3CTL
1952 #define OFS_DMA3CTL_H OFS_DMA3CTL+1
1953 #define OFS_DMA3SA (0x0042u) /* DMA Channel 3 Source Address */
1954 #define OFS_DMA3DA (0x0046u) /* DMA Channel 3 Destination Address */
1955 #define OFS_DMA3SZ (0x004Au) /* DMA Channel 3 Transfer Size */
1956 
1957 #define OFS_DMA4CTL (0x0050u) /* DMA Channel 4 Control */
1958 #define OFS_DMA4CTL_L OFS_DMA4CTL
1959 #define OFS_DMA4CTL_H OFS_DMA4CTL+1
1960 #define OFS_DMA4SA (0x0052u) /* DMA Channel 4 Source Address */
1961 #define OFS_DMA4DA (0x0056u) /* DMA Channel 4 Destination Address */
1962 #define OFS_DMA4SZ (0x005Au) /* DMA Channel 4 Transfer Size */
1963 
1964 #define OFS_DMA5CTL (0x0060u) /* DMA Channel 5 Control */
1965 #define OFS_DMA5CTL_L OFS_DMA5CTL
1966 #define OFS_DMA5CTL_H OFS_DMA5CTL+1
1967 #define OFS_DMA5SA (0x0062u) /* DMA Channel 5 Source Address */
1968 #define OFS_DMA5DA (0x0066u) /* DMA Channel 5 Destination Address */
1969 #define OFS_DMA5SZ (0x006Au) /* DMA Channel 5 Transfer Size */
1970 
1971 /* DMACTL0 Control Bits */
1972 #define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */
1973 #define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */
1974 #define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */
1975 #define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */
1976 #define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */
1977 #define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */
1978 #define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */
1979 #define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */
1980 #define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */
1981 #define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */
1982 
1983 /* DMACTL0 Control Bits */
1984 #define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */
1985 #define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */
1986 #define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */
1987 #define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */
1988 #define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */
1989 
1990 /* DMACTL0 Control Bits */
1991 #define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */
1992 #define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */
1993 #define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */
1994 #define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */
1995 #define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */
1996 
1997 /* DMACTL01 Control Bits */
1998 #define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */
1999 #define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */
2000 #define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */
2001 #define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */
2002 #define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */
2003 #define DMA3TSEL0 (0x0100u) /* DMA channel 3 transfer select bit 0 */
2004 #define DMA3TSEL1 (0x0200u) /* DMA channel 3 transfer select bit 1 */
2005 #define DMA3TSEL2 (0x0400u) /* DMA channel 3 transfer select bit 2 */
2006 #define DMA3TSEL3 (0x0800u) /* DMA channel 3 transfer select bit 3 */
2007 #define DMA3TSEL4 (0x1000u) /* DMA channel 3 transfer select bit 4 */
2008 
2009 /* DMACTL01 Control Bits */
2010 #define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */
2011 #define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */
2012 #define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */
2013 #define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */
2014 #define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */
2015 
2016 /* DMACTL01 Control Bits */
2017 #define DMA3TSEL0_H (0x0001u) /* DMA channel 3 transfer select bit 0 */
2018 #define DMA3TSEL1_H (0x0002u) /* DMA channel 3 transfer select bit 1 */
2019 #define DMA3TSEL2_H (0x0004u) /* DMA channel 3 transfer select bit 2 */
2020 #define DMA3TSEL3_H (0x0008u) /* DMA channel 3 transfer select bit 3 */
2021 #define DMA3TSEL4_H (0x0010u) /* DMA channel 3 transfer select bit 4 */
2022 
2023 /* DMACTL0 Control Bits */
2024 #define DMA4TSEL0 (0x0001u) /* DMA channel 4 transfer select bit 0 */
2025 #define DMA4TSEL1 (0x0002u) /* DMA channel 4 transfer select bit 1 */
2026 #define DMA4TSEL2 (0x0004u) /* DMA channel 4 transfer select bit 2 */
2027 #define DMA4TSEL3 (0x0008u) /* DMA channel 4 transfer select bit 3 */
2028 #define DMA4TSEL4 (0x0010u) /* DMA channel 4 transfer select bit 4 */
2029 #define DMA5TSEL0 (0x0100u) /* DMA channel 5 transfer select bit 0 */
2030 #define DMA5TSEL1 (0x0200u) /* DMA channel 5 transfer select bit 1 */
2031 #define DMA5TSEL2 (0x0400u) /* DMA channel 5 transfer select bit 2 */
2032 #define DMA5TSEL3 (0x0800u) /* DMA channel 5 transfer select bit 3 */
2033 #define DMA5TSEL4 (0x1000u) /* DMA channel 5 transfer select bit 4 */
2034 
2035 /* DMACTL0 Control Bits */
2036 #define DMA4TSEL0_L (0x0001u) /* DMA channel 4 transfer select bit 0 */
2037 #define DMA4TSEL1_L (0x0002u) /* DMA channel 4 transfer select bit 1 */
2038 #define DMA4TSEL2_L (0x0004u) /* DMA channel 4 transfer select bit 2 */
2039 #define DMA4TSEL3_L (0x0008u) /* DMA channel 4 transfer select bit 3 */
2040 #define DMA4TSEL4_L (0x0010u) /* DMA channel 4 transfer select bit 4 */
2041 
2042 /* DMACTL0 Control Bits */
2043 #define DMA5TSEL0_H (0x0001u) /* DMA channel 5 transfer select bit 0 */
2044 #define DMA5TSEL1_H (0x0002u) /* DMA channel 5 transfer select bit 1 */
2045 #define DMA5TSEL2_H (0x0004u) /* DMA channel 5 transfer select bit 2 */
2046 #define DMA5TSEL3_H (0x0008u) /* DMA channel 5 transfer select bit 3 */
2047 #define DMA5TSEL4_H (0x0010u) /* DMA channel 5 transfer select bit 4 */
2048 
2049 /* DMACTL4 Control Bits */
2050 #define ENNMI (0x0001u) /* Enable NMI interruption of DMA */
2051 #define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */
2052 #define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */
2053 
2054 /* DMACTL4 Control Bits */
2055 #define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */
2056 #define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */
2057 #define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */
2058 
2059 /* DMAxCTL Control Bits */
2060 #define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */
2061 #define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */
2062 #define DMAIE (0x0004u) /* DMA interrupt enable */
2063 #define DMAIFG (0x0008u) /* DMA interrupt flag */
2064 #define DMAEN (0x0010u) /* DMA enable */
2065 #define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */
2066 #define DMASRCBYTE (0x0040u) /* DMA source byte */
2067 #define DMADSTBYTE (0x0080u) /* DMA destination byte */
2068 #define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */
2069 #define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */
2070 #define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */
2071 #define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */
2072 #define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */
2073 #define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */
2074 #define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */
2075 
2076 /* DMAxCTL Control Bits */
2077 #define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */
2078 #define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */
2079 #define DMAIE_L (0x0004u) /* DMA interrupt enable */
2080 #define DMAIFG_L (0x0008u) /* DMA interrupt flag */
2081 #define DMAEN_L (0x0010u) /* DMA enable */
2082 #define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */
2083 #define DMASRCBYTE_L (0x0040u) /* DMA source byte */
2084 #define DMADSTBYTE_L (0x0080u) /* DMA destination byte */
2085 
2086 /* DMAxCTL Control Bits */
2087 #define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */
2088 #define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */
2089 #define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */
2090 #define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */
2091 #define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */
2092 #define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */
2093 #define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */
2094 
2095 #define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
2096 #define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
2097 #define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
2098 #define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
2099 
2100 #define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
2101 #define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
2102 #define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
2103 #define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
2104 
2105 #define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
2106 #define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
2107 #define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
2108 #define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
2109 
2110 #define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
2111 #define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
2112 #define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
2113 #define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
2114 #define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
2115 #define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
2116 #define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
2117 #define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
2118 
2119 /* DMAIV Definitions */
2120 #define DMAIV_NONE (0x0000u) /* No Interrupt pending */
2121 #define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/
2122 #define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/
2123 #define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/
2124 #define DMAIV_DMA3IFG (0x0008u) /* DMA3IFG*/
2125 #define DMAIV_DMA4IFG (0x000Au) /* DMA4IFG*/
2126 #define DMAIV_DMA5IFG (0x000Cu) /* DMA5IFG*/
2127 
2128 #endif
2129 /*************************************************************
2130 * Flash Memory
2131 *************************************************************/
2132 #ifdef __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
2133 
2134 #define OFS_FCTL1 (0x0000u) /* FLASH Control 1 */
2135 #define OFS_FCTL1_L OFS_FCTL1
2136 #define OFS_FCTL1_H OFS_FCTL1+1
2137 //#define FCTL2_O (0x0002u) /* FLASH Control 2 */
2138 #define OFS_FCTL3 (0x0004u) /* FLASH Control 3 */
2139 #define OFS_FCTL3_L OFS_FCTL3
2140 #define OFS_FCTL3_H OFS_FCTL3+1
2141 #define OFS_FCTL4 (0x0006u) /* FLASH Control 4 */
2142 #define OFS_FCTL4_L OFS_FCTL4
2143 #define OFS_FCTL4_H OFS_FCTL4+1
2144 
2145 #define FRPW (0x9600u) /* Flash password returned by read */
2146 #define FWPW (0xA500u) /* Flash password for write */
2147 #define FXPW (0x3300u) /* for use with XOR instruction */
2148 #define FRKEY (0x9600u) /* (legacy definition) Flash key returned by read */
2149 #define FWKEY (0xA500u) /* (legacy definition) Flash key for write */
2150 #define FXKEY (0x3300u) /* (legacy definition) for use with XOR instruction */
2151 
2152 /* FCTL1 Control Bits */
2153 //#define RESERVED (0x0001u) /* Reserved */
2154 #define ERASE (0x0002u) /* Enable bit for Flash segment erase */
2155 #define MERAS (0x0004u) /* Enable bit for Flash mass erase */
2156 //#define RESERVED (0x0008u) /* Reserved */
2157 //#define RESERVED (0x0010u) /* Reserved */
2158 #define SWRT (0x0020u) /* Smart Write enable */
2159 #define WRT (0x0040u) /* Enable bit for Flash write */
2160 #define BLKWRT (0x0080u) /* Enable bit for Flash segment write */
2161 
2162 /* FCTL1 Control Bits */
2163 //#define RESERVED (0x0001u) /* Reserved */
2164 #define ERASE_L (0x0002u) /* Enable bit for Flash segment erase */
2165 #define MERAS_L (0x0004u) /* Enable bit for Flash mass erase */
2166 //#define RESERVED (0x0008u) /* Reserved */
2167 //#define RESERVED (0x0010u) /* Reserved */
2168 #define SWRT_L (0x0020u) /* Smart Write enable */
2169 #define WRT_L (0x0040u) /* Enable bit for Flash write */
2170 #define BLKWRT_L (0x0080u) /* Enable bit for Flash segment write */
2171 
2172 /* FCTL3 Control Bits */
2173 #define BUSY (0x0001u) /* Flash busy: 1 */
2174 #define KEYV (0x0002u) /* Flash Key violation flag */
2175 #define ACCVIFG (0x0004u) /* Flash Access violation flag */
2176 #define WAIT (0x0008u) /* Wait flag for segment write */
2177 #define LOCK (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */
2178 #define EMEX (0x0020u) /* Flash Emergency Exit */
2179 #define LOCKA (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
2180 //#define RESERVED (0x0080u) /* Reserved */
2181 
2182 /* FCTL3 Control Bits */
2183 #define BUSY_L (0x0001u) /* Flash busy: 1 */
2184 #define KEYV_L (0x0002u) /* Flash Key violation flag */
2185 #define ACCVIFG_L (0x0004u) /* Flash Access violation flag */
2186 #define WAIT_L (0x0008u) /* Wait flag for segment write */
2187 #define LOCK_L (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */
2188 #define EMEX_L (0x0020u) /* Flash Emergency Exit */
2189 #define LOCKA_L (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
2190 //#define RESERVED (0x0080u) /* Reserved */
2191 
2192 /* FCTL4 Control Bits */
2193 #define VPE (0x0001u) /* Voltage Changed during Program Error Flag */
2194 #define MGR0 (0x0010u) /* Marginal read 0 mode. */
2195 #define MGR1 (0x0020u) /* Marginal read 1 mode. */
2196 #define LOCKINFO (0x0080u) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
2197 
2198 /* FCTL4 Control Bits */
2199 #define VPE_L (0x0001u) /* Voltage Changed during Program Error Flag */
2200 #define MGR0_L (0x0010u) /* Marginal read 0 mode. */
2201 #define MGR1_L (0x0020u) /* Marginal read 1 mode. */
2202 #define LOCKINFO_L (0x0080u) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
2203 
2204 #endif
2205 /************************************************************
2206 * LCD_B
2207 ************************************************************/
2208 #ifdef __MSP430_HAS_LCD_B__ /* Definition to show that Module is available */
2209 
2210 #define OFS_LCDBCTL0 (0x0000u) /* LCD_B Control Register 0 */
2211 #define OFS_LCDBCTL0_L OFS_LCDBCTL0
2212 #define OFS_LCDBCTL0_H OFS_LCDBCTL0+1
2213 #define OFS_LCDBCTL1 (0x0002u) /* LCD_B Control Register 1 */
2214 #define OFS_LCDBCTL1_L OFS_LCDBCTL1
2215 #define OFS_LCDBCTL1_H OFS_LCDBCTL1+1
2216 #define OFS_LCDBBLKCTL (0x0004u) /* LCD_B blinking control register */
2217 #define OFS_LCDBBLKCTL_L OFS_LCDBBLKCTL
2218 #define OFS_LCDBBLKCTL_H OFS_LCDBBLKCTL+1
2219 #define OFS_LCDBMEMCTL (0x0006u) /* LCD_B memory control register */
2220 #define OFS_LCDBMEMCTL_L OFS_LCDBMEMCTL
2221 #define OFS_LCDBMEMCTL_H OFS_LCDBMEMCTL+1
2222 #define OFS_LCDBVCTL (0x0008u) /* LCD_B Voltage Control Register */
2223 #define OFS_LCDBVCTL_L OFS_LCDBVCTL
2224 #define OFS_LCDBVCTL_H OFS_LCDBVCTL+1
2225 #define OFS_LCDBPCTL0 (0x000Au) /* LCD_B Port Control Register 0 */
2226 #define OFS_LCDBPCTL0_L OFS_LCDBPCTL0
2227 #define OFS_LCDBPCTL0_H OFS_LCDBPCTL0+1
2228 #define OFS_LCDBPCTL1 (0x000Cu) /* LCD_B Port Control Register 1 */
2229 #define OFS_LCDBPCTL1_L OFS_LCDBPCTL1
2230 #define OFS_LCDBPCTL1_H OFS_LCDBPCTL1+1
2231 #define OFS_LCDBPCTL2 (0x000Eu) /* LCD_B Port Control Register 2 */
2232 #define OFS_LCDBPCTL2_L OFS_LCDBPCTL2
2233 #define OFS_LCDBPCTL2_H OFS_LCDBPCTL2+1
2234 #define OFS_LCDBPCTL3 (0x0010u) /* LCD_B Port Control Register 3 */
2235 #define OFS_LCDBPCTL3_L OFS_LCDBPCTL3
2236 #define OFS_LCDBPCTL3_H OFS_LCDBPCTL3+1
2237 #define OFS_LCDBCPCTL (0x0012u) /* LCD_B Charge Pump Control Register 3 */
2238 #define OFS_LCDBCPCTL_L OFS_LCDBCPCTL
2239 #define OFS_LCDBCPCTL_H OFS_LCDBCPCTL+1
2240 #define OFS_LCDBIV (0x001Eu) /* LCD_B Interrupt Vector Register */
2241 
2242 // LCDBCTL0
2243 #define LCDON (0x0001u) /* LCD_B LCD On */
2244 #define LCDSON (0x0004u) /* LCD_B LCD Segments On */
2245 #define LCDMX0 (0x0008u) /* LCD_B Mux Rate Bit: 0 */
2246 #define LCDMX1 (0x0010u) /* LCD_B Mux Rate Bit: 1 */
2247 //#define RESERVED (0x0020u) /* LCD_B RESERVED */
2248 //#define RESERVED (0x0040u) /* LCD_B RESERVED */
2249 #define LCDSSEL (0x0080u) /* LCD_B Clock Select */
2250 #define LCDPRE0 (0x0100u) /* LCD_B LCD frequency pre-scaler Bit: 0 */
2251 #define LCDPRE1 (0x0200u) /* LCD_B LCD frequency pre-scaler Bit: 1 */
2252 #define LCDPRE2 (0x0400u) /* LCD_B LCD frequency pre-scaler Bit: 2 */
2253 #define LCDDIV0 (0x0800u) /* LCD_B LCD frequency divider Bit: 0 */
2254 #define LCDDIV1 (0x1000u) /* LCD_B LCD frequency divider Bit: 1 */
2255 #define LCDDIV2 (0x2000u) /* LCD_B LCD frequency divider Bit: 2 */
2256 #define LCDDIV3 (0x4000u) /* LCD_B LCD frequency divider Bit: 3 */
2257 #define LCDDIV4 (0x8000u) /* LCD_B LCD frequency divider Bit: 4 */
2258 
2259 // LCDBCTL0
2260 #define LCDON_L (0x0001u) /* LCD_B LCD On */
2261 #define LCDSON_L (0x0004u) /* LCD_B LCD Segments On */
2262 #define LCDMX0_L (0x0008u) /* LCD_B Mux Rate Bit: 0 */
2263 #define LCDMX1_L (0x0010u) /* LCD_B Mux Rate Bit: 1 */
2264 //#define RESERVED (0x0020u) /* LCD_B RESERVED */
2265 //#define RESERVED (0x0040u) /* LCD_B RESERVED */
2266 #define LCDSSEL_L (0x0080u) /* LCD_B Clock Select */
2267 
2268 // LCDBCTL0
2269 //#define RESERVED (0x0020u) /* LCD_B RESERVED */
2270 //#define RESERVED (0x0040u) /* LCD_B RESERVED */
2271 #define LCDPRE0_H (0x0001u) /* LCD_B LCD frequency pre-scaler Bit: 0 */
2272 #define LCDPRE1_H (0x0002u) /* LCD_B LCD frequency pre-scaler Bit: 1 */
2273 #define LCDPRE2_H (0x0004u) /* LCD_B LCD frequency pre-scaler Bit: 2 */
2274 #define LCDDIV0_H (0x0008u) /* LCD_B LCD frequency divider Bit: 0 */
2275 #define LCDDIV1_H (0x0010u) /* LCD_B LCD frequency divider Bit: 1 */
2276 #define LCDDIV2_H (0x0020u) /* LCD_B LCD frequency divider Bit: 2 */
2277 #define LCDDIV3_H (0x0040u) /* LCD_B LCD frequency divider Bit: 3 */
2278 #define LCDDIV4_H (0x0080u) /* LCD_B LCD frequency divider Bit: 4 */
2279 
2280 #define LCDPRE_0 (0x0000u) /* LCD_B LCD frequency pre-scaler: /1 */
2281 #define LCDPRE_1 (0x0100u) /* LCD_B LCD frequency pre-scaler: /2 */
2282 #define LCDPRE_2 (0x0200u) /* LCD_B LCD frequency pre-scaler: /4 */
2283 #define LCDPRE_3 (0x0300u) /* LCD_B LCD frequency pre-scaler: /8 */
2284 #define LCDPRE_4 (0x0400u) /* LCD_B LCD frequency pre-scaler: /16 */
2285 #define LCDPRE_5 (0x0500u) /* LCD_B LCD frequency pre-scaler: /32 */
2286 #define LCDPRE__1 (0x0000u) /* LCD_B LCD frequency pre-scaler: /1 */
2287 #define LCDPRE__2 (0x0100u) /* LCD_B LCD frequency pre-scaler: /2 */
2288 #define LCDPRE__4 (0x0200u) /* LCD_B LCD frequency pre-scaler: /4 */
2289 #define LCDPRE__8 (0x0300u) /* LCD_B LCD frequency pre-scaler: /8 */
2290 #define LCDPRE__16 (0x0400u) /* LCD_B LCD frequency pre-scaler: /16 */
2291 #define LCDPRE__32 (0x0500u) /* LCD_B LCD frequency pre-scaler: /32 */
2292 
2293 #define LCDDIV_0 (0x0000u) /* LCD_B LCD frequency divider: /1 */
2294 #define LCDDIV_1 (0x0800u) /* LCD_B LCD frequency divider: /2 */
2295 #define LCDDIV_2 (0x1000u) /* LCD_B LCD frequency divider: /3 */
2296 #define LCDDIV_3 (0x1800u) /* LCD_B LCD frequency divider: /4 */
2297 #define LCDDIV_4 (0x2000u) /* LCD_B LCD frequency divider: /5 */
2298 #define LCDDIV_5 (0x2800u) /* LCD_B LCD frequency divider: /6 */
2299 #define LCDDIV_6 (0x3000u) /* LCD_B LCD frequency divider: /7 */
2300 #define LCDDIV_7 (0x3800u) /* LCD_B LCD frequency divider: /8 */
2301 #define LCDDIV_8 (0x4000u) /* LCD_B LCD frequency divider: /9 */
2302 #define LCDDIV_9 (0x4800u) /* LCD_B LCD frequency divider: /10 */
2303 #define LCDDIV_10 (0x5000u) /* LCD_B LCD frequency divider: /11 */
2304 #define LCDDIV_11 (0x5800u) /* LCD_B LCD frequency divider: /12 */
2305 #define LCDDIV_12 (0x6000u) /* LCD_B LCD frequency divider: /13 */
2306 #define LCDDIV_13 (0x6800u) /* LCD_B LCD frequency divider: /14 */
2307 #define LCDDIV_14 (0x7000u) /* LCD_B LCD frequency divider: /15 */
2308 #define LCDDIV_15 (0x7800u) /* LCD_B LCD frequency divider: /16 */
2309 #define LCDDIV_16 (0x8000u) /* LCD_B LCD frequency divider: /17 */
2310 #define LCDDIV_17 (0x8800u) /* LCD_B LCD frequency divider: /18 */
2311 #define LCDDIV_18 (0x9000u) /* LCD_B LCD frequency divider: /19 */
2312 #define LCDDIV_19 (0x9800u) /* LCD_B LCD frequency divider: /20 */
2313 #define LCDDIV_20 (0xA000u) /* LCD_B LCD frequency divider: /21 */
2314 #define LCDDIV_21 (0xA800u) /* LCD_B LCD frequency divider: /22 */
2315 #define LCDDIV_22 (0xB000u) /* LCD_B LCD frequency divider: /23 */
2316 #define LCDDIV_23 (0xB800u) /* LCD_B LCD frequency divider: /24 */
2317 #define LCDDIV_24 (0xC000u) /* LCD_B LCD frequency divider: /25 */
2318 #define LCDDIV_25 (0xC800u) /* LCD_B LCD frequency divider: /26 */
2319 #define LCDDIV_26 (0xD000u) /* LCD_B LCD frequency divider: /27 */
2320 #define LCDDIV_27 (0xD800u) /* LCD_B LCD frequency divider: /28 */
2321 #define LCDDIV_28 (0xE000u) /* LCD_B LCD frequency divider: /29 */
2322 #define LCDDIV_29 (0xE800u) /* LCD_B LCD frequency divider: /30 */
2323 #define LCDDIV_30 (0xF000u) /* LCD_B LCD frequency divider: /31 */
2324 #define LCDDIV_31 (0xF800u) /* LCD_B LCD frequency divider: /32 */
2325 #define LCDDIV__1 (0x0000u) /* LCD_B LCD frequency divider: /1 */
2326 #define LCDDIV__2 (0x0800u) /* LCD_B LCD frequency divider: /2 */
2327 #define LCDDIV__3 (0x1000u) /* LCD_B LCD frequency divider: /3 */
2328 #define LCDDIV__4 (0x1800u) /* LCD_B LCD frequency divider: /4 */
2329 #define LCDDIV__5 (0x2000u) /* LCD_B LCD frequency divider: /5 */
2330 #define LCDDIV__6 (0x2800u) /* LCD_B LCD frequency divider: /6 */
2331 #define LCDDIV__7 (0x3000u) /* LCD_B LCD frequency divider: /7 */
2332 #define LCDDIV__8 (0x3800u) /* LCD_B LCD frequency divider: /8 */
2333 #define LCDDIV__9 (0x4000u) /* LCD_B LCD frequency divider: /9 */
2334 #define LCDDIV__10 (0x4800u) /* LCD_B LCD frequency divider: /10 */
2335 #define LCDDIV__11 (0x5000u) /* LCD_B LCD frequency divider: /11 */
2336 #define LCDDIV__12 (0x5800u) /* LCD_B LCD frequency divider: /12 */
2337 #define LCDDIV__13 (0x6000u) /* LCD_B LCD frequency divider: /13 */
2338 #define LCDDIV__14 (0x6800u) /* LCD_B LCD frequency divider: /14 */
2339 #define LCDDIV__15 (0x7000u) /* LCD_B LCD frequency divider: /15 */
2340 #define LCDDIV__16 (0x7800u) /* LCD_B LCD frequency divider: /16 */
2341 #define LCDDIV__17 (0x8000u) /* LCD_B LCD frequency divider: /17 */
2342 #define LCDDIV__18 (0x8800u) /* LCD_B LCD frequency divider: /18 */
2343 #define LCDDIV__19 (0x9000u) /* LCD_B LCD frequency divider: /19 */
2344 #define LCDDIV__20 (0x9800u) /* LCD_B LCD frequency divider: /20 */
2345 #define LCDDIV__21 (0xA000u) /* LCD_B LCD frequency divider: /21 */
2346 #define LCDDIV__22 (0xA800u) /* LCD_B LCD frequency divider: /22 */
2347 #define LCDDIV__23 (0xB000u) /* LCD_B LCD frequency divider: /23 */
2348 #define LCDDIV__24 (0xB800u) /* LCD_B LCD frequency divider: /24 */
2349 #define LCDDIV__25 (0xC000u) /* LCD_B LCD frequency divider: /25 */
2350 #define LCDDIV__26 (0xC800u) /* LCD_B LCD frequency divider: /26 */
2351 #define LCDDIV__27 (0xD000u) /* LCD_B LCD frequency divider: /27 */
2352 #define LCDDIV__28 (0xD800u) /* LCD_B LCD frequency divider: /28 */
2353 #define LCDDIV__29 (0xE000u) /* LCD_B LCD frequency divider: /29 */
2354 #define LCDDIV__30 (0xE800u) /* LCD_B LCD frequency divider: /30 */
2355 #define LCDDIV__31 (0xF000u) /* LCD_B LCD frequency divider: /31 */
2356 #define LCDDIV__32 (0xF800u) /* LCD_B LCD frequency divider: /32 */
2357 
2358 /* Display modes coded with Bits 2-4 */
2359 #define LCDSTATIC (LCDSON)
2360 #define LCD2MUX (LCDMX0+LCDSON)
2361 #define LCD3MUX (LCDMX1+LCDSON)
2362 #define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
2363 
2364 // LCDBCTL1
2365 #define LCDFRMIFG (0x0001u) /* LCD_B LCD frame interrupt flag */
2366 #define LCDBLKOFFIFG (0x0002u) /* LCD_B LCD blinking off interrupt flag, */
2367 #define LCDBLKONIFG (0x0004u) /* LCD_B LCD blinking on interrupt flag, */
2368 #define LCDNOCAPIFG (0x0008u) /* LCD_B No cpacitance connected interrupt flag */
2369 #define LCDFRMIE (0x0100u) /* LCD_B LCD frame interrupt enable */
2370 #define LCDBLKOFFIE (0x0200u) /* LCD_B LCD blinking off interrupt flag, */
2371 #define LCDBLKONIE (0x0400u) /* LCD_B LCD blinking on interrupt flag, */
2372 #define LCDNOCAPIE (0x0800u) /* LCD_B No cpacitance connected interrupt enable */
2373 
2374 // LCDBCTL1
2375 #define LCDFRMIFG_L (0x0001u) /* LCD_B LCD frame interrupt flag */
2376 #define LCDBLKOFFIFG_L (0x0002u) /* LCD_B LCD blinking off interrupt flag, */
2377 #define LCDBLKONIFG_L (0x0004u) /* LCD_B LCD blinking on interrupt flag, */
2378 #define LCDNOCAPIFG_L (0x0008u) /* LCD_B No cpacitance connected interrupt flag */
2379 
2380 // LCDBCTL1
2381 #define LCDFRMIE_H (0x0001u) /* LCD_B LCD frame interrupt enable */
2382 #define LCDBLKOFFIE_H (0x0002u) /* LCD_B LCD blinking off interrupt flag, */
2383 #define LCDBLKONIE_H (0x0004u) /* LCD_B LCD blinking on interrupt flag, */
2384 #define LCDNOCAPIE_H (0x0008u) /* LCD_B No cpacitance connected interrupt enable */
2385 
2386 // LCDBBLKCTL
2387 #define LCDBLKMOD0 (0x0001u) /* LCD_B Blinking mode Bit: 0 */
2388 #define LCDBLKMOD1 (0x0002u) /* LCD_B Blinking mode Bit: 1 */
2389 #define LCDBLKPRE0 (0x0004u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */
2390 #define LCDBLKPRE1 (0x0008u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */
2391 #define LCDBLKPRE2 (0x0010u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */
2392 #define LCDBLKDIV0 (0x0020u) /* LCD_B Clock divider for blinking frequency Bit: 0 */
2393 #define LCDBLKDIV1 (0x0040u) /* LCD_B Clock divider for blinking frequency Bit: 1 */
2394 #define LCDBLKDIV2 (0x0080u) /* LCD_B Clock divider for blinking frequency Bit: 2 */
2395 
2396 // LCDBBLKCTL
2397 #define LCDBLKMOD0_L (0x0001u) /* LCD_B Blinking mode Bit: 0 */
2398 #define LCDBLKMOD1_L (0x0002u) /* LCD_B Blinking mode Bit: 1 */
2399 #define LCDBLKPRE0_L (0x0004u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */
2400 #define LCDBLKPRE1_L (0x0008u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */
2401 #define LCDBLKPRE2_L (0x0010u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */
2402 #define LCDBLKDIV0_L (0x0020u) /* LCD_B Clock divider for blinking frequency Bit: 0 */
2403 #define LCDBLKDIV1_L (0x0040u) /* LCD_B Clock divider for blinking frequency Bit: 1 */
2404 #define LCDBLKDIV2_L (0x0080u) /* LCD_B Clock divider for blinking frequency Bit: 2 */
2405 
2406 #define LCDBLKMOD_0 (0x0000u) /* LCD_B Blinking mode: Off */
2407 #define LCDBLKMOD_1 (0x0001u) /* LCD_B Blinking mode: Individual */
2408 #define LCDBLKMOD_2 (0x0002u) /* LCD_B Blinking mode: All */
2409 #define LCDBLKMOD_3 (0x0003u) /* LCD_B Blinking mode: Switching */
2410 
2411 // LCDBMEMCTL
2412 #define LCDDISP (0x0001u) /* LCD_B LCD memory registers for display */
2413 #define LCDCLRM (0x0002u) /* LCD_B Clear LCD memory */
2414 #define LCDCLRBM (0x0004u) /* LCD_B Clear LCD blinking memory */
2415 
2416 // LCDBMEMCTL
2417 #define LCDDISP_L (0x0001u) /* LCD_B LCD memory registers for display */
2418 #define LCDCLRM_L (0x0002u) /* LCD_B Clear LCD memory */
2419 #define LCDCLRBM_L (0x0004u) /* LCD_B Clear LCD blinking memory */
2420 
2421 // LCDBVCTL
2422 #define LCD2B (0x0001u) /* Selects 1/2 bias. */
2423 #define VLCDREF0 (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */
2424 #define VLCDREF1 (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */
2425 #define LCDCPEN (0x0008u) /* LCD Voltage Charge Pump Enable. */
2426 #define VLCDEXT (0x0010u) /* Select external source for VLCD. */
2427 #define LCDEXTBIAS (0x0020u) /* V2 - V4 voltage select. */
2428 #define R03EXT (0x0040u) /* Selects external connections for LCD mid voltages. */
2429 #define LCDREXT (0x0080u) /* Selects external connection for lowest LCD voltage. */
2430 #define VLCD0 (0x0200u) /* VLCD select: 0 */
2431 #define VLCD1 (0x0400u) /* VLCD select: 1 */
2432 #define VLCD2 (0x0800u) /* VLCD select: 2 */
2433 #define VLCD3 (0x1000u) /* VLCD select: 3 */
2434 
2435 // LCDBVCTL
2436 #define LCD2B_L (0x0001u) /* Selects 1/2 bias. */
2437 #define VLCDREF0_L (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */
2438 #define VLCDREF1_L (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */
2439 #define LCDCPEN_L (0x0008u) /* LCD Voltage Charge Pump Enable. */
2440 #define VLCDEXT_L (0x0010u) /* Select external source for VLCD. */
2441 #define LCDEXTBIAS_L (0x0020u) /* V2 - V4 voltage select. */
2442 #define R03EXT_L (0x0040u) /* Selects external connections for LCD mid voltages. */
2443 #define LCDREXT_L (0x0080u) /* Selects external connection for lowest LCD voltage. */
2444 
2445 // LCDBVCTL
2446 #define VLCD0_H (0x0002u) /* VLCD select: 0 */
2447 #define VLCD1_H (0x0004u) /* VLCD select: 1 */
2448 #define VLCD2_H (0x0008u) /* VLCD select: 2 */
2449 #define VLCD3_H (0x0010u) /* VLCD select: 3 */
2450 
2451 /* Reference voltage source select for the regulated charge pump */
2452 #define VLCDREF_0 (0<<1) /* Internal */
2453 #define VLCDREF_1 (1<<1) /* External */
2454 #define VLCDREF_2 (2<<1) /* Reserved */
2455 #define VLCDREF_3 (3<<1) /* Reserved */
2456 
2457 /* Charge pump voltage selections */
2458 #define VLCD_0 (0<<9) /* Charge pump disabled */
2459 #define VLCD_1 (1<<9) /* VLCD = 2.60V */
2460 #define VLCD_2 (2<<9) /* VLCD = 2.66V */
2461 #define VLCD_3 (3<<9) /* VLCD = 2.72V */
2462 #define VLCD_4 (4<<9) /* VLCD = 2.78V */
2463 #define VLCD_5 (5<<9) /* VLCD = 2.84V */
2464 #define VLCD_6 (6<<9) /* VLCD = 2.90V */
2465 #define VLCD_7 (7<<9) /* VLCD = 2.96V */
2466 #define VLCD_8 (8<<9) /* VLCD = 3.02V */
2467 #define VLCD_9 (9<<9) /* VLCD = 3.08V */
2468 #define VLCD_10 (10<<9) /* VLCD = 3.14V */
2469 #define VLCD_11 (11<<9) /* VLCD = 3.20V */
2470 #define VLCD_12 (12<<9) /* VLCD = 3.26V */
2471 #define VLCD_13 (13<<9) /* VLCD = 3.32V */
2472 #define VLCD_14 (14<<9) /* VLCD = 3.38V */
2473 #define VLCD_15 (15<<9) /* VLCD = 3.44V */
2474 
2475 #define VLCD_DISABLED (0<<9) /* Charge pump disabled */
2476 #define VLCD_2_60 (1<<9) /* VLCD = 2.60V */
2477 #define VLCD_2_66 (2<<9) /* VLCD = 2.66V */
2478 #define VLCD_2_72 (3<<9) /* VLCD = 2.72V */
2479 #define VLCD_2_78 (4<<9) /* VLCD = 2.78V */
2480 #define VLCD_2_84 (5<<9) /* VLCD = 2.84V */
2481 #define VLCD_2_90 (6<<9) /* VLCD = 2.90V */
2482 #define VLCD_2_96 (7<<9) /* VLCD = 2.96V */
2483 #define VLCD_3_02 (8<<9) /* VLCD = 3.02V */
2484 #define VLCD_3_08 (9<<9) /* VLCD = 3.08V */
2485 #define VLCD_3_14 (10<<9) /* VLCD = 3.14V */
2486 #define VLCD_3_20 (11<<9) /* VLCD = 3.20V */
2487 #define VLCD_3_26 (12<<9) /* VLCD = 3.26V */
2488 #define VLCD_3_32 (13<<9) /* VLCD = 3.32V */
2489 #define VLCD_3_38 (14<<9) /* VLCD = 3.38V */
2490 #define VLCD_3_44 (15<<9) /* VLCD = 3.44V */
2491 
2492 // LCDBPCTL0
2493 #define LCDS0 (0x0001u) /* LCD Segment 0 enable. */
2494 #define LCDS1 (0x0002u) /* LCD Segment 1 enable. */
2495 #define LCDS2 (0x0004u) /* LCD Segment 2 enable. */
2496 #define LCDS3 (0x0008u) /* LCD Segment 3 enable. */
2497 #define LCDS4 (0x0010u) /* LCD Segment 4 enable. */
2498 #define LCDS5 (0x0020u) /* LCD Segment 5 enable. */
2499 #define LCDS6 (0x0040u) /* LCD Segment 6 enable. */
2500 #define LCDS7 (0x0080u) /* LCD Segment 7 enable. */
2501 #define LCDS8 (0x0100u) /* LCD Segment 8 enable. */
2502 #define LCDS9 (0x0200u) /* LCD Segment 9 enable. */
2503 #define LCDS10 (0x0400u) /* LCD Segment 10 enable. */
2504 #define LCDS11 (0x0800u) /* LCD Segment 11 enable. */
2505 #define LCDS12 (0x1000u) /* LCD Segment 12 enable. */
2506 #define LCDS13 (0x2000u) /* LCD Segment 13 enable. */
2507 #define LCDS14 (0x4000u) /* LCD Segment 14 enable. */
2508 #define LCDS15 (0x8000u) /* LCD Segment 15 enable. */
2509 
2510 // LCDBPCTL0
2511 #define LCDS0_L (0x0001u) /* LCD Segment 0 enable. */
2512 #define LCDS1_L (0x0002u) /* LCD Segment 1 enable. */
2513 #define LCDS2_L (0x0004u) /* LCD Segment 2 enable. */
2514 #define LCDS3_L (0x0008u) /* LCD Segment 3 enable. */
2515 #define LCDS4_L (0x0010u) /* LCD Segment 4 enable. */
2516 #define LCDS5_L (0x0020u) /* LCD Segment 5 enable. */
2517 #define LCDS6_L (0x0040u) /* LCD Segment 6 enable. */
2518 #define LCDS7_L (0x0080u) /* LCD Segment 7 enable. */
2519 
2520 // LCDBPCTL0
2521 #define LCDS8_H (0x0001u) /* LCD Segment 8 enable. */
2522 #define LCDS9_H (0x0002u) /* LCD Segment 9 enable. */
2523 #define LCDS10_H (0x0004u) /* LCD Segment 10 enable. */
2524 #define LCDS11_H (0x0008u) /* LCD Segment 11 enable. */
2525 #define LCDS12_H (0x0010u) /* LCD Segment 12 enable. */
2526 #define LCDS13_H (0x0020u) /* LCD Segment 13 enable. */
2527 #define LCDS14_H (0x0040u) /* LCD Segment 14 enable. */
2528 #define LCDS15_H (0x0080u) /* LCD Segment 15 enable. */
2529 
2530 // LCDBPCTL1
2531 #define LCDS16 (0x0001u) /* LCD Segment 16 enable. */
2532 #define LCDS17 (0x0002u) /* LCD Segment 17 enable. */
2533 #define LCDS18 (0x0004u) /* LCD Segment 18 enable. */
2534 #define LCDS19 (0x0008u) /* LCD Segment 19 enable. */
2535 #define LCDS20 (0x0010u) /* LCD Segment 20 enable. */
2536 #define LCDS21 (0x0020u) /* LCD Segment 21 enable. */
2537 #define LCDS22 (0x0040u) /* LCD Segment 22 enable. */
2538 #define LCDS23 (0x0080u) /* LCD Segment 23 enable. */
2539 #define LCDS24 (0x0100u) /* LCD Segment 24 enable. */
2540 #define LCDS25 (0x0200u) /* LCD Segment 25 enable. */
2541 #define LCDS26 (0x0400u) /* LCD Segment 26 enable. */
2542 #define LCDS27 (0x0800u) /* LCD Segment 27 enable. */
2543 #define LCDS28 (0x1000u) /* LCD Segment 28 enable. */
2544 #define LCDS29 (0x2000u) /* LCD Segment 29 enable. */
2545 #define LCDS30 (0x4000u) /* LCD Segment 30 enable. */
2546 #define LCDS31 (0x8000u) /* LCD Segment 31 enable. */
2547 
2548 // LCDBPCTL1
2549 #define LCDS16_L (0x0001u) /* LCD Segment 16 enable. */
2550 #define LCDS17_L (0x0002u) /* LCD Segment 17 enable. */
2551 #define LCDS18_L (0x0004u) /* LCD Segment 18 enable. */
2552 #define LCDS19_L (0x0008u) /* LCD Segment 19 enable. */
2553 #define LCDS20_L (0x0010u) /* LCD Segment 20 enable. */
2554 #define LCDS21_L (0x0020u) /* LCD Segment 21 enable. */
2555 #define LCDS22_L (0x0040u) /* LCD Segment 22 enable. */
2556 #define LCDS23_L (0x0080u) /* LCD Segment 23 enable. */
2557 
2558 // LCDBPCTL1
2559 #define LCDS24_H (0x0001u) /* LCD Segment 24 enable. */
2560 #define LCDS25_H (0x0002u) /* LCD Segment 25 enable. */
2561 #define LCDS26_H (0x0004u) /* LCD Segment 26 enable. */
2562 #define LCDS27_H (0x0008u) /* LCD Segment 27 enable. */
2563 #define LCDS28_H (0x0010u) /* LCD Segment 28 enable. */
2564 #define LCDS29_H (0x0020u) /* LCD Segment 29 enable. */
2565 #define LCDS30_H (0x0040u) /* LCD Segment 30 enable. */
2566 #define LCDS31_H (0x0080u) /* LCD Segment 31 enable. */
2567 
2568 // LCDBPCTL2
2569 #define LCDS32 (0x0001u) /* LCD Segment 32 enable. */
2570 #define LCDS33 (0x0002u) /* LCD Segment 33 enable. */
2571 #define LCDS34 (0x0004u) /* LCD Segment 34 enable. */
2572 #define LCDS35 (0x0008u) /* LCD Segment 35 enable. */
2573 #define LCDS36 (0x0010u) /* LCD Segment 36 enable. */
2574 #define LCDS37 (0x0020u) /* LCD Segment 37 enable. */
2575 #define LCDS38 (0x0040u) /* LCD Segment 38 enable. */
2576 #define LCDS39 (0x0080u) /* LCD Segment 39 enable. */
2577 #define LCDS40 (0x0100u) /* LCD Segment 40 enable. */
2578 #define LCDS41 (0x0200u) /* LCD Segment 41 enable. */
2579 #define LCDS42 (0x0400u) /* LCD Segment 42 enable. */
2580 #define LCDS43 (0x0800u) /* LCD Segment 43 enable. */
2581 #define LCDS44 (0x1000u) /* LCD Segment 44 enable. */
2582 #define LCDS45 (0x2000u) /* LCD Segment 45 enable. */
2583 #define LCDS46 (0x4000u) /* LCD Segment 46 enable. */
2584 #define LCDS47 (0x8000u) /* LCD Segment 47 enable. */
2585 
2586 // LCDBPCTL2
2587 #define LCDS32_L (0x0001u) /* LCD Segment 32 enable. */
2588 #define LCDS33_L (0x0002u) /* LCD Segment 33 enable. */
2589 #define LCDS34_L (0x0004u) /* LCD Segment 34 enable. */
2590 #define LCDS35_L (0x0008u) /* LCD Segment 35 enable. */
2591 #define LCDS36_L (0x0010u) /* LCD Segment 36 enable. */
2592 #define LCDS37_L (0x0020u) /* LCD Segment 37 enable. */
2593 #define LCDS38_L (0x0040u) /* LCD Segment 38 enable. */
2594 #define LCDS39_L (0x0080u) /* LCD Segment 39 enable. */
2595 
2596 // LCDBPCTL2
2597 #define LCDS40_H (0x0001u) /* LCD Segment 40 enable. */
2598 #define LCDS41_H (0x0002u) /* LCD Segment 41 enable. */
2599 #define LCDS42_H (0x0004u) /* LCD Segment 42 enable. */
2600 #define LCDS43_H (0x0008u) /* LCD Segment 43 enable. */
2601 #define LCDS44_H (0x0010u) /* LCD Segment 44 enable. */
2602 #define LCDS45_H (0x0020u) /* LCD Segment 45 enable. */
2603 #define LCDS46_H (0x0040u) /* LCD Segment 46 enable. */
2604 #define LCDS47_H (0x0080u) /* LCD Segment 47 enable. */
2605 
2606 // LCDBPCTL3
2607 #define LCDS48 (0x0001u) /* LCD Segment 48 enable. */
2608 #define LCDS49 (0x0002u) /* LCD Segment 49 enable. */
2609 #define LCDS50 (0x0004u) /* LCD Segment 50 enable. */
2610 
2611 // LCDBPCTL3
2612 #define LCDS48_L (0x0001u) /* LCD Segment 48 enable. */
2613 #define LCDS49_L (0x0002u) /* LCD Segment 49 enable. */
2614 #define LCDS50_L (0x0004u) /* LCD Segment 50 enable. */
2615 
2616 // LCDBCPCTL
2617 #define LCDCPDIS0 (0x0001u) /* LCD charge pump disable */
2618 #define LCDCPDIS1 (0x0002u) /* LCD charge pump disable */
2619 #define LCDCPDIS2 (0x0004u) /* LCD charge pump disable */
2620 #define LCDCPDIS3 (0x0008u) /* LCD charge pump disable */
2621 #define LCDCPDIS4 (0x0010u) /* LCD charge pump disable */
2622 #define LCDCPDIS5 (0x0020u) /* LCD charge pump disable */
2623 #define LCDCPDIS6 (0x0040u) /* LCD charge pump disable */
2624 #define LCDCPDIS7 (0x0080u) /* LCD charge pump disable */
2625 #define LCDCPCLKSYNC (0x8000u) /* LCD charge pump clock synchronization */
2626 
2627 // LCDBCPCTL
2628 #define LCDCPDIS0_L (0x0001u) /* LCD charge pump disable */
2629 #define LCDCPDIS1_L (0x0002u) /* LCD charge pump disable */
2630 #define LCDCPDIS2_L (0x0004u) /* LCD charge pump disable */
2631 #define LCDCPDIS3_L (0x0008u) /* LCD charge pump disable */
2632 #define LCDCPDIS4_L (0x0010u) /* LCD charge pump disable */
2633 #define LCDCPDIS5_L (0x0020u) /* LCD charge pump disable */
2634 #define LCDCPDIS6_L (0x0040u) /* LCD charge pump disable */
2635 #define LCDCPDIS7_L (0x0080u) /* LCD charge pump disable */
2636 
2637 // LCDBCPCTL
2638 #define LCDCPCLKSYNC_H (0x0080u) /* LCD charge pump clock synchronization */
2639 
2640 #define OFS_LCDM1 (0x0020u) /* LCD Memory 1 */
2641 #define LCDMEM_ LCDM1 /* LCD Memory */
2642 #ifndef __IAR_SYSTEMS_ICC__
2643 #define LCDMEM LCDM1 /* LCD Memory (for assembler) */
2644 #else
2645 #define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */
2646 #endif
2647 #define OFS_LCDM2 (0x0021u) /* LCD Memory 2 */
2648 #define OFS_LCDM3 (0x0022u) /* LCD Memory 3 */
2649 #define OFS_LCDM4 (0x0023u) /* LCD Memory 4 */
2650 #define OFS_LCDM5 (0x0024u) /* LCD Memory 5 */
2651 #define OFS_LCDM6 (0x0025u) /* LCD Memory 6 */
2652 #define OFS_LCDM7 (0x0026u) /* LCD Memory 7 */
2653 #define OFS_LCDM8 (0x0027u) /* LCD Memory 8 */
2654 #define OFS_LCDM9 (0x0028u) /* LCD Memory 9 */
2655 #define OFS_LCDM10 (0x0029u) /* LCD Memory 10 */
2656 #define OFS_LCDM11 (0x002Au) /* LCD Memory 11 */
2657 #define OFS_LCDM12 (0x002Bu) /* LCD Memory 12 */
2658 #define OFS_LCDM13 (0x002Cu) /* LCD Memory 13 */
2659 #define OFS_LCDM14 (0x002Du) /* LCD Memory 14 */
2660 #define OFS_LCDM15 (0x002Eu) /* LCD Memory 15 */
2661 #define OFS_LCDM16 (0x002Fu) /* LCD Memory 16 */
2662 #define OFS_LCDM17 (0x0030u) /* LCD Memory 17 */
2663 #define OFS_LCDM18 (0x0031u) /* LCD Memory 18 */
2664 #define OFS_LCDM19 (0x0032u) /* LCD Memory 19 */
2665 #define OFS_LCDM20 (0x0033u) /* LCD Memory 20 */
2666 #define OFS_LCDM21 (0x0034u) /* LCD Memory 21 */
2667 #define OFS_LCDM22 (0x0035u) /* LCD Memory 22 */
2668 #define OFS_LCDM23 (0x0036u) /* LCD Memory 23 */
2669 #define OFS_LCDM24 (0x0037u) /* LCD Memory 24 */
2670 
2671 #define OFS_LCDBM1 (0x0040u) /* LCD Blinking Memory 1 */
2672 #define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */
2673 #ifndef __IAR_SYSTEMS_ICC__
2674 #define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */
2675 #else
2676 #define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */
2677 #endif
2678 #define OFS_LCDBM2 (0x0041u) /* LCD Blinking Memory 2 */
2679 #define OFS_LCDBM3 (0x0042u) /* LCD Blinking Memory 3 */
2680 #define OFS_LCDBM4 (0x0043u) /* LCD Blinking Memory 4 */
2681 #define OFS_LCDBM5 (0x0044u) /* LCD Blinking Memory 5 */
2682 #define OFS_LCDBM6 (0x0045u) /* LCD Blinking Memory 6 */
2683 #define OFS_LCDBM7 (0x0046u) /* LCD Blinking Memory 7 */
2684 #define OFS_LCDBM8 (0x0047u) /* LCD Blinking Memory 8 */
2685 #define OFS_LCDBM9 (0x0048u) /* LCD Blinking Memory 9 */
2686 #define OFS_LCDBM10 (0x0049u) /* LCD Blinking Memory 10 */
2687 #define OFS_LCDBM11 (0x004Au) /* LCD Blinking Memory 11 */
2688 #define OFS_LCDBM12 (0x004Bu) /* LCD Blinking Memory 12 */
2689 #define OFS_LCDBM13 (0x004Cu) /* LCD Blinking Memory 13 */
2690 #define OFS_LCDBM14 (0x004Du) /* LCD Blinking Memory 14 */
2691 #define OFS_LCDBM15 (0x004Eu) /* LCD Blinking Memory 15 */
2692 #define OFS_LCDBM16 (0x004Fu) /* LCD Blinking Memory 16 */
2693 #define OFS_LCDBM17 (0x0050u) /* LCD Blinking Memory 17 */
2694 #define OFS_LCDBM18 (0x0051u) /* LCD Blinking Memory 18 */
2695 #define OFS_LCDBM19 (0x0052u) /* LCD Blinking Memory 19 */
2696 #define OFS_LCDBM20 (0x0053u) /* LCD Blinking Memory 20 */
2697 #define OFS_LCDBM21 (0x0054u) /* LCD Blinking Memory 21 */
2698 #define OFS_LCDBM22 (0x0055u) /* LCD Blinking Memory 22 */
2699 #define OFS_LCDBM23 (0x0056u) /* LCD Blinking Memory 23 */
2700 #define OFS_LCDBM24 (0x0057u) /* LCD Blinking Memory 24 */
2701 
2702 /* LCDBIV Definitions */
2703 #define LCDBIV_NONE (0x0000u) /* No Interrupt pending */
2704 #define LCDBIV_LCDNOCAPIFG (0x0002u) /* No capacitor connected */
2705 #define LCDBIV_LCDBLKOFFIFG (0x0004u) /* Blink, segments off */
2706 #define LCDBIV_LCDBLKONIFG (0x0006u) /* Blink, segments on */
2707 #define LCDBIV_LCDFRMIFG (0x0008u) /* Frame interrupt */
2708 
2709 #endif
2710 /************************************************************
2711 * HARDWARE MULTIPLIER 32Bit
2712 ************************************************************/
2713 #ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */
2714 
2715 #define OFS_MPY (0x0000u) /* Multiply Unsigned/Operand 1 */
2716 #define OFS_MPY_L OFS_MPY
2717 #define OFS_MPY_H OFS_MPY+1
2718 #define OFS_MPYS (0x0002u) /* Multiply Signed/Operand 1 */
2719 #define OFS_MPYS_L OFS_MPYS
2720 #define OFS_MPYS_H OFS_MPYS+1
2721 #define OFS_MAC (0x0004u) /* Multiply Unsigned and Accumulate/Operand 1 */
2722 #define OFS_MAC_L OFS_MAC
2723 #define OFS_MAC_H OFS_MAC+1
2724 #define OFS_MACS (0x0006u) /* Multiply Signed and Accumulate/Operand 1 */
2725 #define OFS_MACS_L OFS_MACS
2726 #define OFS_MACS_H OFS_MACS+1
2727 #define OFS_OP2 (0x0008u) /* Operand 2 */
2728 #define OFS_OP2_L OFS_OP2
2729 #define OFS_OP2_H OFS_OP2+1
2730 #define OFS_RESLO (0x000Au) /* Result Low Word */
2731 #define OFS_RESLO_L OFS_RESLO
2732 #define OFS_RESLO_H OFS_RESLO+1
2733 #define OFS_RESHI (0x000Cu) /* Result High Word */
2734 #define OFS_RESHI_L OFS_RESHI
2735 #define OFS_RESHI_H OFS_RESHI+1
2736 #define OFS_SUMEXT (0x000Eu) /* Sum Extend */
2737 #define OFS_SUMEXT_L OFS_SUMEXT
2738 #define OFS_SUMEXT_H OFS_SUMEXT+1
2739 #define OFS_MPY32CTL0 (0x002Cu)
2740 #define OFS_MPY32CTL0_L OFS_MPY32CTL0
2741 #define OFS_MPY32CTL0_H OFS_MPY32CTL0+1
2742 
2743 #define OFS_MPY32L (0x0010u) /* 32-bit operand 1 - multiply - low word */
2744 #define OFS_MPY32L_L OFS_MPY32L
2745 #define OFS_MPY32L_H OFS_MPY32L+1
2746 #define OFS_MPY32H (0x0012u) /* 32-bit operand 1 - multiply - high word */
2747 #define OFS_MPY32H_L OFS_MPY32H
2748 #define OFS_MPY32H_H OFS_MPY32H+1
2749 #define OFS_MPYS32L (0x0014u) /* 32-bit operand 1 - signed multiply - low word */
2750 #define OFS_MPYS32L_L OFS_MPYS32L
2751 #define OFS_MPYS32L_H OFS_MPYS32L+1
2752 #define OFS_MPYS32H (0x0016u) /* 32-bit operand 1 - signed multiply - high word */
2753 #define OFS_MPYS32H_L OFS_MPYS32H
2754 #define OFS_MPYS32H_H OFS_MPYS32H+1
2755 #define OFS_MAC32L (0x0018u) /* 32-bit operand 1 - multiply accumulate - low word */
2756 #define OFS_MAC32L_L OFS_MAC32L
2757 #define OFS_MAC32L_H OFS_MAC32L+1
2758 #define OFS_MAC32H (0x001Au) /* 32-bit operand 1 - multiply accumulate - high word */
2759 #define OFS_MAC32H_L OFS_MAC32H
2760 #define OFS_MAC32H_H OFS_MAC32H+1
2761 #define OFS_MACS32L (0x001Cu) /* 32-bit operand 1 - signed multiply accumulate - low word */
2762 #define OFS_MACS32L_L OFS_MACS32L
2763 #define OFS_MACS32L_H OFS_MACS32L+1
2764 #define OFS_MACS32H (0x001Eu) /* 32-bit operand 1 - signed multiply accumulate - high word */
2765 #define OFS_MACS32H_L OFS_MACS32H
2766 #define OFS_MACS32H_H OFS_MACS32H+1
2767 #define OFS_OP2L (0x0020u) /* 32-bit operand 2 - low word */
2768 #define OFS_OP2L_L OFS_OP2L
2769 #define OFS_OP2L_H OFS_OP2L+1
2770 #define OFS_OP2H (0x0022u) /* 32-bit operand 2 - high word */
2771 #define OFS_OP2H_L OFS_OP2H
2772 #define OFS_OP2H_H OFS_OP2H+1
2773 #define OFS_RES0 (0x0024u) /* 32x32-bit result 0 - least significant word */
2774 #define OFS_RES0_L OFS_RES0
2775 #define OFS_RES0_H OFS_RES0+1
2776 #define OFS_RES1 (0x0026u) /* 32x32-bit result 1 */
2777 #define OFS_RES1_L OFS_RES1
2778 #define OFS_RES1_H OFS_RES1+1
2779 #define OFS_RES2 (0x0028u) /* 32x32-bit result 2 */
2780 #define OFS_RES2_L OFS_RES2
2781 #define OFS_RES2_H OFS_RES2+1
2782 #define OFS_RES3 (0x002Au) /* 32x32-bit result 3 - most significant word */
2783 #define OFS_RES3_L OFS_RES3
2784 #define OFS_RES3_H OFS_RES3+1
2785 #define OFS_SUMEXT (0x000Eu)
2786 #define OFS_SUMEXT_L OFS_SUMEXT
2787 #define OFS_SUMEXT_H OFS_SUMEXT+1
2788 #define OFS_MPY32CTL0 (0x002Cu) /* MPY32 Control Register 0 */
2789 #define OFS_MPY32CTL0_L OFS_MPY32CTL0
2790 #define OFS_MPY32CTL0_H OFS_MPY32CTL0+1
2791 
2792 #define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
2793 #define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
2794 #define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
2795 #define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
2796 #define OP2_B OP2_L /* Operand 2 (Byte Access) */
2797 #define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
2798 #define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
2799 #define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
2800 #define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
2801 #define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
2802 #define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
2803 #define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
2804 #define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
2805 #define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
2806 #define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */
2807 
2808 /* MPY32CTL0 Control Bits */
2809 #define MPYC (0x0001u) /* Carry of the multiplier */
2810 //#define RESERVED (0x0002u) /* Reserved */
2811 #define MPYFRAC (0x0004u) /* Fractional mode */
2812 #define MPYSAT (0x0008u) /* Saturation mode */
2813 #define MPYM0 (0x0010u) /* Multiplier mode Bit:0 */
2814 #define MPYM1 (0x0020u) /* Multiplier mode Bit:1 */
2815 #define OP1_32 (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
2816 #define OP2_32 (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
2817 #define MPYDLYWRTEN (0x0100u) /* Delayed write enable */
2818 #define MPYDLY32 (0x0200u) /* Delayed write mode */
2819 
2820 /* MPY32CTL0 Control Bits */
2821 #define MPYC_L (0x0001u) /* Carry of the multiplier */
2822 //#define RESERVED (0x0002u) /* Reserved */
2823 #define MPYFRAC_L (0x0004u) /* Fractional mode */
2824 #define MPYSAT_L (0x0008u) /* Saturation mode */
2825 #define MPYM0_L (0x0010u) /* Multiplier mode Bit:0 */
2826 #define MPYM1_L (0x0020u) /* Multiplier mode Bit:1 */
2827 #define OP1_32_L (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
2828 #define OP2_32_L (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
2829 
2830 /* MPY32CTL0 Control Bits */
2831 //#define RESERVED (0x0002u) /* Reserved */
2832 #define MPYDLYWRTEN_H (0x0001u) /* Delayed write enable */
2833 #define MPYDLY32_H (0x0002u) /* Delayed write mode */
2834 
2835 #define MPYM_0 (0x0000u) /* Multiplier mode: MPY */
2836 #define MPYM_1 (0x0010u) /* Multiplier mode: MPYS */
2837 #define MPYM_2 (0x0020u) /* Multiplier mode: MAC */
2838 #define MPYM_3 (0x0030u) /* Multiplier mode: MACS */
2839 #define MPYM__MPY (0x0000u) /* Multiplier mode: MPY */
2840 #define MPYM__MPYS (0x0010u) /* Multiplier mode: MPYS */
2841 #define MPYM__MAC (0x0020u) /* Multiplier mode: MAC */
2842 #define MPYM__MACS (0x0030u) /* Multiplier mode: MACS */
2843 
2844 #endif
2845 /************************************************************
2846 * DIGITAL I/O Port1/2 Pull up / Pull down Resistors
2847 ************************************************************/
2848 #ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
2849 #ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
2850 #ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */
2851 
2852 #define OFS_PAIN (0x0000u) /* Port A Input */
2853 #define OFS_PAIN_L OFS_PAIN
2854 #define OFS_PAIN_H OFS_PAIN+1
2855 #define OFS_PAOUT (0x0002u) /* Port A Output */
2856 #define OFS_PAOUT_L OFS_PAOUT
2857 #define OFS_PAOUT_H OFS_PAOUT+1
2858 #define OFS_PADIR (0x0004u) /* Port A Direction */
2859 #define OFS_PADIR_L OFS_PADIR
2860 #define OFS_PADIR_H OFS_PADIR+1
2861 #define OFS_PAREN (0x0006u) /* Port A Resistor Enable */
2862 #define OFS_PAREN_L OFS_PAREN
2863 #define OFS_PAREN_H OFS_PAREN+1
2864 #define OFS_PADS (0x0008u) /* Port A Drive Strenght */
2865 #define OFS_PADS_L OFS_PADS
2866 #define OFS_PADS_H OFS_PADS+1
2867 #define OFS_PASEL (0x000Au) /* Port A Selection */
2868 #define OFS_PASEL_L OFS_PASEL
2869 #define OFS_PASEL_H OFS_PASEL+1
2870 #define OFS_PAIES (0x0018u) /* Port A Interrupt Edge Select */
2871 #define OFS_PAIES_L OFS_PAIES
2872 #define OFS_PAIES_H OFS_PAIES+1
2873 #define OFS_PAIE (0x001Au) /* Port A Interrupt Enable */
2874 #define OFS_PAIE_L OFS_PAIE
2875 #define OFS_PAIE_H OFS_PAIE+1
2876 #define OFS_PAIFG (0x001Cu) /* Port A Interrupt Flag */
2877 #define OFS_PAIFG_L OFS_PAIFG
2878 #define OFS_PAIFG_H OFS_PAIFG+1
2879 
2880 
2881 #define OFS_P1IN (0x0000u)
2882 #define OFS_P1OUT (0x0002u)
2883 #define OFS_P1DIR (0x0004u)
2884 #define OFS_P1REN (0x0006u)
2885 #define OFS_P1DS (0x0008u)
2886 #define OFS_P1SEL (0x000Au)
2887 #define OFS_P1IV (0x000Eu) /* Port 1 Interrupt Vector Word */
2888 #define OFS_P1IES (0x0018u)
2889 #define OFS_P1IE (0x001Au)
2890 #define OFS_P1IFG (0x001Cu)
2891 #define OFS_P2IN (0x0001u)
2892 #define OFS_P2OUT (0x0003u)
2893 #define OFS_P2DIR (0x0005u)
2894 #define OFS_P2REN (0x0007u)
2895 #define OFS_P2DS (0x0009u)
2896 #define OFS_P2SEL (0x000Bu)
2897 #define OFS_P2IV (0x001Eu) /* Port 2 Interrupt Vector Word */
2898 #define OFS_P2IES (0x0019u)
2899 #define OFS_P2IE (0x001Bu)
2900 #define OFS_P2IFG (0x001du)
2901 #define P1IN (PAIN_L) /* Port 1 Input */
2902 #define P1OUT (PAOUT_L) /* Port 1 Output */
2903 #define P1DIR (PADIR_L) /* Port 1 Direction */
2904 #define P1REN (PAREN_L) /* Port 1 Resistor Enable */
2905 #define P1DS (PADS_L) /* Port 1 Drive Strenght */
2906 #define P1SEL (PASEL_L) /* Port 1 Selection */
2907 #define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
2908 #define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
2909 #define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */
2910 
2911 //Definitions for P1IV
2912 #define P1IV_NONE (0x0000u) /* No Interrupt pending */
2913 #define P1IV_P1IFG0 (0x0002u) /* P1IV P1IFG.0 */
2914 #define P1IV_P1IFG1 (0x0004u) /* P1IV P1IFG.1 */
2915 #define P1IV_P1IFG2 (0x0006u) /* P1IV P1IFG.2 */
2916 #define P1IV_P1IFG3 (0x0008u) /* P1IV P1IFG.3 */
2917 #define P1IV_P1IFG4 (0x000Au) /* P1IV P1IFG.4 */
2918 #define P1IV_P1IFG5 (0x000Cu) /* P1IV P1IFG.5 */
2919 #define P1IV_P1IFG6 (0x000Eu) /* P1IV P1IFG.6 */
2920 #define P1IV_P1IFG7 (0x0010u) /* P1IV P1IFG.7 */
2921 
2922 #define P2IN (PAIN_H) /* Port 2 Input */
2923 #define P2OUT (PAOUT_H) /* Port 2 Output */
2924 #define P2DIR (PADIR_H) /* Port 2 Direction */
2925 #define P2REN (PAREN_H) /* Port 2 Resistor Enable */
2926 #define P2DS (PADS_H) /* Port 2 Drive Strenght */
2927 #define P2SEL (PASEL_H) /* Port 2 Selection */
2928 #define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
2929 #define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
2930 #define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */
2931 
2932 //Definitions for P2IV
2933 #define P2IV_NONE (0x0000u) /* No Interrupt pending */
2934 #define P2IV_P2IFG0 (0x0002u) /* P2IV P2IFG.0 */
2935 #define P2IV_P2IFG1 (0x0004u) /* P2IV P2IFG.1 */
2936 #define P2IV_P2IFG2 (0x0006u) /* P2IV P2IFG.2 */
2937 #define P2IV_P2IFG3 (0x0008u) /* P2IV P2IFG.3 */
2938 #define P2IV_P2IFG4 (0x000Au) /* P2IV P2IFG.4 */
2939 #define P2IV_P2IFG5 (0x000Cu) /* P2IV P2IFG.5 */
2940 #define P2IV_P2IFG6 (0x000Eu) /* P2IV P2IFG.6 */
2941 #define P2IV_P2IFG7 (0x0010u) /* P2IV P2IFG.7 */
2942 
2943 
2944 #endif
2945 #endif
2946 #endif
2947 /************************************************************
2948 * DIGITAL I/O Port3/4 Pull up / Pull down Resistors
2949 ************************************************************/
2950 #ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
2951 #ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */
2952 #ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */
2953 
2954 #define OFS_PBIN (0x0000u) /* Port B Input */
2955 #define OFS_PBIN_L OFS_PBIN
2956 #define OFS_PBIN_H OFS_PBIN+1
2957 #define OFS_PBOUT (0x0002u) /* Port B Output */
2958 #define OFS_PBOUT_L OFS_PBOUT
2959 #define OFS_PBOUT_H OFS_PBOUT+1
2960 #define OFS_PBDIR (0x0004u) /* Port B Direction */
2961 #define OFS_PBDIR_L OFS_PBDIR
2962 #define OFS_PBDIR_H OFS_PBDIR+1
2963 #define OFS_PBREN (0x0006u) /* Port B Resistor Enable */
2964 #define OFS_PBREN_L OFS_PBREN
2965 #define OFS_PBREN_H OFS_PBREN+1
2966 #define OFS_PBDS (0x0008u) /* Port B Drive Strenght */
2967 #define OFS_PBDS_L OFS_PBDS
2968 #define OFS_PBDS_H OFS_PBDS+1
2969 #define OFS_PBSEL (0x000Au) /* Port B Selection */
2970 #define OFS_PBSEL_L OFS_PBSEL
2971 #define OFS_PBSEL_H OFS_PBSEL+1
2972 #define OFS_PBIES (0x0018u) /* Port B Interrupt Edge Select */
2973 #define OFS_PBIES_L OFS_PBIES
2974 #define OFS_PBIES_H OFS_PBIES+1
2975 #define OFS_PBIE (0x001Au) /* Port B Interrupt Enable */
2976 #define OFS_PBIE_L OFS_PBIE
2977 #define OFS_PBIE_H OFS_PBIE+1
2978 #define OFS_PBIFG (0x001Cu) /* Port B Interrupt Flag */
2979 #define OFS_PBIFG_L OFS_PBIFG
2980 #define OFS_PBIFG_H OFS_PBIFG+1
2981 
2982 
2983 #define OFS_P3IN (0x0000u)
2984 #define OFS_P3OUT (0x0002u)
2985 #define OFS_P3DIR (0x0004u)
2986 #define OFS_P3REN (0x0006u)
2987 #define OFS_P3DS (0x0008u)
2988 #define OFS_P3SEL (0x000Au)
2989 #define OFS_P3IV (0x000Eu) /* Port 3 Interrupt Vector Word */
2990 #define OFS_P3IES (0x0018u)
2991 #define OFS_P3IE (0x001Au)
2992 #define OFS_P3IFG (0x001Cu)
2993 #define OFS_P4IN (0x0001u)
2994 #define OFS_P4OUT (0x0003u)
2995 #define OFS_P4DIR (0x0005u)
2996 #define OFS_P4REN (0x0007u)
2997 #define OFS_P4DS (0x0009u)
2998 #define OFS_P4SEL (0x000Bu)
2999 #define OFS_P4IV (0x001Eu) /* Port 4 Interrupt Vector Word */
3000 #define OFS_P4IES (0x0019u)
3001 #define OFS_P4IE (0x001Bu)
3002 #define OFS_P4IFG (0x001du)
3003 #define P3IN (PBIN_L) /* Port 3 Input */
3004 #define P3OUT (PBOUT_L) /* Port 3 Output */
3005 #define P3DIR (PBDIR_L) /* Port 3 Direction */
3006 #define P3REN (PBREN_L) /* Port 3 Resistor Enable */
3007 #define P3DS (PBDS_L) /* Port 3 Drive Strenght */
3008 #define P3SEL (PBSEL_L) /* Port 3 Selection */
3009 #define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */
3010 #define P3IE (PBIE_L) /* Port 3 Interrupt Enable */
3011 #define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */
3012 
3013 //Definitions for P3IV
3014 #define P3IV_NONE (0x0000u) /* No Interrupt pending */
3015 #define P3IV_P3IFG0 (0x0002u) /* P3IV P3IFG.0 */
3016 #define P3IV_P3IFG1 (0x0004u) /* P3IV P3IFG.1 */
3017 #define P3IV_P3IFG2 (0x0006u) /* P3IV P3IFG.2 */
3018 #define P3IV_P3IFG3 (0x0008u) /* P3IV P3IFG.3 */
3019 #define P3IV_P3IFG4 (0x000Au) /* P3IV P3IFG.4 */
3020 #define P3IV_P3IFG5 (0x000Cu) /* P3IV P3IFG.5 */
3021 #define P3IV_P3IFG6 (0x000Eu) /* P3IV P3IFG.6 */
3022 #define P3IV_P3IFG7 (0x0010u) /* P3IV P3IFG.7 */
3023 
3024 #define P4IN (PBIN_H) /* Port 4 Input */
3025 #define P4OUT (PBOUT_H) /* Port 4 Output */
3026 #define P4DIR (PBDIR_H) /* Port 4 Direction */
3027 #define P4REN (PBREN_H) /* Port 4 Resistor Enable */
3028 #define P4DS (PBDS_H) /* Port 4 Drive Strenght */
3029 #define P4SEL (PBSEL_H) /* Port 4 Selection */
3030 #define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */
3031 #define P4IE (PBIE_H) /* Port 4 Interrupt Enable */
3032 #define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */
3033 
3034 //Definitions for P4IV
3035 #define P4IV_NONE (0x0000u) /* No Interrupt pending */
3036 #define P4IV_P4IFG0 (0x0002u) /* P4IV P4IFG.0 */
3037 #define P4IV_P4IFG1 (0x0004u) /* P4IV P4IFG.1 */
3038 #define P4IV_P4IFG2 (0x0006u) /* P4IV P4IFG.2 */
3039 #define P4IV_P4IFG3 (0x0008u) /* P4IV P4IFG.3 */
3040 #define P4IV_P4IFG4 (0x000Au) /* P4IV P4IFG.4 */
3041 #define P4IV_P4IFG5 (0x000Cu) /* P4IV P4IFG.5 */
3042 #define P4IV_P4IFG6 (0x000Eu) /* P4IV P4IFG.6 */
3043 #define P4IV_P4IFG7 (0x0010u) /* P4IV P4IFG.7 */
3044 
3045 
3046 #endif
3047 #endif
3048 #endif
3049 /************************************************************
3050 * DIGITAL I/O Port5/6 Pull up / Pull down Resistors
3051 ************************************************************/
3052 #ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */
3053 #ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */
3054 #ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */
3055 
3056 #define OFS_PCIN (0x0000u) /* Port C Input */
3057 #define OFS_PCIN_L OFS_PCIN
3058 #define OFS_PCIN_H OFS_PCIN+1
3059 #define OFS_PCOUT (0x0002u) /* Port C Output */
3060 #define OFS_PCOUT_L OFS_PCOUT
3061 #define OFS_PCOUT_H OFS_PCOUT+1
3062 #define OFS_PCDIR (0x0004u) /* Port C Direction */
3063 #define OFS_PCDIR_L OFS_PCDIR
3064 #define OFS_PCDIR_H OFS_PCDIR+1
3065 #define OFS_PCREN (0x0006u) /* Port C Resistor Enable */
3066 #define OFS_PCREN_L OFS_PCREN
3067 #define OFS_PCREN_H OFS_PCREN+1
3068 #define OFS_PCDS (0x0008u) /* Port C Drive Strenght */
3069 #define OFS_PCDS_L OFS_PCDS
3070 #define OFS_PCDS_H OFS_PCDS+1
3071 #define OFS_PCSEL (0x000Au) /* Port C Selection */
3072 #define OFS_PCSEL_L OFS_PCSEL
3073 #define OFS_PCSEL_H OFS_PCSEL+1
3074 #define OFS_PCIES (0x0018u) /* Port C Interrupt Edge Select */
3075 #define OFS_PCIES_L OFS_PCIES
3076 #define OFS_PCIES_H OFS_PCIES+1
3077 #define OFS_PCIE (0x001Au) /* Port C Interrupt Enable */
3078 #define OFS_PCIE_L OFS_PCIE
3079 #define OFS_PCIE_H OFS_PCIE+1
3080 #define OFS_PCIFG (0x001Cu) /* Port C Interrupt Flag */
3081 #define OFS_PCIFG_L OFS_PCIFG
3082 #define OFS_PCIFG_H OFS_PCIFG+1
3083 
3084 
3085 #define OFS_P5IN (0x0000u)
3086 #define OFS_P5OUT (0x0002u)
3087 #define OFS_P5DIR (0x0004u)
3088 #define OFS_P5REN (0x0006u)
3089 #define OFS_P5DS (0x0008u)
3090 #define OFS_P5SEL (0x000Au)
3091 #define OFS_P5IV (0x000Eu) /* Port 5 Interrupt Vector Word */
3092 #define OFS_P5IES (0x0018u)
3093 #define OFS_P5IE (0x001Au)
3094 #define OFS_P5IFG (0x001Cu)
3095 #define OFS_P6IN (0x0001u)
3096 #define OFS_P6OUT (0x0003u)
3097 #define OFS_P6DIR (0x0005u)
3098 #define OFS_P6REN (0x0007u)
3099 #define OFS_P6DS (0x0009u)
3100 #define OFS_P6SEL (0x000Bu)
3101 #define OFS_P6IV (0x001Eu) /* Port 6 Interrupt Vector Word */
3102 #define OFS_P6IES (0x0019u)
3103 #define OFS_P6IE (0x001Bu)
3104 #define OFS_P6IFG (0x001du)
3105 #define P5IN (PCIN_L) /* Port 5 Input */
3106 #define P5OUT (PCOUT_L) /* Port 5 Output */
3107 #define P5DIR (PCDIR_L) /* Port 5 Direction */
3108 #define P5REN (PCREN_L) /* Port 5 Resistor Enable */
3109 #define P5DS (PCDS_L) /* Port 5 Drive Strenght */
3110 #define P5SEL (PCSEL_L) /* Port 5 Selection */
3111 #define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */
3112 #define P5IE (PCIE_L) /* Port 5 Interrupt Enable */
3113 #define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */
3114 
3115 //Definitions for P5IV
3116 #define P5IV_NONE (0x0000u) /* No Interrupt pending */
3117 #define P5IV_P5IFG0 (0x0002u) /* P5IV P5IFG.0 */
3118 #define P5IV_P5IFG1 (0x0004u) /* P5IV P5IFG.1 */
3119 #define P5IV_P5IFG2 (0x0006u) /* P5IV P5IFG.2 */
3120 #define P5IV_P5IFG3 (0x0008u) /* P5IV P5IFG.3 */
3121 #define P5IV_P5IFG4 (0x000Au) /* P5IV P5IFG.4 */
3122 #define P5IV_P5IFG5 (0x000Cu) /* P5IV P5IFG.5 */
3123 #define P5IV_P5IFG6 (0x000Eu) /* P5IV P5IFG.6 */
3124 #define P5IV_P5IFG7 (0x0010u) /* P5IV P5IFG.7 */
3125 
3126 #define P6IN (PCIN_H) /* Port 6 Input */
3127 #define P6OUT (PCOUT_H) /* Port 6 Output */
3128 #define P6DIR (PCDIR_H) /* Port 6 Direction */
3129 #define P6REN (PCREN_H) /* Port 6 Resistor Enable */
3130 #define P6DS (PCDS_H) /* Port 6 Drive Strenght */
3131 #define P6SEL (PCSEL_H) /* Port 6 Selection */
3132 #define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */
3133 #define P6IE (PCIE_H) /* Port 6 Interrupt Enable */
3134 #define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */
3135 
3136 //Definitions for P6IV
3137 #define P6IV_NONE (0x0000u) /* No Interrupt pending */
3138 #define P6IV_P6IFG0 (0x0002u) /* P6IV P6IFG.0 */
3139 #define P6IV_P6IFG1 (0x0004u) /* P6IV P6IFG.1 */
3140 #define P6IV_P6IFG2 (0x0006u) /* P6IV P6IFG.2 */
3141 #define P6IV_P6IFG3 (0x0008u) /* P6IV P6IFG.3 */
3142 #define P6IV_P6IFG4 (0x000Au) /* P6IV P6IFG.4 */
3143 #define P6IV_P6IFG5 (0x000Cu) /* P6IV P6IFG.5 */
3144 #define P6IV_P6IFG6 (0x000Eu) /* P6IV P6IFG.6 */
3145 #define P6IV_P6IFG7 (0x0010u) /* P6IV P6IFG.7 */
3146 
3147 
3148 #endif
3149 #endif
3150 #endif
3151 /************************************************************
3152 * DIGITAL I/O Port7/8 Pull up / Pull down Resistors
3153 ************************************************************/
3154 #ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */
3155 #ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */
3156 #ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */
3157 
3158 #define OFS_PDIN (0x0000u) /* Port D Input */
3159 #define OFS_PDIN_L OFS_PDIN
3160 #define OFS_PDIN_H OFS_PDIN+1
3161 #define OFS_PDOUT (0x0002u) /* Port D Output */
3162 #define OFS_PDOUT_L OFS_PDOUT
3163 #define OFS_PDOUT_H OFS_PDOUT+1
3164 #define OFS_PDDIR (0x0004u) /* Port D Direction */
3165 #define OFS_PDDIR_L OFS_PDDIR
3166 #define OFS_PDDIR_H OFS_PDDIR+1
3167 #define OFS_PDREN (0x0006u) /* Port D Resistor Enable */
3168 #define OFS_PDREN_L OFS_PDREN
3169 #define OFS_PDREN_H OFS_PDREN+1
3170 #define OFS_PDDS (0x0008u) /* Port D Drive Strenght */
3171 #define OFS_PDDS_L OFS_PDDS
3172 #define OFS_PDDS_H OFS_PDDS+1
3173 #define OFS_PDSEL (0x000Au) /* Port D Selection */
3174 #define OFS_PDSEL_L OFS_PDSEL
3175 #define OFS_PDSEL_H OFS_PDSEL+1
3176 #define OFS_PDIES (0x0018u) /* Port D Interrupt Edge Select */
3177 #define OFS_PDIES_L OFS_PDIES
3178 #define OFS_PDIES_H OFS_PDIES+1
3179 #define OFS_PDIE (0x001Au) /* Port D Interrupt Enable */
3180 #define OFS_PDIE_L OFS_PDIE
3181 #define OFS_PDIE_H OFS_PDIE+1
3182 #define OFS_PDIFG (0x001Cu) /* Port D Interrupt Flag */
3183 #define OFS_PDIFG_L OFS_PDIFG
3184 #define OFS_PDIFG_H OFS_PDIFG+1
3185 
3186 
3187 #define OFS_P7IN (0x0000u)
3188 #define OFS_P7OUT (0x0002u)
3189 #define OFS_P7DIR (0x0004u)
3190 #define OFS_P7REN (0x0006u)
3191 #define OFS_P7DS (0x0008u)
3192 #define OFS_P7SEL (0x000Au)
3193 #define OFS_P7IV (0x000Eu) /* Port 7 Interrupt Vector Word */
3194 #define OFS_P7IES (0x0018u)
3195 #define OFS_P7IE (0x001Au)
3196 #define OFS_P7IFG (0x001Cu)
3197 #define OFS_P8IN (0x0001u)
3198 #define OFS_P8OUT (0x0003u)
3199 #define OFS_P8DIR (0x0005u)
3200 #define OFS_P8REN (0x0007u)
3201 #define OFS_P8DS (0x0009u)
3202 #define OFS_P8SEL (0x000Bu)
3203 #define OFS_P8IV (0x001Eu) /* Port 8 Interrupt Vector Word */
3204 #define OFS_P8IES (0x0019u)
3205 #define OFS_P8IE (0x001Bu)
3206 #define OFS_P8IFG (0x001du)
3207 #define P7IN (PDIN_L) /* Port 7 Input */
3208 #define P7OUT (PDOUT_L) /* Port 7 Output */
3209 #define P7DIR (PDDIR_L) /* Port 7 Direction */
3210 #define P7REN (PDREN_L) /* Port 7 Resistor Enable */
3211 #define P7DS (PDDS_L) /* Port 7 Drive Strenght */
3212 #define P7SEL (PDSEL_L) /* Port 7 Selection */
3213 #define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */
3214 #define P7IE (PDIE_L) /* Port 7 Interrupt Enable */
3215 #define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */
3216 
3217 //Definitions for P7IV
3218 #define P7IV_NONE (0x0000u) /* No Interrupt pending */
3219 #define P7IV_P7IFG0 (0x0002u) /* P7IV P7IFG.0 */
3220 #define P7IV_P7IFG1 (0x0004u) /* P7IV P7IFG.1 */
3221 #define P7IV_P7IFG2 (0x0006u) /* P7IV P7IFG.2 */
3222 #define P7IV_P7IFG3 (0x0008u) /* P7IV P7IFG.3 */
3223 #define P7IV_P7IFG4 (0x000Au) /* P7IV P7IFG.4 */
3224 #define P7IV_P7IFG5 (0x000Cu) /* P7IV P7IFG.5 */
3225 #define P7IV_P7IFG6 (0x000Eu) /* P7IV P7IFG.6 */
3226 #define P7IV_P7IFG7 (0x0010u) /* P7IV P7IFG.7 */
3227 
3228 #define P8IN (PDIN_H) /* Port 8 Input */
3229 #define P8OUT (PDOUT_H) /* Port 8 Output */
3230 #define P8DIR (PDDIR_H) /* Port 8 Direction */
3231 #define P8REN (PDREN_H) /* Port 8 Resistor Enable */
3232 #define P8DS (PDDS_H) /* Port 8 Drive Strenght */
3233 #define P8SEL (PDSEL_H) /* Port 8 Selection */
3234 #define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */
3235 #define P8IE (PDIE_H) /* Port 8 Interrupt Enable */
3236 #define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */
3237 
3238 //Definitions for P8IV
3239 #define P8IV_NONE (0x0000u) /* No Interrupt pending */
3240 #define P8IV_P8IFG0 (0x0002u) /* P8IV P8IFG.0 */
3241 #define P8IV_P8IFG1 (0x0004u) /* P8IV P8IFG.1 */
3242 #define P8IV_P8IFG2 (0x0006u) /* P8IV P8IFG.2 */
3243 #define P8IV_P8IFG3 (0x0008u) /* P8IV P8IFG.3 */
3244 #define P8IV_P8IFG4 (0x000Au) /* P8IV P8IFG.4 */
3245 #define P8IV_P8IFG5 (0x000Cu) /* P8IV P8IFG.5 */
3246 #define P8IV_P8IFG6 (0x000Eu) /* P8IV P8IFG.6 */
3247 #define P8IV_P8IFG7 (0x0010u) /* P8IV P8IFG.7 */
3248 
3249 
3250 #endif
3251 #endif
3252 #endif
3253 /************************************************************
3254 * DIGITAL I/O Port9/10 Pull up / Pull down Resistors
3255 ************************************************************/
3256 #ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */
3257 #ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */
3258 #ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */
3259 
3260 #define OFS_PEIN (0x0000u) /* Port E Input */
3261 #define OFS_PEIN_L OFS_PEIN
3262 #define OFS_PEIN_H OFS_PEIN+1
3263 #define OFS_PEOUT (0x0002u) /* Port E Output */
3264 #define OFS_PEOUT_L OFS_PEOUT
3265 #define OFS_PEOUT_H OFS_PEOUT+1
3266 #define OFS_PEDIR (0x0004u) /* Port E Direction */
3267 #define OFS_PEDIR_L OFS_PEDIR
3268 #define OFS_PEDIR_H OFS_PEDIR+1
3269 #define OFS_PEREN (0x0006u) /* Port E Resistor Enable */
3270 #define OFS_PEREN_L OFS_PEREN
3271 #define OFS_PEREN_H OFS_PEREN+1
3272 #define OFS_PEDS (0x0008u) /* Port E Drive Strenght */
3273 #define OFS_PEDS_L OFS_PEDS
3274 #define OFS_PEDS_H OFS_PEDS+1
3275 #define OFS_PESEL (0x000Au) /* Port E Selection */
3276 #define OFS_PESEL_L OFS_PESEL
3277 #define OFS_PESEL_H OFS_PESEL+1
3278 #define OFS_PEIES (0x0018u) /* Port E Interrupt Edge Select */
3279 #define OFS_PEIES_L OFS_PEIES
3280 #define OFS_PEIES_H OFS_PEIES+1
3281 #define OFS_PEIE (0x001Au) /* Port E Interrupt Enable */
3282 #define OFS_PEIE_L OFS_PEIE
3283 #define OFS_PEIE_H OFS_PEIE+1
3284 #define OFS_PEIFG (0x001Cu) /* Port E Interrupt Flag */
3285 #define OFS_PEIFG_L OFS_PEIFG
3286 #define OFS_PEIFG_H OFS_PEIFG+1
3287 
3288 
3289 #define OFS_P9IN (0x0000u)
3290 #define OFS_P9OUT (0x0002u)
3291 #define OFS_P9DIR (0x0004u)
3292 #define OFS_P9REN (0x0006u)
3293 #define OFS_P9DS (0x0008u)
3294 #define OFS_P9SEL (0x000Au)
3295 #define OFS_P9IV (0x000Eu) /* Port 9 Interrupt Vector Word */
3296 #define OFS_P9IES (0x0018u)
3297 #define OFS_P9IE (0x001Au)
3298 #define OFS_P9IFG (0x001Cu)
3299 #define OFS_P10IN (0x0001u)
3300 #define OFS_P10OUT (0x0003u)
3301 #define OFS_P10DIR (0x0005u)
3302 #define OFS_P10REN (0x0007u)
3303 #define OFS_P10DS (0x0009u)
3304 #define OFS_P10SEL (0x000Bu)
3305 #define OFS_P10IV (0x001Eu) /* Port 10 Interrupt Vector Word */
3306 #define OFS_P10IES (0x0019u)
3307 #define OFS_P10IE (0x001Bu)
3308 #define OFS_P10IFG (0x001du)
3309 #define P9IN (PEIN_L) /* Port 9 Input */
3310 #define P9OUT (PEOUT_L) /* Port 9 Output */
3311 #define P9DIR (PEDIR_L) /* Port 9 Direction */
3312 #define P9REN (PEREN_L) /* Port 9 Resistor Enable */
3313 #define P9DS (PEDS_L) /* Port 9 Drive Strenght */
3314 #define P9SEL (PESEL_L) /* Port 9 Selection */
3315 #define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */
3316 #define P9IE (PEIE_L) /* Port 9 Interrupt Enable */
3317 #define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */
3318 
3319 //Definitions for P9IV
3320 #define P9IV_NONE (0x0000u) /* No Interrupt pending */
3321 #define P9IV_P9IFG0 (0x0002u) /* P9IV P9IFG.0 */
3322 #define P9IV_P9IFG1 (0x0004u) /* P9IV P9IFG.1 */
3323 #define P9IV_P9IFG2 (0x0006u) /* P9IV P9IFG.2 */
3324 #define P9IV_P9IFG3 (0x0008u) /* P9IV P9IFG.3 */
3325 #define P9IV_P9IFG4 (0x000Au) /* P9IV P9IFG.4 */
3326 #define P9IV_P9IFG5 (0x000Cu) /* P9IV P9IFG.5 */
3327 #define P9IV_P9IFG6 (0x000Eu) /* P9IV P9IFG.6 */
3328 #define P9IV_P9IFG7 (0x0010u) /* P9IV P9IFG.7 */
3329 
3330 #define P10IN (PEIN_H) /* Port 10 Input */
3331 #define P10OUT (PEOUT_H) /* Port 10 Output */
3332 #define P10DIR (PEDIR_H) /* Port 10 Direction */
3333 #define P10REN (PEREN_H) /* Port 10 Resistor Enable */
3334 #define P10DS (PEDS_H) /* Port 10 Drive Strenght */
3335 #define P10SEL (PESEL_H) /* Port 10 Selection */
3336 #define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */
3337 #define P10IE (PEIE_H) /* Port 10 Interrupt Enable */
3338 #define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */
3339 
3340 //Definitions for P10IV
3341 #define P10IV_NONE (0x0000u) /* No Interrupt pending */
3342 #define P10IV_P10IFG0 (0x0002u) /* P10IV P10IFG.0 */
3343 #define P10IV_P10IFG1 (0x0004u) /* P10IV P10IFG.1 */
3344 #define P10IV_P10IFG2 (0x0006u) /* P10IV P10IFG.2 */
3345 #define P10IV_P10IFG3 (0x0008u) /* P10IV P10IFG.3 */
3346 #define P10IV_P10IFG4 (0x000Au) /* P10IV P10IFG.4 */
3347 #define P10IV_P10IFG5 (0x000Cu) /* P10IV P10IFG.5 */
3348 #define P10IV_P10IFG6 (0x000Eu) /* P10IV P10IFG.6 */
3349 #define P10IV_P10IFG7 (0x0010u) /* P10IV P10IFG.7 */
3350 
3351 
3352 #endif
3353 #endif
3354 #endif
3355 /************************************************************
3356 * DIGITAL I/O Port11 Pull up / Pull down Resistors
3357 ************************************************************/
3358 #ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */
3359 #ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */
3360 
3361 #define OFS_PFIN (0x0000u) /* Port F Input */
3362 #define OFS_PFIN_L OFS_PFIN
3363 #define OFS_PFIN_H OFS_PFIN+1
3364 #define OFS_PFOUT (0x0002u) /* Port F Output */
3365 #define OFS_PFOUT_L OFS_PFOUT
3366 #define OFS_PFOUT_H OFS_PFOUT+1
3367 #define OFS_PFDIR (0x0004u) /* Port F Direction */
3368 #define OFS_PFDIR_L OFS_PFDIR
3369 #define OFS_PFDIR_H OFS_PFDIR+1
3370 #define OFS_PFREN (0x0006u) /* Port F Resistor Enable */
3371 #define OFS_PFREN_L OFS_PFREN
3372 #define OFS_PFREN_H OFS_PFREN+1
3373 #define OFS_PFDS (0x0008u) /* Port F Drive Strenght */
3374 #define OFS_PFDS_L OFS_PFDS
3375 #define OFS_PFDS_H OFS_PFDS+1
3376 #define OFS_PFSEL (0x000Au) /* Port F Selection */
3377 #define OFS_PFSEL_L OFS_PFSEL
3378 #define OFS_PFSEL_H OFS_PFSEL+1
3379 #define OFS_PFIES (0x0018u) /* Port F Interrupt Edge Select */
3380 #define OFS_PFIES_L OFS_PFIES
3381 #define OFS_PFIES_H OFS_PFIES+1
3382 #define OFS_PFIE (0x001Au) /* Port F Interrupt Enable */
3383 #define OFS_PFIE_L OFS_PFIE
3384 #define OFS_PFIE_H OFS_PFIE+1
3385 #define OFS_PFIFG (0x001Cu) /* Port F Interrupt Flag */
3386 #define OFS_PFIFG_L OFS_PFIFG
3387 #define OFS_PFIFG_H OFS_PFIFG+1
3388 
3389 
3390 #define OFS_P11IN (0x0000u)
3391 #define OFS_P11OUT (0x0002u)
3392 #define OFS_P11DIR (0x0004u)
3393 #define OFS_P11REN (0x0006u)
3394 #define OFS_P11DS (0x0008u)
3395 #define OFS_P11SEL (0x000Au)
3396 #define OFS_P11IV (0x000Eu) /* Port 11 Interrupt Vector Word */
3397 #define OFS_P11IES (0x0018u)
3398 #define OFS_P11IE (0x001Au)
3399 #define OFS_P11IFG (0x001Cu)
3400 #define P11IN (PFIN_L) /* Port 11 Input */
3401 #define P11OUT (PFOUT_L) /* Port 11 Output */
3402 #define P11DIR (PFDIR_L) /* Port 11 Direction */
3403 #define P11REN (PFREN_L) /* Port 11 Resistor Enable */
3404 #define P11DS (PFDS_L) /* Port 11 Drive Strenght */
3405 #define P11SEL (PFSEL_L) /* Port 11 Selection */
3406 
3407 #define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */
3408 #define P11IE (PFIE_L) /* Port 11 Interrupt Enable */
3409 #define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */
3410 
3411 //Definitions for P11IV
3412 #define P11IV_NONE (0x0000u) /* No Interrupt pending */
3413 #define P11IV_P11IFG0 (0x0002u) /* P11IV P11IFG.0 */
3414 #define P11IV_P11IFG1 (0x0004u) /* P11IV P11IFG.1 */
3415 #define P11IV_P11IFG2 (0x0006u) /* P11IV P11IFG.2 */
3416 #define P11IV_P11IFG3 (0x0008u) /* P11IV P11IFG.3 */
3417 #define P11IV_P11IFG4 (0x000Au) /* P11IV P11IFG.4 */
3418 #define P11IV_P11IFG5 (0x000Cu) /* P11IV P11IFG.5 */
3419 #define P11IV_P11IFG6 (0x000Eu) /* P11IV P11IFG.6 */
3420 #define P11IV_P11IFG7 (0x0010u) /* P11IV P11IFG.7 */
3421 
3422 
3423 #endif
3424 #endif
3425 /************************************************************
3426 * DIGITAL I/O PortJ Pull up / Pull down Resistors
3427 ************************************************************/
3428 #ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */
3429 
3430 #define OFS_PJIN (0x0000u) /* Port J Input */
3431 #define OFS_PJIN_L OFS_PJIN
3432 #define OFS_PJIN_H OFS_PJIN+1
3433 #define OFS_PJOUT (0x0002u) /* Port J Output */
3434 #define OFS_PJOUT_L OFS_PJOUT
3435 #define OFS_PJOUT_H OFS_PJOUT+1
3436 #define OFS_PJDIR (0x0004u) /* Port J Direction */
3437 #define OFS_PJDIR_L OFS_PJDIR
3438 #define OFS_PJDIR_H OFS_PJDIR+1
3439 #define OFS_PJREN (0x0006u) /* Port J Resistor Enable */
3440 #define OFS_PJREN_L OFS_PJREN
3441 #define OFS_PJREN_H OFS_PJREN+1
3442 #define OFS_PJDS (0x0008u) /* Port J Drive Strenght */
3443 #define OFS_PJDS_L OFS_PJDS
3444 #define OFS_PJDS_H OFS_PJDS+1
3445 #define OFS_PJSEL (0x000Au) /* Port J Selection */
3446 #define OFS_PJSEL_L OFS_PJSEL
3447 #define OFS_PJSEL_H OFS_PJSEL+1
3448 
3449 #endif
3450 /************************************************************
3451 * PORT MAPPING CONTROLLER
3452 ************************************************************/
3453 #ifdef __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */
3454 
3455 #define OFS_PMAPKEYID (0x0000u) /* Port Mapping Key register */
3456 #define OFS_PMAPKEYID_L OFS_PMAPKEYID
3457 #define OFS_PMAPKEYID_H OFS_PMAPKEYID+1
3458 #define OFS_PMAPCTL (0x0002u) /* Port Mapping control register */
3459 #define OFS_PMAPCTL_L OFS_PMAPCTL
3460 #define OFS_PMAPCTL_H OFS_PMAPCTL+1
3461 
3462 #define PMAPKEY (0x2D52u) /* Port Mapping Key */
3463 #define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */
3464 #define PMAPPW (0x2D52u) /* Legacy Definition: Port Mapping Password */
3465 
3466 /* PMAPCTL Control Bits */
3467 #define PMAPLOCKED (0x0001u) /* Port Mapping Lock bit. Read only */
3468 #define PMAPRECFG (0x0002u) /* Port Mapping re-configuration control bit */
3469 
3470 /* PMAPCTL Control Bits */
3471 #define PMAPLOCKED_L (0x0001u) /* Port Mapping Lock bit. Read only */
3472 #define PMAPRECFG_L (0x0002u) /* Port Mapping re-configuration control bit */
3473 
3474 #endif
3475 /************************************************************
3476 * PORT 2 MAPPING CONTROLLER
3477 ************************************************************/
3478 #ifdef __MSP430_HAS_PORT2_MAPPING__ /* Definition to show that Module is available */
3479 
3480 #define OFS_P2MAP01 (0x0000u) /* Port P2.0/1 mapping register */
3481 #define OFS_P2MAP01_L OFS_P2MAP01
3482 #define OFS_P2MAP01_H OFS_P2MAP01+1
3483 #define OFS_P2MAP23 (0x0002u) /* Port P2.2/3 mapping register */
3484 #define OFS_P2MAP23_L OFS_P2MAP23
3485 #define OFS_P2MAP23_H OFS_P2MAP23+1
3486 #define OFS_P2MAP45 (0x0004u) /* Port P2.4/5 mapping register */
3487 #define OFS_P2MAP45_L OFS_P2MAP45
3488 #define OFS_P2MAP45_H OFS_P2MAP45+1
3489 #define OFS_P2MAP67 (0x0006u) /* Port P2.6/7 mapping register */
3490 #define OFS_P2MAP67_L OFS_P2MAP67
3491 #define OFS_P2MAP67_H OFS_P2MAP67+1
3492 #define OFS_P2MAP0 (0x0000u)
3493 #define OFS_P2MAP1 (0x0001u)
3494 #define OFS_P2MAP2 (0x0002u)
3495 #define OFS_P2MAP3 (0x0003u)
3496 #define OFS_P2MAP4 (0x0004u)
3497 #define OFS_P2MAP5 (0x0005u)
3498 #define OFS_P2MAP6 (0x0006u)
3499 #define OFS_P2MAP7 (0x0007u)
3500 
3501 #define P2MAP0 P2MAP01_L /* Port P2.0 mapping register */
3502 #define P2MAP1 P2MAP01_H /* Port P2.1 mapping register */
3503 #define P2MAP2 P2MAP23_L /* Port P2.2 mapping register */
3504 #define P2MAP3 P2MAP23_H /* Port P2.3 mapping register */
3505 #define P2MAP4 P2MAP45_L /* Port P2.4 mapping register */
3506 #define P2MAP5 P2MAP45_H /* Port P2.5 mapping register */
3507 #define P2MAP6 P2MAP67_L /* Port P2.6 mapping register */
3508 #define P2MAP7 P2MAP67_H /* Port P2.7 mapping register */
3509 
3510 #endif
3511 /************************************************************
3512 * PMM - Power Management System
3513 ************************************************************/
3514 #ifdef __MSP430_HAS_PMM__ /* Definition to show that Module is available */
3515 
3516 #define OFS_PMMCTL0 (0x0000u) /* PMM Control 0 */
3517 #define OFS_PMMCTL0_L OFS_PMMCTL0
3518 #define OFS_PMMCTL0_H OFS_PMMCTL0+1
3519 #define OFS_PMMCTL1 (0x0002u) /* PMM Control 1 */
3520 #define OFS_PMMCTL1_L OFS_PMMCTL1
3521 #define OFS_PMMCTL1_H OFS_PMMCTL1+1
3522 #define OFS_SVSMHCTL (0x0004u) /* SVS and SVM high side control register */
3523 #define OFS_SVSMHCTL_L OFS_SVSMHCTL
3524 #define OFS_SVSMHCTL_H OFS_SVSMHCTL+1
3525 #define OFS_SVSMLCTL (0x0006u) /* SVS and SVM low side control register */
3526 #define OFS_SVSMLCTL_L OFS_SVSMLCTL
3527 #define OFS_SVSMLCTL_H OFS_SVSMLCTL+1
3528 #define OFS_SVSMIO (0x0008u) /* SVSIN and SVSOUT control register */
3529 #define OFS_SVSMIO_L OFS_SVSMIO
3530 #define OFS_SVSMIO_H OFS_SVSMIO+1
3531 #define OFS_PMMIFG (0x000Cu) /* PMM Interrupt Flag */
3532 #define OFS_PMMIFG_L OFS_PMMIFG
3533 #define OFS_PMMIFG_H OFS_PMMIFG+1
3534 #define OFS_PMMRIE (0x000Eu) /* PMM and RESET Interrupt Enable */
3535 #define OFS_PMMRIE_L OFS_PMMRIE
3536 #define OFS_PMMRIE_H OFS_PMMRIE+1
3537 
3538 #define PMMPW (0xA500u) /* PMM Register Write Password */
3539 #define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */
3540 
3541 /* PMMCTL0 Control Bits */
3542 #define PMMCOREV0 (0x0001u) /* PMM Core Voltage Bit: 0 */
3543 #define PMMCOREV1 (0x0002u) /* PMM Core Voltage Bit: 1 */
3544 #define PMMSWBOR (0x0004u) /* PMM Software BOR */
3545 #define PMMSWPOR (0x0008u) /* PMM Software POR */
3546 #define PMMREGOFF (0x0010u) /* PMM Turn Regulator off */
3547 #define PMMHPMRE (0x0080u) /* PMM Global High Power Module Request Enable */
3548 
3549 /* PMMCTL0 Control Bits */
3550 #define PMMCOREV0_L (0x0001u) /* PMM Core Voltage Bit: 0 */
3551 #define PMMCOREV1_L (0x0002u) /* PMM Core Voltage Bit: 1 */
3552 #define PMMSWBOR_L (0x0004u) /* PMM Software BOR */
3553 #define PMMSWPOR_L (0x0008u) /* PMM Software POR */
3554 #define PMMREGOFF_L (0x0010u) /* PMM Turn Regulator off */
3555 #define PMMHPMRE_L (0x0080u) /* PMM Global High Power Module Request Enable */
3556 
3557 #define PMMCOREV_0 (0x0000u) /* PMM Core Voltage 0 (1.35V) */
3558 #define PMMCOREV_1 (0x0001u) /* PMM Core Voltage 1 (1.55V) */
3559 #define PMMCOREV_2 (0x0002u) /* PMM Core Voltage 2 (1.75V) */
3560 #define PMMCOREV_3 (0x0003u) /* PMM Core Voltage 3 (1.85V) */
3561 
3562 /* PMMCTL1 Control Bits */
3563 #define PMMREFMD (0x0001u) /* PMM Reference Mode */
3564 #define PMMCMD0 (0x0010u) /* PMM Voltage Regulator Current Mode Bit: 0 */
3565 #define PMMCMD1 (0x0020u) /* PMM Voltage Regulator Current Mode Bit: 1 */
3566 
3567 /* PMMCTL1 Control Bits */
3568 #define PMMREFMD_L (0x0001u) /* PMM Reference Mode */
3569 #define PMMCMD0_L (0x0010u) /* PMM Voltage Regulator Current Mode Bit: 0 */
3570 #define PMMCMD1_L (0x0020u) /* PMM Voltage Regulator Current Mode Bit: 1 */
3571 
3572 /* SVSMHCTL Control Bits */
3573 #define SVSMHRRL0 (0x0001u) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
3574 #define SVSMHRRL1 (0x0002u) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
3575 #define SVSMHRRL2 (0x0004u) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
3576 #define SVSMHDLYST (0x0008u) /* SVS and SVM high side delay status */
3577 #define SVSHMD (0x0010u) /* SVS high side mode */
3578 #define SVSMHEVM (0x0040u) /* SVS and SVM high side event mask */
3579 #define SVSMHACE (0x0080u) /* SVS and SVM high side auto control enable */
3580 #define SVSHRVL0 (0x0100u) /* SVS high side reset voltage level Bit: 0 */
3581 #define SVSHRVL1 (0x0200u) /* SVS high side reset voltage level Bit: 1 */
3582 #define SVSHE (0x0400u) /* SVS high side enable */
3583 #define SVSHFP (0x0800u) /* SVS high side full performace mode */
3584 #define SVMHOVPE (0x1000u) /* SVM high side over-voltage enable */
3585 #define SVMHE (0x4000u) /* SVM high side enable */
3586 #define SVMHFP (0x8000u) /* SVM high side full performace mode */
3587 
3588 /* SVSMHCTL Control Bits */
3589 #define SVSMHRRL0_L (0x0001u) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
3590 #define SVSMHRRL1_L (0x0002u) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
3591 #define SVSMHRRL2_L (0x0004u) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
3592 #define SVSMHDLYST_L (0x0008u) /* SVS and SVM high side delay status */
3593 #define SVSHMD_L (0x0010u) /* SVS high side mode */
3594 #define SVSMHEVM_L (0x0040u) /* SVS and SVM high side event mask */
3595 #define SVSMHACE_L (0x0080u) /* SVS and SVM high side auto control enable */
3596 
3597 /* SVSMHCTL Control Bits */
3598 #define SVSHRVL0_H (0x0001u) /* SVS high side reset voltage level Bit: 0 */
3599 #define SVSHRVL1_H (0x0002u) /* SVS high side reset voltage level Bit: 1 */
3600 #define SVSHE_H (0x0004u) /* SVS high side enable */
3601 #define SVSHFP_H (0x0008u) /* SVS high side full performace mode */
3602 #define SVMHOVPE_H (0x0010u) /* SVM high side over-voltage enable */
3603 #define SVMHE_H (0x0040u) /* SVM high side enable */
3604 #define SVMHFP_H (0x0080u) /* SVM high side full performace mode */
3605 
3606 #define SVSMHRRL_0 (0x0000u) /* SVS and SVM high side Reset Release Voltage Level 0 */
3607 #define SVSMHRRL_1 (0x0001u) /* SVS and SVM high side Reset Release Voltage Level 1 */
3608 #define SVSMHRRL_2 (0x0002u) /* SVS and SVM high side Reset Release Voltage Level 2 */
3609 #define SVSMHRRL_3 (0x0003u) /* SVS and SVM high side Reset Release Voltage Level 3 */
3610 #define SVSMHRRL_4 (0x0004u) /* SVS and SVM high side Reset Release Voltage Level 4 */
3611 #define SVSMHRRL_5 (0x0005u) /* SVS and SVM high side Reset Release Voltage Level 5 */
3612 #define SVSMHRRL_6 (0x0006u) /* SVS and SVM high side Reset Release Voltage Level 6 */
3613 #define SVSMHRRL_7 (0x0007u) /* SVS and SVM high side Reset Release Voltage Level 7 */
3614 
3615 #define SVSHRVL_0 (0x0000u) /* SVS high side Reset Release Voltage Level 0 */
3616 #define SVSHRVL_1 (0x0100u) /* SVS high side Reset Release Voltage Level 1 */
3617 #define SVSHRVL_2 (0x0200u) /* SVS high side Reset Release Voltage Level 2 */
3618 #define SVSHRVL_3 (0x0300u) /* SVS high side Reset Release Voltage Level 3 */
3619 
3620 /* SVSMLCTL Control Bits */
3621 #define SVSMLRRL0 (0x0001u) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
3622 #define SVSMLRRL1 (0x0002u) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
3623 #define SVSMLRRL2 (0x0004u) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
3624 #define SVSMLDLYST (0x0008u) /* SVS and SVM low side delay status */
3625 #define SVSLMD (0x0010u) /* SVS low side mode */
3626 #define SVSMLEVM (0x0040u) /* SVS and SVM low side event mask */
3627 #define SVSMLACE (0x0080u) /* SVS and SVM low side auto control enable */
3628 #define SVSLRVL0 (0x0100u) /* SVS low side reset voltage level Bit: 0 */
3629 #define SVSLRVL1 (0x0200u) /* SVS low side reset voltage level Bit: 1 */
3630 #define SVSLE (0x0400u) /* SVS low side enable */
3631 #define SVSLFP (0x0800u) /* SVS low side full performace mode */
3632 #define SVMLOVPE (0x1000u) /* SVM low side over-voltage enable */
3633 #define SVMLE (0x4000u) /* SVM low side enable */
3634 #define SVMLFP (0x8000u) /* SVM low side full performace mode */
3635 
3636 /* SVSMLCTL Control Bits */
3637 #define SVSMLRRL0_L (0x0001u) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
3638 #define SVSMLRRL1_L (0x0002u) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
3639 #define SVSMLRRL2_L (0x0004u) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
3640 #define SVSMLDLYST_L (0x0008u) /* SVS and SVM low side delay status */
3641 #define SVSLMD_L (0x0010u) /* SVS low side mode */
3642 #define SVSMLEVM_L (0x0040u) /* SVS and SVM low side event mask */
3643 #define SVSMLACE_L (0x0080u) /* SVS and SVM low side auto control enable */
3644 
3645 /* SVSMLCTL Control Bits */
3646 #define SVSLRVL0_H (0x0001u) /* SVS low side reset voltage level Bit: 0 */
3647 #define SVSLRVL1_H (0x0002u) /* SVS low side reset voltage level Bit: 1 */
3648 #define SVSLE_H (0x0004u) /* SVS low side enable */
3649 #define SVSLFP_H (0x0008u) /* SVS low side full performace mode */
3650 #define SVMLOVPE_H (0x0010u) /* SVM low side over-voltage enable */
3651 #define SVMLE_H (0x0040u) /* SVM low side enable */
3652 #define SVMLFP_H (0x0080u) /* SVM low side full performace mode */
3653 
3654 #define SVSMLRRL_0 (0x0000u) /* SVS and SVM low side Reset Release Voltage Level 0 */
3655 #define SVSMLRRL_1 (0x0001u) /* SVS and SVM low side Reset Release Voltage Level 1 */
3656 #define SVSMLRRL_2 (0x0002u) /* SVS and SVM low side Reset Release Voltage Level 2 */
3657 #define SVSMLRRL_3 (0x0003u) /* SVS and SVM low side Reset Release Voltage Level 3 */
3658 #define SVSMLRRL_4 (0x0004u) /* SVS and SVM low side Reset Release Voltage Level 4 */
3659 #define SVSMLRRL_5 (0x0005u) /* SVS and SVM low side Reset Release Voltage Level 5 */
3660 #define SVSMLRRL_6 (0x0006u) /* SVS and SVM low side Reset Release Voltage Level 6 */
3661 #define SVSMLRRL_7 (0x0007u) /* SVS and SVM low side Reset Release Voltage Level 7 */
3662 
3663 #define SVSLRVL_0 (0x0000u) /* SVS low side Reset Release Voltage Level 0 */
3664 #define SVSLRVL_1 (0x0100u) /* SVS low side Reset Release Voltage Level 1 */
3665 #define SVSLRVL_2 (0x0200u) /* SVS low side Reset Release Voltage Level 2 */
3666 #define SVSLRVL_3 (0x0300u) /* SVS low side Reset Release Voltage Level 3 */
3667 
3668 /* SVSMIO Control Bits */
3669 #define SVMLOE (0x0008u) /* SVM low side output enable */
3670 #define SVMLVLROE (0x0010u) /* SVM low side voltage level reached output enable */
3671 #define SVMOUTPOL (0x0020u) /* SVMOUT pin polarity */
3672 #define SVMHOE (0x0800u) /* SVM high side output enable */
3673 #define SVMHVLROE (0x1000u) /* SVM high side voltage level reached output enable */
3674 
3675 /* SVSMIO Control Bits */
3676 #define SVMLOE_L (0x0008u) /* SVM low side output enable */
3677 #define SVMLVLROE_L (0x0010u) /* SVM low side voltage level reached output enable */
3678 #define SVMOUTPOL_L (0x0020u) /* SVMOUT pin polarity */
3679 
3680 /* SVSMIO Control Bits */
3681 #define SVMHOE_H (0x0008u) /* SVM high side output enable */
3682 #define SVMHVLROE_H (0x0010u) /* SVM high side voltage level reached output enable */
3683 
3684 /* PMMIFG Control Bits */
3685 #define SVSMLDLYIFG (0x0001u) /* SVS and SVM low side Delay expired interrupt flag */
3686 #define SVMLIFG (0x0002u) /* SVM low side interrupt flag */
3687 #define SVMLVLRIFG (0x0004u) /* SVM low side Voltage Level Reached interrupt flag */
3688 #define SVSMHDLYIFG (0x0010u) /* SVS and SVM high side Delay expired interrupt flag */
3689 #define SVMHIFG (0x0020u) /* SVM high side interrupt flag */
3690 #define SVMHVLRIFG (0x0040u) /* SVM high side Voltage Level Reached interrupt flag */
3691 #define PMMBORIFG (0x0100u) /* PMM Software BOR interrupt flag */
3692 #define PMMRSTIFG (0x0200u) /* PMM RESET pin interrupt flag */
3693 #define PMMPORIFG (0x0400u) /* PMM Software POR interrupt flag */
3694 #define SVSHIFG (0x1000u) /* SVS low side interrupt flag */
3695 #define SVSLIFG (0x2000u) /* SVS high side interrupt flag */
3696 #define PMMLPM5IFG (0x8000u) /* LPM5 indication Flag */
3697 
3698 /* PMMIFG Control Bits */
3699 #define SVSMLDLYIFG_L (0x0001u) /* SVS and SVM low side Delay expired interrupt flag */
3700 #define SVMLIFG_L (0x0002u) /* SVM low side interrupt flag */
3701 #define SVMLVLRIFG_L (0x0004u) /* SVM low side Voltage Level Reached interrupt flag */
3702 #define SVSMHDLYIFG_L (0x0010u) /* SVS and SVM high side Delay expired interrupt flag */
3703 #define SVMHIFG_L (0x0020u) /* SVM high side interrupt flag */
3704 #define SVMHVLRIFG_L (0x0040u) /* SVM high side Voltage Level Reached interrupt flag */
3705 
3706 /* PMMIFG Control Bits */
3707 #define PMMBORIFG_H (0x0001u) /* PMM Software BOR interrupt flag */
3708 #define PMMRSTIFG_H (0x0002u) /* PMM RESET pin interrupt flag */
3709 #define PMMPORIFG_H (0x0004u) /* PMM Software POR interrupt flag */
3710 #define SVSHIFG_H (0x0010u) /* SVS low side interrupt flag */
3711 #define SVSLIFG_H (0x0020u) /* SVS high side interrupt flag */
3712 #define PMMLPM5IFG_H (0x0080u) /* LPM5 indication Flag */
3713 
3714 #define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */
3715 
3716 /* PMMIE and RESET Control Bits */
3717 #define SVSMLDLYIE (0x0001u) /* SVS and SVM low side Delay expired interrupt enable */
3718 #define SVMLIE (0x0002u) /* SVM low side interrupt enable */
3719 #define SVMLVLRIE (0x0004u) /* SVM low side Voltage Level Reached interrupt enable */
3720 #define SVSMHDLYIE (0x0010u) /* SVS and SVM high side Delay expired interrupt enable */
3721 #define SVMHIE (0x0020u) /* SVM high side interrupt enable */
3722 #define SVMHVLRIE (0x0040u) /* SVM high side Voltage Level Reached interrupt enable */
3723 #define SVSLPE (0x0100u) /* SVS low side POR enable */
3724 #define SVMLVLRPE (0x0200u) /* SVM low side Voltage Level reached POR enable */
3725 #define SVSHPE (0x1000u) /* SVS high side POR enable */
3726 #define SVMHVLRPE (0x2000u) /* SVM high side Voltage Level reached POR enable */
3727 
3728 /* PMMIE and RESET Control Bits */
3729 #define SVSMLDLYIE_L (0x0001u) /* SVS and SVM low side Delay expired interrupt enable */
3730 #define SVMLIE_L (0x0002u) /* SVM low side interrupt enable */
3731 #define SVMLVLRIE_L (0x0004u) /* SVM low side Voltage Level Reached interrupt enable */
3732 #define SVSMHDLYIE_L (0x0010u) /* SVS and SVM high side Delay expired interrupt enable */
3733 #define SVMHIE_L (0x0020u) /* SVM high side interrupt enable */
3734 #define SVMHVLRIE_L (0x0040u) /* SVM high side Voltage Level Reached interrupt enable */
3735 
3736 /* PMMIE and RESET Control Bits */
3737 #define SVSLPE_H (0x0001u) /* SVS low side POR enable */
3738 #define SVMLVLRPE_H (0x0002u) /* SVM low side Voltage Level reached POR enable */
3739 #define SVSHPE_H (0x0010u) /* SVS high side POR enable */
3740 #define SVMHVLRPE_H (0x0020u) /* SVM high side Voltage Level reached POR enable */
3741 
3742 #endif
3743 /************************************************************
3744 * Port U
3745 ************************************************************/
3746 #ifdef __MSP430_HAS_PU__ /* Definition to show that Module is available */
3747 
3748 /* ========================================================================= */
3749 /* Port U and LDO Control Registers */
3750 /* ========================================================================= */
3751 #define OFS_LDOKEYPID (0x0000u) /* LDO Controller peripheral ID and key register */
3752 #define OFS_LDOKEYPID_L OFS_LDOKEYPID
3753 #define OFS_LDOKEYPID_H OFS_LDOKEYPID+1
3754 #define OFS_PUCTL (0x0004u) /* PU Control register */
3755 #define OFS_PUCTL_L OFS_PUCTL
3756 #define OFS_PUCTL_H OFS_PUCTL+1
3757 #define OFS_LDOPWRCTL (0x0008u) /* LDO Power control register */
3758 #define OFS_LDOPWRCTL_L OFS_LDOPWRCTL
3759 #define OFS_LDOPWRCTL_H OFS_LDOPWRCTL+1
3760 
3761 #define LDOKEY (0x9628u) /* LDO Control Register key */
3762 #define LDOKEYID LDOKEYPID /* Legacy Definiton */
3763 
3764 /* PUCTL Control Bits */
3765 #define PUOUT0 (0x0001u) /* PU - PU Output Signal Bit 0 */
3766 #define PUOUT1 (0x0002u) /* PU - PU Output Signal Bit 1 */
3767 #define PUIN0 (0x0004u) /* PU - PU0/DP Input Data */
3768 #define PUIN1 (0x0008u) /* PU - PU1/DM Input Data */
3769 #define PUOPE (0x0020u) /* PU - Port Output Enable */
3770 #define PUIPE (0x0100u) /* PU - PHY Single Ended Input enable */
3771 
3772 /* PUCTL Control Bits */
3773 #define PUOUT0_L (0x0001u) /* PU - PU Output Signal Bit 0 */
3774 #define PUOUT1_L (0x0002u) /* PU - PU Output Signal Bit 1 */
3775 #define PUIN0_L (0x0004u) /* PU - PU0/DP Input Data */
3776 #define PUIN1_L (0x0008u) /* PU - PU1/DM Input Data */
3777 #define PUOPE_L (0x0020u) /* PU - Port Output Enable */
3778 
3779 /* PUCTL Control Bits */
3780 #define PUIPE_H (0x0001u) /* PU - PHY Single Ended Input enable */
3781 
3782 #define PUDIR (0x0020u) /* Legacy Definiton */
3783 #define PSEIEN (0x0100u) /* Legacy Definiton */
3784 
3785 /* LDOPWRCTL Control Bits */
3786 #define LDOOVLIFG (0x0001u) /* PU - LDOO Overload Interrupt Flag */
3787 #define LDOONIFG (0x0002u) /* PU - LDOI "Coming ON" Interrupt Flag */
3788 #define LDOOFFIFG (0x0004u) /* PU - LDOI "Going OFF" Interrupt Flag */
3789 #define LDOBGVBV (0x0008u) /* PU - LDO Bandgap and LDOI valid */
3790 #define OVLAOFF (0x0020u) /* PU - LDO overload auto off enable */
3791 #define LDOOVLIE (0x0100u) /* PU - Overload indication Interrupt Enable */
3792 #define LDOONIE (0x0200u) /* PU - LDOI "Coming ON" Interrupt Enable */
3793 #define LDOOFFIE (0x0400u) /* PU - LDOI "Going OFF" Interrupt Enable */
3794 #define LDOEN (0x0800u) /* PU - LDO Enable (3.3V) */
3795 
3796 /* LDOPWRCTL Control Bits */
3797 #define LDOOVLIFG_L (0x0001u) /* PU - LDOO Overload Interrupt Flag */
3798 #define LDOONIFG_L (0x0002u) /* PU - LDOI "Coming ON" Interrupt Flag */
3799 #define LDOOFFIFG_L (0x0004u) /* PU - LDOI "Going OFF" Interrupt Flag */
3800 #define LDOBGVBV_L (0x0008u) /* PU - LDO Bandgap and LDOI valid */
3801 #define OVLAOFF_L (0x0020u) /* PU - LDO overload auto off enable */
3802 
3803 /* LDOPWRCTL Control Bits */
3804 #define LDOOVLIE_H (0x0001u) /* PU - Overload indication Interrupt Enable */
3805 #define LDOONIE_H (0x0002u) /* PU - LDOI "Coming ON" Interrupt Enable */
3806 #define LDOOFFIE_H (0x0004u) /* PU - LDOI "Going OFF" Interrupt Enable */
3807 #define LDOEN_H (0x0008u) /* PU - LDO Enable (3.3V) */
3808 #define LDOOEN LDOEN /* Deprecated support for LDO Enable (3.3V) */
3809 
3810 #define VUOVLIFG (0x0001u) /* PU - Legacy Definiton: LDOO Overload Interrupt Flag */
3811 #define VBONIFG (0x0002u) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Flag */
3812 #define VBOFFIFG (0x0004u) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Flag */
3813 #define VUOVLIE (0x0100u) /* PU - Legacy Definiton: Overload indication Interrupt Enable */
3814 #define VBONIE (0x0200u) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Enable */
3815 #define VBOFFIE (0x0400u) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Enable */
3816 
3817 
3818 #endif
3819 /*************************************************************
3820 * RAM Control Module
3821 *************************************************************/
3822 #ifdef __MSP430_HAS_RC__ /* Definition to show that Module is available */
3823 
3824 #define OFS_RCCTL0 (0x0000u) /* Ram Controller Control Register */
3825 #define OFS_RCCTL0_L OFS_RCCTL0
3826 #define OFS_RCCTL0_H OFS_RCCTL0+1
3827 
3828 /* RCCTL0 Control Bits */
3829 #define RCRS0OFF (0x0001u) /* RAM Controller RAM Sector 0 Off */
3830 #define RCRS1OFF (0x0002u) /* RAM Controller RAM Sector 1 Off */
3831 #define RCRS2OFF (0x0004u) /* RAM Controller RAM Sector 2 Off */
3832 #define RCRS3OFF (0x0008u) /* RAM Controller RAM Sector 3 Off */
3833 #define RCRS4OFF (0x0010u) /* RAM Controller RAM Sector 4 Off */
3834 #define RCRS5OFF (0x0020u) /* RAM Controller RAM Sector 5 Off */
3835 #define RCRS6OFF (0x0040u) /* RAM Controller RAM Sector 6 Off */
3836 #define RCRS7OFF (0x0080u) /* RAM Controller RAM Sector 7 (USB) Off */
3837 
3838 /* RCCTL0 Control Bits */
3839 #define RCRS0OFF_L (0x0001u) /* RAM Controller RAM Sector 0 Off */
3840 #define RCRS1OFF_L (0x0002u) /* RAM Controller RAM Sector 1 Off */
3841 #define RCRS2OFF_L (0x0004u) /* RAM Controller RAM Sector 2 Off */
3842 #define RCRS3OFF_L (0x0008u) /* RAM Controller RAM Sector 3 Off */
3843 #define RCRS4OFF_L (0x0010u) /* RAM Controller RAM Sector 4 Off */
3844 #define RCRS5OFF_L (0x0020u) /* RAM Controller RAM Sector 5 Off */
3845 #define RCRS6OFF_L (0x0040u) /* RAM Controller RAM Sector 6 Off */
3846 #define RCRS7OFF_L (0x0080u) /* RAM Controller RAM Sector 7 (USB) Off */
3847 
3848 #define RCKEY (0x5A00u)
3849 
3850 #endif
3851 /************************************************************
3852 * Shared Reference
3853 ************************************************************/
3854 #ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */
3855 
3856 #define OFS_REFCTL0 (0x0000u) /* REF Shared Reference control register 0 */
3857 #define OFS_REFCTL0_L OFS_REFCTL0
3858 #define OFS_REFCTL0_H OFS_REFCTL0+1
3859 
3860 /* REFCTL0 Control Bits */
3861 #define REFON (0x0001u) /* REF Reference On */
3862 #define REFOUT (0x0002u) /* REF Reference output Buffer On */
3863 //#define RESERVED (0x0004u) /* Reserved */
3864 #define REFTCOFF (0x0008u) /* REF Temp.Sensor off */
3865 #define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */
3866 #define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */
3867 //#define RESERVED (0x0040u) /* Reserved */
3868 #define REFMSTR (0x0080u) /* REF Master Control */
3869 #define REFGENACT (0x0100u) /* REF Reference generator active */
3870 #define REFBGACT (0x0200u) /* REF Reference bandgap active */
3871 #define REFGENBUSY (0x0400u) /* REF Reference generator busy */
3872 #define BGMODE (0x0800u) /* REF Bandgap mode */
3873 //#define RESERVED (0x1000u) /* Reserved */
3874 //#define RESERVED (0x2000u) /* Reserved */
3875 //#define RESERVED (0x4000u) /* Reserved */
3876 //#define RESERVED (0x8000u) /* Reserved */
3877 
3878 /* REFCTL0 Control Bits */
3879 #define REFON_L (0x0001u) /* REF Reference On */
3880 #define REFOUT_L (0x0002u) /* REF Reference output Buffer On */
3881 //#define RESERVED (0x0004u) /* Reserved */
3882 #define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */
3883 #define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */
3884 #define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */
3885 //#define RESERVED (0x0040u) /* Reserved */
3886 #define REFMSTR_L (0x0080u) /* REF Master Control */
3887 //#define RESERVED (0x1000u) /* Reserved */
3888 //#define RESERVED (0x2000u) /* Reserved */
3889 //#define RESERVED (0x4000u) /* Reserved */
3890 //#define RESERVED (0x8000u) /* Reserved */
3891 
3892 /* REFCTL0 Control Bits */
3893 //#define RESERVED (0x0004u) /* Reserved */
3894 //#define RESERVED (0x0040u) /* Reserved */
3895 #define REFGENACT_H (0x0001u) /* REF Reference generator active */
3896 #define REFBGACT_H (0x0002u) /* REF Reference bandgap active */
3897 #define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */
3898 #define BGMODE_H (0x0008u) /* REF Bandgap mode */
3899 //#define RESERVED (0x1000u) /* Reserved */
3900 //#define RESERVED (0x2000u) /* Reserved */
3901 //#define RESERVED (0x4000u) /* Reserved */
3902 //#define RESERVED (0x8000u) /* Reserved */
3903 
3904 #define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.5V */
3905 #define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */
3906 #define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */
3907 #define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */
3908 
3909 #endif
3910 /************************************************************
3911 * Shared Reference
3912 ************************************************************/
3913 #ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */
3914 
3915 #define OFS_REFCTL0 (0x0000u) /* REF Shared Reference control register 0 */
3916 #define OFS_REFCTL0_L OFS_REFCTL0
3917 #define OFS_REFCTL0_H OFS_REFCTL0+1
3918 
3919 /* REFCTL0 Control Bits */
3920 #define REFON (0x0001u) /* REF Reference On */
3921 //#define RESERVED (0x0002u) /* Reserved */
3922 //#define RESERVED (0x0004u) /* Reserved */
3923 #define REFTCOFF (0x0008u) /* REF Temp.Sensor off */
3924 #define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */
3925 #define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */
3926 //#define RESERVED (0x0040u) /* Reserved */
3927 //#define RESERVED (0x0080u) /* Reserved */
3928 #define REFGENACT (0x0100u) /* REF Reference generator active */
3929 #define REFBGACT (0x0200u) /* REF Reference bandgap active */
3930 #define REFGENBUSY (0x0400u) /* REF Reference generator busy */
3931 #define BGMODE (0x0800u) /* REF Bandgap mode */
3932 //#define RESERVED (0x1000u) /* Reserved */
3933 //#define RESERVED (0x2000u) /* Reserved */
3934 //#define RESERVED (0x4000u) /* Reserved */
3935 //#define RESERVED (0x8000u) /* Reserved */
3936 
3937 /* REFCTL0 Control Bits */
3938 #define REFON_L (0x0001u) /* REF Reference On */
3939 //#define RESERVED (0x0002u) /* Reserved */
3940 //#define RESERVED (0x0004u) /* Reserved */
3941 #define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */
3942 #define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */
3943 #define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */
3944 //#define RESERVED (0x0040u) /* Reserved */
3945 //#define RESERVED (0x0080u) /* Reserved */
3946 //#define RESERVED (0x1000u) /* Reserved */
3947 //#define RESERVED (0x2000u) /* Reserved */
3948 //#define RESERVED (0x4000u) /* Reserved */
3949 //#define RESERVED (0x8000u) /* Reserved */
3950 
3951 /* REFCTL0 Control Bits */
3952 //#define RESERVED (0x0002u) /* Reserved */
3953 //#define RESERVED (0x0004u) /* Reserved */
3954 //#define RESERVED (0x0040u) /* Reserved */
3955 //#define RESERVED (0x0080u) /* Reserved */
3956 #define REFGENACT_H (0x0001u) /* REF Reference generator active */
3957 #define REFBGACT_H (0x0002u) /* REF Reference bandgap active */
3958 #define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */
3959 #define BGMODE_H (0x0008u) /* REF Bandgap mode */
3960 //#define RESERVED (0x1000u) /* Reserved */
3961 //#define RESERVED (0x2000u) /* Reserved */
3962 //#define RESERVED (0x4000u) /* Reserved */
3963 //#define RESERVED (0x8000u) /* Reserved */
3964 
3965 #define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.5V */
3966 #define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */
3967 #define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */
3968 #define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */
3969 
3970 #endif
3971 /************************************************************
3972 * Real Time Clock
3973 ************************************************************/
3974 #ifdef __MSP430_HAS_RTC__ /* Definition to show that Module is available */
3975 
3976 #define OFS_RTCCTL01 (0x0000u) /* Real Timer Control 0/1 */
3977 #define OFS_RTCCTL01_L OFS_RTCCTL01
3978 #define OFS_RTCCTL01_H OFS_RTCCTL01+1
3979 #define OFS_RTCCTL23 (0x0002u) /* Real Timer Control 2/3 */
3980 #define OFS_RTCCTL23_L OFS_RTCCTL23
3981 #define OFS_RTCCTL23_H OFS_RTCCTL23+1
3982 #define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */
3983 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
3984 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
3985 #define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */
3986 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
3987 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
3988 #define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */
3989 #define OFS_RTCPS_L OFS_RTCPS
3990 #define OFS_RTCPS_H OFS_RTCPS+1
3991 #define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */
3992 #define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */
3993 #define OFS_RTCTIM0_L OFS_RTCTIM0
3994 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
3995 #define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */
3996 #define OFS_RTCTIM1_L OFS_RTCTIM1
3997 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
3998 #define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */
3999 #define OFS_RTCDATE_L OFS_RTCDATE
4000 #define OFS_RTCDATE_H OFS_RTCDATE+1
4001 #define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */
4002 #define OFS_RTCYEAR_L OFS_RTCYEAR
4003 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
4004 #define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */
4005 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
4006 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
4007 #define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */
4008 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
4009 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
4010 #define OFS_RTCSEC (0x0010u)
4011 #define OFS_RTCMIN (0x0011u)
4012 #define OFS_RTCHOUR (0x0012u)
4013 #define OFS_RTCDOW (0x0013u)
4014 #define OFS_RTCDAY (0x0014u)
4015 #define OFS_RTCMON (0x0015u)
4016 #define OFS_RTCAMIN (0x0018u)
4017 #define OFS_RTCAHOUR (0x0019u)
4018 #define OFS_RTCADOW (0x001Au)
4019 #define OFS_RTCADAY (0x001Bu)
4020 
4021 #define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
4022 #define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
4023 #define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
4024 #define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
4025 #define RTCNT12 RTCTIM0
4026 #define RTCNT34 RTCTIM1
4027 #define RTCNT1 RTCTIM0_L
4028 #define RTCNT2 RTCTIM0_H
4029 #define RTCNT3 RTCTIM1_L
4030 #define RTCNT4 RTCTIM1_H
4031 #define RTCSEC RTCTIM0_L
4032 #define RTCMIN RTCTIM0_H
4033 #define RTCHOUR RTCTIM1_L
4034 #define RTCDOW RTCTIM1_H
4035 #define RTCDAY RTCDATE_L
4036 #define RTCMON RTCDATE_H
4037 #define RTCYEARL RTCYEAR_L
4038 #define RTCYEARH RTCYEAR_H
4039 #define RT0PS RTCPS_L
4040 #define RT1PS RTCPS_H
4041 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
4042 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
4043 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
4044 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
4045 
4046 /* RTCCTL01 Control Bits */
4047 #define RTCBCD (0x8000u) /* RTC BCD 0:Binary / 1:BCD */
4048 #define RTCHOLD (0x4000u) /* RTC Hold */
4049 #define RTCMODE (0x2000u) /* RTC Mode 0:Counter / 1: Calendar */
4050 #define RTCRDY (0x1000u) /* RTC Ready */
4051 #define RTCSSEL1 (0x0800u) /* RTC Source Select 1 */
4052 #define RTCSSEL0 (0x0400u) /* RTC Source Select 0 */
4053 #define RTCTEV1 (0x0200u) /* RTC Time Event 1 */
4054 #define RTCTEV0 (0x0100u) /* RTC Time Event 0 */
4055 //#define Reserved (0x0080u)
4056 #define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */
4057 #define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */
4058 #define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */
4059 //#define Reserved (0x0008u)
4060 #define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */
4061 #define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */
4062 #define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */
4063 
4064 /* RTCCTL01 Control Bits */
4065 //#define Reserved (0x0080u)
4066 #define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */
4067 #define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */
4068 #define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */
4069 //#define Reserved (0x0008u)
4070 #define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */
4071 #define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */
4072 #define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */
4073 
4074 /* RTCCTL01 Control Bits */
4075 #define RTCBCD_H (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
4076 #define RTCHOLD_H (0x0040u) /* RTC Hold */
4077 #define RTCMODE_H (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */
4078 #define RTCRDY_H (0x0010u) /* RTC Ready */
4079 #define RTCSSEL1_H (0x0008u) /* RTC Source Select 1 */
4080 #define RTCSSEL0_H (0x0004u) /* RTC Source Select 0 */
4081 #define RTCTEV1_H (0x0002u) /* RTC Time Event 1 */
4082 #define RTCTEV0_H (0x0001u) /* RTC Time Event 0 */
4083 //#define Reserved (0x0080u)
4084 //#define Reserved (0x0008u)
4085 
4086 #define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */
4087 #define RTCSSEL_1 (0x0400u) /* RTC Source Select SMCLK */
4088 #define RTCSSEL_2 (0x0800u) /* RTC Source Select RT1PS */
4089 #define RTCSSEL_3 (0x0C00u) /* RTC Source Select RT1PS */
4090 #define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */
4091 #define RTCSSEL__SMCLK (0x0400u) /* RTC Source Select SMCLK */
4092 #define RTCSSEL__RT1PS (0x0800u) /* RTC Source Select RT1PS */
4093 #define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */
4094 #define RTCTEV_1 (0x0100u) /* RTC Time Event: 1 (Hour changed) */
4095 #define RTCTEV_2 (0x0200u) /* RTC Time Event: 2 (12:00 changed) */
4096 #define RTCTEV_3 (0x0300u) /* RTC Time Event: 3 (00:00 changed) */
4097 #define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */
4098 #define RTCTEV__HOUR (0x0100u) /* RTC Time Event: 1 (Hour changed) */
4099 #define RTCTEV__0000 (0x0200u) /* RTC Time Event: 2 (00:00 changed) */
4100 #define RTCTEV__1200 (0x0300u) /* RTC Time Event: 3 (12:00 changed) */
4101 
4102 /* RTCCTL23 Control Bits */
4103 #define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */
4104 #define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */
4105 #define RTCCALS (0x0080u) /* RTC Calibration Sign */
4106 //#define Reserved (0x0040u)
4107 #define RTCCAL5 (0x0020u) /* RTC Calibration Bit 5 */
4108 #define RTCCAL4 (0x0010u) /* RTC Calibration Bit 4 */
4109 #define RTCCAL3 (0x0008u) /* RTC Calibration Bit 3 */
4110 #define RTCCAL2 (0x0004u) /* RTC Calibration Bit 2 */
4111 #define RTCCAL1 (0x0002u) /* RTC Calibration Bit 1 */
4112 #define RTCCAL0 (0x0001u) /* RTC Calibration Bit 0 */
4113 
4114 /* RTCCTL23 Control Bits */
4115 #define RTCCALS_L (0x0080u) /* RTC Calibration Sign */
4116 //#define Reserved (0x0040u)
4117 #define RTCCAL5_L (0x0020u) /* RTC Calibration Bit 5 */
4118 #define RTCCAL4_L (0x0010u) /* RTC Calibration Bit 4 */
4119 #define RTCCAL3_L (0x0008u) /* RTC Calibration Bit 3 */
4120 #define RTCCAL2_L (0x0004u) /* RTC Calibration Bit 2 */
4121 #define RTCCAL1_L (0x0002u) /* RTC Calibration Bit 1 */
4122 #define RTCCAL0_L (0x0001u) /* RTC Calibration Bit 0 */
4123 
4124 /* RTCCTL23 Control Bits */
4125 #define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */
4126 #define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */
4127 //#define Reserved (0x0040u)
4128 
4129 #define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */
4130 #define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */
4131 #define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */
4132 #define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */
4133 
4134 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
4135 
4136 /* RTCPS0CTL Control Bits */
4137 //#define Reserved (0x8000u)
4138 #define RT0SSEL (0x4000u) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
4139 #define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
4140 #define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
4141 #define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
4142 //#define Reserved (0x0400u)
4143 //#define Reserved (0x0200u)
4144 #define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */
4145 //#define Reserved (0x0080u)
4146 //#define Reserved (0x0040u)
4147 //#define Reserved (0x0020u)
4148 #define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4149 #define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4150 #define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4151 #define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4152 #define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
4153 
4154 /* RTCPS0CTL Control Bits */
4155 //#define Reserved (0x8000u)
4156 //#define Reserved (0x0400u)
4157 //#define Reserved (0x0200u)
4158 //#define Reserved (0x0080u)
4159 //#define Reserved (0x0040u)
4160 //#define Reserved (0x0020u)
4161 #define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4162 #define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4163 #define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4164 #define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4165 #define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
4166 
4167 /* RTCPS0CTL Control Bits */
4168 //#define Reserved (0x8000u)
4169 #define RT0SSEL_H (0x0040u) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
4170 #define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
4171 #define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
4172 #define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
4173 //#define Reserved (0x0400u)
4174 //#define Reserved (0x0200u)
4175 #define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */
4176 //#define Reserved (0x0080u)
4177 //#define Reserved (0x0040u)
4178 //#define Reserved (0x0020u)
4179 
4180 #define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4181 #define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4182 #define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4183 #define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4184 #define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4185 #define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4186 #define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4187 #define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4188 
4189 #define RT0PSDIV_0 (0x0000u) /* RTC Prescale Timer 0 Clock Divide /2 */
4190 #define RT0PSDIV_1 (0x0800u) /* RTC Prescale Timer 0 Clock Divide /4 */
4191 #define RT0PSDIV_2 (0x1000u) /* RTC Prescale Timer 0 Clock Divide /8 */
4192 #define RT0PSDIV_3 (0x1800u) /* RTC Prescale Timer 0 Clock Divide /16 */
4193 #define RT0PSDIV_4 (0x2000u) /* RTC Prescale Timer 0 Clock Divide /32 */
4194 #define RT0PSDIV_5 (0x2800u) /* RTC Prescale Timer 0 Clock Divide /64 */
4195 #define RT0PSDIV_6 (0x3000u) /* RTC Prescale Timer 0 Clock Divide /128 */
4196 #define RT0PSDIV_7 (0x3800u) /* RTC Prescale Timer 0 Clock Divide /256 */
4197 
4198 /* RTCPS1CTL Control Bits */
4199 #define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */
4200 #define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */
4201 #define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
4202 #define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
4203 #define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
4204 //#define Reserved (0x0400u)
4205 //#define Reserved (0x0200u)
4206 #define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */
4207 //#define Reserved (0x0080u)
4208 //#define Reserved (0x0040u)
4209 //#define Reserved (0x0020u)
4210 #define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4211 #define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4212 #define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4213 #define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4214 #define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
4215 
4216 /* RTCPS1CTL Control Bits */
4217 //#define Reserved (0x0400u)
4218 //#define Reserved (0x0200u)
4219 //#define Reserved (0x0080u)
4220 //#define Reserved (0x0040u)
4221 //#define Reserved (0x0020u)
4222 #define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4223 #define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4224 #define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4225 #define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4226 #define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
4227 
4228 /* RTCPS1CTL Control Bits */
4229 #define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */
4230 #define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */
4231 #define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
4232 #define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
4233 #define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
4234 //#define Reserved (0x0400u)
4235 //#define Reserved (0x0200u)
4236 #define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */
4237 //#define Reserved (0x0080u)
4238 //#define Reserved (0x0040u)
4239 //#define Reserved (0x0020u)
4240 
4241 #define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4242 #define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4243 #define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4244 #define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4245 #define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4246 #define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4247 #define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */
4248 #define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */
4249 
4250 #define RT1PSDIV_0 (0x0000u) /* RTC Prescale Timer 1 Clock Divide /2 */
4251 #define RT1PSDIV_1 (0x0800u) /* RTC Prescale Timer 1 Clock Divide /4 */
4252 #define RT1PSDIV_2 (0x1000u) /* RTC Prescale Timer 1 Clock Divide /8 */
4253 #define RT1PSDIV_3 (0x1800u) /* RTC Prescale Timer 1 Clock Divide /16 */
4254 #define RT1PSDIV_4 (0x2000u) /* RTC Prescale Timer 1 Clock Divide /32 */
4255 #define RT1PSDIV_5 (0x2800u) /* RTC Prescale Timer 1 Clock Divide /64 */
4256 #define RT1PSDIV_6 (0x3000u) /* RTC Prescale Timer 1 Clock Divide /128 */
4257 #define RT1PSDIV_7 (0x3800u) /* RTC Prescale Timer 1 Clock Divide /256 */
4258 
4259 #define RT1SSEL_0 (0x0000u) /* RTC Prescale Timer Source Select ACLK */
4260 #define RT1SSEL_1 (0x4000u) /* RTC Prescale Timer Source Select SMCLK */
4261 #define RT1SSEL_2 (0x8000u) /* RTC Prescale Timer Source Select RT0PS */
4262 #define RT1SSEL_3 (0xC000u) /* RTC Prescale Timer Source Select RT0PS */
4263 
4264 /* RTC Definitions */
4265 #define RTCIV_NONE (0x0000u) /* No Interrupt pending */
4266 #define RTCIV_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */
4267 #define RTCIV_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */
4268 #define RTCIV_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */
4269 #define RTCIV_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */
4270 #define RTCIV_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */
4271 
4272 /* Legacy Definitions */
4273 #define RTC_NONE (0x0000u) /* No Interrupt pending */
4274 #define RTC_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */
4275 #define RTC_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */
4276 #define RTC_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */
4277 #define RTC_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */
4278 #define RTC_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */
4279 
4280 #endif
4281 /************************************************************
4282 * Real Time Clock
4283 ************************************************************/
4284 #ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */
4285 
4286 #define OFS_RTCCTL01 (0x0000u) /* Real Timer Control 0/1 */
4287 #define OFS_RTCCTL01_L OFS_RTCCTL01
4288 #define OFS_RTCCTL01_H OFS_RTCCTL01+1
4289 #define OFS_RTCCTL23 (0x0002u) /* Real Timer Control 2/3 */
4290 #define OFS_RTCCTL23_L OFS_RTCCTL23
4291 #define OFS_RTCCTL23_H OFS_RTCCTL23+1
4292 #define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */
4293 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
4294 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
4295 #define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */
4296 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
4297 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
4298 #define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */
4299 #define OFS_RTCPS_L OFS_RTCPS
4300 #define OFS_RTCPS_H OFS_RTCPS+1
4301 #define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */
4302 #define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */
4303 #define OFS_RTCTIM0_L OFS_RTCTIM0
4304 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
4305 #define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */
4306 #define OFS_RTCTIM1_L OFS_RTCTIM1
4307 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
4308 #define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */
4309 #define OFS_RTCDATE_L OFS_RTCDATE
4310 #define OFS_RTCDATE_H OFS_RTCDATE+1
4311 #define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */
4312 #define OFS_RTCYEAR_L OFS_RTCYEAR
4313 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
4314 #define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */
4315 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
4316 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
4317 #define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */
4318 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
4319 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
4320 #define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */
4321 #define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */
4322 #define OFS_RTCSEC (0x0010u)
4323 #define OFS_RTCMIN (0x0011u)
4324 #define OFS_RTCHOUR (0x0012u)
4325 #define OFS_RTCDOW (0x0013u)
4326 #define OFS_RTCDAY (0x0014u)
4327 #define OFS_RTCMON (0x0015u)
4328 #define OFS_RTCAMIN (0x0018u)
4329 #define OFS_RTCAHOUR (0x0019u)
4330 #define OFS_RTCADOW (0x001Au)
4331 #define OFS_RTCADAY (0x001Bu)
4332 
4333 #define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
4334 #define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
4335 #define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
4336 #define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
4337 #define RTCNT12 RTCTIM0
4338 #define RTCNT34 RTCTIM1
4339 #define RTCNT1 RTCTIM0_L
4340 #define RTCNT2 RTCTIM0_H
4341 #define RTCNT3 RTCTIM1_L
4342 #define RTCNT4 RTCTIM1_H
4343 #define RTCSEC RTCTIM0_L
4344 #define RTCMIN RTCTIM0_H
4345 #define RTCHOUR RTCTIM1_L
4346 #define RTCDOW RTCTIM1_H
4347 #define RTCDAY RTCDATE_L
4348 #define RTCMON RTCDATE_H
4349 #define RTCYEARL RTCYEAR_L
4350 #define RTCYEARH RTCYEAR_H
4351 #define RT0PS RTCPS_L
4352 #define RT1PS RTCPS_H
4353 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
4354 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
4355 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
4356 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
4357 
4358 /* RTCCTL01 Control Bits */
4359 #define RTCBCD (0x8000u) /* RTC BCD 0:Binary / 1:BCD */
4360 #define RTCHOLD (0x4000u) /* RTC Hold */
4361 //#define RESERVED (0x2000u) /* RESERVED */
4362 #define RTCRDY (0x1000u) /* RTC Ready */
4363 //#define RESERVED (0x0800u) /* RESERVED */
4364 //#define RESERVED (0x0400u) /* RESERVED */
4365 #define RTCTEV1 (0x0200u) /* RTC Time Event 1 */
4366 #define RTCTEV0 (0x0100u) /* RTC Time Event 0 */
4367 #define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4368 #define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */
4369 #define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */
4370 #define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */
4371 #define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4372 #define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */
4373 #define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */
4374 #define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */
4375 
4376 /* RTCCTL01 Control Bits */
4377 //#define RESERVED (0x2000u) /* RESERVED */
4378 //#define RESERVED (0x0800u) /* RESERVED */
4379 //#define RESERVED (0x0400u) /* RESERVED */
4380 #define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4381 #define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */
4382 #define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */
4383 #define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */
4384 #define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4385 #define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */
4386 #define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */
4387 #define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */
4388 
4389 /* RTCCTL01 Control Bits */
4390 #define RTCBCD_H (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
4391 #define RTCHOLD_H (0x0040u) /* RTC Hold */
4392 //#define RESERVED (0x2000u) /* RESERVED */
4393 #define RTCRDY_H (0x0010u) /* RTC Ready */
4394 //#define RESERVED (0x0800u) /* RESERVED */
4395 //#define RESERVED (0x0400u) /* RESERVED */
4396 #define RTCTEV1_H (0x0002u) /* RTC Time Event 1 */
4397 #define RTCTEV0_H (0x0001u) /* RTC Time Event 0 */
4398 
4399 #define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */
4400 #define RTCTEV_1 (0x0100u) /* RTC Time Event: 1 (Hour changed) */
4401 #define RTCTEV_2 (0x0200u) /* RTC Time Event: 2 (12:00 changed) */
4402 #define RTCTEV_3 (0x0300u) /* RTC Time Event: 3 (00:00 changed) */
4403 #define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */
4404 #define RTCTEV__HOUR (0x0100u) /* RTC Time Event: 1 (Hour changed) */
4405 #define RTCTEV__0000 (0x0200u) /* RTC Time Event: 2 (00:00 changed) */
4406 #define RTCTEV__1200 (0x0300u) /* RTC Time Event: 3 (12:00 changed) */
4407 
4408 /* RTCCTL23 Control Bits */
4409 #define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */
4410 #define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */
4411 #define RTCCALS (0x0080u) /* RTC Calibration Sign */
4412 //#define Reserved (0x0040u)
4413 #define RTCCAL5 (0x0020u) /* RTC Calibration Bit 5 */
4414 #define RTCCAL4 (0x0010u) /* RTC Calibration Bit 4 */
4415 #define RTCCAL3 (0x0008u) /* RTC Calibration Bit 3 */
4416 #define RTCCAL2 (0x0004u) /* RTC Calibration Bit 2 */
4417 #define RTCCAL1 (0x0002u) /* RTC Calibration Bit 1 */
4418 #define RTCCAL0 (0x0001u) /* RTC Calibration Bit 0 */
4419 
4420 /* RTCCTL23 Control Bits */
4421 #define RTCCALS_L (0x0080u) /* RTC Calibration Sign */
4422 //#define Reserved (0x0040u)
4423 #define RTCCAL5_L (0x0020u) /* RTC Calibration Bit 5 */
4424 #define RTCCAL4_L (0x0010u) /* RTC Calibration Bit 4 */
4425 #define RTCCAL3_L (0x0008u) /* RTC Calibration Bit 3 */
4426 #define RTCCAL2_L (0x0004u) /* RTC Calibration Bit 2 */
4427 #define RTCCAL1_L (0x0002u) /* RTC Calibration Bit 1 */
4428 #define RTCCAL0_L (0x0001u) /* RTC Calibration Bit 0 */
4429 
4430 /* RTCCTL23 Control Bits */
4431 #define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */
4432 #define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */
4433 //#define Reserved (0x0040u)
4434 
4435 #define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */
4436 #define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */
4437 #define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */
4438 #define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */
4439 
4440 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
4441 
4442 /* RTCPS0CTL Control Bits */
4443 //#define Reserved (0x0080u)
4444 //#define Reserved (0x0040u)
4445 //#define Reserved (0x0020u)
4446 #define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4447 #define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4448 #define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4449 #define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4450 #define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
4451 
4452 /* RTCPS0CTL Control Bits */
4453 //#define Reserved (0x0080u)
4454 //#define Reserved (0x0040u)
4455 //#define Reserved (0x0020u)
4456 #define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4457 #define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4458 #define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4459 #define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4460 #define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
4461 
4462 #define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4463 #define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4464 #define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4465 #define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4466 #define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4467 #define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4468 #define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4469 #define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4470 
4471 #define RT0IP__2 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4472 #define RT0IP__4 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4473 #define RT0IP__8 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4474 #define RT0IP__16 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4475 #define RT0IP__32 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4476 #define RT0IP__64 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4477 #define RT0IP__128 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4478 #define RT0IP__256 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4479 
4480 /* RTCPS1CTL Control Bits */
4481 //#define Reserved (0x0080u)
4482 //#define Reserved (0x0040u)
4483 //#define Reserved (0x0020u)
4484 #define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4485 #define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4486 #define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4487 #define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4488 #define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
4489 
4490 /* RTCPS1CTL Control Bits */
4491 //#define Reserved (0x0080u)
4492 //#define Reserved (0x0040u)
4493 //#define Reserved (0x0020u)
4494 #define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4495 #define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4496 #define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4497 #define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4498 #define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
4499 
4500 #define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4501 #define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4502 #define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4503 #define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4504 #define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4505 #define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4506 #define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */
4507 #define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */
4508 
4509 #define RT1IP__2 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4510 #define RT1IP__4 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4511 #define RT1IP__8 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4512 #define RT1IP__16 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4513 #define RT1IP__32 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4514 #define RT1IP__64 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4515 #define RT1IP__128 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */
4516 #define RT1IP__256 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */
4517 
4518 /* RTC Definitions */
4519 #define RTCIV_NONE (0x0000u) /* No Interrupt pending */
4520 #define RTCIV_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */
4521 #define RTCIV_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */
4522 #define RTCIV_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */
4523 #define RTCIV_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */
4524 #define RTCIV_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */
4525 #define RTCIV_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */
4526 
4527 /* Legacy Definitions */
4528 #define RTC_NONE (0x0000u) /* No Interrupt pending */
4529 #define RTC_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */
4530 #define RTC_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */
4531 #define RTC_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */
4532 #define RTC_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */
4533 #define RTC_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */
4534 #define RTC_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */
4535 
4536 #endif
4537 /************************************************************
4538 * Real Time Clock
4539 ************************************************************/
4540 #ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */
4541 
4542 #define OFS_RTCCTL0 (0x0000u) /* Real Timer Clock Control 0/Key */
4543 #define OFS_RTCCTL0_L OFS_RTCCTL0
4544 #define OFS_RTCCTL0_H OFS_RTCCTL0+1
4545 #define OFS_RTCCTL13 (0x0002u) /* Real Timer Clock Control 1/3 */
4546 #define OFS_RTCCTL13_L OFS_RTCCTL13
4547 #define OFS_RTCCTL13_H OFS_RTCCTL13+1
4548 #define RTCCTL1 RTCCTL13_L
4549 #define RTCCTL3 RTCCTL13_H
4550 #define OFS_RTCOCAL (0x0004u) /* Real Timer Clock Offset Calibartion */
4551 #define OFS_RTCOCAL_L OFS_RTCOCAL
4552 #define OFS_RTCOCAL_H OFS_RTCOCAL+1
4553 #define OFS_RTCTCMP (0x0006u) /* Real Timer Temperature Compensation */
4554 #define OFS_RTCTCMP_L OFS_RTCTCMP
4555 #define OFS_RTCTCMP_H OFS_RTCTCMP+1
4556 #define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */
4557 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
4558 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
4559 #define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */
4560 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
4561 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
4562 #define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */
4563 #define OFS_RTCPS_L OFS_RTCPS
4564 #define OFS_RTCPS_H OFS_RTCPS+1
4565 #define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */
4566 #define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */
4567 #define OFS_RTCTIM0_L OFS_RTCTIM0
4568 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
4569 #define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */
4570 #define OFS_RTCTIM1_L OFS_RTCTIM1
4571 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
4572 #define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */
4573 #define OFS_RTCDATE_L OFS_RTCDATE
4574 #define OFS_RTCDATE_H OFS_RTCDATE+1
4575 #define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */
4576 #define OFS_RTCYEAR_L OFS_RTCYEAR
4577 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
4578 #define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */
4579 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
4580 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
4581 #define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */
4582 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
4583 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
4584 #define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */
4585 #define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */
4586 #define OFS_RTCSEC (0x0010u)
4587 #define OFS_RTCMIN (0x0011u)
4588 #define OFS_RTCHOUR (0x0012u)
4589 #define OFS_RTCDOW (0x0013u)
4590 #define OFS_RTCDAY (0x0014u)
4591 #define OFS_RTCMON (0x0015u)
4592 #define OFS_RTCAMIN (0x0018u)
4593 #define OFS_RTCAHOUR (0x0019u)
4594 #define OFS_RTCADOW (0x001Au)
4595 #define OFS_RTCADAY (0x001Bu)
4596 
4597 #define RTCSEC RTCTIM0_L
4598 #define RTCMIN RTCTIM0_H
4599 #define RTCHOUR RTCTIM1_L
4600 #define RTCDOW RTCTIM1_H
4601 #define RTCDAY RTCDATE_L
4602 #define RTCMON RTCDATE_H
4603 #define RTCYEARL RTCYEAR_L
4604 #define RT0PS RTCPS_L
4605 #define RT1PS RTCPS_H
4606 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
4607 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
4608 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
4609 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
4610 
4611 /* RTCCTL0 Control Bits */
4612 #define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4613 #define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */
4614 #define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */
4615 #define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */
4616 #define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4617 #define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */
4618 #define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */
4619 #define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */
4620 
4621 /* RTCCTL0 Control Bits */
4622 #define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4623 #define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */
4624 #define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */
4625 #define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */
4626 #define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4627 #define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */
4628 #define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */
4629 #define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */
4630 
4631 #define RTCKEY (0xA500u) /* RTC Key for RTC write access */
4632 #define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */
4633 
4634 /* RTCCTL13 Control Bits */
4635 #define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */
4636 #define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */
4637 #define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
4638 #define RTCHOLD (0x0040u) /* RTC Hold */
4639 #define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */
4640 #define RTCRDY (0x0010u) /* RTC Ready */
4641 #define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */
4642 #define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */
4643 #define RTCTEV1 (0x0002u) /* RTC Time Event 1 */
4644 #define RTCTEV0 (0x0001u) /* RTC Time Event 0 */
4645 
4646 /* RTCCTL13 Control Bits */
4647 #define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
4648 #define RTCHOLD_L (0x0040u) /* RTC Hold */
4649 #define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */
4650 #define RTCRDY_L (0x0010u) /* RTC Ready */
4651 #define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */
4652 #define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */
4653 #define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */
4654 #define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */
4655 
4656 /* RTCCTL13 Control Bits */
4657 #define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */
4658 #define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */
4659 
4660 #define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */
4661 #define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */
4662 #define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */
4663 #define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */
4664 #define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */
4665 #define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */
4666 #define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */
4667 
4668 #define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */
4669 #define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */
4670 #define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */
4671 #define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */
4672 #define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */
4673 #define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */
4674 #define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */
4675 #define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */
4676 
4677 #define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */
4678 #define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */
4679 #define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */
4680 #define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */
4681 
4682 /* RTCOCAL Control Bits */
4683 #define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */
4684 #define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */
4685 #define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */
4686 #define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */
4687 #define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */
4688 #define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */
4689 #define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */
4690 #define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */
4691 #define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */
4692 
4693 /* RTCOCAL Control Bits */
4694 #define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */
4695 #define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */
4696 #define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */
4697 #define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */
4698 #define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */
4699 #define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */
4700 #define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */
4701 #define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */
4702 
4703 /* RTCOCAL Control Bits */
4704 #define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */
4705 
4706 /* RTCTCMP Control Bits */
4707 #define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */
4708 #define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */
4709 #define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */
4710 #define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */
4711 #define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */
4712 #define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */
4713 #define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */
4714 #define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */
4715 #define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */
4716 #define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */
4717 #define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */
4718 
4719 /* RTCTCMP Control Bits */
4720 #define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */
4721 #define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */
4722 #define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */
4723 #define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */
4724 #define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */
4725 #define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */
4726 #define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */
4727 #define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */
4728 
4729 /* RTCTCMP Control Bits */
4730 #define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */
4731 #define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */
4732 #define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */
4733 
4734 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
4735 
4736 /* RTCPS0CTL Control Bits */
4737 //#define Reserved (0x8000u)
4738 //#define Reserved (0x4000u)
4739 #define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
4740 #define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
4741 #define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
4742 //#define Reserved (0x0400u)
4743 //#define Reserved (0x0200u)
4744 #define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */
4745 //#define Reserved (0x0080u)
4746 //#define Reserved (0x0040u)
4747 //#define Reserved (0x0020u)
4748 #define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4749 #define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4750 #define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4751 #define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4752 #define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
4753 
4754 /* RTCPS0CTL Control Bits */
4755 //#define Reserved (0x8000u)
4756 //#define Reserved (0x4000u)
4757 //#define Reserved (0x0400u)
4758 //#define Reserved (0x0200u)
4759 //#define Reserved (0x0080u)
4760 //#define Reserved (0x0040u)
4761 //#define Reserved (0x0020u)
4762 #define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4763 #define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4764 #define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4765 #define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4766 #define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
4767 
4768 /* RTCPS0CTL Control Bits */
4769 //#define Reserved (0x8000u)
4770 //#define Reserved (0x4000u)
4771 #define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
4772 #define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
4773 #define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
4774 //#define Reserved (0x0400u)
4775 //#define Reserved (0x0200u)
4776 #define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */
4777 //#define Reserved (0x0080u)
4778 //#define Reserved (0x0040u)
4779 //#define Reserved (0x0020u)
4780 
4781 #define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4782 #define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4783 #define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4784 #define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4785 #define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4786 #define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4787 #define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4788 #define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4789 
4790 /* RTCPS1CTL Control Bits */
4791 #define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */
4792 #define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */
4793 #define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
4794 #define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
4795 #define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
4796 //#define Reserved (0x0400u)
4797 //#define Reserved (0x0200u)
4798 #define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */
4799 //#define Reserved (0x0080u)
4800 //#define Reserved (0x0040u)
4801 //#define Reserved (0x0020u)
4802 #define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4803 #define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4804 #define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4805 #define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4806 #define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
4807 
4808 /* RTCPS1CTL Control Bits */
4809 //#define Reserved (0x0400u)
4810 //#define Reserved (0x0200u)
4811 //#define Reserved (0x0080u)
4812 //#define Reserved (0x0040u)
4813 //#define Reserved (0x0020u)
4814 #define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4815 #define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4816 #define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4817 #define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4818 #define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
4819 
4820 /* RTCPS1CTL Control Bits */
4821 #define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */
4822 #define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */
4823 #define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
4824 #define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
4825 #define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
4826 //#define Reserved (0x0400u)
4827 //#define Reserved (0x0200u)
4828 #define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */
4829 //#define Reserved (0x0080u)
4830 //#define Reserved (0x0040u)
4831 //#define Reserved (0x0020u)
4832 
4833 #define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4834 #define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4835 #define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4836 #define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4837 #define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4838 #define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4839 #define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */
4840 #define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */
4841 
4842 /* RTC Definitions */
4843 #define RTCIV_NONE (0x0000u) /* No Interrupt pending */
4844 #define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */
4845 #define RTCIV_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */
4846 #define RTCIV_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */
4847 #define RTCIV_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */
4848 #define RTCIV_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */
4849 #define RTCIV_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */
4850 
4851 /* Legacy Definitions */
4852 #define RTC_NONE (0x0000u) /* No Interrupt pending */
4853 #define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */
4854 #define RTC_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */
4855 #define RTC_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */
4856 #define RTC_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */
4857 #define RTC_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */
4858 #define RTC_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */
4859 
4860 #endif
4861 /************************************************************
4862 * Real Time Clock
4863 ************************************************************/
4864 #ifdef __MSP430_HAS_RTC_CE__ /* Definition to show that Module is available */
4865 
4866 #define OFS_RTCCTL0 (0x0000u) /* Real Timer Clock Control 0/Key */
4867 #define OFS_RTCCTL0_L OFS_RTCCTL0
4868 #define OFS_RTCCTL0_H OFS_RTCCTL0+1
4869 #define OFS_RTCCTL13 (0x0002u) /* Real Timer Clock Control 1/3 */
4870 #define OFS_RTCCTL13_L OFS_RTCCTL13
4871 #define OFS_RTCCTL13_H OFS_RTCCTL13+1
4872 #define RTCCTL1 RTCCTL13_L
4873 #define RTCCTL3 RTCCTL13_H
4874 #define OFS_RTCOCAL (0x0004u) /* Real Timer Clock Offset Calibartion */
4875 #define OFS_RTCOCAL_L OFS_RTCOCAL
4876 #define OFS_RTCOCAL_H OFS_RTCOCAL+1
4877 #define OFS_RTCTCMP (0x0006u) /* Real Timer Temperature Compensation */
4878 #define OFS_RTCTCMP_L OFS_RTCTCMP
4879 #define OFS_RTCTCMP_H OFS_RTCTCMP+1
4880 #define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */
4881 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
4882 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
4883 #define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */
4884 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
4885 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
4886 #define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */
4887 #define OFS_RTCPS_L OFS_RTCPS
4888 #define OFS_RTCPS_H OFS_RTCPS+1
4889 #define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */
4890 #define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */
4891 #define OFS_RTCTIM0_L OFS_RTCTIM0
4892 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
4893 #define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */
4894 #define OFS_RTCTIM1_L OFS_RTCTIM1
4895 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
4896 #define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */
4897 #define OFS_RTCDATE_L OFS_RTCDATE
4898 #define OFS_RTCDATE_H OFS_RTCDATE+1
4899 #define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */
4900 #define OFS_RTCYEAR_L OFS_RTCYEAR
4901 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
4902 #define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */
4903 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
4904 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
4905 #define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */
4906 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
4907 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
4908 #define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */
4909 #define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */
4910 #define OFS_RTCSEC (0x0010u)
4911 #define OFS_RTCMIN (0x0011u)
4912 #define OFS_RTCHOUR (0x0012u)
4913 #define OFS_RTCDOW (0x0013u)
4914 #define OFS_RTCDAY (0x0014u)
4915 #define OFS_RTCMON (0x0015u)
4916 #define OFS_RTCAMIN (0x0018u)
4917 #define OFS_RTCAHOUR (0x0019u)
4918 #define OFS_RTCADOW (0x001Au)
4919 #define OFS_RTCADAY (0x001Bu)
4920 
4921 #define OFS_RTCTCCTL0 (0x0020u) /* Real-Time Clock Time Capture Control Register 0 */
4922 #define OFS_RTCTCCTL1 (0x0021u) /* Real-Time Clock Time Capture Control Register 1 */
4923 #define OFS_RTCCAP0CTL (0x0022u) /* Tamper Detect Pin 0 Control Register */
4924 #define OFS_RTCCAP1CTL (0x0023u) /* Tamper Detect Pin 1 Control Register */
4925 #define OFS_RTCSECBAK0 (0x0030u) /* Real-Time Clock Seconds Backup Register 0 */
4926 #define OFS_RTCMINBAK0 (0x0031u) /* Real-Time Clock Minutes Backup Register 0 */
4927 #define OFS_RTCHOURBAK0 (0x0032u) /* Real-Time Clock Hours Backup Register 0 */
4928 #define OFS_RTCDAYBAK0 (0x0033u) /* Real-Time Clock Days Backup Register 0 */
4929 #define OFS_RTCMONBAK0 (0x0034u) /* Real-Time Clock Months Backup Register 0 */
4930 #define OFS_RTCYEARBAK0 (0x0036u) /* Real-Time Clock year Backup Register 0 */
4931 #define OFS_RTCSECBAK1 (0x0038u) /* Real-Time Clock Seconds Backup Register 1 */
4932 #define OFS_RTCMINBAK1 (0x0039u) /* Real-Time Clock Minutes Backup Register 1 */
4933 #define OFS_RTCHOURBAK1 (0x003Au) /* Real-Time Clock Hours Backup Register 1 */
4934 #define OFS_RTCDAYBAK1 (0x003Bu) /* Real-Time Clock Days Backup Register 1 */
4935 #define OFS_RTCMONBAK1 (0x003Cu) /* Real-Time Clock Months Backup Register 1 */
4936 #define OFS_RTCYEARBAK1 (0x003Eu) /* Real-Time Clock Year Backup Register 1 */
4937 
4938 #define RTCSEC RTCTIM0_L
4939 #define RTCMIN RTCTIM0_H
4940 #define RTCHOUR RTCTIM1_L
4941 #define RTCDOW RTCTIM1_H
4942 #define RTCDAY RTCDATE_L
4943 #define RTCMON RTCDATE_H
4944 #define RTCYEARL RTCYEAR_L
4945 #define RT0PS RTCPS_L
4946 #define RT1PS RTCPS_H
4947 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
4948 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
4949 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
4950 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
4951 
4952 /* RTCCTL0 Control Bits */
4953 #define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4954 #define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */
4955 #define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */
4956 #define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */
4957 #define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4958 #define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */
4959 #define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */
4960 #define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */
4961 
4962 /* RTCCTL0 Control Bits */
4963 #define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4964 #define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */
4965 #define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */
4966 #define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */
4967 #define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4968 #define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */
4969 #define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */
4970 #define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */
4971 
4972 #define RTCKEY (0xA500u) /* RTC Key for RTC write access */
4973 #define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */
4974 
4975 /* RTCCTL13 Control Bits */
4976 #define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */
4977 #define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */
4978 #define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
4979 #define RTCHOLD (0x0040u) /* RTC Hold */
4980 #define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */
4981 #define RTCRDY (0x0010u) /* RTC Ready */
4982 #define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */
4983 #define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */
4984 #define RTCTEV1 (0x0002u) /* RTC Time Event 1 */
4985 #define RTCTEV0 (0x0001u) /* RTC Time Event 0 */
4986 
4987 /* RTCCTL13 Control Bits */
4988 #define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
4989 #define RTCHOLD_L (0x0040u) /* RTC Hold */
4990 #define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */
4991 #define RTCRDY_L (0x0010u) /* RTC Ready */
4992 #define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */
4993 #define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */
4994 #define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */
4995 #define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */
4996 
4997 /* RTCCTL13 Control Bits */
4998 #define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */
4999 #define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */
5000 
5001 #define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */
5002 #define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */
5003 #define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */
5004 #define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */
5005 #define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */
5006 #define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */
5007 #define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */
5008 
5009 #define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */
5010 #define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */
5011 #define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */
5012 #define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */
5013 #define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */
5014 #define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */
5015 #define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */
5016 #define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */
5017 
5018 #define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */
5019 #define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */
5020 #define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */
5021 #define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */
5022 
5023 /* RTCOCAL Control Bits */
5024 #define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */
5025 #define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */
5026 #define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */
5027 #define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */
5028 #define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */
5029 #define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */
5030 #define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */
5031 #define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */
5032 #define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */
5033 
5034 /* RTCOCAL Control Bits */
5035 #define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */
5036 #define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */
5037 #define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */
5038 #define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */
5039 #define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */
5040 #define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */
5041 #define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */
5042 #define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */
5043 
5044 /* RTCOCAL Control Bits */
5045 #define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */
5046 
5047 /* RTCTCMP Control Bits */
5048 #define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */
5049 #define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */
5050 #define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */
5051 #define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */
5052 #define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */
5053 #define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */
5054 #define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */
5055 #define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */
5056 #define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */
5057 #define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */
5058 #define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */
5059 
5060 /* RTCTCMP Control Bits */
5061 #define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */
5062 #define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */
5063 #define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */
5064 #define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */
5065 #define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */
5066 #define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */
5067 #define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */
5068 #define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */
5069 
5070 /* RTCTCMP Control Bits */
5071 #define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */
5072 #define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */
5073 #define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */
5074 
5075 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
5076 
5077 /* RTCPS0CTL Control Bits */
5078 //#define Reserved (0x8000u)
5079 //#define Reserved (0x4000u)
5080 #define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
5081 #define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
5082 #define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
5083 //#define Reserved (0x0400u)
5084 //#define Reserved (0x0200u)
5085 #define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */
5086 //#define Reserved (0x0080u)
5087 //#define Reserved (0x0040u)
5088 //#define Reserved (0x0020u)
5089 #define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
5090 #define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
5091 #define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
5092 #define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
5093 #define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
5094 
5095 /* RTCPS0CTL Control Bits */
5096 //#define Reserved (0x8000u)
5097 //#define Reserved (0x4000u)
5098 //#define Reserved (0x0400u)
5099 //#define Reserved (0x0200u)
5100 //#define Reserved (0x0080u)
5101 //#define Reserved (0x0040u)
5102 //#define Reserved (0x0020u)
5103 #define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
5104 #define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
5105 #define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
5106 #define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
5107 #define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */
5108 
5109 /* RTCPS0CTL Control Bits */
5110 //#define Reserved (0x8000u)
5111 //#define Reserved (0x4000u)
5112 #define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
5113 #define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
5114 #define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
5115 //#define Reserved (0x0400u)
5116 //#define Reserved (0x0200u)
5117 #define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */
5118 //#define Reserved (0x0080u)
5119 //#define Reserved (0x0040u)
5120 //#define Reserved (0x0020u)
5121 
5122 #define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */
5123 #define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */
5124 #define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */
5125 #define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */
5126 #define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */
5127 #define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */
5128 #define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */
5129 #define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */
5130 
5131 /* RTCPS1CTL Control Bits */
5132 #define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */
5133 #define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */
5134 #define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
5135 #define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
5136 #define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
5137 //#define Reserved (0x0400u)
5138 //#define Reserved (0x0200u)
5139 #define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */
5140 //#define Reserved (0x0080u)
5141 //#define Reserved (0x0040u)
5142 //#define Reserved (0x0020u)
5143 #define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
5144 #define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
5145 #define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
5146 #define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
5147 #define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
5148 
5149 /* RTCPS1CTL Control Bits */
5150 //#define Reserved (0x0400u)
5151 //#define Reserved (0x0200u)
5152 //#define Reserved (0x0080u)
5153 //#define Reserved (0x0040u)
5154 //#define Reserved (0x0020u)
5155 #define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
5156 #define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
5157 #define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
5158 #define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
5159 #define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */
5160 
5161 /* RTCPS1CTL Control Bits */
5162 #define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */
5163 #define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */
5164 #define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
5165 #define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
5166 #define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
5167 //#define Reserved (0x0400u)
5168 //#define Reserved (0x0200u)
5169 #define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */
5170 //#define Reserved (0x0080u)
5171 //#define Reserved (0x0040u)
5172 //#define Reserved (0x0020u)
5173 
5174 #define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */
5175 #define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */
5176 #define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */
5177 #define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */
5178 #define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */
5179 #define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */
5180 #define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */
5181 #define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */
5182 
5183 /* RTCTCCTL0 Control Bits */
5184 #define TCEN (0x0001u) /* RTC Enable for RTC Tamper Detection with Time Stamp */
5185 #define AUX3RST (0x0002u) /* RTC Indication of power cycle on AUXVCC3 */
5186 
5187 /* RTCTCCTL1 Control Bits */
5188 #define RTCCAPIFG (0x0001u) /* RTC Tamper Event Interrupt Flag */
5189 #define RTCCAPIE (0x0002u) /* RTC Tamper Event Interrupt Enable */
5190 
5191 /* RTCCAPxCTL Control Bits */
5192 #define CAPEV (0x0001u) /* RTC Tamper Event Flag */
5193 #define CAPES (0x0004u) /* RTC Event Edge Select */
5194 #define RTCREN (0x0008u) /* RTC RTCCAPx pin pullup/pulldown resistor enable */
5195 #define RTCCAPIN (0x0010u) /* RTC RTCCAPx input */
5196 #define RTCCAPDIR (0x0020u) /* RTC RTCCAPx Pin direction */
5197 #define RTCCAPOUT (0x0040u) /* RTC RTCCAPx Output */
5198 
5199 /* RTCIV Definitions */
5200 #define RTCIV_NONE (0x0000u) /* No Interrupt pending */
5201 #define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */
5202 #define RTCIV_RTCCAPIFG (0x0004u) /* RTC RTC Tamper Event: RTCCAPIFG */
5203 #define RTCIV_RTCRDYIFG (0x0006u) /* RTC ready: RTCRDYIFG */
5204 #define RTCIV_RTCTEVIFG (0x0008u) /* RTC interval timer: RTCTEVIFG */
5205 #define RTCIV_RTCAIFG (0x000Au) /* RTC user alarm: RTCAIFG */
5206 #define RTCIV_RT0PSIFG (0x000Cu) /* RTC prescaler 0: RT0PSIFG */
5207 #define RTCIV_RT1PSIFG (0x000Eu) /* RTC prescaler 1: RT1PSIFG */
5208 
5209 /* Legacy RTCIV Definitions */
5210 #define RTC_NONE (0x0000u) /* No Interrupt pending */
5211 #define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */
5212 #define RTC_RTCRDYIFG (0x0006u) /* RTC ready: RTCRDYIFG */
5213 #define RTC_RTCTEVIFG (0x0008u) /* RTC interval timer: RTCTEVIFG */
5214 #define RTC_RTCAIFG (0x000Au) /* RTC user alarm: RTCAIFG */
5215 #define RTC_RT0PSIFG (0x000Cu) /* RTC prescaler 0: RT0PSIFG */
5216 #define RTC_RT1PSIFG (0x000Eu) /* RTC prescaler 1: RT1PSIFG */
5217 
5218 #endif
5219 /************************************************************
5220 * SD24_B - Sigma Delta 24 Bit
5221 ************************************************************/
5222 #ifdef __MSP430_HAS_SD24_B__ /* Definition to show that Module is available */
5223 
5224 #define OFS_SD24BCTL0 (0x0000u) /* SD24B Control Register 0 */
5225 #define OFS_SD24BCTL0_L OFS_SD24BCTL0
5226 #define OFS_SD24BCTL0_H OFS_SD24BCTL0+1
5227 #define OFS_SD24BCTL1 (0x0002u) /* SD24B Control Register 1 */
5228 #define OFS_SD24BCTL1_L OFS_SD24BCTL1
5229 #define OFS_SD24BCTL1_H OFS_SD24BCTL1+1
5230 #define OFS_SD24BTRGCTL (0x0004u) /* SD24B Trigger Control Register */
5231 #define OFS_SD24BTRGCTL_L OFS_SD24BTRGCTL
5232 #define OFS_SD24BTRGCTL_H OFS_SD24BTRGCTL+1
5233 #define OFS_SD24BTRGOSR (0x0006u) /* SD24B Trigger OSR Control Register */
5234 #define OFS_SD24BTRGOSR_L OFS_SD24BTRGOSR
5235 #define OFS_SD24BTRGOSR_H OFS_SD24BTRGOSR+1
5236 #define OFS_SD24BTRGPRE (0x0008u) /* SD24B Trigger Preload Register */
5237 #define OFS_SD24BTRGPRE_L OFS_SD24BTRGPRE
5238 #define OFS_SD24BTRGPRE_H OFS_SD24BTRGPRE+1
5239 #define OFS_SD24BIFG (0x000Au) /* SD24B Interrupt Flag Register */
5240 #define OFS_SD24BIFG_L OFS_SD24BIFG
5241 #define OFS_SD24BIFG_H OFS_SD24BIFG+1
5242 #define OFS_SD24BIE (0x000Cu) /* SD24B Interrupt Enable Register */
5243 #define OFS_SD24BIE_L OFS_SD24BIE
5244 #define OFS_SD24BIE_H OFS_SD24BIE+1
5245 #define OFS_SD24BIV (0x000Eu) /* SD24B Interrupt Vector Register */
5246 #define OFS_SD24BIV_L OFS_SD24BIV
5247 #define OFS_SD24BIV_H OFS_SD24BIV+1
5248 
5249 #define OFS_SD24BCCTL0 (0x0010u) /* SD24B Channel 0 Control Register */
5250 #define OFS_SD24BCCTL0_L OFS_SD24BCCTL0
5251 #define OFS_SD24BCCTL0_H OFS_SD24BCCTL0+1
5252 #define OFS_SD24BINCTL0 (0x0012u) /* SD24B Channel 0 Input Control Register */
5253 #define OFS_SD24BINCTL0_L OFS_SD24BINCTL0
5254 #define OFS_SD24BINCTL0_H OFS_SD24BINCTL0+1
5255 #define OFS_SD24BOSR0 (0x0014u) /* SD24B Channel 0 OSR Control Register */
5256 #define OFS_SD24BOSR0_L OFS_SD24BOSR0
5257 #define OFS_SD24BOSR0_H OFS_SD24BOSR0+1
5258 #define OFS_SD24BPRE0 (0x0016u) /* SD24B Channel 0 Preload Register */
5259 #define OFS_SD24BPRE0_L OFS_SD24BPRE0
5260 #define OFS_SD24BPRE0_H OFS_SD24BPRE0+1
5261 
5262 #define OFS_SD24BMEML0 (0x0050u) /* SD24B Channel 0 Conversion Memory Low word */
5263 #define OFS_SD24BMEML0_L OFS_SD24BMEML0
5264 #define OFS_SD24BMEML0_H OFS_SD24BMEML0+1
5265 #define OFS_SD24BMEMH0 (0x0052u) /* SD24B Channel 0 Conversion Memory High Word */
5266 #define OFS_SD24BMEMH0_L OFS_SD24BMEMH0
5267 #define OFS_SD24BMEMH0_H OFS_SD24BMEMH0+1
5268 
5269 /* SD24BCTL0 */
5270 #define SD24OV32 (0x0002u) /* SD24B Overflow Control */
5271 #define SD24REFS (0x0004u) /* SD24B Reference Select */
5272 #define SD24SSEL0 (0x0010u) /* SD24B Clock Source Select 0 */
5273 #define SD24SSEL1 (0x0020u) /* SD24B Clock Source Select 1 */
5274 #define SD24M4 (0x0040u) /* SD24B Modulator clock to Manchester decoder clock ratio */
5275 #define SD24CLKOS (0x0080u) /* SD24B Clock Output Select */
5276 #define SD24PDIV0 (0x0100u) /* SD24B Frequency pre-scaler Bit 0 */
5277 #define SD24PDIV1 (0x0200u) /* SD24B Frequency pre-scaler Bit 1 */
5278 #define SD24PDIV2 (0x0400u) /* SD24B Frequency pre-scaler Bit 2 */
5279 #define SD24DIV0 (0x0800u) /* SD24B Frequency Divider Bit 0 */
5280 #define SD24DIV1 (0x1000u) /* SD24B Frequency Divider Bit 1 */
5281 #define SD24DIV2 (0x2000u) /* SD24B Frequency Divider Bit 2 */
5282 #define SD24DIV3 (0x4000u) /* SD24B Frequency Divider Bit 3 */
5283 #define SD24DIV4 (0x8000u) /* SD24B Frequency Divider Bit 4 */
5284 
5285 #define SD24OV32_L (0x0002u) /* SD24B Overflow Control */
5286 #define SD24REFS_L (0x0004u) /* SD24B Reference Select */
5287 #define SD24SSEL0_L (0x0010u) /* SD24B Clock Source Select 0 */
5288 #define SD24SSEL1_L (0x0020u) /* SD24B Clock Source Select 1 */
5289 #define SD24M4_L (0x0040u) /* SD24B Modulator clock to Manchester decoder clock ratio */
5290 #define SD24CLKOS_L (0x0080u) /* SD24B Clock Output Select */
5291 
5292 #define SD24PDIV0_H (0x0001u) /* SD24B Frequency pre-scaler Bit 0 */
5293 #define SD24PDIV1_H (0x0002u) /* SD24B Frequency pre-scaler Bit 1 */
5294 #define SD24PDIV2_H (0x0004u) /* SD24B Frequency pre-scaler Bit 2 */
5295 #define SD24DIV0_H (0x0008u) /* SD24B Frequency Divider Bit 0 */
5296 #define SD24DIV1_H (0x0010u) /* SD24B Frequency Divider Bit 1 */
5297 #define SD24DIV2_H (0x0020u) /* SD24B Frequency Divider Bit 2 */
5298 #define SD24DIV3_H (0x0040u) /* SD24B Frequency Divider Bit 3 */
5299 #define SD24DIV4_H (0x0080u) /* SD24B Frequency Divider Bit 4 */
5300 
5301 #define SD24SSEL_0 (0x0000u) /* SD24B Clock Source Select MCLK */
5302 #define SD24SSEL_1 (0x0010u) /* SD24B Clock Source Select SMCLK */
5303 #define SD24SSEL_2 (0x0020u) /* SD24B Clock Source Select ACLK */
5304 #define SD24SSEL_3 (0x0030u) /* SD24B Clock Source Select TACLK */
5305 #define SD24SSEL__MCLK (0x0000u) /* SD24B Clock Source Select MCLK */
5306 #define SD24SSEL__SMCLK (0x0010u) /* SD24B Clock Source Select SMCLK */
5307 #define SD24SSEL__ACLK (0x0020u) /* SD24B Clock Source Select ACLK */
5308 #define SD24SSEL__SD24CLK (0x0030u) /* SD24B Clock Source Select SD24CLK */
5309 
5310 #define SD24PDIV_0 (0x0000u) /* SD24B Frequency pre-scaler /1 */
5311 #define SD24PDIV_1 (0x0100u) /* SD24B Frequency pre-scaler /2 */
5312 #define SD24PDIV_2 (0x0200u) /* SD24B Frequency pre-scaler /4 */
5313 #define SD24PDIV_3 (0x0300u) /* SD24B Frequency pre-scaler /8 */
5314 #define SD24PDIV_4 (0x0400u) /* SD24B Frequency pre-scaler /16 */
5315 #define SD24PDIV_5 (0x0500u) /* SD24B Frequency pre-scaler /32 */
5316 #define SD24PDIV_6 (0x0600u) /* SD24B Frequency pre-scaler /64 */
5317 #define SD24PDIV_7 (0x0700u) /* SD24B Frequency pre-scaler /128 */
5318 
5319 /* SD24BCTL1 */
5320 #define SD24GRP0SC (0x0001u) /* SD24B Group 0 Start Conversion */
5321 #define SD24GRP1SC (0x0002u) /* SD24B Group 1 Start Conversion */
5322 #define SD24GRP2SC (0x0004u) /* SD24B Group 2 Start Conversion */
5323 #define SD24GRP3SC (0x0008u) /* SD24B Group 3 Start Conversion */
5324 #define SD24DMA0 (0x0100u) /* SD24B DMA Trigger Select Bit 0 */
5325 #define SD24DMA1 (0x0200u) /* SD24B DMA Trigger Select Bit 1 */
5326 #define SD24DMA2 (0x0400u) /* SD24B DMA Trigger Select Bit 2 */
5327 #define SD24DMA3 (0x0800u) /* SD24B DMA Trigger Select Bit 3 */
5328 
5329 #define SD24GRP0SC_L (0x0001u) /* SD24B Group 0 Start Conversion */
5330 #define SD24GRP1SC_L (0x0002u) /* SD24B Group 1 Start Conversion */
5331 #define SD24GRP2SC_L (0x0004u) /* SD24B Group 2 Start Conversion */
5332 #define SD24GRP3SC_L (0x0008u) /* SD24B Group 3 Start Conversion */
5333 
5334 #define SD24DMA0_H (0x0001u) /* SD24B DMA Trigger Select Bit 0 */
5335 #define SD24DMA1_H (0x0002u) /* SD24B DMA Trigger Select Bit 1 */
5336 #define SD24DMA2_H (0x0004u) /* SD24B DMA Trigger Select Bit 2 */
5337 #define SD24DMA3_H (0x0008u) /* SD24B DMA Trigger Select Bit 3 */
5338 
5339 #define SD24DMA_0 (0x0000u) /* SD24B DMA Trigger: 0 */
5340 #define SD24DMA_1 (0x0100u) /* SD24B DMA Trigger: 1 */
5341 #define SD24DMA_2 (0x0200u) /* SD24B DMA Trigger: 2 */
5342 #define SD24DMA_3 (0x0300u) /* SD24B DMA Trigger: 3 */
5343 #define SD24DMA_4 (0x0400u) /* SD24B DMA Trigger: 4 */
5344 #define SD24DMA_5 (0x0500u) /* SD24B DMA Trigger: 5 */
5345 #define SD24DMA_6 (0x0600u) /* SD24B DMA Trigger: 6 */
5346 #define SD24DMA_7 (0x0700u) /* SD24B DMA Trigger: 7 */
5347 #define SD24DMA_8 (0x0800u) /* SD24B DMA Trigger: 8 */
5348 
5349 /* SD24BTRGCTL */
5350 #define SD24SC (0x0001u) /* SD24B Start Conversion */
5351 #define SD24SCS0 (0x0002u) /* SD24B Start Conversion Select Bit 0 */
5352 #define SD24SCS1 (0x0004u) /* SD24B Start Conversion Select Bit 1 */
5353 #define SD24SCS2 (0x0008u) /* SD24B Start Conversion Select Bit 2 */
5354 #define SD24SNGL (0x0100u) /* SD24B Single Trigger Mode */
5355 #define SD24TRGIFG (0x0400u) /* SD24B Trigger Interrupt Flag */
5356 #define SD24TRGIE (0x0800u) /* SD24B Trigger Interrupt Enable */
5357 
5358 #define SD24SC_L (0x0001u) /* SD24B Start Conversion */
5359 #define SD24SCS0_L (0x0002u) /* SD24B Start Conversion Select Bit 0 */
5360 #define SD24SCS1_L (0x0004u) /* SD24B Start Conversion Select Bit 1 */
5361 #define SD24SCS2_L (0x0008u) /* SD24B Start Conversion Select Bit 2 */
5362 
5363 #define SD24SNGL_H (0x0001u) /* SD24B Single Trigger Mode */
5364 #define SD24TRGIFG_H (0x0004u) /* SD24B Trigger Interrupt Flag */
5365 #define SD24TRGIE_H (0x0008u) /* SD24B Trigger Interrupt Enable */
5366 
5367 #define SD24SCS_0 (0x0000u) /* SD24B Start Conversion Select: 0 */
5368 #define SD24SCS_1 (0x0002u) /* SD24B Start Conversion Select: 1 */
5369 #define SD24SCS_2 (0x0004u) /* SD24B Start Conversion Select: 2 */
5370 #define SD24SCS_3 (0x0006u) /* SD24B Start Conversion Select: 3 */
5371 #define SD24SCS_4 (0x0008u) /* SD24B Start Conversion Select: 4 */
5372 #define SD24SCS_5 (0x000Au) /* SD24B Start Conversion Select: 5 */
5373 #define SD24SCS_6 (0x000Cu) /* SD24B Start Conversion Select: 6 */
5374 #define SD24SCS_7 (0x000Eu) /* SD24B Start Conversion Select: 7 */
5375 #define SD24SCS__SD24SC (0x0000u) /* SD24B Start Conversion Select: SD24SC */
5376 #define SD24SCS__EXT1 (0x0002u) /* SD24B Start Conversion Select: EXT1 */
5377 #define SD24SCS__EXT2 (0x0004u) /* SD24B Start Conversion Select: EXT2 */
5378 #define SD24SCS__EXT3 (0x0006u) /* SD24B Start Conversion Select: EXT3 */
5379 #define SD24SCS__GROUP0 (0x0008u) /* SD24B Start Conversion Select: GROUP0 */
5380 #define SD24SCS__GROUP1 (0x000Au) /* SD24B Start Conversion Select: GROUP1 */
5381 #define SD24SCS__GROUP2 (0x000Cu) /* SD24B Start Conversion Select: GROUP2 */
5382 #define SD24SCS__GROUP3 (0x000Eu) /* SD24B Start Conversion Select: GROUP3 */
5383 
5384 /* SD24BIFG */
5385 #define SD24IFG0 (0x0001u) /* SD24B Channel 0 Interrupt Flag */
5386 #define SD24OVIFG0 (0x0100u) /* SD24B Channel 0 Overflow Interrupt Flag */
5387 
5388 #define SD24IFG0_L (0x0001u) /* SD24B Channel 0 Interrupt Flag */
5389 
5390 #define SD24OVIFG0_H (0x0001u) /* SD24B Channel 0 Overflow Interrupt Flag */
5391 
5392 /* SD24BIE */
5393 #define SD24IE0 (0x0001u) /* SD24B Channel 0 Interrupt Enable */
5394 #define SD24OVIE0 (0x0100u) /* SD24B Channel 0 Overflow Interrupt Enable */
5395 
5396 #define SD24IE0_L (0x0001u) /* SD24B Channel 0 Interrupt Enable */
5397 
5398 #define SD24OVIE0_H (0x0001u) /* SD24B Channel 0 Overflow Interrupt Enable */
5399 
5400 /* SD24BIV Definitions */
5401 #define SD24BIV_NONE (0x0000u) /* No Interrupt pending */
5402 #define SD24BIV_SD24OVIFG (0x0002u) /* SD24OVIFG */
5403 #define SD24BIV_SD24TRGIFG (0x0004u) /* SD24TRGIFG */
5404 #define SD24BIV_SD24IFG0 (0x0006u) /* SD24IFG0 */
5405 
5406 /* SD24BCCTLx */
5407 #define SD24DF0 (0x0010u) /* SD24B Data Format Bit: 0 */
5408 #define SD24DF1 (0x0020u) /* SD24B Data Format Bit: 1 */
5409 #define SD24ALGN (0x0040u) /* SD24B Data Alignment */
5410 #define SD24CAL (0x0200u) /* SD24B Calibration */
5411 #define SD24DFS0 (0x0400u) /* SD24B Digital Filter Bit: 0 */
5412 #define SD24DFS1 (0x0800u) /* SD24B Digital Filter Bit: 1 */
5413 #define SD24DI (0x1000u) /* SD24B Digital Bitstream Input */
5414 #define SD24MC0 (0x2000u) /* SD24B Manchaster Encoding Bit: 0 */
5415 #define SD24MC1 (0x4000u) /* SD24B Manchaster Encoding Bit: 1 */
5416 
5417 #define SD24DF0_L (0x0010u) /* SD24B Data Format Bit: 0 */
5418 #define SD24DF1_L (0x0020u) /* SD24B Data Format Bit: 1 */
5419 #define SD24ALGN_L (0x0040u) /* SD24B Data Alignment */
5420 
5421 #define SD24CAL_H (0x0002u) /* SD24B Calibration */
5422 #define SD24DFS0_H (0x0004u) /* SD24B Digital Filter Bit: 0 */
5423 #define SD24DFS1_H (0x0008u) /* SD24B Digital Filter Bit: 1 */
5424 #define SD24DI_H (0x0010u) /* SD24B Digital Bitstream Input */
5425 #define SD24MC0_H (0x0020u) /* SD24B Manchaster Encoding Bit: 0 */
5426 #define SD24MC1_H (0x0040u) /* SD24B Manchaster Encoding Bit: 1 */
5427 
5428 #define SD24DF_0 (0x0000u) /* SD24B Data Format: Offset Binary */
5429 #define SD24DF_1 (0x0010u) /* SD24B Data Format: 2's complement */
5430 
5431 #define SD24DFS_0 (0x0000u) /* SD24B Digital Filter 0 */
5432 #define SD24DFS_1 (0x0400u) /* SD24B Digital Filter 1 */
5433 #define SD24DFS_2 (0x0800u) /* SD24B Digital Filter 2 */
5434 #define SD24DFS_3 (0x0C00u) /* SD24B Digital Filter 3 */
5435 
5436 #define SD24MC_0 (0x0000u) /* SD24B Manchaster Encoding 0 */
5437 #define SD24MC_1 (0x2000u) /* SD24B Manchaster Encoding 1 */
5438 #define SD24MC_2 (0x4000u) /* SD24B Manchaster Encoding 2 */
5439 #define SD24MC_3 (0x6000u) /* SD24B Manchaster Encoding 3 */
5440 
5441 /* SD24BINCTLx */
5442 #define SD24GAIN0 (0x0008u) /* SD24B Input Pre-Amplifier Gain Select 0 */
5443 #define SD24GAIN1 (0x0010u) /* SD24B Input Pre-Amplifier Gain Select 1 */
5444 #define SD24GAIN2 (0x0020u) /* SD24B Input Pre-Amplifier Gain Select 2 */
5445 #define SD24INTDLY0 (0x0040u) /* SD24B Interrupt Delay after 1.Conversion 0 */
5446 #define SD24INTDLY1 (0x0080u) /* SD24B Interrupt Delay after 1.Conversion 1 */
5447 
5448 #define SD24GAIN0_L (0x0008u) /* SD24B Input Pre-Amplifier Gain Select 0 */
5449 #define SD24GAIN1_L (0x0010u) /* SD24B Input Pre-Amplifier Gain Select 1 */
5450 #define SD24GAIN2_L (0x0020u) /* SD24B Input Pre-Amplifier Gain Select 2 */
5451 #define SD24INTDLY0_L (0x0040u) /* SD24B Interrupt Delay after 1.Conversion 0 */
5452 #define SD24INTDLY1_L (0x0080u) /* SD24B Interrupt Delay after 1.Conversion 1 */
5453 
5454 #define SD24GAIN_1 (0x0000u) /* SD24B Input Pre-Amplifier Gain Select *1 */
5455 #define SD24GAIN_2 (0x0008u) /* SD24B Input Pre-Amplifier Gain Select *2 */
5456 #define SD24GAIN_4 (0x0010u) /* SD24B Input Pre-Amplifier Gain Select *4 */
5457 #define SD24GAIN_8 (0x0018u) /* SD24B Input Pre-Amplifier Gain Select *8 */
5458 #define SD24GAIN_16 (0x0020u) /* SD24B Input Pre-Amplifier Gain Select *16 */
5459 #define SD24GAIN_32 (0x0028u) /* SD24B Input Pre-Amplifier Gain Select *32 */
5460 #define SD24GAIN_64 (0x0030u) /* SD24B Input Pre-Amplifier Gain Select *64 */
5461 #define SD24GAIN_128 (0x0038u) /* SD24B Input Pre-Amplifier Gain Select *128 */
5462 
5463 #define SD24INTDLY_0 (0x0000u) /* SD24B Interrupt Delay: Int. after 4.Conversion */
5464 #define SD24INTDLY_1 (0x0040u) /* SD24B Interrupt Delay: Int. after 3.Conversion */
5465 #define SD24INTDLY_2 (0x0080u) /* SD24B Interrupt Delay: Int. after 2.Conversion */
5466 #define SD24INTDLY_3 (0x00C0u) /* SD24B Interrupt Delay: Int. after 1.Conversion */
5467 
5468 /* SD24BOSRx */
5469 #define OSR0 (0x0001u) /* SD24B Oversampling Rate Bit: 0 */
5470 #define OSR1 (0x0002u) /* SD24B Oversampling Rate Bit: 1 */
5471 #define OSR2 (0x0004u) /* SD24B Oversampling Rate Bit: 2 */
5472 #define OSR3 (0x0008u) /* SD24B Oversampling Rate Bit: 3 */
5473 #define OSR4 (0x0010u) /* SD24B Oversampling Rate Bit: 4 */
5474 #define OSR5 (0x0020u) /* SD24B Oversampling Rate Bit: 5 */
5475 #define OSR6 (0x0040u) /* SD24B Oversampling Rate Bit: 6 */
5476 #define OSR7 (0x0080u) /* SD24B Oversampling Rate Bit: 7 */
5477 #define OSR8 (0x0100u) /* SD24B Oversampling Rate Bit: 8 */
5478 #define OSR9 (0x0200u) /* SD24B Oversampling Rate Bit: 9 */
5479 #define OSR10 (0x0400u) /* SD24B Oversampling Rate Bit: 10 */
5480 
5481 #define OSR0_L (0x0001u) /* SD24B Oversampling Rate Bit: 0 */
5482 #define OSR1_L (0x0002u) /* SD24B Oversampling Rate Bit: 1 */
5483 #define OSR2_L (0x0004u) /* SD24B Oversampling Rate Bit: 2 */
5484 #define OSR3_L (0x0008u) /* SD24B Oversampling Rate Bit: 3 */
5485 #define OSR4_L (0x0010u) /* SD24B Oversampling Rate Bit: 4 */
5486 #define OSR5_L (0x0020u) /* SD24B Oversampling Rate Bit: 5 */
5487 #define OSR6_L (0x0040u) /* SD24B Oversampling Rate Bit: 6 */
5488 #define OSR7_L (0x0080u) /* SD24B Oversampling Rate Bit: 7 */
5489 
5490 #define OSR8_H (0x0001u) /* SD24B Oversampling Rate Bit: 8 */
5491 #define OSR9_H (0x0002u) /* SD24B Oversampling Rate Bit: 9 */
5492 #define OSR10_H (0x0004u) /* SD24B Oversampling Rate Bit: 10 */
5493 
5494 /* SD24BTRGOSR */
5495 
5496 #define OSR__32 (32-1) /* SD24B Oversampling Rate: 32 */
5497 #define OSR__64 (64-1) /* SD24B Oversampling Rate: 64 */
5498 #define OSR__128 (128-1) /* SD24B Oversampling Rate: 128 */
5499 #define OSR__256 (256-1) /* SD24B Oversampling Rate: 256 */
5500 #define OSR__512 (512-1) /* SD24B Oversampling Rate: 512 */
5501 #define OSR__1024 (1024-1) /* SD24B Oversampling Rate: 1024 */
5502 
5503 
5504 #endif
5505 /************************************************************
5506 * SFR - Special Function Register Module
5507 ************************************************************/
5508 #ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */
5509 
5510 #define OFS_SFRIE1 (0x0000u) /* Interrupt Enable 1 */
5511 #define OFS_SFRIE1_L OFS_SFRIE1
5512 #define OFS_SFRIE1_H OFS_SFRIE1+1
5513 
5514 /* SFRIE1 Control Bits */
5515 #define WDTIE (0x0001u) /* WDT Interrupt Enable */
5516 #define OFIE (0x0002u) /* Osc Fault Enable */
5517 //#define Reserved (0x0004u)
5518 #define VMAIE (0x0008u) /* Vacant Memory Interrupt Enable */
5519 #define NMIIE (0x0010u) /* NMI Interrupt Enable */
5520 #ifndef ACCVIE
5521 #define ACCVIE (0x0020u) /* Flash Access Violation Interrupt Enable */
5522 #endif
5523 #define JMBINIE (0x0040u) /* JTAG Mail Box input Interrupt Enable */
5524 #define JMBOUTIE (0x0080u) /* JTAG Mail Box output Interrupt Enable */
5525 
5526 #define WDTIE_L (0x0001u) /* WDT Interrupt Enable */
5527 #define OFIE_L (0x0002u) /* Osc Fault Enable */
5528 //#define Reserved (0x0004u)
5529 #define VMAIE_L (0x0008u) /* Vacant Memory Interrupt Enable */
5530 #define NMIIE_L (0x0010u) /* NMI Interrupt Enable */
5531 #ifndef ACCVIE
5532 #define ACCVIE_L (0x0020u) /* Flash Access Violation Interrupt Enable */
5533 #endif
5534 #define JMBINIE_L (0x0040u) /* JTAG Mail Box input Interrupt Enable */
5535 #define JMBOUTIE_L (0x0080u) /* JTAG Mail Box output Interrupt Enable */
5536 
5537 #define OFS_SFRIFG1 (0x0002u) /* Interrupt Flag 1 */
5538 #define OFS_SFRIFG1_L OFS_SFRIFG1
5539 #define OFS_SFRIFG1_H OFS_SFRIFG1+1
5540 /* SFRIFG1 Control Bits */
5541 #define WDTIFG (0x0001u) /* WDT Interrupt Flag */
5542 #define OFIFG (0x0002u) /* Osc Fault Flag */
5543 //#define Reserved (0x0004u)
5544 #define VMAIFG (0x0008u) /* Vacant Memory Interrupt Flag */
5545 #define NMIIFG (0x0010u) /* NMI Interrupt Flag */
5546 //#define Reserved (0x0020u)
5547 #define JMBINIFG (0x0040u) /* JTAG Mail Box input Interrupt Flag */
5548 #define JMBOUTIFG (0x0080u) /* JTAG Mail Box output Interrupt Flag */
5549 
5550 #define WDTIFG_L (0x0001u) /* WDT Interrupt Flag */
5551 #define OFIFG_L (0x0002u) /* Osc Fault Flag */
5552 //#define Reserved (0x0004u)
5553 #define VMAIFG_L (0x0008u) /* Vacant Memory Interrupt Flag */
5554 #define NMIIFG_L (0x0010u) /* NMI Interrupt Flag */
5555 //#define Reserved (0x0020u)
5556 #define JMBINIFG_L (0x0040u) /* JTAG Mail Box input Interrupt Flag */
5557 #define JMBOUTIFG_L (0x0080u) /* JTAG Mail Box output Interrupt Flag */
5558 
5559 #define OFS_SFRRPCR (0x0004u) /* RESET Pin Control Register */
5560 #define OFS_SFRRPCR_L OFS_SFRRPCR
5561 #define OFS_SFRRPCR_H OFS_SFRRPCR+1
5562 /* SFRRPCR Control Bits */
5563 #define SYSNMI (0x0001u) /* NMI select */
5564 #define SYSNMIIES (0x0002u) /* NMI edge select */
5565 #define SYSRSTUP (0x0004u) /* RESET Pin pull down/up select */
5566 #define SYSRSTRE (0x0008u) /* RESET Pin Resistor enable */
5567 
5568 #define SYSNMI_L (0x0001u) /* NMI select */
5569 #define SYSNMIIES_L (0x0002u) /* NMI edge select */
5570 #define SYSRSTUP_L (0x0004u) /* RESET Pin pull down/up select */
5571 #define SYSRSTRE_L (0x0008u) /* RESET Pin Resistor enable */
5572 
5573 #endif
5574 /************************************************************
5575 * SYS - System Module
5576 ************************************************************/
5577 #ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */
5578 
5579 #define OFS_SYSCTL (0x0000u) /* System control */
5580 #define OFS_SYSCTL_L OFS_SYSCTL
5581 #define OFS_SYSCTL_H OFS_SYSCTL+1
5582 #define OFS_SYSBSLC (0x0002u) /* Boot strap configuration area */
5583 #define OFS_SYSBSLC_L OFS_SYSBSLC
5584 #define OFS_SYSBSLC_H OFS_SYSBSLC+1
5585 #define OFS_SYSJMBC (0x0006u) /* JTAG mailbox control */
5586 #define OFS_SYSJMBC_L OFS_SYSJMBC
5587 #define OFS_SYSJMBC_H OFS_SYSJMBC+1
5588 #define OFS_SYSJMBI0 (0x0008u) /* JTAG mailbox input 0 */
5589 #define OFS_SYSJMBI0_L OFS_SYSJMBI0
5590 #define OFS_SYSJMBI0_H OFS_SYSJMBI0+1
5591 #define OFS_SYSJMBI1 (0x000Au) /* JTAG mailbox input 1 */
5592 #define OFS_SYSJMBI1_L OFS_SYSJMBI1
5593 #define OFS_SYSJMBI1_H OFS_SYSJMBI1+1
5594 #define OFS_SYSJMBO0 (0x000Cu) /* JTAG mailbox output 0 */
5595 #define OFS_SYSJMBO0_L OFS_SYSJMBO0
5596 #define OFS_SYSJMBO0_H OFS_SYSJMBO0+1
5597 #define OFS_SYSJMBO1 (0x000Eu) /* JTAG mailbox output 1 */
5598 #define OFS_SYSJMBO1_L OFS_SYSJMBO1
5599 #define OFS_SYSJMBO1_H OFS_SYSJMBO1+1
5600 
5601 #define OFS_SYSBERRIV (0x0018u) /* Bus Error vector generator */
5602 #define OFS_SYSBERRIV_L OFS_SYSBERRIV
5603 #define OFS_SYSBERRIV_H OFS_SYSBERRIV+1
5604 #define OFS_SYSUNIV (0x001Au) /* User NMI vector generator */
5605 #define OFS_SYSUNIV_L OFS_SYSUNIV
5606 #define OFS_SYSUNIV_H OFS_SYSUNIV+1
5607 #define OFS_SYSSNIV (0x001Cu) /* System NMI vector generator */
5608 #define OFS_SYSSNIV_L OFS_SYSSNIV
5609 #define OFS_SYSSNIV_H OFS_SYSSNIV+1
5610 #define OFS_SYSRSTIV (0x001Eu) /* Reset vector generator */
5611 #define OFS_SYSRSTIV_L OFS_SYSRSTIV
5612 #define OFS_SYSRSTIV_H OFS_SYSRSTIV+1
5613 
5614 /* SYSCTL Control Bits */
5615 #define SYSRIVECT (0x0001u) /* SYS - RAM based interrupt vectors */
5616 //#define RESERVED (0x0002u) /* SYS - Reserved */
5617 #define SYSPMMPE (0x0004u) /* SYS - PMM access protect */
5618 //#define RESERVED (0x0008u) /* SYS - Reserved */
5619 #define SYSBSLIND (0x0010u) /* SYS - TCK/RST indication detected */
5620 #define SYSJTAGPIN (0x0020u) /* SYS - Dedicated JTAG pins enabled */
5621 //#define RESERVED (0x0040u) /* SYS - Reserved */
5622 //#define RESERVED (0x0080u) /* SYS - Reserved */
5623 //#define RESERVED (0x0100u) /* SYS - Reserved */
5624 //#define RESERVED (0x0200u) /* SYS - Reserved */
5625 //#define RESERVED (0x0400u) /* SYS - Reserved */
5626 //#define RESERVED (0x0800u) /* SYS - Reserved */
5627 //#define RESERVED (0x1000u) /* SYS - Reserved */
5628 //#define RESERVED (0x2000u) /* SYS - Reserved */
5629 //#define RESERVED (0x4000u) /* SYS - Reserved */
5630 //#define RESERVED (0x8000u) /* SYS - Reserved */
5631 
5632 /* SYSCTL Control Bits */
5633 #define SYSRIVECT_L (0x0001u) /* SYS - RAM based interrupt vectors */
5634 //#define RESERVED (0x0002u) /* SYS - Reserved */
5635 #define SYSPMMPE_L (0x0004u) /* SYS - PMM access protect */
5636 //#define RESERVED (0x0008u) /* SYS - Reserved */
5637 #define SYSBSLIND_L (0x0010u) /* SYS - TCK/RST indication detected */
5638 #define SYSJTAGPIN_L (0x0020u) /* SYS - Dedicated JTAG pins enabled */
5639 //#define RESERVED (0x0040u) /* SYS - Reserved */
5640 //#define RESERVED (0x0080u) /* SYS - Reserved */
5641 //#define RESERVED (0x0100u) /* SYS - Reserved */
5642 //#define RESERVED (0x0200u) /* SYS - Reserved */
5643 //#define RESERVED (0x0400u) /* SYS - Reserved */
5644 //#define RESERVED (0x0800u) /* SYS - Reserved */
5645 //#define RESERVED (0x1000u) /* SYS - Reserved */
5646 //#define RESERVED (0x2000u) /* SYS - Reserved */
5647 //#define RESERVED (0x4000u) /* SYS - Reserved */
5648 //#define RESERVED (0x8000u) /* SYS - Reserved */
5649 
5650 /* SYSBSLC Control Bits */
5651 #define SYSBSLSIZE0 (0x0001u) /* SYS - BSL Protection Size 0 */
5652 #define SYSBSLSIZE1 (0x0002u) /* SYS - BSL Protection Size 1 */
5653 #define SYSBSLR (0x0004u) /* SYS - RAM assigned to BSL */
5654 //#define RESERVED (0x0008u) /* SYS - Reserved */
5655 //#define RESERVED (0x0010u) /* SYS - Reserved */
5656 //#define RESERVED (0x0020u) /* SYS - Reserved */
5657 //#define RESERVED (0x0040u) /* SYS - Reserved */
5658 //#define RESERVED (0x0080u) /* SYS - Reserved */
5659 //#define RESERVED (0x0100u) /* SYS - Reserved */
5660 //#define RESERVED (0x0200u) /* SYS - Reserved */
5661 //#define RESERVED (0x0400u) /* SYS - Reserved */
5662 //#define RESERVED (0x0800u) /* SYS - Reserved */
5663 //#define RESERVED (0x1000u) /* SYS - Reserved */
5664 //#define RESERVED (0x2000u) /* SYS - Reserved */
5665 #define SYSBSLOFF (0x4000u) /* SYS - BSL Memory disabled */
5666 #define SYSBSLPE (0x8000u) /* SYS - BSL Memory protection enabled */
5667 
5668 /* SYSBSLC Control Bits */
5669 #define SYSBSLSIZE0_L (0x0001u) /* SYS - BSL Protection Size 0 */
5670 #define SYSBSLSIZE1_L (0x0002u) /* SYS - BSL Protection Size 1 */
5671 #define SYSBSLR_L (0x0004u) /* SYS - RAM assigned to BSL */
5672 //#define RESERVED (0x0008u) /* SYS - Reserved */
5673 //#define RESERVED (0x0010u) /* SYS - Reserved */
5674 //#define RESERVED (0x0020u) /* SYS - Reserved */
5675 //#define RESERVED (0x0040u) /* SYS - Reserved */
5676 //#define RESERVED (0x0080u) /* SYS - Reserved */
5677 //#define RESERVED (0x0100u) /* SYS - Reserved */
5678 //#define RESERVED (0x0200u) /* SYS - Reserved */
5679 //#define RESERVED (0x0400u) /* SYS - Reserved */
5680 //#define RESERVED (0x0800u) /* SYS - Reserved */
5681 //#define RESERVED (0x1000u) /* SYS - Reserved */
5682 //#define RESERVED (0x2000u) /* SYS - Reserved */
5683 
5684 /* SYSBSLC Control Bits */
5685 //#define RESERVED (0x0008u) /* SYS - Reserved */
5686 //#define RESERVED (0x0010u) /* SYS - Reserved */
5687 //#define RESERVED (0x0020u) /* SYS - Reserved */
5688 //#define RESERVED (0x0040u) /* SYS - Reserved */
5689 //#define RESERVED (0x0080u) /* SYS - Reserved */
5690 //#define RESERVED (0x0100u) /* SYS - Reserved */
5691 //#define RESERVED (0x0200u) /* SYS - Reserved */
5692 //#define RESERVED (0x0400u) /* SYS - Reserved */
5693 //#define RESERVED (0x0800u) /* SYS - Reserved */
5694 //#define RESERVED (0x1000u) /* SYS - Reserved */
5695 //#define RESERVED (0x2000u) /* SYS - Reserved */
5696 #define SYSBSLOFF_H (0x0040u) /* SYS - BSL Memory disabled */
5697 #define SYSBSLPE_H (0x0080u) /* SYS - BSL Memory protection enabled */
5698 
5699 /* SYSJMBC Control Bits */
5700 #define JMBIN0FG (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */
5701 #define JMBIN1FG (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */
5702 #define JMBOUT0FG (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */
5703 #define JMBOUT1FG (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */
5704 #define JMBMODE (0x0010u) /* SYS - JMB 16/32 Bit Mode */
5705 //#define RESERVED (0x0020u) /* SYS - Reserved */
5706 #define JMBCLR0OFF (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
5707 #define JMBCLR1OFF (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
5708 //#define RESERVED (0x0100u) /* SYS - Reserved */
5709 //#define RESERVED (0x0200u) /* SYS - Reserved */
5710 //#define RESERVED (0x0400u) /* SYS - Reserved */
5711 //#define RESERVED (0x0800u) /* SYS - Reserved */
5712 //#define RESERVED (0x1000u) /* SYS - Reserved */
5713 //#define RESERVED (0x2000u) /* SYS - Reserved */
5714 //#define RESERVED (0x4000u) /* SYS - Reserved */
5715 //#define RESERVED (0x8000u) /* SYS - Reserved */
5716 
5717 /* SYSJMBC Control Bits */
5718 #define JMBIN0FG_L (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */
5719 #define JMBIN1FG_L (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */
5720 #define JMBOUT0FG_L (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */
5721 #define JMBOUT1FG_L (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */
5722 #define JMBMODE_L (0x0010u) /* SYS - JMB 16/32 Bit Mode */
5723 //#define RESERVED (0x0020u) /* SYS - Reserved */
5724 #define JMBCLR0OFF_L (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
5725 #define JMBCLR1OFF_L (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
5726 //#define RESERVED (0x0100u) /* SYS - Reserved */
5727 //#define RESERVED (0x0200u) /* SYS - Reserved */
5728 //#define RESERVED (0x0400u) /* SYS - Reserved */
5729 //#define RESERVED (0x0800u) /* SYS - Reserved */
5730 //#define RESERVED (0x1000u) /* SYS - Reserved */
5731 //#define RESERVED (0x2000u) /* SYS - Reserved */
5732 //#define RESERVED (0x4000u) /* SYS - Reserved */
5733 //#define RESERVED (0x8000u) /* SYS - Reserved */
5734 
5735 #endif
5736 /************************************************************
5737 * Timerx_A7
5738 ************************************************************/
5739 #ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */
5740 
5741 #define OFS_TAxCTL (0x0000u) /* Timerx_A7 Control */
5742 #define OFS_TAxCCTL0 (0x0002u) /* Timerx_A7 Capture/Compare Control 0 */
5743 #define OFS_TAxCCTL1 (0x0004u) /* Timerx_A7 Capture/Compare Control 1 */
5744 #define OFS_TAxCCTL2 (0x0006u) /* Timerx_A7 Capture/Compare Control 2 */
5745 #define OFS_TAxCCTL3 (0x0008u) /* Timerx_A7 Capture/Compare Control 3 */
5746 #define OFS_TAxCCTL4 (0x000Au) /* Timerx_A7 Capture/Compare Control 4 */
5747 #define OFS_TAxCCTL5 (0x000Cu) /* Timerx_A7 Capture/Compare Control 5 */
5748 #define OFS_TAxCCTL6 (0x000Eu) /* Timerx_A7 Capture/Compare Control 6 */
5749 #define OFS_TAxR (0x0010u) /* Timerx_A7 */
5750 #define OFS_TAxCCR0 (0x0012u) /* Timerx_A7 Capture/Compare 0 */
5751 #define OFS_TAxCCR1 (0x0014u) /* Timerx_A7 Capture/Compare 1 */
5752 #define OFS_TAxCCR2 (0x0016u) /* Timerx_A7 Capture/Compare 2 */
5753 #define OFS_TAxCCR3 (0x0018u) /* Timerx_A7 Capture/Compare 3 */
5754 #define OFS_TAxCCR4 (0x001Au) /* Timerx_A7 Capture/Compare 4 */
5755 #define OFS_TAxCCR5 (0x001Cu) /* Timerx_A7 Capture/Compare 5 */
5756 #define OFS_TAxCCR6 (0x001Eu) /* Timerx_A7 Capture/Compare 6 */
5757 #define OFS_TAxIV (0x002Eu) /* Timerx_A7 Interrupt Vector Word */
5758 #define OFS_TAxEX0 (0x0020u) /* Timerx_A7 Expansion Register 0 */
5759 
5760 /* Bits are already defined within the Timer0_Ax */
5761 
5762 /* TAxIV Definitions */
5763 #define TAxIV_NONE (0x0000u) /* No Interrupt pending */
5764 #define TAxIV_TACCR1 (0x0002u) /* TAxCCR1_CCIFG */
5765 #define TAxIV_TACCR2 (0x0004u) /* TAxCCR2_CCIFG */
5766 #define TAxIV_TACCR3 (0x0006u) /* TAxCCR3_CCIFG */
5767 #define TAxIV_TACCR4 (0x0008u) /* TAxCCR4_CCIFG */
5768 #define TAxIV_TACCR5 (0x000Au) /* TAxCCR5_CCIFG */
5769 #define TAxIV_TACCR6 (0x000Cu) /* TAxCCR6_CCIFG */
5770 #define TAxIV_TAIFG (0x000Eu) /* TAxIFG */
5771 
5772 /* Legacy Defines */
5773 #define TAxIV_TAxCCR1 (0x0002u) /* TAxCCR1_CCIFG */
5774 #define TAxIV_TAxCCR2 (0x0004u) /* TAxCCR2_CCIFG */
5775 #define TAxIV_TAxCCR3 (0x0006u) /* TAxCCR3_CCIFG */
5776 #define TAxIV_TAxCCR4 (0x0008u) /* TAxCCR4_CCIFG */
5777 #define TAxIV_TAxCCR5 (0x000Au) /* TAxCCR5_CCIFG */
5778 #define TAxIV_TAxCCR6 (0x000Cu) /* TAxCCR6_CCIFG */
5779 #define TAxIV_TAxIFG (0x000Eu) /* TAxIFG */
5780 
5781 /* TAxCTL Control Bits */
5782 #define TASSEL1 (0x0200u) /* Timer A clock source select 1 */
5783 #define TASSEL0 (0x0100u) /* Timer A clock source select 0 */
5784 #define ID1 (0x0080u) /* Timer A clock input divider 1 */
5785 #define ID0 (0x0040u) /* Timer A clock input divider 0 */
5786 #define MC1 (0x0020u) /* Timer A mode control 1 */
5787 #define MC0 (0x0010u) /* Timer A mode control 0 */
5788 #define TACLR (0x0004u) /* Timer A counter clear */
5789 #define TAIE (0x0002u) /* Timer A counter interrupt enable */
5790 #define TAIFG (0x0001u) /* Timer A counter interrupt flag */
5791 
5792 #define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
5793 #define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
5794 #define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */
5795 #define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
5796 #define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
5797 #define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
5798 #define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
5799 #define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
5800 #define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
5801 #define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
5802 #define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
5803 #define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
5804 #define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */
5805 #define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
5806 #define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */
5807 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
5808 #define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */
5809 #define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */
5810 #define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */
5811 #define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */
5812 #define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */
5813 #define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */
5814 #define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */
5815 #define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
5816 #define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */
5817 
5818 /* TAxCCTLx Control Bits */
5819 #define CM1 (0x8000u) /* Capture mode 1 */
5820 #define CM0 (0x4000u) /* Capture mode 0 */
5821 #define CCIS1 (0x2000u) /* Capture input select 1 */
5822 #define CCIS0 (0x1000u) /* Capture input select 0 */
5823 #define SCS (0x0800u) /* Capture sychronize */
5824 #define SCCI (0x0400u) /* Latched capture signal (read) */
5825 #define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */
5826 #define OUTMOD2 (0x0080u) /* Output mode 2 */
5827 #define OUTMOD1 (0x0040u) /* Output mode 1 */
5828 #define OUTMOD0 (0x0020u) /* Output mode 0 */
5829 #define CCIE (0x0010u) /* Capture/compare interrupt enable */
5830 #define CCI (0x0008u) /* Capture input signal (read) */
5831 #define OUT (0x0004u) /* PWM Output signal if output mode 0 */
5832 #define COV (0x0002u) /* Capture/compare overflow flag */
5833 #define CCIFG (0x0001u) /* Capture/compare interrupt flag */
5834 
5835 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
5836 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
5837 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
5838 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
5839 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
5840 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
5841 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
5842 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
5843 #define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
5844 #define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
5845 #define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
5846 #define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
5847 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
5848 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
5849 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
5850 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
5851 
5852 /* TAxEX0 Control Bits */
5853 #define TAIDEX0 (0x0001u) /* Timer A Input divider expansion Bit: 0 */
5854 #define TAIDEX1 (0x0002u) /* Timer A Input divider expansion Bit: 1 */
5855 #define TAIDEX2 (0x0004u) /* Timer A Input divider expansion Bit: 2 */
5856 
5857 #define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */
5858 #define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */
5859 #define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */
5860 #define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */
5861 #define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */
5862 #define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */
5863 #define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */
5864 #define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */
5865 
5866 #endif
5867 /************************************************************
5868 * Timerx_B7
5869 ************************************************************/
5870 #ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */
5871 
5872 #define OFS_TBxCTL (0x0000u) /* Timerx_B7 Control */
5873 #define OFS_TBxCCTL0 (0x0002u) /* Timerx_B7 Capture/Compare Control 0 */
5874 #define OFS_TBxCCTL1 (0x0004u) /* Timerx_B7 Capture/Compare Control 1 */
5875 #define OFS_TBxCCTL2 (0x0006u) /* Timerx_B7 Capture/Compare Control 2 */
5876 #define OFS_TBxCCTL3 (0x0008u) /* Timerx_B7 Capture/Compare Control 3 */
5877 #define OFS_TBxCCTL4 (0x000Au) /* Timerx_B7 Capture/Compare Control 4 */
5878 #define OFS_TBxCCTL5 (0x000Cu) /* Timerx_B7 Capture/Compare Control 5 */
5879 #define OFS_TBxCCTL6 (0x000Eu) /* Timerx_B7 Capture/Compare Control 6 */
5880 #define OFS_TBxR (0x0010u) /* Timerx_B7 */
5881 #define OFS_TBxCCR0 (0x0012u) /* Timerx_B7 Capture/Compare 0 */
5882 #define OFS_TBxCCR1 (0x0014u) /* Timerx_B7 Capture/Compare 1 */
5883 #define OFS_TBxCCR2 (0x0016u) /* Timerx_B7 Capture/Compare 2 */
5884 #define OFS_TBxCCR3 (0x0018u) /* Timerx_B7 Capture/Compare 3 */
5885 #define OFS_TBxCCR4 (0x001Au) /* Timerx_B7 Capture/Compare 4 */
5886 #define OFS_TBxCCR5 (0x001Cu) /* Timerx_B7 Capture/Compare 5 */
5887 #define OFS_TBxCCR6 (0x001Eu) /* Timerx_B7 Capture/Compare 6 */
5888 #define OFS_TBxIV (0x002Eu) /* Timerx_B7 Interrupt Vector Word */
5889 #define OFS_TBxEX0 (0x0020u) /* Timerx_B7 Expansion Register 0 */
5890 
5891 /* Bits are already defined within the Timer0_Ax */
5892 
5893 /* TBxIV Definitions */
5894 #define TBxIV_NONE (0x0000u) /* No Interrupt pending */
5895 #define TBxIV_TBCCR1 (0x0002u) /* TBxCCR1_CCIFG */
5896 #define TBxIV_TBCCR2 (0x0004u) /* TBxCCR2_CCIFG */
5897 #define TBxIV_TBCCR3 (0x0006u) /* TBxCCR3_CCIFG */
5898 #define TBxIV_TBCCR4 (0x0008u) /* TBxCCR4_CCIFG */
5899 #define TBxIV_TBCCR5 (0x000Au) /* TBxCCR5_CCIFG */
5900 #define TBxIV_TBCCR6 (0x000Cu) /* TBxCCR6_CCIFG */
5901 #define TBxIV_TBIFG (0x000Eu) /* TBxIFG */
5902 
5903 /* Legacy Defines */
5904 #define TBxIV_TBxCCR1 (0x0002u) /* TBxCCR1_CCIFG */
5905 #define TBxIV_TBxCCR2 (0x0004u) /* TBxCCR2_CCIFG */
5906 #define TBxIV_TBxCCR3 (0x0006u) /* TBxCCR3_CCIFG */
5907 #define TBxIV_TBxCCR4 (0x0008u) /* TBxCCR4_CCIFG */
5908 #define TBxIV_TBxCCR5 (0x000Au) /* TBxCCR5_CCIFG */
5909 #define TBxIV_TBxCCR6 (0x000Cu) /* TBxCCR6_CCIFG */
5910 #define TBxIV_TBxIFG (0x000Eu) /* TBxIFG */
5911 
5912 /* TBxCTL Control Bits */
5913 #define TBCLGRP1 (0x4000u) /* Timer_B7 Compare latch load group 1 */
5914 #define TBCLGRP0 (0x2000u) /* Timer_B7 Compare latch load group 0 */
5915 #define CNTL1 (0x1000u) /* Counter lenght 1 */
5916 #define CNTL0 (0x0800u) /* Counter lenght 0 */
5917 #define TBSSEL1 (0x0200u) /* Clock source 1 */
5918 #define TBSSEL0 (0x0100u) /* Clock source 0 */
5919 #define TBCLR (0x0004u) /* Timer_B7 counter clear */
5920 #define TBIE (0x0002u) /* Timer_B7 interrupt enable */
5921 #define TBIFG (0x0001u) /* Timer_B7 interrupt flag */
5922 
5923 #define SHR1 (0x4000u) /* Timer_B7 Compare latch load group 1 */
5924 #define SHR0 (0x2000u) /* Timer_B7 Compare latch load group 0 */
5925 
5926 #define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */
5927 #define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
5928 #define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
5929 #define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
5930 #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
5931 #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
5932 #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
5933 #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
5934 #define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */
5935 #define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
5936 #define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/
5937 #define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */
5938 #define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */
5939 #define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
5940 #define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/
5941 #define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */
5942 #define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */
5943 #define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */
5944 #define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */
5945 #define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */
5946 #define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */
5947 #define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */
5948 #define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */
5949 #define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */
5950 #define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */
5951 
5952 /* Additional Timer B Control Register bits are defined in Timer A */
5953 /* TBxCCTLx Control Bits */
5954 #define CLLD1 (0x0400u) /* Compare latch load source 1 */
5955 #define CLLD0 (0x0200u) /* Compare latch load source 0 */
5956 
5957 #define SLSHR1 (0x0400u) /* Compare latch load source 1 */
5958 #define SLSHR0 (0x0200u) /* Compare latch load source 0 */
5959 
5960 #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
5961 #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
5962 #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
5963 #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
5964 
5965 #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
5966 #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
5967 #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
5968 #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
5969 
5970 /* TBxEX0 Control Bits */
5971 #define TBIDEX0 (0x0001u) /* Timer_B7 Input divider expansion Bit: 0 */
5972 #define TBIDEX1 (0x0002u) /* Timer_B7 Input divider expansion Bit: 1 */
5973 #define TBIDEX2 (0x0004u) /* Timer_B7 Input divider expansion Bit: 2 */
5974 
5975 #define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */
5976 #define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */
5977 #define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */
5978 #define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */
5979 #define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */
5980 #define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */
5981 #define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */
5982 #define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */
5983 #define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */
5984 #define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */
5985 #define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */
5986 #define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */
5987 #define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */
5988 #define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */
5989 #define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */
5990 #define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */
5991 
5992 
5993 #define ID1 (0x0080u) /* Timer B clock input divider 1 */
5994 #define ID0 (0x0040u) /* Timer B clock input divider 0 */
5995 #define MC1 (0x0020u) /* Timer B mode control 1 */
5996 #define MC0 (0x0010u) /* Timer B mode control 0 */
5997 #define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */
5998 #define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */
5999 #define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */
6000 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
6001 #define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */
6002 #define CM1 (0x8000u) /* Capture mode 1 */
6003 #define CM0 (0x4000u) /* Capture mode 0 */
6004 #define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */
6005 #define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */
6006 #define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */
6007 #define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */
6008 #define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */
6009 #define CCIE (0x0010u) /* Capture/compare interrupt enable */
6010 #define CCIFG (0x0001u) /* Capture/compare interrupt flag */
6011 #define CCIS_0 (0*0x1000u)
6012 #define CCIS_1 (1*0x1000u)
6013 #define CCIS_2 (2*0x1000u)
6014 #define CCIS_3 (3*0x1000u)
6015 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
6016 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
6017 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
6018 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
6019 #define OUT (0x0004u) /* PWM Output signal if output mode 0 */
6020 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
6021 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
6022 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
6023 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
6024 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
6025 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
6026 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
6027 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
6028 #define SCCI (0x0400u) /* Latched capture signal (read) */
6029 #define SCS (0x0800u) /* Capture sychronize */
6030 #define CCI (0x0008u) /* Capture input signal (read) */
6031 #define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */
6032 #define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */
6033 #define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */
6034 #define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */
6035 #define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */
6036 #define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */
6037 #define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */
6038 #define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */
6039 
6040 #endif
6041 /************************************************************
6042 * Timerx_D7
6043 ************************************************************/
6044 #ifdef __MSP430_HAS_TxD7__ /* Definition to show that Module is available */
6045 
6046 #define OFS_TDxCTL0 (0x0000u) /* Timerx_D7 Control 0 */
6047 #define OFS_TDxCTL1 (0x0002u) /* Timerx_D7 Control 1 */
6048 #define OFS_TDxCTL2 (0x0004u) /* Timerx_D7 Control 2 */
6049 #define OFS_TDxR (0x0006u) /* Timerx_D7 Counter */
6050 #define OFS_TDxCCTL0 (0x0008u) /* Timerx_D7 Capture/Compare Control 0 */
6051 #define OFS_TDxCCR0 (0x000Au) /* Timerx_D7 Capture/Compare 0 */
6052 #define OFS_TDxCL0 (0x000Cu) /* Timerx_D7 Capture/Compare Latch 0 */
6053 #define OFS_TDxCCTL1 (0x000Eu) /* Timerx_D7 Capture/Compare Control 1 */
6054 #define OFS_TDxCCR1 (0x0010u) /* Timerx_D7 Capture/Compare 1 */
6055 #define OFS_TDxCL1 (0x0012u) /* Timerx_D7 Capture/Compare Latch 1 */
6056 #define OFS_TDxCCTL2 (0x0014u) /* Timerx_D7 Capture/Compare Control 2 */
6057 #define OFS_TDxCCR2 (0x0016u) /* Timerx_D7 Capture/Compare 2 */
6058 #define OFS_TDxCL2 (0x0018u) /* Timerx_D7 Capture/Compare Latch 2 */
6059 #define OFS_TDxCCTL3 (0x001Au) /* Timerx_D7 Capture/Compare Control 3 */
6060 #define OFS_TDxCCR3 (0x001Cu) /* Timerx_D7 Capture/Compare 3 */
6061 #define OFS_TDxCL3 (0x001Eu) /* Timerx_D7 Capture/Compare Latch 3 */
6062 #define OFS_TDxCCTL4 (0x0020u) /* Timerx_D7 Capture/Compare Control 4 */
6063 #define OFS_TDxCCR4 (0x0022u) /* Timerx_D7 Capture/Compare 4 */
6064 #define OFS_TDxCL4 (0x0024u) /* Timerx_D7 Capture/Compare Latch 4 */
6065 #define OFS_TDxCCTL5 (0x0026u) /* Timerx_D7 Capture/Compare Control 5 */
6066 #define OFS_TDxCCR5 (0x0028u) /* Timerx_D7 Capture/Compare 5 */
6067 #define OFS_TDxCL5 (0x002Au) /* Timerx_D7 Capture/Compare Latch 5 */
6068 #define OFS_TDxCCTL6 (0x002Cu) /* Timerx_D7 Capture/Compare Control 6 */
6069 #define OFS_TDxCCR6 (0x002Eu) /* Timerx_D7 Capture/Compare 6 */
6070 #define OFS_TDxCL6 (0x0030u) /* Timerx_D7 Capture/Compare Latch 6 */
6071 #define OFS_TDxHCTL0 (0x0038u) /* Timerx_D7 High-resolution Control Register 0 */
6072 #define OFS_TDxHCTL1 (0x003Au) /* Timerx_D7 High-resolution Control Register 1 */
6073 #define OFS_TDxHINT (0x003Cu) /* Timerx_D7 High-resolution Interrupt Register */
6074 #define OFS_TDxIV (0x003Eu) /* Timerx_D7 Interrupt Vector Word */
6075 
6076 /* Bits are already defined within the Timer0_Dx */
6077 
6078 /* TDxIV Definitions */
6079 #define TDxIV_NONE (0x0000u) /* No Interrupt pending */
6080 #define TDxIV_TDCCR1 (0x0002u) /* TDxCCR1_CCIFG */
6081 #define TDxIV_TDCCR2 (0x0004u) /* TDxCCR2_CCIFG */
6082 #define TDxIV_TDCCR3 (0x0006u) /* TDxCCR3_CCIFG */
6083 #define TDxIV_TDCCR4 (0x0008u) /* TDxCCR4_CCIFG */
6084 #define TDxIV_TDCCR5 (0x000Au) /* TDxCCR5_CCIFG */
6085 #define TDxIV_TDCCR6 (0x000Cu) /* TDxCCR6_CCIFG */
6086 #define TDxIV_RES_14 (0x000Eu) /* Reserverd */
6087 #define TDxIV_TDIFG (0x0010u) /* TDxIFG */
6088 #define TDxIV_TDHFLIFG (0x0012u) /* TDHFLIFG Clock fail low */
6089 #define TDxIV_TDHFHIFG (0x0014u) /* TDHFLIFG Clock fail high */
6090 #define TDxIV_TDHLKIFG (0x0016u) /* TDHLKIE Clock lock*/
6091 #define TDxIV_TDHUNLKIFG (0x0018u) /* TDHUNLKIE Clock unlock */
6092 
6093 /* Legacy Defines */
6094 #define TDxIV_TDxCCR1 (0x0002u) /* TDxCCR1_CCIFG */
6095 #define TDxIV_TDxCCR2 (0x0004u) /* TDxCCR2_CCIFG */
6096 #define TDxIV_TDxCCR3 (0x0006u) /* TDxCCR3_CCIFG */
6097 #define TDxIV_TDxCCR4 (0x0008u) /* TDxCCR4_CCIFG */
6098 #define TDxIV_TDxCCR5 (0x000Au) /* TDxCCR5_CCIFG */
6099 #define TDxIV_TDxCCR6 (0x000Cu) /* TDxCCR6_CCIFG */
6100 #define TDxIV_TDxIFG (0x0010u) /* TDxIFG */
6101 
6102 /* TDxCTL0 Control Bits */
6103 #define TDCLGRP1 (0x4000u) /* Timer_D7 Compare latch load group 1 */
6104 #define TDCLGRP0 (0x2000u) /* Timer_D7 Compare latch load group 0 */
6105 #define CNTL1 (0x1000u) /* Counter lenght 1 */
6106 #define CNTL0 (0x0800u) /* Counter lenght 0 */
6107 #define TDSSEL1 (0x0200u) /* Clock source 1 */
6108 #define TDSSEL0 (0x0100u) /* Clock source 0 */
6109 #define TDCLR (0x0004u) /* Timer_D7 counter clear */
6110 #define TDIE (0x0002u) /* Timer_D7 interrupt enable */
6111 #define TDIFG (0x0001u) /* Timer_D7 interrupt flag */
6112 
6113 #define SHR1 (0x4000u) /* Timer_D7 Compare latch load group 1 */
6114 #define SHR0 (0x2000u) /* Timer_D7 Compare latch load group 0 */
6115 
6116 #define TDSSEL_0 (0*0x0100u) /* Clock Source: TDCLK */
6117 #define TDSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
6118 #define TDSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
6119 #define TDSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
6120 #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
6121 #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
6122 #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
6123 #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
6124 #define SHR_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */
6125 #define SHR_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
6126 #define SHR_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/
6127 #define SHR_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */
6128 #define TDCLGRP_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */
6129 #define TDCLGRP_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
6130 #define TDCLGRP_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/
6131 #define TDCLGRP_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */
6132 #define TDSSEL__TACLK (0*0x0100u) /* Timer_D7 clock source select: 0 - TACLK */
6133 #define TDSSEL__ACLK (1*0x0100u) /* Timer_D7 clock source select: 1 - ACLK */
6134 #define TDSSEL__SMCLK (2*0x0100u) /* Timer_D7 clock source select: 2 - SMCLK */
6135 #define TDSSEL__INCLK (3*0x0100u) /* Timer_D7 clock source select: 3 - INCLK */
6136 #define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */
6137 #define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */
6138 #define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */
6139 #define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */
6140 
6141 /* Additional Timer B Control Register bits are defined in Timer A */
6142 
6143 /* TDxCTL1 Control Bits */
6144 #define TDCLKM0 (0x0001u) /* Timer_D7 Clocking Mode Bit: 0 */
6145 #define TDCLKM1 (0x0002u) /* Timer_D7 Clocking Mode Bit: 1 */
6146 #define TD2CMB (0x0010u) /* Timer_D7 TD0CCR Combination in TD2 */
6147 #define TD4CMB (0x0020u) /* Timer_D7 TD0CCR Combination in TD4 */
6148 #define TD6CMB (0x0040u) /* Timer_D7 TD0CCR Combination in TD6 */
6149 #define TDIDEX0 (0x0100u) /* Timer_D7 Input divider expansion Bit: 0 */
6150 #define TDIDEX1 (0x0200u) /* Timer_D7 Input divider expansion Bit: 1 */
6151 #define TDIDEX2 (0x0400u) /* Timer_D7 Input divider expansion Bit: 2 */
6152 
6153 #define TDCLKM_0 (0x0000u) /* Timer_D7 Clocking Mode: External */
6154 #define TDCLKM_1 (0x0001u) /* Timer_D7 Clocking Mode: High-Res. local clock */
6155 #define TDCLKM_2 (0x0002u) /* Timer_D7 Clocking Mode: Aux Clock */
6156 #define TDCLKM__EXT (0x0000u) /* Timer_D7 Clocking Mode: External */
6157 #define TDCLKM__HIGHRES (0x0001u) /* Timer_D7 Clocking Mode: High-Res. local clock */
6158 #define TDCLKM__AUX (0x0002u) /* Timer_D7 Clocking Mode: Aux Clock */
6159 
6160 #define TDIDEX_0 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */
6161 #define TDIDEX_1 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */
6162 #define TDIDEX_2 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */
6163 #define TDIDEX_3 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */
6164 #define TDIDEX_4 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */
6165 #define TDIDEX_5 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */
6166 #define TDIDEX_6 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */
6167 #define TDIDEX_7 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */
6168 #define TDIDEX__1 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */
6169 #define TDIDEX__2 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */
6170 #define TDIDEX__3 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */
6171 #define TDIDEX__4 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */
6172 #define TDIDEX__5 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */
6173 #define TDIDEX__6 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */
6174 #define TDIDEX__7 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */
6175 #define TDIDEX__8 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */
6176 
6177 /* TDxCTL2 Control Bits */
6178 #define TDCAPM0 (0x0001u) /* Timer_D7 Capture Mode of Channel 0 */
6179 #define TDCAPM1 (0x0002u) /* Timer_D7 Capture Mode of Channel 1 */
6180 #define TDCAPM2 (0x0004u) /* Timer_D7 Capture Mode of Channel 2 */
6181 #define TDCAPM3 (0x0008u) /* Timer_D7 Capture Mode of Channel 3 */
6182 #define TDCAPM4 (0x0010u) /* Timer_D7 Capture Mode of Channel 4 */
6183 #define TDCAPM5 (0x0020u) /* Timer_D7 Capture Mode of Channel 5 */
6184 #define TDCAPM6 (0x0040u) /* Timer_D7 Capture Mode of Channel 6 */
6185 
6186 /* TDxCCTLx Control Bits */
6187 #define CLLD1 (0x0400u) /* Compare latch load source 1 */
6188 #define CLLD0 (0x0200u) /* Compare latch load source 0 */
6189 
6190 #define SLSHR1 (0x0400u) /* Compare latch load source 1 */
6191 #define SLSHR0 (0x0200u) /* Compare latch load source 0 */
6192 
6193 #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
6194 #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */
6195 #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
6196 #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */
6197 
6198 #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
6199 #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */
6200 #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
6201 #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */
6202 
6203 /* TDxHCTL0 Control Bits */
6204 #define TDHEN (0x0001u) /* Timer_D7 High-Resolution Enable */
6205 #define TDHREGEN (0x0002u) /* Timer_D7 High-Resolution Regulatied Mode */
6206 #define TDHEAEN (0x0004u) /* Timer_D7 High-Resolution clock error accum. enable */
6207 #define TDHRON (0x0008u) /* Timer_D7 High-Resolution Generator forced on*/
6208 #define TDHM0 (0x0010u) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 0 */
6209 #define TDHM1 (0x0020u) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 1 */
6210 #define TDHD0 (0x0040u) /* Timer_D7 High-Resolution clock divider Bit: 0 */
6211 #define TDHD1 (0x0080u) /* Timer_D7 High-Resolution clock divider Bit: 1 */
6212 #define TDHFW (0x0100u) /* Timer_D7 High-resolution generator fast wakeup enable */
6213 
6214 #define TDHCALEN TDHREGEN /* Timer_D7 Lagacy Definition */
6215 
6216 #define TDHM_0 (0x0000u) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */
6217 #define TDHM_1 (0x0010u) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */
6218 #define TDHM__8 (0x0000u) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */
6219 #define TDHM__16 (0x0010u) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */
6220 #define TDHD_0 (0x0000u) /* Timer_D7 High-Resolution clock divider: /1 */
6221 #define TDHD_1 (0x0040u) /* Timer_D7 High-Resolution clock divider: /2 */
6222 #define TDHD_2 (0x0080u) /* Timer_D7 High-Resolution clock divider: /4 */
6223 #define TDHD_3 (0x00C0u) /* Timer_D7 High-Resolution clock divider: /8 */
6224 #define TDHD__1 (0x0000u) /* Timer_D7 High-Resolution clock divider: /1 */
6225 #define TDHD__2 (0x0040u) /* Timer_D7 High-Resolution clock divider: /2 */
6226 #define TDHD__4 (0x0080u) /* Timer_D7 High-Resolution clock divider: /4 */
6227 #define TDHD__8 (0x00C0u) /* Timer_D7 High-Resolution clock divider: /8 */
6228 
6229 /* TDxHCTL1 Control Bits */
6230 #define TDHCLKTRIM0 (0x0002u) /* Timer_D7 High-Resolution Clock Trim Bit: 0 */
6231 #define TDHCLKTRIM1 (0x0004u) /* Timer_D7 High-Resolution Clock Trim Bit: 1 */
6232 #define TDHCLKTRIM2 (0x0008u) /* Timer_D7 High-Resolution Clock Trim Bit: 2 */
6233 #define TDHCLKTRIM3 (0x0010u) /* Timer_D7 High-Resolution Clock Trim Bit: 3 */
6234 #define TDHCLKTRIM4 (0x0020u) /* Timer_D7 High-Resolution Clock Trim Bit: 4 */
6235 #define TDHCLKTRIM5 (0x0040u) /* Timer_D7 High-Resolution Clock Trim Bit: 5 */
6236 #define TDHCLKTRIM6 (0x0080u) /* Timer_D7 High-Resolution Clock Trim Bit: 6 */
6237 #define TDHCLKSR0 (0x0100u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 0 */
6238 #define TDHCLKSR1 (0x0200u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 1 */
6239 #define TDHCLKSR2 (0x0400u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 2 */
6240 #define TDHCLKSR3 (0x0800u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 3 */
6241 #define TDHCLKSR4 (0x1000u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 4 */
6242 #define TDHCLKR0 (0x2000u) /* Timer_D7 High-Resolution Clock Range Bit: 0 */
6243 #define TDHCLKR1 (0x4000u) /* Timer_D7 High-Resolution Clock Range Bit: 1 */
6244 #define TDHCLKCR (0x8000u) /* Timer_D7 High-Resolution Coarse Clock Range */
6245 
6246 /* TDxHINT Control Bits */
6247 #define TDHFLIFG (0x0001u) /* Timer_D7 High-Res. fail low Interrupt Flag */
6248 #define TDHFHIFG (0x0002u) /* Timer_D7 High-Res. fail high Interrupt Flag */
6249 #define TDHLKIFG (0x0004u) /* Timer_D7 High-Res. frequency lock Interrupt Flag */
6250 #define TDHUNLKIFG (0x0008u) /* Timer_D7 High-Res. frequency unlock Interrupt Flag */
6251 #define TDHFLIE (0x0100u) /* Timer_D7 High-Res. fail low Interrupt Enable */
6252 #define TDHFHIE (0x0200u) /* Timer_D7 High-Res. fail high Interrupt Enable */
6253 #define TDHLKIE (0x0400u) /* Timer_D7 High-Res. frequency lock Interrupt Enable */
6254 #define TDHUNLKIE (0x0800u) /* Timer_D7 High-Res. frequency unlock Interrupt Enable */
6255 
6256 #define ID1 (0x0080u) /* Timer D clock input divider 1 */
6257 #define ID0 (0x0040u) /* Timer D clock input divider 0 */
6258 #define MC1 (0x0020u) /* Timer D mode control 1 */
6259 #define MC0 (0x0010u) /* Timer D mode control 0 */
6260 #define MC__STOP (0*0x10u) /* Timer D mode control: 0 - Stop */
6261 #define MC__UP (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */
6262 #define MC__CONTINUOUS (2*0x10u) /* Timer D mode control: 2 - Continuous up */
6263 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
6264 #define MC__UPDOWN (3*0x10u) /* Timer D mode control: 3 - Up/Down */
6265 #define CM1 (0x8000u) /* Capture mode 1 */
6266 #define CM0 (0x4000u) /* Capture mode 0 */
6267 #define MC_0 (0*0x10u) /* Timer D mode control: 0 - Stop */
6268 #define MC_1 (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */
6269 #define MC_2 (2*0x10u) /* Timer D mode control: 2 - Continuous up */
6270 #define MC_3 (3*0x10u) /* Timer D mode control: 3 - Up/Down */
6271 #define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */
6272 #define CCIE (0x0010u) /* Capture/compare interrupt enable */
6273 #define CCIFG (0x0001u) /* Capture/compare interrupt flag */
6274 #define CCIS_0 (0*0x1000u)
6275 #define CCIS_1 (1*0x1000u)
6276 #define CCIS_2 (2*0x1000u)
6277 #define CCIS_3 (3*0x1000u)
6278 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
6279 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
6280 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
6281 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
6282 #define OUT (0x0004u) /* PWM Output signal if output mode 0 */
6283 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
6284 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
6285 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
6286 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
6287 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
6288 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
6289 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
6290 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
6291 #define SCCI (0x0400u) /* Latched capture signal (read) */
6292 #define SCS (0x0800u) /* Capture sychronize */
6293 #define CCI (0x0008u) /* Capture input signal (read) */
6294 #define ID__1 (0*0x40u) /* Timer D input divider: 0 - /1 */
6295 #define ID__2 (1*0x40u) /* Timer D input divider: 1 - /2 */
6296 #define ID__4 (2*0x40u) /* Timer D input divider: 2 - /4 */
6297 #define ID__8 (3*0x40u) /* Timer D input divider: 3 - /8 */
6298 #define ID_0 (0*0x40u) /* Timer D input divider: 0 - /1 */
6299 #define ID_1 (1*0x40u) /* Timer D input divider: 1 - /2 */
6300 #define ID_2 (2*0x40u) /* Timer D input divider: 2 - /4 */
6301 #define ID_3 (3*0x40u) /* Timer D input divider: 3 - /8 */
6302 
6303 #endif
6304 /************************************************************
6305 * Timer Event Control 0
6306 ************************************************************/
6307 #ifdef __MSP430_HAS_TEV0__ /* Definition to show that Module is available */
6308 
6309 #define OFS_TEC0XCTL0 (0x0000u) /* Timer Event Control 0 External Control 0 */
6310 #define OFS_TEC0XCTL0_L OFS_TEC0XCTL0
6311 #define OFS_TEC0XCTL0_H OFS_TEC0XCTL0+1
6312 #define OFS_TEC0XCTL1 (0x0002u) /* Timer Event Control 0 External Control 1 */
6313 #define OFS_TEC0XCTL1_L OFS_TEC0XCTL1
6314 #define OFS_TEC0XCTL1_H OFS_TEC0XCTL1+1
6315 #define OFS_TEC0XCTL2 (0x0004u) /* Timer Event Control 0 External Control 2 */
6316 #define OFS_TEC0XCTL2_L OFS_TEC0XCTL2
6317 #define OFS_TEC0XCTL2_H OFS_TEC0XCTL2+1
6318 #define OFS_TEC0STA (0x0006u) /* Timer Event Control 0 Status */
6319 #define OFS_TEC0STA_L OFS_TEC0STA
6320 #define OFS_TEC0STA_H OFS_TEC0STA+1
6321 #define OFS_TEC0XINT (0x0008u) /* Timer Event Control 0 External Interrupt */
6322 #define OFS_TEC0XINT_L OFS_TEC0XINT
6323 #define OFS_TEC0XINT_H OFS_TEC0XINT+1
6324 #define OFS_TEC0IV (0x000Au) /* Timer Event Control 0 Interrupt Vector */
6325 #define OFS_TEC0IV_L OFS_TEC0IV
6326 #define OFS_TEC0IV_H OFS_TEC0IV+1
6327 
6328 /* TECxXCTL0 Control Bits */
6329 #define TECXFLTHLD0 (0x0001u) /* TEV Ext. fault signal hold for CE0 */
6330 #define TECXFLTHLD1 (0x0002u) /* TEV Ext. fault signal hold for CE1 */
6331 #define TECXFLTHLD2 (0x0004u) /* TEV Ext. fault signal hold for CE2 */
6332 #define TECXFLTHLD3 (0x0008u) /* TEV Ext. fault signal hold for CE3 */
6333 #define TECXFLTHLD4 (0x0010u) /* TEV Ext. fault signal hold for CE4 */
6334 #define TECXFLTHLD5 (0x0020u) /* TEV Ext. fault signal hold for CE5 */
6335 #define TECXFLTHLD6 (0x0040u) /* TEV Ext. fault signal hold for CE6 */
6336 #define TECXFLTEN0 (0x0100u) /* TEV Ext. fault signal enable for CE0 */
6337 #define TECXFLTEN1 (0x0200u) /* TEV Ext. fault signal enable for CE1 */
6338 #define TECXFLTEN2 (0x0400u) /* TEV Ext. fault signal enable for CE2 */
6339 #define TECXFLTEN3 (0x0800u) /* TEV Ext. fault signal enable for CE3 */
6340 #define TECXFLTEN4 (0x1000u) /* TEV Ext. fault signal enable for CE4 */
6341 #define TECXFLTEN5 (0x2000u) /* TEV Ext. fault signal enable for CE5 */
6342 #define TECXFLTEN6 (0x4000u) /* TEV Ext. fault signal enable for CE6 */
6343 
6344 /* TECxXCTL0 Control Bits */
6345 #define TECXFLTHLD0_L (0x0001u) /* TEV Ext. fault signal hold for CE0 */
6346 #define TECXFLTHLD1_L (0x0002u) /* TEV Ext. fault signal hold for CE1 */
6347 #define TECXFLTHLD2_L (0x0004u) /* TEV Ext. fault signal hold for CE2 */
6348 #define TECXFLTHLD3_L (0x0008u) /* TEV Ext. fault signal hold for CE3 */
6349 #define TECXFLTHLD4_L (0x0010u) /* TEV Ext. fault signal hold for CE4 */
6350 #define TECXFLTHLD5_L (0x0020u) /* TEV Ext. fault signal hold for CE5 */
6351 #define TECXFLTHLD6_L (0x0040u) /* TEV Ext. fault signal hold for CE6 */
6352 
6353 /* TECxXCTL0 Control Bits */
6354 #define TECXFLTEN0_H (0x0001u) /* TEV Ext. fault signal enable for CE0 */
6355 #define TECXFLTEN1_H (0x0002u) /* TEV Ext. fault signal enable for CE1 */
6356 #define TECXFLTEN2_H (0x0004u) /* TEV Ext. fault signal enable for CE2 */
6357 #define TECXFLTEN3_H (0x0008u) /* TEV Ext. fault signal enable for CE3 */
6358 #define TECXFLTEN4_H (0x0010u) /* TEV Ext. fault signal enable for CE4 */
6359 #define TECXFLTEN5_H (0x0020u) /* TEV Ext. fault signal enable for CE5 */
6360 #define TECXFLTEN6_H (0x0040u) /* TEV Ext. fault signal enable for CE6 */
6361 
6362 /* TECxXCTL1 Control Bits */
6363 #define TECXFLTPOL0 (0x0001u) /* TEV Polarity Bit of ext. fault 0 */
6364 #define TECXFLTPOL1 (0x0002u) /* TEV Polarity Bit of ext. fault 1 */
6365 #define TECXFLTPOL2 (0x0004u) /* TEV Polarity Bit of ext. fault 2 */
6366 #define TECXFLTPOL3 (0x0008u) /* TEV Polarity Bit of ext. fault 3 */
6367 #define TECXFLTPOL4 (0x0010u) /* TEV Polarity Bit of ext. fault 4 */
6368 #define TECXFLTPOL5 (0x0020u) /* TEV Polarity Bit of ext. fault 5 */
6369 #define TECXFLTPOL6 (0x0040u) /* TEV Polarity Bit of ext. fault 6 */
6370 #define TECXFLTLVS0 (0x0100u) /* TEV Signal Type of Ext. fault 0 */
6371 #define TECXFLTLVS1 (0x0200u) /* TEV Signal Type of Ext. fault 1 */
6372 #define TECXFLTLVS2 (0x0400u) /* TEV Signal Type of Ext. fault 2 */
6373 #define TECXFLTLVS3 (0x0800u) /* TEV Signal Type of Ext. fault 3 */
6374 #define TECXFLTLVS4 (0x1000u) /* TEV Signal Type of Ext. fault 4 */
6375 #define TECXFLTLVS5 (0x2000u) /* TEV Signal Type of Ext. fault 5 */
6376 #define TECXFLTLVS6 (0x4000u) /* TEV Signal Type of Ext. fault 6 */
6377 
6378 /* TECxXCTL1 Control Bits */
6379 #define TECXFLTPOL0_L (0x0001u) /* TEV Polarity Bit of ext. fault 0 */
6380 #define TECXFLTPOL1_L (0x0002u) /* TEV Polarity Bit of ext. fault 1 */
6381 #define TECXFLTPOL2_L (0x0004u) /* TEV Polarity Bit of ext. fault 2 */
6382 #define TECXFLTPOL3_L (0x0008u) /* TEV Polarity Bit of ext. fault 3 */
6383 #define TECXFLTPOL4_L (0x0010u) /* TEV Polarity Bit of ext. fault 4 */
6384 #define TECXFLTPOL5_L (0x0020u) /* TEV Polarity Bit of ext. fault 5 */
6385 #define TECXFLTPOL6_L (0x0040u) /* TEV Polarity Bit of ext. fault 6 */
6386 
6387 /* TECxXCTL1 Control Bits */
6388 #define TECXFLTLVS0_H (0x0001u) /* TEV Signal Type of Ext. fault 0 */
6389 #define TECXFLTLVS1_H (0x0002u) /* TEV Signal Type of Ext. fault 1 */
6390 #define TECXFLTLVS2_H (0x0004u) /* TEV Signal Type of Ext. fault 2 */
6391 #define TECXFLTLVS3_H (0x0008u) /* TEV Signal Type of Ext. fault 3 */
6392 #define TECXFLTLVS4_H (0x0010u) /* TEV Signal Type of Ext. fault 4 */
6393 #define TECXFLTLVS5_H (0x0020u) /* TEV Signal Type of Ext. fault 5 */
6394 #define TECXFLTLVS6_H (0x0040u) /* TEV Signal Type of Ext. fault 6 */
6395 
6396 /* TECxXCTL2 Control Bits */
6397 #define TECCLKSEL0 (0x0001u) /* TEV Aux. Clock Select Bit: 0 */
6398 #define TECCLKSEL1 (0x0002u) /* TEV Aux. Clock Select Bit: 1 */
6399 #define TECAXCLREN (0x0004u) /* TEV Auxilary clear signal control */
6400 #define TECEXCLREN (0x0008u) /* TEV Ext. clear signal control */
6401 #define TECEXCLRHLD (0x0010u) /* TEV External clear signal hold bit */
6402 #define TECEXCLRPOL (0x0020u) /* TEV Polarity Bit of ext. clear */
6403 #define TECEXCLRLVS (0x0040u) /* TEV Signal Type of Ext. clear */
6404 
6405 /* TECxXCTL2 Control Bits */
6406 #define TECCLKSEL0_L (0x0001u) /* TEV Aux. Clock Select Bit: 0 */
6407 #define TECCLKSEL1_L (0x0002u) /* TEV Aux. Clock Select Bit: 1 */
6408 #define TECAXCLREN_L (0x0004u) /* TEV Auxilary clear signal control */
6409 #define TECEXCLREN_L (0x0008u) /* TEV Ext. clear signal control */
6410 #define TECEXCLRHLD_L (0x0010u) /* TEV External clear signal hold bit */
6411 #define TECEXCLRPOL_L (0x0020u) /* TEV Polarity Bit of ext. clear */
6412 #define TECEXCLRLVS_L (0x0040u) /* TEV Signal Type of Ext. clear */
6413 
6414 #define TECCLKSEL_0 (0x0000u) /* TEV Aux. Clock Select: CLK0 */
6415 #define TECCLKSEL_1 (0x0001u) /* TEV Aux. Clock Select: CLK1 */
6416 #define TECCLKSEL_2 (0x0002u) /* TEV Aux. Clock Select: CLK2 */
6417 #define TECCLKSEL_3 (0x0003u) /* TEV Aux. Clock Select: CLK3 */
6418 
6419 /* TECxSTA Control Bits */
6420 #define TECXFLT0STA (0x0001u) /* TEV External fault status flag for CE0 */
6421 #define TECXFLT1STA (0x0002u) /* TEV External fault status flag for CE1 */
6422 #define TECXFLT2STA (0x0004u) /* TEV External fault status flag for CE2 */
6423 #define TECXFLT3STA (0x0008u) /* TEV External fault status flag for CE3 */
6424 #define TECXFLT4STA (0x0010u) /* TEV External fault status flag for CE4 */
6425 #define TECXFLT5STA (0x0020u) /* TEV External fault status flag for CE5 */
6426 #define TECXFLT6STA (0x0040u) /* TEV External fault status flag for CE6 */
6427 #define TECXCLRSTA (0x0100u) /* TEC External clear status flag */
6428 
6429 /* TECxSTA Control Bits */
6430 #define TECXFLT0STA_L (0x0001u) /* TEV External fault status flag for CE0 */
6431 #define TECXFLT1STA_L (0x0002u) /* TEV External fault status flag for CE1 */
6432 #define TECXFLT2STA_L (0x0004u) /* TEV External fault status flag for CE2 */
6433 #define TECXFLT3STA_L (0x0008u) /* TEV External fault status flag for CE3 */
6434 #define TECXFLT4STA_L (0x0010u) /* TEV External fault status flag for CE4 */
6435 #define TECXFLT5STA_L (0x0020u) /* TEV External fault status flag for CE5 */
6436 #define TECXFLT6STA_L (0x0040u) /* TEV External fault status flag for CE6 */
6437 
6438 /* TECxSTA Control Bits */
6439 #define TECXCLRSTA_H (0x0001u) /* TEC External clear status flag */
6440 
6441 /* TECxXINT Control Bits */
6442 #define TECAXCLRIFG (0x0001u) /* TEC Aux. Clear Interrupt Flag */
6443 #define TECEXCLRIFG (0x0002u) /* TEC External Clear Interrupt Flag */
6444 #define TECXFLTIFG (0x0004u) /* TEC External Fault Interrupt Flag */
6445 #define TECAXCLRIE (0x0100u) /* TEC Aux. Clear Interrupt Enable */
6446 #define TECEXCLRIE (0x0200u) /* TEC External Clear Interrupt Enable */
6447 #define TECXFLTIE (0x0400u) /* TEC External Fault Interrupt Enable */
6448 
6449 /* TECxXINT Control Bits */
6450 #define TECAXCLRIFG_L (0x0001u) /* TEC Aux. Clear Interrupt Flag */
6451 #define TECEXCLRIFG_L (0x0002u) /* TEC External Clear Interrupt Flag */
6452 #define TECXFLTIFG_L (0x0004u) /* TEC External Fault Interrupt Flag */
6453 
6454 /* TECxXINT Control Bits */
6455 #define TECAXCLRIE_H (0x0001u) /* TEC Aux. Clear Interrupt Enable */
6456 #define TECEXCLRIE_H (0x0002u) /* TEC External Clear Interrupt Enable */
6457 #define TECXFLTIE_H (0x0004u) /* TEC External Fault Interrupt Enable */
6458 
6459 /* TEC0IV Definitions */
6460 #define TEC0IV_NONE (0x0000u) /* No Interrupt pending */
6461 #define TEC0IV_TECXFLTIFG (0x0002u) /* TEC0XFLTIFG */
6462 #define TEC0IV_TECEXCLRIFG (0x0004u) /* TEC0EXCLRIFG */
6463 #define TEC0IV_TECAXCLRIFG (0x0006u) /* TEC0AXCLRIFG */
6464 
6465 #endif
6466 /************************************************************
6467 * Timer Event Control x
6468 ************************************************************/
6469 #ifdef __MSP430_HAS_TEVx__ /* Definition to show that Module is available */
6470 
6471 #define OFS_TECxXCTL0 (0x0000u) /* Timer Event Control x External Control 0 */
6472 #define OFS_TECxXCTL0_L OFS_TECxXCTL0
6473 #define OFS_TECxXCTL0_H OFS_TECxXCTL0+1
6474 #define OFS_TECxXCTL1 (0x0002u) /* Timer Event Control x External Control 1 */
6475 #define OFS_TECxXCTL1_L OFS_TECxXCTL1
6476 #define OFS_TECxXCTL1_H OFS_TECxXCTL1+1
6477 #define OFS_TECxXCTL2 (0x0004u) /* Timer Event Control x External Control 2 */
6478 #define OFS_TECxXCTL2_L OFS_TECxXCTL2
6479 #define OFS_TECxXCTL2_H OFS_TECxXCTL2+1
6480 #define OFS_TECxSTA (0x0006u) /* Timer Event Control x Status */
6481 #define OFS_TECxSTA_L OFS_TECxSTA
6482 #define OFS_TECxSTA_H OFS_TECxSTA+1
6483 #define OFS_TECxXINT (0x0008u) /* Timer Event Control x External Interrupt */
6484 #define OFS_TECxXINT_L OFS_TECxXINT
6485 #define OFS_TECxXINT_H OFS_TECxXINT+1
6486 #define OFS_TECxIV (0x000Au) /* Timer Event Control x Interrupt Vector */
6487 #define OFS_TECxIV_L OFS_TECxIV
6488 #define OFS_TECxIV_H OFS_TECxIV+1
6489 
6490 /* TECIV Definitions */
6491 #define TECxIV_NONE (0x0000u) /* No Interrupt pending */
6492 #define TECxIV_TECXFLTIFG (0x0002u) /* TECxXFLTIFG */
6493 #define TECxIV_TECEXCLRIFG (0x0004u) /* TECxEXCLRIFG */
6494 #define TECxIV_TECAXCLRIFG (0x0006u) /* TECxAXCLRIFG */
6495 
6496 
6497 #endif
6498 
6499 /************************************************************
6500 * UNIFIED CLOCK SYSTEM
6501 ************************************************************/
6502 #ifdef __MSP430_HAS_UCS__ /* Definition to show that Module is available */
6503 
6504 #define OFS_UCSCTL0 (0x0000u) /* UCS Control Register 0 */
6505 #define OFS_UCSCTL0_L OFS_UCSCTL0
6506 #define OFS_UCSCTL0_H OFS_UCSCTL0+1
6507 #define OFS_UCSCTL1 (0x0002u) /* UCS Control Register 1 */
6508 #define OFS_UCSCTL1_L OFS_UCSCTL1
6509 #define OFS_UCSCTL1_H OFS_UCSCTL1+1
6510 #define OFS_UCSCTL2 (0x0004u) /* UCS Control Register 2 */
6511 #define OFS_UCSCTL2_L OFS_UCSCTL2
6512 #define OFS_UCSCTL2_H OFS_UCSCTL2+1
6513 #define OFS_UCSCTL3 (0x0006u) /* UCS Control Register 3 */
6514 #define OFS_UCSCTL3_L OFS_UCSCTL3
6515 #define OFS_UCSCTL3_H OFS_UCSCTL3+1
6516 #define OFS_UCSCTL4 (0x0008u) /* UCS Control Register 4 */
6517 #define OFS_UCSCTL4_L OFS_UCSCTL4
6518 #define OFS_UCSCTL4_H OFS_UCSCTL4+1
6519 #define OFS_UCSCTL5 (0x000Au) /* UCS Control Register 5 */
6520 #define OFS_UCSCTL5_L OFS_UCSCTL5
6521 #define OFS_UCSCTL5_H OFS_UCSCTL5+1
6522 #define OFS_UCSCTL6 (0x000Cu) /* UCS Control Register 6 */
6523 #define OFS_UCSCTL6_L OFS_UCSCTL6
6524 #define OFS_UCSCTL6_H OFS_UCSCTL6+1
6525 #define OFS_UCSCTL7 (0x000Eu) /* UCS Control Register 7 */
6526 #define OFS_UCSCTL7_L OFS_UCSCTL7
6527 #define OFS_UCSCTL7_H OFS_UCSCTL7+1
6528 #define OFS_UCSCTL8 (0x0010u) /* UCS Control Register 8 */
6529 #define OFS_UCSCTL8_L OFS_UCSCTL8
6530 #define OFS_UCSCTL8_H OFS_UCSCTL8+1
6531 
6532 /* UCSCTL0 Control Bits */
6533 //#define RESERVED (0x0001u) /* RESERVED */
6534 //#define RESERVED (0x0002u) /* RESERVED */
6535 //#define RESERVED (0x0004u) /* RESERVED */
6536 #define MOD0 (0x0008u) /* Modulation Bit Counter Bit : 0 */
6537 #define MOD1 (0x0010u) /* Modulation Bit Counter Bit : 1 */
6538 #define MOD2 (0x0020u) /* Modulation Bit Counter Bit : 2 */
6539 #define MOD3 (0x0040u) /* Modulation Bit Counter Bit : 3 */
6540 #define MOD4 (0x0080u) /* Modulation Bit Counter Bit : 4 */
6541 #define DCO0 (0x0100u) /* DCO TAP Bit : 0 */
6542 #define DCO1 (0x0200u) /* DCO TAP Bit : 1 */
6543 #define DCO2 (0x0400u) /* DCO TAP Bit : 2 */
6544 #define DCO3 (0x0800u) /* DCO TAP Bit : 3 */
6545 #define DCO4 (0x1000u) /* DCO TAP Bit : 4 */
6546 //#define RESERVED (0x2000u) /* RESERVED */
6547 //#define RESERVED (0x4000u) /* RESERVED */
6548 //#define RESERVED (0x8000u) /* RESERVED */
6549 
6550 /* UCSCTL0 Control Bits */
6551 //#define RESERVED (0x0001u) /* RESERVED */
6552 //#define RESERVED (0x0002u) /* RESERVED */
6553 //#define RESERVED (0x0004u) /* RESERVED */
6554 #define MOD0_L (0x0008u) /* Modulation Bit Counter Bit : 0 */
6555 #define MOD1_L (0x0010u) /* Modulation Bit Counter Bit : 1 */
6556 #define MOD2_L (0x0020u) /* Modulation Bit Counter Bit : 2 */
6557 #define MOD3_L (0x0040u) /* Modulation Bit Counter Bit : 3 */
6558 #define MOD4_L (0x0080u) /* Modulation Bit Counter Bit : 4 */
6559 //#define RESERVED (0x2000u) /* RESERVED */
6560 //#define RESERVED (0x4000u) /* RESERVED */
6561 //#define RESERVED (0x8000u) /* RESERVED */
6562 
6563 /* UCSCTL0 Control Bits */
6564 //#define RESERVED (0x0001u) /* RESERVED */
6565 //#define RESERVED (0x0002u) /* RESERVED */
6566 //#define RESERVED (0x0004u) /* RESERVED */
6567 #define DCO0_H (0x0001u) /* DCO TAP Bit : 0 */
6568 #define DCO1_H (0x0002u) /* DCO TAP Bit : 1 */
6569 #define DCO2_H (0x0004u) /* DCO TAP Bit : 2 */
6570 #define DCO3_H (0x0008u) /* DCO TAP Bit : 3 */
6571 #define DCO4_H (0x0010u) /* DCO TAP Bit : 4 */
6572 //#define RESERVED (0x2000u) /* RESERVED */
6573 //#define RESERVED (0x4000u) /* RESERVED */
6574 //#define RESERVED (0x8000u) /* RESERVED */
6575 
6576 /* UCSCTL1 Control Bits */
6577 #define DISMOD (0x0001u) /* Disable Modulation */
6578 //#define RESERVED (0x0002u) /* RESERVED */
6579 //#define RESERVED (0x0004u) /* RESERVED */
6580 //#define RESERVED (0x0008u) /* RESERVED */
6581 #define DCORSEL0 (0x0010u) /* DCO Freq. Range Select Bit : 0 */
6582 #define DCORSEL1 (0x0020u) /* DCO Freq. Range Select Bit : 1 */
6583 #define DCORSEL2 (0x0040u) /* DCO Freq. Range Select Bit : 2 */
6584 //#define RESERVED (0x0080u) /* RESERVED */
6585 //#define RESERVED (0x0100u) /* RESERVED */
6586 //#define RESERVED (0x0200u) /* RESERVED */
6587 //#define RESERVED (0x0400u) /* RESERVED */
6588 //#define RESERVED (0x0800u) /* RESERVED */
6589 //#define RESERVED (0x1000u) /* RESERVED */
6590 //#define RESERVED (0x2000u) /* RESERVED */
6591 //#define RESERVED (0x4000u) /* RESERVED */
6592 //#define RESERVED (0x8000u) /* RESERVED */
6593 
6594 /* UCSCTL1 Control Bits */
6595 #define DISMOD_L (0x0001u) /* Disable Modulation */
6596 //#define RESERVED (0x0002u) /* RESERVED */
6597 //#define RESERVED (0x0004u) /* RESERVED */
6598 //#define RESERVED (0x0008u) /* RESERVED */
6599 #define DCORSEL0_L (0x0010u) /* DCO Freq. Range Select Bit : 0 */
6600 #define DCORSEL1_L (0x0020u) /* DCO Freq. Range Select Bit : 1 */
6601 #define DCORSEL2_L (0x0040u) /* DCO Freq. Range Select Bit : 2 */
6602 //#define RESERVED (0x0080u) /* RESERVED */
6603 //#define RESERVED (0x0100u) /* RESERVED */
6604 //#define RESERVED (0x0200u) /* RESERVED */
6605 //#define RESERVED (0x0400u) /* RESERVED */
6606 //#define RESERVED (0x0800u) /* RESERVED */
6607 //#define RESERVED (0x1000u) /* RESERVED */
6608 //#define RESERVED (0x2000u) /* RESERVED */
6609 //#define RESERVED (0x4000u) /* RESERVED */
6610 //#define RESERVED (0x8000u) /* RESERVED */
6611 
6612 #define DCORSEL_0 (0x0000u) /* DCO RSEL 0 */
6613 #define DCORSEL_1 (0x0010u) /* DCO RSEL 1 */
6614 #define DCORSEL_2 (0x0020u) /* DCO RSEL 2 */
6615 #define DCORSEL_3 (0x0030u) /* DCO RSEL 3 */
6616 #define DCORSEL_4 (0x0040u) /* DCO RSEL 4 */
6617 #define DCORSEL_5 (0x0050u) /* DCO RSEL 5 */
6618 #define DCORSEL_6 (0x0060u) /* DCO RSEL 6 */
6619 #define DCORSEL_7 (0x0070u) /* DCO RSEL 7 */
6620 
6621 /* UCSCTL2 Control Bits */
6622 #define FLLN0 (0x0001u) /* FLL Multipier Bit : 0 */
6623 #define FLLN1 (0x0002u) /* FLL Multipier Bit : 1 */
6624 #define FLLN2 (0x0004u) /* FLL Multipier Bit : 2 */
6625 #define FLLN3 (0x0008u) /* FLL Multipier Bit : 3 */
6626 #define FLLN4 (0x0010u) /* FLL Multipier Bit : 4 */
6627 #define FLLN5 (0x0020u) /* FLL Multipier Bit : 5 */
6628 #define FLLN6 (0x0040u) /* FLL Multipier Bit : 6 */
6629 #define FLLN7 (0x0080u) /* FLL Multipier Bit : 7 */
6630 #define FLLN8 (0x0100u) /* FLL Multipier Bit : 8 */
6631 #define FLLN9 (0x0200u) /* FLL Multipier Bit : 9 */
6632 //#define RESERVED (0x0400u) /* RESERVED */
6633 //#define RESERVED (0x0800u) /* RESERVED */
6634 #define FLLD0 (0x1000u) /* Loop Divider Bit : 0 */
6635 #define FLLD1 (0x2000u) /* Loop Divider Bit : 1 */
6636 #define FLLD2 (0x4000u) /* Loop Divider Bit : 1 */
6637 //#define RESERVED (0x8000u) /* RESERVED */
6638 
6639 /* UCSCTL2 Control Bits */
6640 #define FLLN0_L (0x0001u) /* FLL Multipier Bit : 0 */
6641 #define FLLN1_L (0x0002u) /* FLL Multipier Bit : 1 */
6642 #define FLLN2_L (0x0004u) /* FLL Multipier Bit : 2 */
6643 #define FLLN3_L (0x0008u) /* FLL Multipier Bit : 3 */
6644 #define FLLN4_L (0x0010u) /* FLL Multipier Bit : 4 */
6645 #define FLLN5_L (0x0020u) /* FLL Multipier Bit : 5 */
6646 #define FLLN6_L (0x0040u) /* FLL Multipier Bit : 6 */
6647 #define FLLN7_L (0x0080u) /* FLL Multipier Bit : 7 */
6648 //#define RESERVED (0x0400u) /* RESERVED */
6649 //#define RESERVED (0x0800u) /* RESERVED */
6650 //#define RESERVED (0x8000u) /* RESERVED */
6651 
6652 /* UCSCTL2 Control Bits */
6653 #define FLLN8_H (0x0001u) /* FLL Multipier Bit : 8 */
6654 #define FLLN9_H (0x0002u) /* FLL Multipier Bit : 9 */
6655 //#define RESERVED (0x0400u) /* RESERVED */
6656 //#define RESERVED (0x0800u) /* RESERVED */
6657 #define FLLD0_H (0x0010u) /* Loop Divider Bit : 0 */
6658 #define FLLD1_H (0x0020u) /* Loop Divider Bit : 1 */
6659 #define FLLD2_H (0x0040u) /* Loop Divider Bit : 1 */
6660 //#define RESERVED (0x8000u) /* RESERVED */
6661 
6662 #define FLLD_0 (0x0000u) /* Multiply Selected Loop Freq. 1 */
6663 #define FLLD_1 (0x1000u) /* Multiply Selected Loop Freq. 2 */
6664 #define FLLD_2 (0x2000u) /* Multiply Selected Loop Freq. 4 */
6665 #define FLLD_3 (0x3000u) /* Multiply Selected Loop Freq. 8 */
6666 #define FLLD_4 (0x4000u) /* Multiply Selected Loop Freq. 16 */
6667 #define FLLD_5 (0x5000u) /* Multiply Selected Loop Freq. 32 */
6668 #define FLLD_6 (0x6000u) /* Multiply Selected Loop Freq. 32 */
6669 #define FLLD_7 (0x7000u) /* Multiply Selected Loop Freq. 32 */
6670 #define FLLD__1 (0x0000u) /* Multiply Selected Loop Freq. By 1 */
6671 #define FLLD__2 (0x1000u) /* Multiply Selected Loop Freq. By 2 */
6672 #define FLLD__4 (0x2000u) /* Multiply Selected Loop Freq. By 4 */
6673 #define FLLD__8 (0x3000u) /* Multiply Selected Loop Freq. By 8 */
6674 #define FLLD__16 (0x4000u) /* Multiply Selected Loop Freq. By 16 */
6675 #define FLLD__32 (0x5000u) /* Multiply Selected Loop Freq. By 32 */
6676 
6677 /* UCSCTL3 Control Bits */
6678 #define FLLREFDIV0 (0x0001u) /* Reference Divider Bit : 0 */
6679 #define FLLREFDIV1 (0x0002u) /* Reference Divider Bit : 1 */
6680 #define FLLREFDIV2 (0x0004u) /* Reference Divider Bit : 2 */
6681 //#define RESERVED (0x0008u) /* RESERVED */
6682 #define SELREF0 (0x0010u) /* FLL Reference Clock Select Bit : 0 */
6683 #define SELREF1 (0x0020u) /* FLL Reference Clock Select Bit : 1 */
6684 #define SELREF2 (0x0040u) /* FLL Reference Clock Select Bit : 2 */
6685 //#define RESERVED (0x0080u) /* RESERVED */
6686 //#define RESERVED (0x0100u) /* RESERVED */
6687 //#define RESERVED (0x0200u) /* RESERVED */
6688 //#define RESERVED (0x0400u) /* RESERVED */
6689 //#define RESERVED (0x0800u) /* RESERVED */
6690 //#define RESERVED (0x1000u) /* RESERVED */
6691 //#define RESERVED (0x2000u) /* RESERVED */
6692 //#define RESERVED (0x4000u) /* RESERVED */
6693 //#define RESERVED (0x8000u) /* RESERVED */
6694 
6695 /* UCSCTL3 Control Bits */
6696 #define FLLREFDIV0_L (0x0001u) /* Reference Divider Bit : 0 */
6697 #define FLLREFDIV1_L (0x0002u) /* Reference Divider Bit : 1 */
6698 #define FLLREFDIV2_L (0x0004u) /* Reference Divider Bit : 2 */
6699 //#define RESERVED (0x0008u) /* RESERVED */
6700 #define SELREF0_L (0x0010u) /* FLL Reference Clock Select Bit : 0 */
6701 #define SELREF1_L (0x0020u) /* FLL Reference Clock Select Bit : 1 */
6702 #define SELREF2_L (0x0040u) /* FLL Reference Clock Select Bit : 2 */
6703 //#define RESERVED (0x0080u) /* RESERVED */
6704 //#define RESERVED (0x0100u) /* RESERVED */
6705 //#define RESERVED (0x0200u) /* RESERVED */
6706 //#define RESERVED (0x0400u) /* RESERVED */
6707 //#define RESERVED (0x0800u) /* RESERVED */
6708 //#define RESERVED (0x1000u) /* RESERVED */
6709 //#define RESERVED (0x2000u) /* RESERVED */
6710 //#define RESERVED (0x4000u) /* RESERVED */
6711 //#define RESERVED (0x8000u) /* RESERVED */
6712 
6713 #define FLLREFDIV_0 (0x0000u) /* Reference Divider: f(LFCLK)/1 */
6714 #define FLLREFDIV_1 (0x0001u) /* Reference Divider: f(LFCLK)/2 */
6715 #define FLLREFDIV_2 (0x0002u) /* Reference Divider: f(LFCLK)/4 */
6716 #define FLLREFDIV_3 (0x0003u) /* Reference Divider: f(LFCLK)/8 */
6717 #define FLLREFDIV_4 (0x0004u) /* Reference Divider: f(LFCLK)/12 */
6718 #define FLLREFDIV_5 (0x0005u) /* Reference Divider: f(LFCLK)/16 */
6719 #define FLLREFDIV_6 (0x0006u) /* Reference Divider: f(LFCLK)/16 */
6720 #define FLLREFDIV_7 (0x0007u) /* Reference Divider: f(LFCLK)/16 */
6721 #define FLLREFDIV__1 (0x0000u) /* Reference Divider: f(LFCLK)/1 */
6722 #define FLLREFDIV__2 (0x0001u) /* Reference Divider: f(LFCLK)/2 */
6723 #define FLLREFDIV__4 (0x0002u) /* Reference Divider: f(LFCLK)/4 */
6724 #define FLLREFDIV__8 (0x0003u) /* Reference Divider: f(LFCLK)/8 */
6725 #define FLLREFDIV__12 (0x0004u) /* Reference Divider: f(LFCLK)/12 */
6726 #define FLLREFDIV__16 (0x0005u) /* Reference Divider: f(LFCLK)/16 */
6727 #define SELREF_0 (0x0000u) /* FLL Reference Clock Select 0 */
6728 #define SELREF_1 (0x0010u) /* FLL Reference Clock Select 1 */
6729 #define SELREF_2 (0x0020u) /* FLL Reference Clock Select 2 */
6730 #define SELREF_3 (0x0030u) /* FLL Reference Clock Select 3 */
6731 #define SELREF_4 (0x0040u) /* FLL Reference Clock Select 4 */
6732 #define SELREF_5 (0x0050u) /* FLL Reference Clock Select 5 */
6733 #define SELREF_6 (0x0060u) /* FLL Reference Clock Select 6 */
6734 #define SELREF_7 (0x0070u) /* FLL Reference Clock Select 7 */
6735 #define SELREF__XT1CLK (0x0000u) /* Multiply Selected Loop Freq. By XT1CLK */
6736 #define SELREF__REFOCLK (0x0020u) /* Multiply Selected Loop Freq. By REFOCLK */
6737 #define SELREF__XT2CLK (0x0050u) /* Multiply Selected Loop Freq. By XT2CLK */
6738 
6739 /* UCSCTL4 Control Bits */
6740 #define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */
6741 #define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */
6742 #define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */
6743 //#define RESERVED (0x0008u) /* RESERVED */
6744 #define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */
6745 #define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */
6746 #define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */
6747 //#define RESERVED (0x0080u) /* RESERVED */
6748 #define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */
6749 #define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */
6750 #define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */
6751 //#define RESERVED (0x0800u) /* RESERVED */
6752 //#define RESERVED (0x1000u) /* RESERVED */
6753 //#define RESERVED (0x2000u) /* RESERVED */
6754 //#define RESERVED (0x4000u) /* RESERVED */
6755 //#define RESERVED (0x8000u) /* RESERVED */
6756 
6757 /* UCSCTL4 Control Bits */
6758 #define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */
6759 #define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */
6760 #define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */
6761 //#define RESERVED (0x0008u) /* RESERVED */
6762 #define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */
6763 #define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */
6764 #define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */
6765 //#define RESERVED (0x0080u) /* RESERVED */
6766 //#define RESERVED (0x0800u) /* RESERVED */
6767 //#define RESERVED (0x1000u) /* RESERVED */
6768 //#define RESERVED (0x2000u) /* RESERVED */
6769 //#define RESERVED (0x4000u) /* RESERVED */
6770 //#define RESERVED (0x8000u) /* RESERVED */
6771 
6772 /* UCSCTL4 Control Bits */
6773 //#define RESERVED (0x0008u) /* RESERVED */
6774 //#define RESERVED (0x0080u) /* RESERVED */
6775 #define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */
6776 #define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */
6777 #define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */
6778 //#define RESERVED (0x0800u) /* RESERVED */
6779 //#define RESERVED (0x1000u) /* RESERVED */
6780 //#define RESERVED (0x2000u) /* RESERVED */
6781 //#define RESERVED (0x4000u) /* RESERVED */
6782 //#define RESERVED (0x8000u) /* RESERVED */
6783 
6784 #define SELM_0 (0x0000u) /* MCLK Source Select 0 */
6785 #define SELM_1 (0x0001u) /* MCLK Source Select 1 */
6786 #define SELM_2 (0x0002u) /* MCLK Source Select 2 */
6787 #define SELM_3 (0x0003u) /* MCLK Source Select 3 */
6788 #define SELM_4 (0x0004u) /* MCLK Source Select 4 */
6789 #define SELM_5 (0x0005u) /* MCLK Source Select 5 */
6790 #define SELM_6 (0x0006u) /* MCLK Source Select 6 */
6791 #define SELM_7 (0x0007u) /* MCLK Source Select 7 */
6792 #define SELM__XT1CLK (0x0000u) /* MCLK Source Select XT1CLK */
6793 #define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */
6794 #define SELM__REFOCLK (0x0002u) /* MCLK Source Select REFOCLK */
6795 #define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */
6796 #define SELM__DCOCLKDIV (0x0004u) /* MCLK Source Select DCOCLKDIV */
6797 #define SELM__XT2CLK (0x0005u) /* MCLK Source Select XT2CLK */
6798 
6799 #define SELS_0 (0x0000u) /* SMCLK Source Select 0 */
6800 #define SELS_1 (0x0010u) /* SMCLK Source Select 1 */
6801 #define SELS_2 (0x0020u) /* SMCLK Source Select 2 */
6802 #define SELS_3 (0x0030u) /* SMCLK Source Select 3 */
6803 #define SELS_4 (0x0040u) /* SMCLK Source Select 4 */
6804 #define SELS_5 (0x0050u) /* SMCLK Source Select 5 */
6805 #define SELS_6 (0x0060u) /* SMCLK Source Select 6 */
6806 #define SELS_7 (0x0070u) /* SMCLK Source Select 7 */
6807 #define SELS__XT1CLK (0x0000u) /* SMCLK Source Select XT1CLK */
6808 #define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */
6809 #define SELS__REFOCLK (0x0020u) /* SMCLK Source Select REFOCLK */
6810 #define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */
6811 #define SELS__DCOCLKDIV (0x0040u) /* SMCLK Source Select DCOCLKDIV */
6812 #define SELS__XT2CLK (0x0050u) /* SMCLK Source Select XT2CLK */
6813 
6814 #define SELA_0 (0x0000u) /* ACLK Source Select 0 */
6815 #define SELA_1 (0x0100u) /* ACLK Source Select 1 */
6816 #define SELA_2 (0x0200u) /* ACLK Source Select 2 */
6817 #define SELA_3 (0x0300u) /* ACLK Source Select 3 */
6818 #define SELA_4 (0x0400u) /* ACLK Source Select 4 */
6819 #define SELA_5 (0x0500u) /* ACLK Source Select 5 */
6820 #define SELA_6 (0x0600u) /* ACLK Source Select 6 */
6821 #define SELA_7 (0x0700u) /* ACLK Source Select 7 */
6822 #define SELA__XT1CLK (0x0000u) /* ACLK Source Select XT1CLK */
6823 #define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */
6824 #define SELA__REFOCLK (0x0200u) /* ACLK Source Select REFOCLK */
6825 #define SELA__DCOCLK (0x0300u) /* ACLK Source Select DCOCLK */
6826 #define SELA__DCOCLKDIV (0x0400u) /* ACLK Source Select DCOCLKDIV */
6827 #define SELA__XT2CLK (0x0500u) /* ACLK Source Select XT2CLK */
6828 
6829 /* UCSCTL5 Control Bits */
6830 #define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */
6831 #define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */
6832 #define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */
6833 //#define RESERVED (0x0008u) /* RESERVED */
6834 #define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */
6835 #define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */
6836 #define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */
6837 //#define RESERVED (0x0080u) /* RESERVED */
6838 #define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */
6839 #define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */
6840 #define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */
6841 //#define RESERVED (0x0800u) /* RESERVED */
6842 #define DIVPA0 (0x1000u) /* ACLK from Pin Divider Bit: 0 */
6843 #define DIVPA1 (0x2000u) /* ACLK from Pin Divider Bit: 1 */
6844 #define DIVPA2 (0x4000u) /* ACLK from Pin Divider Bit: 2 */
6845 //#define RESERVED (0x8000u) /* RESERVED */
6846 
6847 /* UCSCTL5 Control Bits */
6848 #define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */
6849 #define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */
6850 #define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */
6851 //#define RESERVED (0x0008u) /* RESERVED */
6852 #define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */
6853 #define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */
6854 #define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */
6855 //#define RESERVED (0x0080u) /* RESERVED */
6856 //#define RESERVED (0x0800u) /* RESERVED */
6857 //#define RESERVED (0x8000u) /* RESERVED */
6858 
6859 /* UCSCTL5 Control Bits */
6860 //#define RESERVED (0x0008u) /* RESERVED */
6861 //#define RESERVED (0x0080u) /* RESERVED */
6862 #define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */
6863 #define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */
6864 #define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */
6865 //#define RESERVED (0x0800u) /* RESERVED */
6866 #define DIVPA0_H (0x0010u) /* ACLK from Pin Divider Bit: 0 */
6867 #define DIVPA1_H (0x0020u) /* ACLK from Pin Divider Bit: 1 */
6868 #define DIVPA2_H (0x0040u) /* ACLK from Pin Divider Bit: 2 */
6869 //#define RESERVED (0x8000u) /* RESERVED */
6870 
6871 #define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */
6872 #define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */
6873 #define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */
6874 #define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */
6875 #define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */
6876 #define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */
6877 #define DIVM_6 (0x0006u) /* MCLK Source Divider 6 */
6878 #define DIVM_7 (0x0007u) /* MCLK Source Divider 7 */
6879 #define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */
6880 #define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */
6881 #define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */
6882 #define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */
6883 #define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */
6884 #define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */
6885 
6886 #define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */
6887 #define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */
6888 #define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */
6889 #define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */
6890 #define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */
6891 #define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */
6892 #define DIVS_6 (0x0060u) /* SMCLK Source Divider 6 */
6893 #define DIVS_7 (0x0070u) /* SMCLK Source Divider 7 */
6894 #define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */
6895 #define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */
6896 #define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */
6897 #define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */
6898 #define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */
6899 #define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */
6900 
6901 #define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */
6902 #define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */
6903 #define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */
6904 #define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */
6905 #define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */
6906 #define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */
6907 #define DIVA_6 (0x0600u) /* ACLK Source Divider 6 */
6908 #define DIVA_7 (0x0700u) /* ACLK Source Divider 7 */
6909 #define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */
6910 #define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */
6911 #define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */
6912 #define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */
6913 #define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */
6914 #define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */
6915 
6916 #define DIVPA_0 (0x0000u) /* ACLK from Pin Source Divider 0 */
6917 #define DIVPA_1 (0x1000u) /* ACLK from Pin Source Divider 1 */
6918 #define DIVPA_2 (0x2000u) /* ACLK from Pin Source Divider 2 */
6919 #define DIVPA_3 (0x3000u) /* ACLK from Pin Source Divider 3 */
6920 #define DIVPA_4 (0x4000u) /* ACLK from Pin Source Divider 4 */
6921 #define DIVPA_5 (0x5000u) /* ACLK from Pin Source Divider 5 */
6922 #define DIVPA_6 (0x6000u) /* ACLK from Pin Source Divider 6 */
6923 #define DIVPA_7 (0x7000u) /* ACLK from Pin Source Divider 7 */
6924 #define DIVPA__1 (0x0000u) /* ACLK from Pin Source Divider f(ACLK)/1 */
6925 #define DIVPA__2 (0x1000u) /* ACLK from Pin Source Divider f(ACLK)/2 */
6926 #define DIVPA__4 (0x2000u) /* ACLK from Pin Source Divider f(ACLK)/4 */
6927 #define DIVPA__8 (0x3000u) /* ACLK from Pin Source Divider f(ACLK)/8 */
6928 #define DIVPA__16 (0x4000u) /* ACLK from Pin Source Divider f(ACLK)/16 */
6929 #define DIVPA__32 (0x5000u) /* ACLK from Pin Source Divider f(ACLK)/32 */
6930 
6931 /* UCSCTL6 Control Bits */
6932 #define XT1OFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */
6933 #define SMCLKOFF (0x0002u) /* SMCLK Off */
6934 #define XCAP0 (0x0004u) /* XIN/XOUT Cap Bit: 0 */
6935 #define XCAP1 (0x0008u) /* XIN/XOUT Cap Bit: 1 */
6936 #define XT1BYPASS (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
6937 #define XTS (0x0020u) /* 1: Selects high-freq. oscillator */
6938 #define XT1DRIVE0 (0x0040u) /* XT1 Drive Level mode Bit 0 */
6939 #define XT1DRIVE1 (0x0080u) /* XT1 Drive Level mode Bit 1 */
6940 #define XT2OFF (0x0100u) /* High Frequency Oscillator 2 (XT2) disable */
6941 //#define RESERVED (0x0200u) /* RESERVED */
6942 //#define RESERVED (0x0400u) /* RESERVED */
6943 //#define RESERVED (0x0800u) /* RESERVED */
6944 #define XT2BYPASS (0x1000u) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
6945 //#define RESERVED (0x2000u) /* RESERVED */
6946 #define XT2DRIVE0 (0x4000u) /* XT2 Drive Level mode Bit 0 */
6947 #define XT2DRIVE1 (0x8000u) /* XT2 Drive Level mode Bit 1 */
6948 
6949 /* UCSCTL6 Control Bits */
6950 #define XT1OFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */
6951 #define SMCLKOFF_L (0x0002u) /* SMCLK Off */
6952 #define XCAP0_L (0x0004u) /* XIN/XOUT Cap Bit: 0 */
6953 #define XCAP1_L (0x0008u) /* XIN/XOUT Cap Bit: 1 */
6954 #define XT1BYPASS_L (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
6955 #define XTS_L (0x0020u) /* 1: Selects high-freq. oscillator */
6956 #define XT1DRIVE0_L (0x0040u) /* XT1 Drive Level mode Bit 0 */
6957 #define XT1DRIVE1_L (0x0080u) /* XT1 Drive Level mode Bit 1 */
6958 //#define RESERVED (0x0200u) /* RESERVED */
6959 //#define RESERVED (0x0400u) /* RESERVED */
6960 //#define RESERVED (0x0800u) /* RESERVED */
6961 //#define RESERVED (0x2000u) /* RESERVED */
6962 
6963 /* UCSCTL6 Control Bits */
6964 #define XT2OFF_H (0x0001u) /* High Frequency Oscillator 2 (XT2) disable */
6965 //#define RESERVED (0x0200u) /* RESERVED */
6966 //#define RESERVED (0x0400u) /* RESERVED */
6967 //#define RESERVED (0x0800u) /* RESERVED */
6968 #define XT2BYPASS_H (0x0010u) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
6969 //#define RESERVED (0x2000u) /* RESERVED */
6970 #define XT2DRIVE0_H (0x0040u) /* XT2 Drive Level mode Bit 0 */
6971 #define XT2DRIVE1_H (0x0080u) /* XT2 Drive Level mode Bit 1 */
6972 
6973 #define XCAP_0 (0x0000u) /* XIN/XOUT Cap 0 */
6974 #define XCAP_1 (0x0004u) /* XIN/XOUT Cap 1 */
6975 #define XCAP_2 (0x0008u) /* XIN/XOUT Cap 2 */
6976 #define XCAP_3 (0x000Cu) /* XIN/XOUT Cap 3 */
6977 #define XT1DRIVE_0 (0x0000u) /* XT1 Drive Level mode: 0 */
6978 #define XT1DRIVE_1 (0x0040u) /* XT1 Drive Level mode: 1 */
6979 #define XT1DRIVE_2 (0x0080u) /* XT1 Drive Level mode: 2 */
6980 #define XT1DRIVE_3 (0x00C0u) /* XT1 Drive Level mode: 3 */
6981 #define XT2DRIVE_0 (0x0000u) /* XT2 Drive Level mode: 0 */
6982 #define XT2DRIVE_1 (0x4000u) /* XT2 Drive Level mode: 1 */
6983 #define XT2DRIVE_2 (0x8000u) /* XT2 Drive Level mode: 2 */
6984 #define XT2DRIVE_3 (0xC000u) /* XT2 Drive Level mode: 3 */
6985 
6986 /* UCSCTL7 Control Bits */
6987 #define DCOFFG (0x0001u) /* DCO Fault Flag */
6988 #define XT1LFOFFG (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */
6989 #define XT1HFOFFG (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */
6990 #define XT2OFFG (0x0008u) /* High Frequency Oscillator 2 Fault Flag */
6991 //#define RESERVED (0x0010u) /* RESERVED */
6992 //#define RESERVED (0x0020u) /* RESERVED */
6993 //#define RESERVED (0x0040u) /* RESERVED */
6994 //#define RESERVED (0x0080u) /* RESERVED */
6995 //#define RESERVED (0x0100u) /* RESERVED */
6996 //#define RESERVED (0x0200u) /* RESERVED */
6997 //#define RESERVED (0x0400u) /* RESERVED */
6998 //#define RESERVED (0x0800u) /* RESERVED */
6999 //#define RESERVED (0x1000u) /* RESERVED */
7000 //#define RESERVED (0x2000u) /* RESERVED */
7001 //#define RESERVED (0x4000u) /* RESERVED */
7002 //#define RESERVED (0x8000u) /* RESERVED */
7003 
7004 /* UCSCTL7 Control Bits */
7005 #define DCOFFG_L (0x0001u) /* DCO Fault Flag */
7006 #define XT1LFOFFG_L (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */
7007 #define XT1HFOFFG_L (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */
7008 #define XT2OFFG_L (0x0008u) /* High Frequency Oscillator 2 Fault Flag */
7009 //#define RESERVED (0x0010u) /* RESERVED */
7010 //#define RESERVED (0x0020u) /* RESERVED */
7011 //#define RESERVED (0x0040u) /* RESERVED */
7012 //#define RESERVED (0x0080u) /* RESERVED */
7013 //#define RESERVED (0x0100u) /* RESERVED */
7014 //#define RESERVED (0x0200u) /* RESERVED */
7015 //#define RESERVED (0x0400u) /* RESERVED */
7016 //#define RESERVED (0x0800u) /* RESERVED */
7017 //#define RESERVED (0x1000u) /* RESERVED */
7018 //#define RESERVED (0x2000u) /* RESERVED */
7019 //#define RESERVED (0x4000u) /* RESERVED */
7020 //#define RESERVED (0x8000u) /* RESERVED */
7021 
7022 /* UCSCTL8 Control Bits */
7023 #define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */
7024 #define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */
7025 #define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */
7026 #define MODOSCREQEN (0x0008u) /* MODOSC Clock Request Enable */
7027 //#define RESERVED (0x0010u) /* RESERVED */
7028 //#define RESERVED (0x0020u) /* RESERVED */
7029 //#define RESERVED (0x0040u) /* RESERVED */
7030 //#define RESERVED (0x0080u) /* RESERVED */
7031 //#define RESERVED (0x0100u) /* RESERVED */
7032 //#define RESERVED (0x0200u) /* RESERVED */
7033 //#define RESERVED (0x0400u) /* RESERVED */
7034 //#define RESERVED (0x0800u) /* RESERVED */
7035 //#define RESERVED (0x1000u) /* RESERVED */
7036 //#define RESERVED (0x2000u) /* RESERVED */
7037 //#define RESERVED (0x4000u) /* RESERVED */
7038 //#define RESERVED (0x8000u) /* RESERVED */
7039 
7040 /* UCSCTL8 Control Bits */
7041 #define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */
7042 #define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */
7043 #define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */
7044 #define MODOSCREQEN_L (0x0008u) /* MODOSC Clock Request Enable */
7045 //#define RESERVED (0x0010u) /* RESERVED */
7046 //#define RESERVED (0x0020u) /* RESERVED */
7047 //#define RESERVED (0x0040u) /* RESERVED */
7048 //#define RESERVED (0x0080u) /* RESERVED */
7049 //#define RESERVED (0x0100u) /* RESERVED */
7050 //#define RESERVED (0x0200u) /* RESERVED */
7051 //#define RESERVED (0x0400u) /* RESERVED */
7052 //#define RESERVED (0x0800u) /* RESERVED */
7053 //#define RESERVED (0x1000u) /* RESERVED */
7054 //#define RESERVED (0x2000u) /* RESERVED */
7055 //#define RESERVED (0x4000u) /* RESERVED */
7056 //#define RESERVED (0x8000u) /* RESERVED */
7057 
7058 #endif
7059 /************************************************************
7060 * UNIFIED CLOCK SYSTEM FOR Radio Devices
7061 ************************************************************/
7062 #ifdef __MSP430_HAS_UCS_RF__ /* Definition to show that Module is available */
7063 
7064 #define OFS_UCSCTL0 (0x0000u) /* UCS Control Register 0 */
7065 #define OFS_UCSCTL0_L OFS_UCSCTL0
7066 #define OFS_UCSCTL0_H OFS_UCSCTL0+1
7067 #define OFS_UCSCTL1 (0x0002u) /* UCS Control Register 1 */
7068 #define OFS_UCSCTL1_L OFS_UCSCTL1
7069 #define OFS_UCSCTL1_H OFS_UCSCTL1+1
7070 #define OFS_UCSCTL2 (0x0004u) /* UCS Control Register 2 */
7071 #define OFS_UCSCTL2_L OFS_UCSCTL2
7072 #define OFS_UCSCTL2_H OFS_UCSCTL2+1
7073 #define OFS_UCSCTL3 (0x0006u) /* UCS Control Register 3 */
7074 #define OFS_UCSCTL3_L OFS_UCSCTL3
7075 #define OFS_UCSCTL3_H OFS_UCSCTL3+1
7076 #define OFS_UCSCTL4 (0x0008u) /* UCS Control Register 4 */
7077 #define OFS_UCSCTL4_L OFS_UCSCTL4
7078 #define OFS_UCSCTL4_H OFS_UCSCTL4+1
7079 #define OFS_UCSCTL5 (0x000Au) /* UCS Control Register 5 */
7080 #define OFS_UCSCTL5_L OFS_UCSCTL5
7081 #define OFS_UCSCTL5_H OFS_UCSCTL5+1
7082 #define OFS_UCSCTL6 (0x000Cu) /* UCS Control Register 6 */
7083 #define OFS_UCSCTL6_L OFS_UCSCTL6
7084 #define OFS_UCSCTL6_H OFS_UCSCTL6+1
7085 #define OFS_UCSCTL7 (0x000Eu) /* UCS Control Register 7 */
7086 #define OFS_UCSCTL7_L OFS_UCSCTL7
7087 #define OFS_UCSCTL7_H OFS_UCSCTL7+1
7088 #define OFS_UCSCTL8 (0x0010u) /* UCS Control Register 8 */
7089 #define OFS_UCSCTL8_L OFS_UCSCTL8
7090 #define OFS_UCSCTL8_H OFS_UCSCTL8+1
7091 
7092 /* UCSCTL0 Control Bits */
7093 //#define RESERVED (0x0001u) /* RESERVED */
7094 //#define RESERVED (0x0002u) /* RESERVED */
7095 //#define RESERVED (0x0004u) /* RESERVED */
7096 #define MOD0 (0x0008u) /* Modulation Bit Counter Bit : 0 */
7097 #define MOD1 (0x0010u) /* Modulation Bit Counter Bit : 1 */
7098 #define MOD2 (0x0020u) /* Modulation Bit Counter Bit : 2 */
7099 #define MOD3 (0x0040u) /* Modulation Bit Counter Bit : 3 */
7100 #define MOD4 (0x0080u) /* Modulation Bit Counter Bit : 4 */
7101 #define DCO0 (0x0100u) /* DCO TAP Bit : 0 */
7102 #define DCO1 (0x0200u) /* DCO TAP Bit : 1 */
7103 #define DCO2 (0x0400u) /* DCO TAP Bit : 2 */
7104 #define DCO3 (0x0800u) /* DCO TAP Bit : 3 */
7105 #define DCO4 (0x1000u) /* DCO TAP Bit : 4 */
7106 //#define RESERVED (0x2000u) /* RESERVED */
7107 //#define RESERVED (0x4000u) /* RESERVED */
7108 //#define RESERVED (0x8000u) /* RESERVED */
7109 
7110 /* UCSCTL0 Control Bits */
7111 //#define RESERVED (0x0001u) /* RESERVED */
7112 //#define RESERVED (0x0002u) /* RESERVED */
7113 //#define RESERVED (0x0004u) /* RESERVED */
7114 #define MOD0_L (0x0008u) /* Modulation Bit Counter Bit : 0 */
7115 #define MOD1_L (0x0010u) /* Modulation Bit Counter Bit : 1 */
7116 #define MOD2_L (0x0020u) /* Modulation Bit Counter Bit : 2 */
7117 #define MOD3_L (0x0040u) /* Modulation Bit Counter Bit : 3 */
7118 #define MOD4_L (0x0080u) /* Modulation Bit Counter Bit : 4 */
7119 //#define RESERVED (0x2000u) /* RESERVED */
7120 //#define RESERVED (0x4000u) /* RESERVED */
7121 //#define RESERVED (0x8000u) /* RESERVED */
7122 
7123 /* UCSCTL0 Control Bits */
7124 //#define RESERVED (0x0001u) /* RESERVED */
7125 //#define RESERVED (0x0002u) /* RESERVED */
7126 //#define RESERVED (0x0004u) /* RESERVED */
7127 #define DCO0_H (0x0001u) /* DCO TAP Bit : 0 */
7128 #define DCO1_H (0x0002u) /* DCO TAP Bit : 1 */
7129 #define DCO2_H (0x0004u) /* DCO TAP Bit : 2 */
7130 #define DCO3_H (0x0008u) /* DCO TAP Bit : 3 */
7131 #define DCO4_H (0x0010u) /* DCO TAP Bit : 4 */
7132 //#define RESERVED (0x2000u) /* RESERVED */
7133 //#define RESERVED (0x4000u) /* RESERVED */
7134 //#define RESERVED (0x8000u) /* RESERVED */
7135 
7136 /* UCSCTL1 Control Bits */
7137 #define DISMOD (0x0001u) /* Disable Modulation */
7138 //#define RESERVED (0x0002u) /* RESERVED */
7139 //#define RESERVED (0x0004u) /* RESERVED */
7140 //#define RESERVED (0x0008u) /* RESERVED */
7141 #define DCORSEL0 (0x0010u) /* DCO Freq. Range Select Bit : 0 */
7142 #define DCORSEL1 (0x0020u) /* DCO Freq. Range Select Bit : 1 */
7143 #define DCORSEL2 (0x0040u) /* DCO Freq. Range Select Bit : 2 */
7144 //#define RESERVED (0x0080u) /* RESERVED */
7145 //#define RESERVED (0x0100u) /* RESERVED */
7146 //#define RESERVED (0x0200u) /* RESERVED */
7147 //#define RESERVED (0x0400u) /* RESERVED */
7148 //#define RESERVED (0x0800u) /* RESERVED */
7149 //#define RESERVED (0x1000u) /* RESERVED */
7150 //#define RESERVED (0x2000u) /* RESERVED */
7151 //#define RESERVED (0x4000u) /* RESERVED */
7152 //#define RESERVED (0x8000u) /* RESERVED */
7153 
7154 /* UCSCTL1 Control Bits */
7155 #define DISMOD_L (0x0001u) /* Disable Modulation */
7156 //#define RESERVED (0x0002u) /* RESERVED */
7157 //#define RESERVED (0x0004u) /* RESERVED */
7158 //#define RESERVED (0x0008u) /* RESERVED */
7159 #define DCORSEL0_L (0x0010u) /* DCO Freq. Range Select Bit : 0 */
7160 #define DCORSEL1_L (0x0020u) /* DCO Freq. Range Select Bit : 1 */
7161 #define DCORSEL2_L (0x0040u) /* DCO Freq. Range Select Bit : 2 */
7162 //#define RESERVED (0x0080u) /* RESERVED */
7163 //#define RESERVED (0x0100u) /* RESERVED */
7164 //#define RESERVED (0x0200u) /* RESERVED */
7165 //#define RESERVED (0x0400u) /* RESERVED */
7166 //#define RESERVED (0x0800u) /* RESERVED */
7167 //#define RESERVED (0x1000u) /* RESERVED */
7168 //#define RESERVED (0x2000u) /* RESERVED */
7169 //#define RESERVED (0x4000u) /* RESERVED */
7170 //#define RESERVED (0x8000u) /* RESERVED */
7171 
7172 #define DCORSEL_0 (0x0000u) /* DCO RSEL 0 */
7173 #define DCORSEL_1 (0x0010u) /* DCO RSEL 1 */
7174 #define DCORSEL_2 (0x0020u) /* DCO RSEL 2 */
7175 #define DCORSEL_3 (0x0030u) /* DCO RSEL 3 */
7176 #define DCORSEL_4 (0x0040u) /* DCO RSEL 4 */
7177 #define DCORSEL_5 (0x0050u) /* DCO RSEL 5 */
7178 #define DCORSEL_6 (0x0060u) /* DCO RSEL 6 */
7179 #define DCORSEL_7 (0x0070u) /* DCO RSEL 7 */
7180 
7181 /* UCSCTL2 Control Bits */
7182 #define FLLN0 (0x0001u) /* FLL Multipier Bit : 0 */
7183 #define FLLN1 (0x0002u) /* FLL Multipier Bit : 1 */
7184 #define FLLN2 (0x0004u) /* FLL Multipier Bit : 2 */
7185 #define FLLN3 (0x0008u) /* FLL Multipier Bit : 3 */
7186 #define FLLN4 (0x0010u) /* FLL Multipier Bit : 4 */
7187 #define FLLN5 (0x0020u) /* FLL Multipier Bit : 5 */
7188 #define FLLN6 (0x0040u) /* FLL Multipier Bit : 6 */
7189 #define FLLN7 (0x0080u) /* FLL Multipier Bit : 7 */
7190 #define FLLN8 (0x0100u) /* FLL Multipier Bit : 8 */
7191 #define FLLN9 (0x0200u) /* FLL Multipier Bit : 9 */
7192 //#define RESERVED (0x0400u) /* RESERVED */
7193 //#define RESERVED (0x0800u) /* RESERVED */
7194 #define FLLD0 (0x1000u) /* Loop Divider Bit : 0 */
7195 #define FLLD1 (0x2000u) /* Loop Divider Bit : 1 */
7196 #define FLLD2 (0x4000u) /* Loop Divider Bit : 1 */
7197 //#define RESERVED (0x8000u) /* RESERVED */
7198 
7199 /* UCSCTL2 Control Bits */
7200 #define FLLN0_L (0x0001u) /* FLL Multipier Bit : 0 */
7201 #define FLLN1_L (0x0002u) /* FLL Multipier Bit : 1 */
7202 #define FLLN2_L (0x0004u) /* FLL Multipier Bit : 2 */
7203 #define FLLN3_L (0x0008u) /* FLL Multipier Bit : 3 */
7204 #define FLLN4_L (0x0010u) /* FLL Multipier Bit : 4 */
7205 #define FLLN5_L (0x0020u) /* FLL Multipier Bit : 5 */
7206 #define FLLN6_L (0x0040u) /* FLL Multipier Bit : 6 */
7207 #define FLLN7_L (0x0080u) /* FLL Multipier Bit : 7 */
7208 //#define RESERVED (0x0400u) /* RESERVED */
7209 //#define RESERVED (0x0800u) /* RESERVED */
7210 //#define RESERVED (0x8000u) /* RESERVED */
7211 
7212 /* UCSCTL2 Control Bits */
7213 #define FLLN8_H (0x0001u) /* FLL Multipier Bit : 8 */
7214 #define FLLN9_H (0x0002u) /* FLL Multipier Bit : 9 */
7215 //#define RESERVED (0x0400u) /* RESERVED */
7216 //#define RESERVED (0x0800u) /* RESERVED */
7217 #define FLLD0_H (0x0010u) /* Loop Divider Bit : 0 */
7218 #define FLLD1_H (0x0020u) /* Loop Divider Bit : 1 */
7219 #define FLLD2_H (0x0040u) /* Loop Divider Bit : 1 */
7220 //#define RESERVED (0x8000u) /* RESERVED */
7221 
7222 #define FLLD_0 (0x0000u) /* Multiply Selected Loop Freq. 1 */
7223 #define FLLD_1 (0x1000u) /* Multiply Selected Loop Freq. 2 */
7224 #define FLLD_2 (0x2000u) /* Multiply Selected Loop Freq. 4 */
7225 #define FLLD_3 (0x3000u) /* Multiply Selected Loop Freq. 8 */
7226 #define FLLD_4 (0x4000u) /* Multiply Selected Loop Freq. 16 */
7227 #define FLLD_5 (0x5000u) /* Multiply Selected Loop Freq. 32 */
7228 #define FLLD_6 (0x6000u) /* Multiply Selected Loop Freq. 32 */
7229 #define FLLD_7 (0x7000u) /* Multiply Selected Loop Freq. 32 */
7230 #define FLLD__1 (0x0000u) /* Multiply Selected Loop Freq. By 1 */
7231 #define FLLD__2 (0x1000u) /* Multiply Selected Loop Freq. By 2 */
7232 #define FLLD__4 (0x2000u) /* Multiply Selected Loop Freq. By 4 */
7233 #define FLLD__8 (0x3000u) /* Multiply Selected Loop Freq. By 8 */
7234 #define FLLD__16 (0x4000u) /* Multiply Selected Loop Freq. By 16 */
7235 #define FLLD__32 (0x5000u) /* Multiply Selected Loop Freq. By 32 */
7236 
7237 /* UCSCTL3 Control Bits */
7238 #define FLLREFDIV0 (0x0001u) /* Reference Divider Bit : 0 */
7239 #define FLLREFDIV1 (0x0002u) /* Reference Divider Bit : 1 */
7240 #define FLLREFDIV2 (0x0004u) /* Reference Divider Bit : 2 */
7241 //#define RESERVED (0x0008u) /* RESERVED */
7242 #define SELREF0 (0x0010u) /* FLL Reference Clock Select Bit : 0 */
7243 #define SELREF1 (0x0020u) /* FLL Reference Clock Select Bit : 1 */
7244 #define SELREF2 (0x0040u) /* FLL Reference Clock Select Bit : 2 */
7245 //#define RESERVED (0x0080u) /* RESERVED */
7246 //#define RESERVED (0x0100u) /* RESERVED */
7247 //#define RESERVED (0x0200u) /* RESERVED */
7248 //#define RESERVED (0x0400u) /* RESERVED */
7249 //#define RESERVED (0x0800u) /* RESERVED */
7250 //#define RESERVED (0x1000u) /* RESERVED */
7251 //#define RESERVED (0x2000u) /* RESERVED */
7252 //#define RESERVED (0x4000u) /* RESERVED */
7253 //#define RESERVED (0x8000u) /* RESERVED */
7254 
7255 /* UCSCTL3 Control Bits */
7256 #define FLLREFDIV0_L (0x0001u) /* Reference Divider Bit : 0 */
7257 #define FLLREFDIV1_L (0x0002u) /* Reference Divider Bit : 1 */
7258 #define FLLREFDIV2_L (0x0004u) /* Reference Divider Bit : 2 */
7259 //#define RESERVED (0x0008u) /* RESERVED */
7260 #define SELREF0_L (0x0010u) /* FLL Reference Clock Select Bit : 0 */
7261 #define SELREF1_L (0x0020u) /* FLL Reference Clock Select Bit : 1 */
7262 #define SELREF2_L (0x0040u) /* FLL Reference Clock Select Bit : 2 */
7263 //#define RESERVED (0x0080u) /* RESERVED */
7264 //#define RESERVED (0x0100u) /* RESERVED */
7265 //#define RESERVED (0x0200u) /* RESERVED */
7266 //#define RESERVED (0x0400u) /* RESERVED */
7267 //#define RESERVED (0x0800u) /* RESERVED */
7268 //#define RESERVED (0x1000u) /* RESERVED */
7269 //#define RESERVED (0x2000u) /* RESERVED */
7270 //#define RESERVED (0x4000u) /* RESERVED */
7271 //#define RESERVED (0x8000u) /* RESERVED */
7272 
7273 #define FLLREFDIV_0 (0x0000u) /* Reference Divider: f(LFCLK)/1 */
7274 #define FLLREFDIV_1 (0x0001u) /* Reference Divider: f(LFCLK)/2 */
7275 #define FLLREFDIV_2 (0x0002u) /* Reference Divider: f(LFCLK)/4 */
7276 #define FLLREFDIV_3 (0x0003u) /* Reference Divider: f(LFCLK)/8 */
7277 #define FLLREFDIV_4 (0x0004u) /* Reference Divider: f(LFCLK)/12 */
7278 #define FLLREFDIV_5 (0x0005u) /* Reference Divider: f(LFCLK)/16 */
7279 #define FLLREFDIV_6 (0x0006u) /* Reference Divider: f(LFCLK)/16 */
7280 #define FLLREFDIV_7 (0x0007u) /* Reference Divider: f(LFCLK)/16 */
7281 #define FLLREFDIV__1 (0x0000u) /* Reference Divider: f(LFCLK)/1 */
7282 #define FLLREFDIV__2 (0x0001u) /* Reference Divider: f(LFCLK)/2 */
7283 #define FLLREFDIV__4 (0x0002u) /* Reference Divider: f(LFCLK)/4 */
7284 #define FLLREFDIV__8 (0x0003u) /* Reference Divider: f(LFCLK)/8 */
7285 #define FLLREFDIV__12 (0x0004u) /* Reference Divider: f(LFCLK)/12 */
7286 #define FLLREFDIV__16 (0x0005u) /* Reference Divider: f(LFCLK)/16 */
7287 #define SELREF_0 (0x0000u) /* FLL Reference Clock Select 0 */
7288 #define SELREF_1 (0x0010u) /* FLL Reference Clock Select 1 */
7289 #define SELREF_2 (0x0020u) /* FLL Reference Clock Select 2 */
7290 #define SELREF_3 (0x0030u) /* FLL Reference Clock Select 3 */
7291 #define SELREF_4 (0x0040u) /* FLL Reference Clock Select 4 */
7292 #define SELREF_5 (0x0050u) /* FLL Reference Clock Select 5 */
7293 #define SELREF_6 (0x0060u) /* FLL Reference Clock Select 6 */
7294 #define SELREF_7 (0x0070u) /* FLL Reference Clock Select 7 */
7295 #define SELREF__XT1CLK (0x0000u) /* Multiply Selected Loop Freq. By XT1CLK */
7296 #define SELREF__REFOCLK (0x0020u) /* Multiply Selected Loop Freq. By REFOCLK */
7297 #define SELREF__XT2CLK (0x0050u) /* Multiply Selected Loop Freq. By XT2CLK */
7298 
7299 /* UCSCTL4 Control Bits */
7300 #define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */
7301 #define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */
7302 #define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */
7303 //#define RESERVED (0x0008u) /* RESERVED */
7304 #define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */
7305 #define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */
7306 #define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */
7307 //#define RESERVED (0x0080u) /* RESERVED */
7308 #define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */
7309 #define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */
7310 #define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */
7311 //#define RESERVED (0x0800u) /* RESERVED */
7312 //#define RESERVED (0x1000u) /* RESERVED */
7313 //#define RESERVED (0x2000u) /* RESERVED */
7314 //#define RESERVED (0x4000u) /* RESERVED */
7315 //#define RESERVED (0x8000u) /* RESERVED */
7316 
7317 /* UCSCTL4 Control Bits */
7318 #define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */
7319 #define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */
7320 #define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */
7321 //#define RESERVED (0x0008u) /* RESERVED */
7322 #define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */
7323 #define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */
7324 #define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */
7325 //#define RESERVED (0x0080u) /* RESERVED */
7326 //#define RESERVED (0x0800u) /* RESERVED */
7327 //#define RESERVED (0x1000u) /* RESERVED */
7328 //#define RESERVED (0x2000u) /* RESERVED */
7329 //#define RESERVED (0x4000u) /* RESERVED */
7330 //#define RESERVED (0x8000u) /* RESERVED */
7331 
7332 /* UCSCTL4 Control Bits */
7333 //#define RESERVED (0x0008u) /* RESERVED */
7334 //#define RESERVED (0x0080u) /* RESERVED */
7335 #define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */
7336 #define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */
7337 #define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */
7338 //#define RESERVED (0x0800u) /* RESERVED */
7339 //#define RESERVED (0x1000u) /* RESERVED */
7340 //#define RESERVED (0x2000u) /* RESERVED */
7341 //#define RESERVED (0x4000u) /* RESERVED */
7342 //#define RESERVED (0x8000u) /* RESERVED */
7343 
7344 #define SELM_0 (0x0000u) /* MCLK Source Select 0 */
7345 #define SELM_1 (0x0001u) /* MCLK Source Select 1 */
7346 #define SELM_2 (0x0002u) /* MCLK Source Select 2 */
7347 #define SELM_3 (0x0003u) /* MCLK Source Select 3 */
7348 #define SELM_4 (0x0004u) /* MCLK Source Select 4 */
7349 #define SELM_5 (0x0005u) /* MCLK Source Select 5 */
7350 #define SELM_6 (0x0006u) /* MCLK Source Select 6 */
7351 #define SELM_7 (0x0007u) /* MCLK Source Select 7 */
7352 #define SELM__XT1CLK (0x0000u) /* MCLK Source Select XT1CLK */
7353 #define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */
7354 #define SELM__REFOCLK (0x0002u) /* MCLK Source Select REFOCLK */
7355 #define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */
7356 #define SELM__DCOCLKDIV (0x0004u) /* MCLK Source Select DCOCLKDIV */
7357 #define SELM__XT2CLK (0x0005u) /* MCLK Source Select XT2CLK */
7358 
7359 #define SELS_0 (0x0000u) /* SMCLK Source Select 0 */
7360 #define SELS_1 (0x0010u) /* SMCLK Source Select 1 */
7361 #define SELS_2 (0x0020u) /* SMCLK Source Select 2 */
7362 #define SELS_3 (0x0030u) /* SMCLK Source Select 3 */
7363 #define SELS_4 (0x0040u) /* SMCLK Source Select 4 */
7364 #define SELS_5 (0x0050u) /* SMCLK Source Select 5 */
7365 #define SELS_6 (0x0060u) /* SMCLK Source Select 6 */
7366 #define SELS_7 (0x0070u) /* SMCLK Source Select 7 */
7367 #define SELS__XT1CLK (0x0000u) /* SMCLK Source Select XT1CLK */
7368 #define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */
7369 #define SELS__REFOCLK (0x0020u) /* SMCLK Source Select REFOCLK */
7370 #define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */
7371 #define SELS__DCOCLKDIV (0x0040u) /* SMCLK Source Select DCOCLKDIV */
7372 #define SELS__XT2CLK (0x0050u) /* SMCLK Source Select XT2CLK */
7373 
7374 #define SELA_0 (0x0000u) /* ACLK Source Select 0 */
7375 #define SELA_1 (0x0100u) /* ACLK Source Select 1 */
7376 #define SELA_2 (0x0200u) /* ACLK Source Select 2 */
7377 #define SELA_3 (0x0300u) /* ACLK Source Select 3 */
7378 #define SELA_4 (0x0400u) /* ACLK Source Select 4 */
7379 #define SELA_5 (0x0500u) /* ACLK Source Select 5 */
7380 #define SELA_6 (0x0600u) /* ACLK Source Select 6 */
7381 #define SELA_7 (0x0700u) /* ACLK Source Select 7 */
7382 #define SELA__XT1CLK (0x0000u) /* ACLK Source Select XT1CLK */
7383 #define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */
7384 #define SELA__REFOCLK (0x0200u) /* ACLK Source Select REFOCLK */
7385 #define SELA__DCOCLK (0x0300u) /* ACLK Source Select DCOCLK */
7386 #define SELA__DCOCLKDIV (0x0400u) /* ACLK Source Select DCOCLKDIV */
7387 #define SELA__XT2CLK (0x0500u) /* ACLK Source Select XT2CLK */
7388 
7389 /* UCSCTL5 Control Bits */
7390 #define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */
7391 #define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */
7392 #define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */
7393 //#define RESERVED (0x0008u) /* RESERVED */
7394 #define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */
7395 #define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */
7396 #define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */
7397 //#define RESERVED (0x0080u) /* RESERVED */
7398 #define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */
7399 #define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */
7400 #define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */
7401 //#define RESERVED (0x0800u) /* RESERVED */
7402 #define DIVPA0 (0x1000u) /* ACLK from Pin Divider Bit: 0 */
7403 #define DIVPA1 (0x2000u) /* ACLK from Pin Divider Bit: 1 */
7404 #define DIVPA2 (0x4000u) /* ACLK from Pin Divider Bit: 2 */
7405 //#define RESERVED (0x8000u) /* RESERVED */
7406 
7407 /* UCSCTL5 Control Bits */
7408 #define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */
7409 #define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */
7410 #define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */
7411 //#define RESERVED (0x0008u) /* RESERVED */
7412 #define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */
7413 #define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */
7414 #define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */
7415 //#define RESERVED (0x0080u) /* RESERVED */
7416 //#define RESERVED (0x0800u) /* RESERVED */
7417 //#define RESERVED (0x8000u) /* RESERVED */
7418 
7419 /* UCSCTL5 Control Bits */
7420 //#define RESERVED (0x0008u) /* RESERVED */
7421 //#define RESERVED (0x0080u) /* RESERVED */
7422 #define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */
7423 #define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */
7424 #define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */
7425 //#define RESERVED (0x0800u) /* RESERVED */
7426 #define DIVPA0_H (0x0010u) /* ACLK from Pin Divider Bit: 0 */
7427 #define DIVPA1_H (0x0020u) /* ACLK from Pin Divider Bit: 1 */
7428 #define DIVPA2_H (0x0040u) /* ACLK from Pin Divider Bit: 2 */
7429 //#define RESERVED (0x8000u) /* RESERVED */
7430 
7431 #define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */
7432 #define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */
7433 #define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */
7434 #define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */
7435 #define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */
7436 #define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */
7437 #define DIVM_6 (0x0006u) /* MCLK Source Divider 6 */
7438 #define DIVM_7 (0x0007u) /* MCLK Source Divider 7 */
7439 #define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */
7440 #define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */
7441 #define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */
7442 #define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */
7443 #define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */
7444 #define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */
7445 
7446 #define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */
7447 #define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */
7448 #define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */
7449 #define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */
7450 #define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */
7451 #define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */
7452 #define DIVS_6 (0x0060u) /* SMCLK Source Divider 6 */
7453 #define DIVS_7 (0x0070u) /* SMCLK Source Divider 7 */
7454 #define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */
7455 #define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */
7456 #define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */
7457 #define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */
7458 #define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */
7459 #define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */
7460 
7461 #define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */
7462 #define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */
7463 #define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */
7464 #define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */
7465 #define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */
7466 #define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */
7467 #define DIVA_6 (0x0600u) /* ACLK Source Divider 6 */
7468 #define DIVA_7 (0x0700u) /* ACLK Source Divider 7 */
7469 #define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */
7470 #define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */
7471 #define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */
7472 #define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */
7473 #define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */
7474 #define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */
7475 
7476 #define DIVPA_0 (0x0000u) /* ACLK from Pin Source Divider 0 */
7477 #define DIVPA_1 (0x1000u) /* ACLK from Pin Source Divider 1 */
7478 #define DIVPA_2 (0x2000u) /* ACLK from Pin Source Divider 2 */
7479 #define DIVPA_3 (0x3000u) /* ACLK from Pin Source Divider 3 */
7480 #define DIVPA_4 (0x4000u) /* ACLK from Pin Source Divider 4 */
7481 #define DIVPA_5 (0x5000u) /* ACLK from Pin Source Divider 5 */
7482 #define DIVPA_6 (0x6000u) /* ACLK from Pin Source Divider 6 */
7483 #define DIVPA_7 (0x7000u) /* ACLK from Pin Source Divider 7 */
7484 #define DIVPA__1 (0x0000u) /* ACLK from Pin Source Divider f(ACLK)/1 */
7485 #define DIVPA__2 (0x1000u) /* ACLK from Pin Source Divider f(ACLK)/2 */
7486 #define DIVPA__4 (0x2000u) /* ACLK from Pin Source Divider f(ACLK)/4 */
7487 #define DIVPA__8 (0x3000u) /* ACLK from Pin Source Divider f(ACLK)/8 */
7488 #define DIVPA__16 (0x4000u) /* ACLK from Pin Source Divider f(ACLK)/16 */
7489 #define DIVPA__32 (0x5000u) /* ACLK from Pin Source Divider f(ACLK)/32 */
7490 
7491 /* UCSCTL6 Control Bits */
7492 #define XT1OFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */
7493 #define SMCLKOFF (0x0002u) /* SMCLK Off */
7494 #define XCAP0 (0x0004u) /* XIN/XOUT Cap Bit: 0 */
7495 #define XCAP1 (0x0008u) /* XIN/XOUT Cap Bit: 1 */
7496 #define XT1BYPASS (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
7497 #define XTS (0x0020u) /* 1: Selects high-freq. oscillator */
7498 #define XT1DRIVE0 (0x0040u) /* XT1 Drive Level mode Bit 0 */
7499 #define XT1DRIVE1 (0x0080u) /* XT1 Drive Level mode Bit 1 */
7500 #define XT2OFF (0x0100u) /* High Frequency Oscillator 2 (XT2) disable */
7501 //#define RESERVED (0x0200u) /* RESERVED */
7502 //#define RESERVED (0x0400u) /* RESERVED */
7503 //#define RESERVED (0x0800u) /* RESERVED */
7504 //#define RESERVED (0x1000u) /* RESERVED */
7505 //#define RESERVED (0x2000u) /* RESERVED */
7506 //#define RESERVED (0x4000u) /* RESERVED */
7507 //#define RESERVED (0x8000u) /* RESERVED */
7508 
7509 /* UCSCTL6 Control Bits */
7510 #define XT1OFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */
7511 #define SMCLKOFF_L (0x0002u) /* SMCLK Off */
7512 #define XCAP0_L (0x0004u) /* XIN/XOUT Cap Bit: 0 */
7513 #define XCAP1_L (0x0008u) /* XIN/XOUT Cap Bit: 1 */
7514 #define XT1BYPASS_L (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
7515 #define XTS_L (0x0020u) /* 1: Selects high-freq. oscillator */
7516 #define XT1DRIVE0_L (0x0040u) /* XT1 Drive Level mode Bit 0 */
7517 #define XT1DRIVE1_L (0x0080u) /* XT1 Drive Level mode Bit 1 */
7518 //#define RESERVED (0x0200u) /* RESERVED */
7519 //#define RESERVED (0x0400u) /* RESERVED */
7520 //#define RESERVED (0x0800u) /* RESERVED */
7521 //#define RESERVED (0x1000u) /* RESERVED */
7522 //#define RESERVED (0x2000u) /* RESERVED */
7523 //#define RESERVED (0x4000u) /* RESERVED */
7524 //#define RESERVED (0x8000u) /* RESERVED */
7525 
7526 /* UCSCTL6 Control Bits */
7527 #define XT2OFF_H (0x0001u) /* High Frequency Oscillator 2 (XT2) disable */
7528 //#define RESERVED (0x0200u) /* RESERVED */
7529 //#define RESERVED (0x0400u) /* RESERVED */
7530 //#define RESERVED (0x0800u) /* RESERVED */
7531 //#define RESERVED (0x1000u) /* RESERVED */
7532 //#define RESERVED (0x2000u) /* RESERVED */
7533 //#define RESERVED (0x4000u) /* RESERVED */
7534 //#define RESERVED (0x8000u) /* RESERVED */
7535 
7536 #define XCAP_0 (0x0000u) /* XIN/XOUT Cap 0 */
7537 #define XCAP_1 (0x0004u) /* XIN/XOUT Cap 1 */
7538 #define XCAP_2 (0x0008u) /* XIN/XOUT Cap 2 */
7539 #define XCAP_3 (0x000Cu) /* XIN/XOUT Cap 3 */
7540 #define XT1DRIVE_0 (0x0000u) /* XT1 Drive Level mode: 0 */
7541 #define XT1DRIVE_1 (0x0040u) /* XT1 Drive Level mode: 1 */
7542 #define XT1DRIVE_2 (0x0080u) /* XT1 Drive Level mode: 2 */
7543 #define XT1DRIVE_3 (0x00C0u) /* XT1 Drive Level mode: 3 */
7544 
7545 /* UCSCTL7 Control Bits */
7546 #define DCOFFG (0x0001u) /* DCO Fault Flag */
7547 #define XT1LFOFFG (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */
7548 #define XT1HFOFFG (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */
7549 #define XT2OFFG (0x0008u) /* High Frequency Oscillator 2 Fault Flag */
7550 //#define RESERVED (0x0010u) /* RESERVED */
7551 //#define RESERVED (0x0020u) /* RESERVED */
7552 //#define RESERVED (0x0040u) /* RESERVED */
7553 //#define RESERVED (0x0080u) /* RESERVED */
7554 //#define RESERVED (0x0100u) /* RESERVED */
7555 //#define RESERVED (0x0200u) /* RESERVED */
7556 //#define RESERVED (0x0400u) /* RESERVED */
7557 //#define RESERVED (0x0800u) /* RESERVED */
7558 //#define RESERVED (0x1000u) /* RESERVED */
7559 //#define RESERVED (0x2000u) /* RESERVED */
7560 //#define RESERVED (0x4000u) /* RESERVED */
7561 //#define RESERVED (0x8000u) /* RESERVED */
7562 
7563 /* UCSCTL7 Control Bits */
7564 #define DCOFFG_L (0x0001u) /* DCO Fault Flag */
7565 #define XT1LFOFFG_L (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */
7566 #define XT1HFOFFG_L (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */
7567 #define XT2OFFG_L (0x0008u) /* High Frequency Oscillator 2 Fault Flag */
7568 //#define RESERVED (0x0010u) /* RESERVED */
7569 //#define RESERVED (0x0020u) /* RESERVED */
7570 //#define RESERVED (0x0040u) /* RESERVED */
7571 //#define RESERVED (0x0080u) /* RESERVED */
7572 //#define RESERVED (0x0100u) /* RESERVED */
7573 //#define RESERVED (0x0200u) /* RESERVED */
7574 //#define RESERVED (0x0400u) /* RESERVED */
7575 //#define RESERVED (0x0800u) /* RESERVED */
7576 //#define RESERVED (0x1000u) /* RESERVED */
7577 //#define RESERVED (0x2000u) /* RESERVED */
7578 //#define RESERVED (0x4000u) /* RESERVED */
7579 //#define RESERVED (0x8000u) /* RESERVED */
7580 
7581 /* UCSCTL8 Control Bits */
7582 #define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */
7583 #define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */
7584 #define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */
7585 #define MODOSCREQEN (0x0008u) /* MODOSC Clock Request Enable */
7586 //#define RESERVED (0x0010u) /* RESERVED */
7587 //#define RESERVED (0x0020u) /* RESERVED */
7588 //#define RESERVED (0x0040u) /* RESERVED */
7589 //#define RESERVED (0x0080u) /* RESERVED */
7590 //#define RESERVED (0x0100u) /* RESERVED */
7591 //#define RESERVED (0x0200u) /* RESERVED */
7592 //#define RESERVED (0x0400u) /* RESERVED */
7593 //#define RESERVED (0x0800u) /* RESERVED */
7594 //#define RESERVED (0x1000u) /* RESERVED */
7595 //#define RESERVED (0x2000u) /* RESERVED */
7596 //#define RESERVED (0x4000u) /* RESERVED */
7597 //#define RESERVED (0x8000u) /* RESERVED */
7598 
7599 /* UCSCTL8 Control Bits */
7600 #define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */
7601 #define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */
7602 #define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */
7603 #define MODOSCREQEN_L (0x0008u) /* MODOSC Clock Request Enable */
7604 //#define RESERVED (0x0010u) /* RESERVED */
7605 //#define RESERVED (0x0020u) /* RESERVED */
7606 //#define RESERVED (0x0040u) /* RESERVED */
7607 //#define RESERVED (0x0080u) /* RESERVED */
7608 //#define RESERVED (0x0100u) /* RESERVED */
7609 //#define RESERVED (0x0200u) /* RESERVED */
7610 //#define RESERVED (0x0400u) /* RESERVED */
7611 //#define RESERVED (0x0800u) /* RESERVED */
7612 //#define RESERVED (0x1000u) /* RESERVED */
7613 //#define RESERVED (0x2000u) /* RESERVED */
7614 //#define RESERVED (0x4000u) /* RESERVED */
7615 //#define RESERVED (0x8000u) /* RESERVED */
7616 
7617 #endif
7618 /************************************************************
7619 * USB
7620 ************************************************************/
7621 #ifdef __MSP430_HAS_USB__ /* Definition to show that Module is available */
7622 
7623 /* ========================================================================= */
7624 /* USB Configuration Registers */
7625 /* ========================================================================= */
7626 #define OFS_USBKEYID (0x0000u) /* USB Controller key register */
7627 #define OFS_USBKEYID_L OFS_USBKEYID
7628 #define OFS_USBKEYID_H OFS_USBKEYID+1
7629 #define OFS_USBCNF (0x0002u) /* USB Module configuration register */
7630 #define OFS_USBCNF_L OFS_USBCNF
7631 #define OFS_USBCNF_H OFS_USBCNF+1
7632 #define OFS_USBPHYCTL (0x0004u) /* USB PHY control register */
7633 #define OFS_USBPHYCTL_L OFS_USBPHYCTL
7634 #define OFS_USBPHYCTL_H OFS_USBPHYCTL+1
7635 #define OFS_USBPWRCTL (0x0008u) /* USB Power control register */
7636 #define OFS_USBPWRCTL_L OFS_USBPWRCTL
7637 #define OFS_USBPWRCTL_H OFS_USBPWRCTL+1
7638 #define OFS_USBPLLCTL (0x0010u) /* USB PLL control register */
7639 #define OFS_USBPLLCTL_L OFS_USBPLLCTL
7640 #define OFS_USBPLLCTL_H OFS_USBPLLCTL+1
7641 #define OFS_USBPLLDIVB (0x0012u) /* USB PLL Clock Divider Buffer control register */
7642 #define OFS_USBPLLDIVB_L OFS_USBPLLDIVB
7643 #define OFS_USBPLLDIVB_H OFS_USBPLLDIVB+1
7644 #define OFS_USBPLLIR (0x0014u) /* USB PLL Interrupt control register */
7645 #define OFS_USBPLLIR_L OFS_USBPLLIR
7646 #define OFS_USBPLLIR_H OFS_USBPLLIR+1
7647 
7648 #define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */
7649 #define USBKEY (0x9628u) /* USB Control Register key */
7650 
7651 /* USBCNF Control Bits */
7652 #define USB_EN (0x0001u) /* USB - Module enable */
7653 #define PUR_EN (0x0002u) /* USB - PUR pin enable */
7654 #define PUR_IN (0x0004u) /* USB - PUR pin input value */
7655 #define BLKRDY (0x0008u) /* USB - Block ready signal for DMA */
7656 #define FNTEN (0x0010u) /* USB - Frame Number receive Trigger enable for DMA */
7657 //#define RESERVED (0x0020u) /* USB - */
7658 //#define RESERVED (0x0040u) /* USB - */
7659 //#define RESERVED (0x0080u) /* USB - */
7660 //#define RESERVED (0x0100u) /* USB - */
7661 //#define RESERVED (0x0200u) /* USB - */
7662 //#define RESERVED (0x0400u) /* USB - */
7663 //#define RESERVED (0x0800u) /* USB - */
7664 //#define RESERVED (0x1000u) /* USB - */
7665 //#define RESERVED (0x2000u) /* USB - */
7666 //#define RESERVED (0x4000u) /* USB - */
7667 //#define RESERVED (0x8000u) /* USB - */
7668 
7669 /* USBCNF Control Bits */
7670 #define USB_EN_L (0x0001u) /* USB - Module enable */
7671 #define PUR_EN_L (0x0002u) /* USB - PUR pin enable */
7672 #define PUR_IN_L (0x0004u) /* USB - PUR pin input value */
7673 #define BLKRDY_L (0x0008u) /* USB - Block ready signal for DMA */
7674 #define FNTEN_L (0x0010u) /* USB - Frame Number receive Trigger enable for DMA */
7675 //#define RESERVED (0x0020u) /* USB - */
7676 //#define RESERVED (0x0040u) /* USB - */
7677 //#define RESERVED (0x0080u) /* USB - */
7678 //#define RESERVED (0x0100u) /* USB - */
7679 //#define RESERVED (0x0200u) /* USB - */
7680 //#define RESERVED (0x0400u) /* USB - */
7681 //#define RESERVED (0x0800u) /* USB - */
7682 //#define RESERVED (0x1000u) /* USB - */
7683 //#define RESERVED (0x2000u) /* USB - */
7684 //#define RESERVED (0x4000u) /* USB - */
7685 //#define RESERVED (0x8000u) /* USB - */
7686 
7687 /* USBPHYCTL Control Bits */
7688 #define PUOUT0 (0x0001u) /* USB - USB Port Output Signal Bit 0 */
7689 #define PUOUT1 (0x0002u) /* USB - USB Port Output Signal Bit 1 */
7690 #define PUIN0 (0x0004u) /* USB - PU0/DP Input Data */
7691 #define PUIN1 (0x0008u) /* USB - PU1/DM Input Data */
7692 //#define RESERVED (0x0010u) /* USB - */
7693 #define PUOPE (0x0020u) /* USB - USB Port Output Enable */
7694 //#define RESERVED (0x0040u) /* USB - */
7695 #define PUSEL (0x0080u) /* USB - USB Port Function Select */
7696 #define PUIPE (0x0100u) /* USB - PHY Single Ended Input enable */
7697 //#define RESERVED (0x0200u) /* USB - */
7698 //#define RESERVED (0x0100u) /* USB - */
7699 //#define RESERVED (0x0200u) /* USB - */
7700 //#define RESERVED (0x0400u) /* USB - */
7701 //#define RESERVED (0x0800u) /* USB - */
7702 //#define RESERVED (0x1000u) /* USB - */
7703 //#define RESERVED (0x2000u) /* USB - */
7704 //#define RESERVED (0x4000u) /* USB - */
7705 //#define RESERVED (0x8000u) /* USB - */
7706 
7707 /* USBPHYCTL Control Bits */
7708 #define PUOUT0_L (0x0001u) /* USB - USB Port Output Signal Bit 0 */
7709 #define PUOUT1_L (0x0002u) /* USB - USB Port Output Signal Bit 1 */
7710 #define PUIN0_L (0x0004u) /* USB - PU0/DP Input Data */
7711 #define PUIN1_L (0x0008u) /* USB - PU1/DM Input Data */
7712 //#define RESERVED (0x0010u) /* USB - */
7713 #define PUOPE_L (0x0020u) /* USB - USB Port Output Enable */
7714 //#define RESERVED (0x0040u) /* USB - */
7715 #define PUSEL_L (0x0080u) /* USB - USB Port Function Select */
7716 //#define RESERVED (0x0200u) /* USB - */
7717 //#define RESERVED (0x0100u) /* USB - */
7718 //#define RESERVED (0x0200u) /* USB - */
7719 //#define RESERVED (0x0400u) /* USB - */
7720 //#define RESERVED (0x0800u) /* USB - */
7721 //#define RESERVED (0x1000u) /* USB - */
7722 //#define RESERVED (0x2000u) /* USB - */
7723 //#define RESERVED (0x4000u) /* USB - */
7724 //#define RESERVED (0x8000u) /* USB - */
7725 
7726 /* USBPHYCTL Control Bits */
7727 //#define RESERVED (0x0010u) /* USB - */
7728 //#define RESERVED (0x0040u) /* USB - */
7729 #define PUIPE_H (0x0001u) /* USB - PHY Single Ended Input enable */
7730 //#define RESERVED (0x0200u) /* USB - */
7731 //#define RESERVED (0x0100u) /* USB - */
7732 //#define RESERVED (0x0200u) /* USB - */
7733 //#define RESERVED (0x0400u) /* USB - */
7734 //#define RESERVED (0x0800u) /* USB - */
7735 //#define RESERVED (0x1000u) /* USB - */
7736 //#define RESERVED (0x2000u) /* USB - */
7737 //#define RESERVED (0x4000u) /* USB - */
7738 //#define RESERVED (0x8000u) /* USB - */
7739 
7740 #define PUDIR (0x0020u) /* USB - Legacy Definition: USB Port Output Enable */
7741 #define PSEIEN (0x0100u) /* USB - Legacy Definition: PHY Single Ended Input enable */
7742 
7743 /* USBPWRCTL Control Bits */
7744 #define VUOVLIFG (0x0001u) /* USB - VUSB Overload Interrupt Flag */
7745 #define VBONIFG (0x0002u) /* USB - VBUS "Coming ON" Interrupt Flag */
7746 #define VBOFFIFG (0x0004u) /* USB - VBUS "Going OFF" Interrupt Flag */
7747 #define USBBGVBV (0x0008u) /* USB - USB Bandgap and VBUS valid */
7748 #define USBDETEN (0x0010u) /* USB - VBUS on/off events enable */
7749 #define OVLAOFF (0x0020u) /* USB - LDO overload auto off enable */
7750 #define SLDOAON (0x0040u) /* USB - Secondary LDO auto on enable */
7751 //#define RESERVED (0x0080u) /* USB - */
7752 #define VUOVLIE (0x0100u) /* USB - Overload indication Interrupt Enable */
7753 #define VBONIE (0x0200u) /* USB - VBUS "Coming ON" Interrupt Enable */
7754 #define VBOFFIE (0x0400u) /* USB - VBUS "Going OFF" Interrupt Enable */
7755 #define VUSBEN (0x0800u) /* USB - LDO Enable (3.3V) */
7756 #define SLDOEN (0x1000u) /* USB - Secondary LDO Enable (1.8V) */
7757 //#define RESERVED (0x2000u) /* USB - */
7758 //#define RESERVED (0x4000u) /* USB - */
7759 //#define RESERVED (0x8000u) /* USB - */
7760 
7761 /* USBPWRCTL Control Bits */
7762 #define VUOVLIFG_L (0x0001u) /* USB - VUSB Overload Interrupt Flag */
7763 #define VBONIFG_L (0x0002u) /* USB - VBUS "Coming ON" Interrupt Flag */
7764 #define VBOFFIFG_L (0x0004u) /* USB - VBUS "Going OFF" Interrupt Flag */
7765 #define USBBGVBV_L (0x0008u) /* USB - USB Bandgap and VBUS valid */
7766 #define USBDETEN_L (0x0010u) /* USB - VBUS on/off events enable */
7767 #define OVLAOFF_L (0x0020u) /* USB - LDO overload auto off enable */
7768 #define SLDOAON_L (0x0040u) /* USB - Secondary LDO auto on enable */
7769 //#define RESERVED (0x0080u) /* USB - */
7770 //#define RESERVED (0x2000u) /* USB - */
7771 //#define RESERVED (0x4000u) /* USB - */
7772 //#define RESERVED (0x8000u) /* USB - */
7773 
7774 /* USBPWRCTL Control Bits */
7775 //#define RESERVED (0x0080u) /* USB - */
7776 #define VUOVLIE_H (0x0001u) /* USB - Overload indication Interrupt Enable */
7777 #define VBONIE_H (0x0002u) /* USB - VBUS "Coming ON" Interrupt Enable */
7778 #define VBOFFIE_H (0x0004u) /* USB - VBUS "Going OFF" Interrupt Enable */
7779 #define VUSBEN_H (0x0008u) /* USB - LDO Enable (3.3V) */
7780 #define SLDOEN_H (0x0010u) /* USB - Secondary LDO Enable (1.8V) */
7781 //#define RESERVED (0x2000u) /* USB - */
7782 //#define RESERVED (0x4000u) /* USB - */
7783 //#define RESERVED (0x8000u) /* USB - */
7784 
7785 /* USBPLLCTL Control Bits */
7786 //#define RESERVED (0x0001u) /* USB - */
7787 //#define RESERVED (0x0002u) /* USB - */
7788 //#define RESERVED (0x0004u) /* USB - */
7789 //#define RESERVED (0x0008u) /* USB - */
7790 //#define RESERVED (0x0010u) /* USB - */
7791 //#define RESERVED (0x0020u) /* USB - */
7792 #define UCLKSEL0 (0x0040u) /* USB - Module Clock Select Bit 0 */
7793 #define UCLKSEL1 (0x0080u) /* USB - Module Clock Select Bit 1 */
7794 #define UPLLEN (0x0100u) /* USB - PLL enable */
7795 #define UPFDEN (0x0200u) /* USB - Phase Freq. Discriminator enable */
7796 //#define RESERVED (0x0400u) /* USB - */
7797 //#define RESERVED (0x0800u) /* USB - */
7798 //#define RESERVED (0x1000u) /* USB - */
7799 //#define RESERVED (0x2000u) /* USB - */
7800 //#define RESERVED (0x4000u) /* USB - */
7801 //#define RESERVED (0x8000u) /* USB - */
7802 
7803 /* USBPLLCTL Control Bits */
7804 //#define RESERVED (0x0001u) /* USB - */
7805 //#define RESERVED (0x0002u) /* USB - */
7806 //#define RESERVED (0x0004u) /* USB - */
7807 //#define RESERVED (0x0008u) /* USB - */
7808 //#define RESERVED (0x0010u) /* USB - */
7809 //#define RESERVED (0x0020u) /* USB - */
7810 #define UCLKSEL0_L (0x0040u) /* USB - Module Clock Select Bit 0 */
7811 #define UCLKSEL1_L (0x0080u) /* USB - Module Clock Select Bit 1 */
7812 //#define RESERVED (0x0400u) /* USB - */
7813 //#define RESERVED (0x0800u) /* USB - */
7814 //#define RESERVED (0x1000u) /* USB - */
7815 //#define RESERVED (0x2000u) /* USB - */
7816 //#define RESERVED (0x4000u) /* USB - */
7817 //#define RESERVED (0x8000u) /* USB - */
7818 
7819 /* USBPLLCTL Control Bits */
7820 //#define RESERVED (0x0001u) /* USB - */
7821 //#define RESERVED (0x0002u) /* USB - */
7822 //#define RESERVED (0x0004u) /* USB - */
7823 //#define RESERVED (0x0008u) /* USB - */
7824 //#define RESERVED (0x0010u) /* USB - */
7825 //#define RESERVED (0x0020u) /* USB - */
7826 #define UPLLEN_H (0x0001u) /* USB - PLL enable */
7827 #define UPFDEN_H (0x0002u) /* USB - Phase Freq. Discriminator enable */
7828 //#define RESERVED (0x0400u) /* USB - */
7829 //#define RESERVED (0x0800u) /* USB - */
7830 //#define RESERVED (0x1000u) /* USB - */
7831 //#define RESERVED (0x2000u) /* USB - */
7832 //#define RESERVED (0x4000u) /* USB - */
7833 //#define RESERVED (0x8000u) /* USB - */
7834 
7835 #define UCLKSEL_0 (0x0000u) /* USB - Module Clock Select: 0 */
7836 #define UCLKSEL_1 (0x0040u) /* USB - Module Clock Select: 1 */
7837 #define UCLKSEL_2 (0x0080u) /* USB - Module Clock Select: 2 */
7838 #define UCLKSEL_3 (0x00C0u) /* USB - Module Clock Select: 3 (Reserved) */
7839 
7840 #define UCLKSEL__PLLCLK (0x0000u) /* USB - Module Clock Select: PLLCLK */
7841 #define UCLKSEL__XT1CLK (0x0040u) /* USB - Module Clock Select: XT1CLK */
7842 #define UCLKSEL__XT2CLK (0x0080u) /* USB - Module Clock Select: XT2CLK */
7843 
7844 /* USBPLLDIVB Control Bits */
7845 #define UPMB0 (0x0001u) /* USB - PLL feedback divider buffer Bit 0 */
7846 #define UPMB1 (0x0002u) /* USB - PLL feedback divider buffer Bit 1 */
7847 #define UPMB2 (0x0004u) /* USB - PLL feedback divider buffer Bit 2 */
7848 #define UPMB3 (0x0008u) /* USB - PLL feedback divider buffer Bit 3 */
7849 #define UPMB4 (0x0010u) /* USB - PLL feedback divider buffer Bit 4 */
7850 #define UPMB5 (0x0020u) /* USB - PLL feedback divider buffer Bit 5 */
7851 //#define RESERVED (0x0040u) /* USB - */
7852 //#define RESERVED (0x0080u) /* USB - */
7853 #define UPQB0 (0x0100u) /* USB - PLL prescale divider buffer Bit 0 */
7854 #define UPQB1 (0x0200u) /* USB - PLL prescale divider buffer Bit 1 */
7855 #define UPQB2 (0x0400u) /* USB - PLL prescale divider buffer Bit 2 */
7856 //#define RESERVED (0x0800u) /* USB - */
7857 //#define RESERVED (0x1000u) /* USB - */
7858 //#define RESERVED (0x2000u) /* USB - */
7859 //#define RESERVED (0x4000u) /* USB - */
7860 //#define RESERVED (0x8000u) /* USB - */
7861 
7862 /* USBPLLDIVB Control Bits */
7863 #define UPMB0_L (0x0001u) /* USB - PLL feedback divider buffer Bit 0 */
7864 #define UPMB1_L (0x0002u) /* USB - PLL feedback divider buffer Bit 1 */
7865 #define UPMB2_L (0x0004u) /* USB - PLL feedback divider buffer Bit 2 */
7866 #define UPMB3_L (0x0008u) /* USB - PLL feedback divider buffer Bit 3 */
7867 #define UPMB4_L (0x0010u) /* USB - PLL feedback divider buffer Bit 4 */
7868 #define UPMB5_L (0x0020u) /* USB - PLL feedback divider buffer Bit 5 */
7869 //#define RESERVED (0x0040u) /* USB - */
7870 //#define RESERVED (0x0080u) /* USB - */
7871 //#define RESERVED (0x0800u) /* USB - */
7872 //#define RESERVED (0x1000u) /* USB - */
7873 //#define RESERVED (0x2000u) /* USB - */
7874 //#define RESERVED (0x4000u) /* USB - */
7875 //#define RESERVED (0x8000u) /* USB - */
7876 
7877 /* USBPLLDIVB Control Bits */
7878 //#define RESERVED (0x0040u) /* USB - */
7879 //#define RESERVED (0x0080u) /* USB - */
7880 #define UPQB0_H (0x0001u) /* USB - PLL prescale divider buffer Bit 0 */
7881 #define UPQB1_H (0x0002u) /* USB - PLL prescale divider buffer Bit 1 */
7882 #define UPQB2_H (0x0004u) /* USB - PLL prescale divider buffer Bit 2 */
7883 //#define RESERVED (0x0800u) /* USB - */
7884 //#define RESERVED (0x1000u) /* USB - */
7885 //#define RESERVED (0x2000u) /* USB - */
7886 //#define RESERVED (0x4000u) /* USB - */
7887 //#define RESERVED (0x8000u) /* USB - */
7888 
7889 #define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */
7890 #define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */
7891 #define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */
7892 #define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */
7893 #define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */
7894 #define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */
7895 #define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */
7896 #define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */
7897 #define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */
7898 #define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */
7899 #define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */
7900 #define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */
7901 #define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */
7902 #define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */
7903 #define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */
7904 #define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */
7905 #define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */
7906 #define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */
7907 #define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */
7908 #define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */
7909 #define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */
7910 #define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */
7911 #define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */
7912 #define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */
7913 #define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */
7914 #define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */
7915 #define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */
7916 #define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */
7917 #define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */
7918 #define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */
7919 #define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */
7920 #define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */
7921 #define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */
7922 #define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */
7923 #define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */
7924 #define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */
7925 #define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */
7926 #define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */
7927 #define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */
7928 #define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */
7929 #define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */
7930 #define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */
7931 #define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */
7932 
7933 /* USBPLLIR Control Bits */
7934 #define USBOOLIFG (0x0001u) /* USB - PLL out of lock Interrupt Flag */
7935 #define USBLOSIFG (0x0002u) /* USB - PLL loss of signal Interrupt Flag */
7936 #define USBOORIFG (0x0004u) /* USB - PLL out of range Interrupt Flag */
7937 //#define RESERVED (0x0008u) /* USB - */
7938 //#define RESERVED (0x0010u) /* USB - */
7939 //#define RESERVED (0x0020u) /* USB - */
7940 //#define RESERVED (0x0040u) /* USB - */
7941 //#define RESERVED (0x0080u) /* USB - */
7942 #define USBOOLIE (0x0100u) /* USB - PLL out of lock Interrupt enable */
7943 #define USBLOSIE (0x0200u) /* USB - PLL loss of signal Interrupt enable */
7944 #define USBOORIE (0x0400u) /* USB - PLL out of range Interrupt enable */
7945 //#define RESERVED (0x0800u) /* USB - */
7946 //#define RESERVED (0x1000u) /* USB - */
7947 //#define RESERVED (0x2000u) /* USB - */
7948 //#define RESERVED (0x4000u) /* USB - */
7949 //#define RESERVED (0x8000u) /* USB - */
7950 
7951 /* USBPLLIR Control Bits */
7952 #define USBOOLIFG_L (0x0001u) /* USB - PLL out of lock Interrupt Flag */
7953 #define USBLOSIFG_L (0x0002u) /* USB - PLL loss of signal Interrupt Flag */
7954 #define USBOORIFG_L (0x0004u) /* USB - PLL out of range Interrupt Flag */
7955 //#define RESERVED (0x0008u) /* USB - */
7956 //#define RESERVED (0x0010u) /* USB - */
7957 //#define RESERVED (0x0020u) /* USB - */
7958 //#define RESERVED (0x0040u) /* USB - */
7959 //#define RESERVED (0x0080u) /* USB - */
7960 //#define RESERVED (0x0800u) /* USB - */
7961 //#define RESERVED (0x1000u) /* USB - */
7962 //#define RESERVED (0x2000u) /* USB - */
7963 //#define RESERVED (0x4000u) /* USB - */
7964 //#define RESERVED (0x8000u) /* USB - */
7965 
7966 /* USBPLLIR Control Bits */
7967 //#define RESERVED (0x0008u) /* USB - */
7968 //#define RESERVED (0x0010u) /* USB - */
7969 //#define RESERVED (0x0020u) /* USB - */
7970 //#define RESERVED (0x0040u) /* USB - */
7971 //#define RESERVED (0x0080u) /* USB - */
7972 #define USBOOLIE_H (0x0001u) /* USB - PLL out of lock Interrupt enable */
7973 #define USBLOSIE_H (0x0002u) /* USB - PLL loss of signal Interrupt enable */
7974 #define USBOORIE_H (0x0004u) /* USB - PLL out of range Interrupt enable */
7975 //#define RESERVED (0x0800u) /* USB - */
7976 //#define RESERVED (0x1000u) /* USB - */
7977 //#define RESERVED (0x2000u) /* USB - */
7978 //#define RESERVED (0x4000u) /* USB - */
7979 //#define RESERVED (0x8000u) /* USB - */
7980 
7981 /* ========================================================================= */
7982 /* USB Control Registers */
7983 /* ========================================================================= */
7984 #define OFS_USBIEPCNF_0 (0x0020u) /* USB Input endpoint_0: Configuration */
7985 #define OFS_USBIEPCNT_0 (0x0021u) /* USB Input endpoint_0: Byte Count */
7986 #define OFS_USBOEPCNF_0 (0x0022u) /* USB Output endpoint_0: Configuration */
7987 #define OFS_USBOEPCNT_0 (0x0023u) /* USB Output endpoint_0: byte count */
7988 #define OFS_USBIEPIE (0x002Eu) /* USB Input endpoint interrupt enable flags */
7989 #define OFS_USBOEPIE (0x002Fu) /* USB Output endpoint interrupt enable flags */
7990 #define OFS_USBIEPIFG (0x0030u) /* USB Input endpoint interrupt flags */
7991 #define OFS_USBOEPIFG (0x0031u) /* USB Output endpoint interrupt flags */
7992 #define OFS_USBVECINT (0x0032u) /* USB Vector interrupt register */
7993 #define OFS_USBVECINT_L OFS_USBVECINT
7994 #define OFS_USBVECINT_H OFS_USBVECINT+1
7995 #define OFS_USBMAINT (0x0036u) /* USB maintenance register */
7996 #define OFS_USBMAINT_L OFS_USBMAINT
7997 #define OFS_USBMAINT_H OFS_USBMAINT+1
7998 #define OFS_USBTSREG (0x0038u) /* USB Time Stamp register */
7999 #define OFS_USBTSREG_L OFS_USBTSREG
8000 #define OFS_USBTSREG_H OFS_USBTSREG+1
8001 #define OFS_USBFN (0x003Au) /* USB Frame number */
8002 #define OFS_USBFN_L OFS_USBFN
8003 #define OFS_USBFN_H OFS_USBFN+1
8004 #define OFS_USBCTL (0x003Cu) /* USB control register */
8005 #define OFS_USBIE (0x003Du) /* USB interrupt enable register */
8006 #define OFS_USBIFG (0x003Eu) /* USB interrupt flag register */
8007 #define OFS_USBFUNADR (0x003Fu) /* USB Function address register */
8008 
8009 #define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */
8010 
8011 /* USBIEPCNF_0 Control Bits */
8012 /* USBOEPCNF_0 Control Bits */
8013 //#define RESERVED (0x0001u) /* USB - */
8014 //#define RESERVED (0x0001u) /* USB - */
8015 #define USBIIE (0x0004u) /* USB - Transaction Interrupt indication enable */
8016 #define STALL (0x0008u) /* USB - Stall Condition */
8017 //#define RESERVED (0x0010u) /* USB - */
8018 #define TOGGLE (0x0020u) /* USB - Toggle Bit */
8019 //#define RESERVED (0x0040u) /* USB - */
8020 #define UBME (0x0080u) /* USB - UBM In-Endpoint Enable */
8021 
8022 /* USBIEPBCNT_0 Control Bits */
8023 /* USBOEPBCNT_0 Control Bits */
8024 #define CNT0 (0x0001u) /* USB - Byte Count Bit 0 */
8025 #define CNT1 (0x0001u) /* USB - Byte Count Bit 1 */
8026 #define CNT2 (0x0004u) /* USB - Byte Count Bit 2 */
8027 #define CNT3 (0x0008u) /* USB - Byte Count Bit 3 */
8028 //#define RESERVED (0x0010u) /* USB - */
8029 //#define RESERVED (0x0020u) /* USB - */
8030 //#define RESERVED (0x0040u) /* USB - */
8031 #define NAK (0x0080u) /* USB - No Acknowledge Status Bit */
8032 
8033 /* USBMAINT Control Bits */
8034 #define UTIFG (0x0001u) /* USB - Timer Interrupt Flag */
8035 #define UTIE (0x0002u) /* USB - Timer Interrupt Enable */
8036 //#define RESERVED (0x0004u) /* USB - */
8037 //#define RESERVED (0x0008u) /* USB - */
8038 //#define RESERVED (0x0010u) /* USB - */
8039 //#define RESERVED (0x0020u) /* USB - */
8040 //#define RESERVED (0x0040u) /* USB - */
8041 //#define RESERVED (0x0080u) /* USB - */
8042 #define TSGEN (0x0100u) /* USB - Time Stamp Generator Enable */
8043 #define TSESEL0 (0x0200u) /* USB - Time Stamp Event Select Bit 0 */
8044 #define TSESEL1 (0x0400u) /* USB - Time Stamp Event Select Bit 1 */
8045 #define TSE3 (0x0800u) /* USB - Time Stamp Event #3 Bit */
8046 //#define RESERVED (0x1000u) /* USB - */
8047 #define UTSEL0 (0x2000u) /* USB - Timer Select Bit 0 */
8048 #define UTSEL1 (0x4000u) /* USB - Timer Select Bit 1 */
8049 #define UTSEL2 (0x8000u) /* USB - Timer Select Bit 2 */
8050 
8051 /* USBMAINT Control Bits */
8052 #define UTIFG_L (0x0001u) /* USB - Timer Interrupt Flag */
8053 #define UTIE_L (0x0002u) /* USB - Timer Interrupt Enable */
8054 //#define RESERVED (0x0004u) /* USB - */
8055 //#define RESERVED (0x0008u) /* USB - */
8056 //#define RESERVED (0x0010u) /* USB - */
8057 //#define RESERVED (0x0020u) /* USB - */
8058 //#define RESERVED (0x0040u) /* USB - */
8059 //#define RESERVED (0x0080u) /* USB - */
8060 //#define RESERVED (0x1000u) /* USB - */
8061 
8062 /* USBMAINT Control Bits */
8063 //#define RESERVED (0x0004u) /* USB - */
8064 //#define RESERVED (0x0008u) /* USB - */
8065 //#define RESERVED (0x0010u) /* USB - */
8066 //#define RESERVED (0x0020u) /* USB - */
8067 //#define RESERVED (0x0040u) /* USB - */
8068 //#define RESERVED (0x0080u) /* USB - */
8069 #define TSGEN_H (0x0001u) /* USB - Time Stamp Generator Enable */
8070 #define TSESEL0_H (0x0002u) /* USB - Time Stamp Event Select Bit 0 */
8071 #define TSESEL1_H (0x0004u) /* USB - Time Stamp Event Select Bit 1 */
8072 #define TSE3_H (0x0008u) /* USB - Time Stamp Event #3 Bit */
8073 //#define RESERVED (0x1000u) /* USB - */
8074 #define UTSEL0_H (0x0020u) /* USB - Timer Select Bit 0 */
8075 #define UTSEL1_H (0x0040u) /* USB - Timer Select Bit 1 */
8076 #define UTSEL2_H (0x0080u) /* USB - Timer Select Bit 2 */
8077 
8078 #define TSESEL_0 (0x0000u) /* USB - Time Stamp Event Select: 0 */
8079 #define TSESEL_1 (0x0200u) /* USB - Time Stamp Event Select: 1 */
8080 #define TSESEL_2 (0x0400u) /* USB - Time Stamp Event Select: 2 */
8081 #define TSESEL_3 (0x0600u) /* USB - Time Stamp Event Select: 3 */
8082 
8083 #define UTSEL_0 (0x0000u) /* USB - Timer Select: 0 */
8084 #define UTSEL_1 (0x2000u) /* USB - Timer Select: 1 */
8085 #define UTSEL_2 (0x4000u) /* USB - Timer Select: 2 */
8086 #define UTSEL_3 (0x6000u) /* USB - Timer Select: 3 */
8087 #define UTSEL_4 (0x8000u) /* USB - Timer Select: 4 */
8088 #define UTSEL_5 (0xA000u) /* USB - Timer Select: 5 */
8089 #define UTSEL_6 (0xC000u) /* USB - Timer Select: 6 */
8090 #define UTSEL_7 (0xE000u) /* USB - Timer Select: 7 */
8091 
8092 /* USBCTL Control Bits */
8093 #define DIR (0x0001u) /* USB - Data Response Bit */
8094 //#define RESERVED (0x0002u) /* USB - */
8095 //#define RESERVED (0x0004u) /* USB - */
8096 //#define RESERVED (0x0008u) /* USB - */
8097 #define FRSTE (0x0010u) /* USB - Function Reset Connection Enable */
8098 #define RWUP (0x0020u) /* USB - Device Remote Wakeup Request */
8099 #define FEN (0x0040u) /* USB - Function Enable Bit */
8100 //#define RESERVED (0x0080u) /* USB - */
8101 
8102 /* USBIE Control Bits */
8103 #define STPOWIE (0x0001u) /* USB - Setup Overwrite Interrupt Enable */
8104 //#define RESERVED (0x0002u) /* USB - */
8105 #define SETUPIE (0x0004u) /* USB - Setup Interrupt Enable */
8106 //#define RESERVED (0x0008u) /* USB - */
8107 //#define RESERVED (0x0010u) /* USB - */
8108 #define RESRIE (0x0020u) /* USB - Function Resume Request Interrupt Enable */
8109 #define SUSRIE (0x0040u) /* USB - Function Suspend Request Interrupt Enable */
8110 #define RSTRIE (0x0080u) /* USB - Function Reset Request Interrupt Enable */
8111 
8112 /* USBIFG Control Bits */
8113 #define STPOWIFG (0x0001u) /* USB - Setup Overwrite Interrupt Flag */
8114 //#define RESERVED (0x0002u) /* USB - */
8115 #define SETUPIFG (0x0004u) /* USB - Setup Interrupt Flag */
8116 //#define RESERVED (0x0008u) /* USB - */
8117 //#define RESERVED (0x0010u) /* USB - */
8118 #define RESRIFG (0x0020u) /* USB - Function Resume Request Interrupt Flag */
8119 #define SUSRIFG (0x0040u) /* USB - Function Suspend Request Interrupt Flag */
8120 #define RSTRIFG (0x0080u) /* USB - Function Reset Request Interrupt Flag */
8121 
8122 //values of USBVECINT when USB-interrupt occured
8123 #define USBVECINT_NONE 0x00
8124 #define USBVECINT_PWR_DROP 0x02
8125 #define USBVECINT_PLL_LOCK 0x04
8126 #define USBVECINT_PLL_SIGNAL 0x06
8127 #define USBVECINT_PLL_RANGE 0x08
8128 #define USBVECINT_PWR_VBUSOn 0x0A
8129 #define USBVECINT_PWR_VBUSOff 0x0C
8130 #define USBVECINT_USB_TIMESTAMP 0x10
8131 #define USBVECINT_INPUT_ENDPOINT0 0x12
8132 #define USBVECINT_OUTPUT_ENDPOINT0 0x14
8133 #define USBVECINT_RSTR 0x16
8134 #define USBVECINT_SUSR 0x18
8135 #define USBVECINT_RESR 0x1A
8136 #define USBVECINT_SETUP_PACKET_RECEIVED 0x20
8137 #define USBVECINT_STPOW_PACKET_RECEIVED 0x22
8138 #define USBVECINT_INPUT_ENDPOINT1 0x24
8139 #define USBVECINT_INPUT_ENDPOINT2 0x26
8140 #define USBVECINT_INPUT_ENDPOINT3 0x28
8141 #define USBVECINT_INPUT_ENDPOINT4 0x2A
8142 #define USBVECINT_INPUT_ENDPOINT5 0x2C
8143 #define USBVECINT_INPUT_ENDPOINT6 0x2E
8144 #define USBVECINT_INPUT_ENDPOINT7 0x30
8145 #define USBVECINT_OUTPUT_ENDPOINT1 0x32
8146 #define USBVECINT_OUTPUT_ENDPOINT2 0x34
8147 #define USBVECINT_OUTPUT_ENDPOINT3 0x36
8148 #define USBVECINT_OUTPUT_ENDPOINT4 0x38
8149 #define USBVECINT_OUTPUT_ENDPOINT5 0x3A
8150 #define USBVECINT_OUTPUT_ENDPOINT6 0x3C
8151 #define USBVECINT_OUTPUT_ENDPOINT7 0x3E
8152 
8153 
8154 /* ========================================================================= */
8155 /* USB Operation Registers */
8156 /* ========================================================================= */
8157 
8158 #define OFS_USBIEPSIZXY_7 (0x23FFu) /* Input Endpoint_7: X/Y-buffer size */
8159 #define OFS_USBIEPBCTY_7 (0x23FEu) /* Input Endpoint_7: Y-byte count */
8160 #define OFS_USBIEPBBAY_7 (0x23FDu) /* Input Endpoint_7: Y-buffer base addr. */
8161 //#define Spare_O (0x23FCu) /* Not used */
8162 //#define Spare_O (0x23FBu) /* Not used */
8163 #define OFS_USBIEPBCTX_7 (0x23FAu) /* Input Endpoint_7: X-byte count */
8164 #define OFS_USBIEPBBAX_7 (0x23F9u) /* Input Endpoint_7: X-buffer base addr. */
8165 #define OFS_USBIEPCNF_7 (0x23F8u) /* Input Endpoint_7: Configuration */
8166 #define OFS_USBIEPSIZXY_6 (0x23F7u) /* Input Endpoint_6: X/Y-buffer size */
8167 #define OFS_USBIEPBCTY_6 (0x23F6u) /* Input Endpoint_6: Y-byte count */
8168 #define OFS_USBIEPBBAY_6 (0x23F5u) /* Input Endpoint_6: Y-buffer base addr. */
8169 //#define Spare_O (0x23F4u) /* Not used */
8170 //#define Spare_O (0x23F3u) /* Not used */
8171 #define OFS_USBIEPBCTX_6 (0x23F2u) /* Input Endpoint_6: X-byte count */
8172 #define OFS_USBIEPBBAX_6 (0x23F1u) /* Input Endpoint_6: X-buffer base addr. */
8173 #define OFS_USBIEPCNF_6 (0x23F0u) /* Input Endpoint_6: Configuration */
8174 #define OFS_USBIEPSIZXY_5 (0x23EFu) /* Input Endpoint_5: X/Y-buffer size */
8175 #define OFS_USBIEPBCTY_5 (0x23EEu) /* Input Endpoint_5: Y-byte count */
8176 #define OFS_USBIEPBBAY_5 (0x23EDu) /* Input Endpoint_5: Y-buffer base addr. */
8177 //#define Spare_O (0x23ECu) /* Not used */
8178 //#define Spare_O (0x23EBu) /* Not used */
8179 #define OFS_USBIEPBCTX_5 (0x23EAu) /* Input Endpoint_5: X-byte count */
8180 #define OFS_USBIEPBBAX_5 (0x23E9u) /* Input Endpoint_5: X-buffer base addr. */
8181 #define OFS_USBIEPCNF_5 (0x23E8u) /* Input Endpoint_5: Configuration */
8182 #define OFS_USBIEPSIZXY_4 (0x23E7u) /* Input Endpoint_4: X/Y-buffer size */
8183 #define OFS_USBIEPBCTY_4 (0x23E6u) /* Input Endpoint_4: Y-byte count */
8184 #define OFS_USBIEPBBAY_4 (0x23E5u) /* Input Endpoint_4: Y-buffer base addr. */
8185 //#define Spare_O (0x23E4u) /* Not used */
8186 //#define Spare_O (0x23E3u) /* Not used */
8187 #define OFS_USBIEPBCTX_4 (0x23E2u) /* Input Endpoint_4: X-byte count */
8188 #define OFS_USBIEPBBAX_4 (0x23E1u) /* Input Endpoint_4: X-buffer base addr. */
8189 #define OFS_USBIEPCNF_4 (0x23E0u) /* Input Endpoint_4: Configuration */
8190 #define OFS_USBIEPSIZXY_3 (0x23DFu) /* Input Endpoint_3: X/Y-buffer size */
8191 #define OFS_USBIEPBCTY_3 (0x23DEu) /* Input Endpoint_3: Y-byte count */
8192 #define OFS_USBIEPBBAY_3 (0x23DDu) /* Input Endpoint_3: Y-buffer base addr. */
8193 //#define Spare_O (0x23DCu) /* Not used */
8194 //#define Spare_O (0x23DBu) /* Not used */
8195 #define OFS_USBIEPBCTX_3 (0x23DAu) /* Input Endpoint_3: X-byte count */
8196 #define OFS_USBIEPBBAX_3 (0x23D9u) /* Input Endpoint_3: X-buffer base addr. */
8197 #define OFS_USBIEPCNF_3 (0x23D8u) /* Input Endpoint_3: Configuration */
8198 #define OFS_USBIEPSIZXY_2 (0x23D7u) /* Input Endpoint_2: X/Y-buffer size */
8199 #define OFS_USBIEPBCTY_2 (0x23D6u) /* Input Endpoint_2: Y-byte count */
8200 #define OFS_USBIEPBBAY_2 (0x23D5u) /* Input Endpoint_2: Y-buffer base addr. */
8201 //#define Spare_O (0x23D4u) /* Not used */
8202 //#define Spare_O (0x23D3u) /* Not used */
8203 #define OFS_USBIEPBCTX_2 (0x23D2u) /* Input Endpoint_2: X-byte count */
8204 #define OFS_USBIEPBBAX_2 (0x23D1u) /* Input Endpoint_2: X-buffer base addr. */
8205 #define OFS_USBIEPCNF_2 (0x23D0u) /* Input Endpoint_2: Configuration */
8206 #define OFS_USBIEPSIZXY_1 (0x23CFu) /* Input Endpoint_1: X/Y-buffer size */
8207 #define OFS_USBIEPBCTY_1 (0x23CEu) /* Input Endpoint_1: Y-byte count */
8208 #define OFS_USBIEPBBAY_1 (0x23CDu) /* Input Endpoint_1: Y-buffer base addr. */
8209 //#define Spare_O (0x23CCu) /* Not used */
8210 //#define Spare_O (0x23CBu) /* Not used */
8211 #define OFS_USBIEPBCTX_1 (0x23CAu) /* Input Endpoint_1: X-byte count */
8212 #define OFS_USBIEPBBAX_1 (0x23C9u) /* Input Endpoint_1: X-buffer base addr. */
8213 #define OFS_USBIEPCNF_1 (0x23C8u) /* Input Endpoint_1: Configuration */
8214 //#define (0x23C7)_O /* */
8215 //#define RESERVED_O (0x1C00u) /* */
8216 //#define (0x23C0)_O /* */
8217 #define OFS_USBOEPSIZXY_7 (0x23BFu) /* Output Endpoint_7: X/Y-buffer size */
8218 #define OFS_USBOEPBCTY_7 (0x23BEu) /* Output Endpoint_7: Y-byte count */
8219 #define OFS_USBOEPBBAY_7 (0x23BDu) /* Output Endpoint_7: Y-buffer base addr. */
8220 //#define Spare_O (0x23BCu) /* Not used */
8221 //#define Spare_O (0x23BBu) /* Not used */
8222 #define OFS_USBOEPBCTX_7 (0x23BAu) /* Output Endpoint_7: X-byte count */
8223 #define OFS_USBOEPBBAX_7 (0x23B9u) /* Output Endpoint_7: X-buffer base addr. */
8224 #define OFS_USBOEPCNF_7 (0x23B8u) /* Output Endpoint_7: Configuration */
8225 #define OFS_USBOEPSIZXY_6 (0x23B7u) /* Output Endpoint_6: X/Y-buffer size */
8226 #define OFS_USBOEPBCTY_6 (0x23B6u) /* Output Endpoint_6: Y-byte count */
8227 #define OFS_USBOEPBBAY_6 (0x23B5u) /* Output Endpoint_6: Y-buffer base addr. */
8228 //#define Spare_O (0x23B4u) /* Not used */
8229 //#define Spare_O (0x23B3u) /* Not used */
8230 #define OFS_USBOEPBCTX_6 (0x23B2u) /* Output Endpoint_6: X-byte count */
8231 #define OFS_USBOEPBBAX_6 (0x23B1u) /* Output Endpoint_6: X-buffer base addr. */
8232 #define OFS_USBOEPCNF_6 (0x23B0u) /* Output Endpoint_6: Configuration */
8233 #define OFS_USBOEPSIZXY_5 (0x23AFu) /* Output Endpoint_5: X/Y-buffer size */
8234 #define OFS_USBOEPBCTY_5 (0x23AEu) /* Output Endpoint_5: Y-byte count */
8235 #define OFS_USBOEPBBAY_5 (0x23ADu) /* Output Endpoint_5: Y-buffer base addr. */
8236 //#define Spare_O (0x23ACu) /* Not used */
8237 //#define Spare_O (0x23ABu) /* Not used */
8238 #define OFS_USBOEPBCTX_5 (0x23AAu) /* Output Endpoint_5: X-byte count */
8239 #define OFS_USBOEPBBAX_5 (0x23A9u) /* Output Endpoint_5: X-buffer base addr. */
8240 #define OFS_USBOEPCNF_5 (0x23A8u) /* Output Endpoint_5: Configuration */
8241 #define OFS_USBOEPSIZXY_4 (0x23A7u) /* Output Endpoint_4: X/Y-buffer size */
8242 #define OFS_USBOEPBCTY_4 (0x23A6u) /* Output Endpoint_4: Y-byte count */
8243 #define OFS_USBOEPBBAY_4 (0x23A5u) /* Output Endpoint_4: Y-buffer base addr. */
8244 //#define Spare_O (0x23A4u) /* Not used */
8245 //#define Spare_O (0x23A3u) /* Not used */
8246 #define OFS_USBOEPBCTX_4 (0x23A2u) /* Output Endpoint_4: X-byte count */
8247 #define OFS_USBOEPBBAX_4 (0x23A1u) /* Output Endpoint_4: X-buffer base addr. */
8248 #define OFS_USBOEPCNF_4 (0x23A0u) /* Output Endpoint_4: Configuration */
8249 #define OFS_USBOEPSIZXY_3 (0x239Fu) /* Output Endpoint_3: X/Y-buffer size */
8250 #define OFS_USBOEPBCTY_3 (0x239Eu) /* Output Endpoint_3: Y-byte count */
8251 #define OFS_USBOEPBBAY_3 (0x239Du) /* Output Endpoint_3: Y-buffer base addr. */
8252 //#define Spare_O (0x239Cu) /* Not used */
8253 //#define Spare_O (0x239Bu) /* Not used */
8254 #define OFS_USBOEPBCTX_3 (0x239Au) /* Output Endpoint_3: X-byte count */
8255 #define OFS_USBOEPBBAX_3 (0x2399u) /* Output Endpoint_3: X-buffer base addr. */
8256 #define OFS_USBOEPCNF_3 (0x2398u) /* Output Endpoint_3: Configuration */
8257 #define OFS_USBOEPSIZXY_2 (0x2397u) /* Output Endpoint_2: X/Y-buffer size */
8258 #define OFS_USBOEPBCTY_2 (0x2396u) /* Output Endpoint_2: Y-byte count */
8259 #define OFS_USBOEPBBAY_2 (0x2395u) /* Output Endpoint_2: Y-buffer base addr. */
8260 //#define Spare_O (0x2394u) /* Not used */
8261 //#define Spare_O (0x2393u) /* Not used */
8262 #define OFS_USBOEPBCTX_2 (0x2392u) /* Output Endpoint_2: X-byte count */
8263 #define OFS_USBOEPBBAX_2 (0x2391u) /* Output Endpoint_2: X-buffer base addr. */
8264 #define OFS_USBOEPCNF_2 (0x2390u) /* Output Endpoint_2: Configuration */
8265 #define OFS_USBOEPSIZXY_1 (0x238Fu) /* Output Endpoint_1: X/Y-buffer size */
8266 #define OFS_USBOEPBCTY_1 (0x238Eu) /* Output Endpoint_1: Y-byte count */
8267 #define OFS_USBOEPBBAY_1 (0x238Du) /* Output Endpoint_1: Y-buffer base addr. */
8268 //#define Spare_O (0x238Cu) /* Not used */
8269 //#define Spare_O (0x238Bu) /* Not used */
8270 #define OFS_USBOEPBCTX_1 (0x238Au) /* Output Endpoint_1: X-byte count */
8271 #define OFS_USBOEPBBAX_1 (0x2389u) /* Output Endpoint_1: X-buffer base addr. */
8272 #define OFS_USBOEPCNF_1 (0x2388u) /* Output Endpoint_1: Configuration */
8273 #define OFS_USBSUBLK (0x2380u) /* Setup Packet Block */
8274 #define OFS_USBIEP0BUF (0x2378u) /* Input endpoint_0 buffer */
8275 #define OFS_USBOEP0BUF (0x2370u) /* Output endpoint_0 buffer */
8276 #define OFS_USBTOPBUFF (0x236Fu) /* Top of buffer space */
8277 // (1904 Bytes) /* Buffer space */
8278 #define OFS_USBSTABUFF (0x1C00u) /* Start of buffer space */
8279 
8280 /* USBIEPCNF_n Control Bits */
8281 /* USBOEPCNF_n Control Bits */
8282 //#define RESERVED (0x0001u) /* USB - */
8283 //#define RESERVED (0x0001u) /* USB - */
8284 #define DBUF (0x0010u) /* USB - Double Buffer Enable */
8285 //#define RESERVED (0x0040u) /* USB - */
8286 
8287 /* USBIEPBCNT_n Control Bits */
8288 /* USBOEPBCNT_n Control Bits */
8289 #define CNT4 (0x0010u) /* USB - Byte Count Bit 3 */
8290 #define CNT5 (0x0020u) /* USB - Byte Count Bit 3 */
8291 #define CNT6 (0x0040u) /* USB - Byte Count Bit 3 */
8292 #endif
8293 /************************************************************
8294 * USCI Ax
8295 ************************************************************/
8296 #ifdef __MSP430_HAS_USCI_Ax__ /* Definition to show that Module is available */
8297 
8298 #define OFS_UCAxCTLW0 (0x0000u) /* USCI Ax Control Word Register 0 */
8299 #define OFS_UCAxCTLW0_L OFS_UCAxCTLW0
8300 #define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1
8301 #define OFS_UCAxCTL0 (0x0001u)
8302 #define OFS_UCAxCTL1 (0x0000u)
8303 #define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */
8304 #define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */
8305 #define OFS_UCAxBRW (0x0006u) /* USCI Ax Baud Word Rate 0 */
8306 #define OFS_UCAxBRW_L OFS_UCAxBRW
8307 #define OFS_UCAxBRW_H OFS_UCAxBRW+1
8308 #define OFS_UCAxBR0 (0x0006u)
8309 #define OFS_UCAxBR1 (0x0007u)
8310 #define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */
8311 #define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */
8312 #define OFS_UCAxMCTL (0x0008u) /* USCI Ax Modulation Control */
8313 #define OFS_UCAxSTAT (0x000Au) /* USCI Ax Status Register */
8314 #define OFS_UCAxRXBUF (0x000Cu) /* USCI Ax Receive Buffer */
8315 #define OFS_UCAxTXBUF (0x000Eu) /* USCI Ax Transmit Buffer */
8316 #define OFS_UCAxABCTL (0x0010u) /* USCI Ax LIN Control */
8317 #define OFS_UCAxIRCTL (0x0012u) /* USCI Ax IrDA Transmit Control */
8318 #define OFS_UCAxIRCTL_L OFS_UCAxIRCTL
8319 #define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1
8320 #define OFS_UCAxIRTCTL (0x0012u)
8321 #define OFS_UCAxIRRCTL (0x0013u)
8322 #define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */
8323 #define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */
8324 #define OFS_UCAxICTL (0x001Cu) /* USCI Ax Interrupt Enable Register */
8325 #define OFS_UCAxICTL_L OFS_UCAxICTL
8326 #define OFS_UCAxICTL_H OFS_UCAxICTL+1
8327 #define OFS_UCAxIE (0x001Cu)
8328 #define OFS_UCAxIFG (0x001Du)
8329 #define UCAxIE UCAxICTL_L /* USCI Ax Interrupt Enable Register */
8330 #define UCAxIFG UCAxICTL_H /* USCI Ax Interrupt Flags Register */
8331 #define OFS_UCAxIV (0x001Eu) /* USCI Ax Interrupt Vector Register */
8332 
8333 #define OFS_UCAxCTLW0__SPI (0x0000u)
8334 #define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI
8335 #define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1
8336 #define OFS_UCAxCTL0__SPI (0x0001u)
8337 #define OFS_UCAxCTL1__SPI (0x0000u)
8338 #define OFS_UCAxBRW__SPI (0x0006u)
8339 #define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI
8340 #define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1
8341 #define OFS_UCAxBR0__SPI (0x0006u)
8342 #define OFS_UCAxBR1__SPI (0x0007u)
8343 #define OFS_UCAxMCTL__SPI (0x0008u)
8344 #define OFS_UCAxSTAT__SPI (0x000Au)
8345 #define OFS_UCAxRXBUF__SPI (0x000Cu)
8346 #define OFS_UCAxTXBUF__SPI (0x000Eu)
8347 #define OFS_UCAxICTL__SPI (0x001Cu)
8348 #define OFS_UCAxICTL__SPI_L OFS_UCAxICTL__SPI
8349 #define OFS_UCAxICTL__SPI_H OFS_UCAxICTL__SPI+1
8350 #define OFS_UCAxIE__SPI (0x001Cu)
8351 #define OFS_UCAxIFG__SPI (0x001Du)
8352 #define OFS_UCAxIV__SPI (0x001Eu)
8353 
8354 #endif
8355 /************************************************************
8356 * USCI Bx
8357 ************************************************************/
8358 #ifdef __MSP430_HAS_USCI_Bx__ /* Definition to show that Module is available */
8359 
8360 #define OFS_UCBxCTLW0__SPI (0x0000u)
8361 #define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI
8362 #define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1
8363 #define OFS_UCBxCTL0__SPI (0x0001u)
8364 #define OFS_UCBxCTL1__SPI (0x0000u)
8365 #define OFS_UCBxBRW__SPI (0x0006u)
8366 #define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI
8367 #define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1
8368 #define OFS_UCBxBR0__SPI (0x0006u)
8369 #define OFS_UCBxBR1__SPI (0x0007u)
8370 #define OFS_UCBxSTAT__SPI (0x000Au)
8371 #define OFS_UCBxRXBUF__SPI (0x000Cu)
8372 #define OFS_UCBxTXBUF__SPI (0x000Eu)
8373 #define OFS_UCBxICTL__SPI (0x001Cu)
8374 #define OFS_UCBxICTL__SPI_L OFS_UCBxICTL__SPI
8375 #define OFS_UCBxICTL__SPI_H OFS_UCBxICTL__SPI+1
8376 #define OFS_UCBxIE__SPI (0x001Cu)
8377 #define OFS_UCBxIFG__SPI (0x001Du)
8378 #define OFS_UCBxIV__SPI (0x001Eu)
8379 
8380 #define OFS_UCBxCTLW0 (0x0000u) /* USCI Bx Control Word Register 0 */
8381 #define OFS_UCBxCTLW0_L OFS_UCBxCTLW0
8382 #define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1
8383 #define OFS_UCBxCTL0 (0x0001u)
8384 #define OFS_UCBxCTL1 (0x0000u)
8385 #define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */
8386 #define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */
8387 #define OFS_UCBxBRW (0x0006u) /* USCI Bx Baud Word Rate 0 */
8388 #define OFS_UCBxBRW_L OFS_UCBxBRW
8389 #define OFS_UCBxBRW_H OFS_UCBxBRW+1
8390 #define OFS_UCBxBR0 (0x0006u)
8391 #define OFS_UCBxBR1 (0x0007u)
8392 #define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */
8393 #define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */
8394 #define OFS_UCBxSTAT (0x000Au) /* USCI Bx Status Register */
8395 #define OFS_UCBxRXBUF (0x000Cu) /* USCI Bx Receive Buffer */
8396 #define OFS_UCBxTXBUF (0x000Eu) /* USCI Bx Transmit Buffer */
8397 #define OFS_UCBxI2COA (0x0010u) /* USCI Bx I2C Own Address */
8398 #define OFS_UCBxI2COA_L OFS_UCBxI2COA
8399 #define OFS_UCBxI2COA_H OFS_UCBxI2COA+1
8400 #define OFS_UCBxI2CSA (0x0012u) /* USCI Bx I2C Slave Address */
8401 #define OFS_UCBxI2CSA_L OFS_UCBxI2CSA
8402 #define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1
8403 #define OFS_UCBxICTL (0x001Cu) /* USCI Bx Interrupt Enable Register */
8404 #define OFS_UCBxICTL_L OFS_UCBxICTL
8405 #define OFS_UCBxICTL_H OFS_UCBxICTL+1
8406 #define OFS_UCBxIE (0x001Cu)
8407 #define OFS_UCBxIFG (0x001Du)
8408 #define UCBxIE UCBxICTL_L /* USCI Bx Interrupt Enable Register */
8409 #define UCBxIFG UCBxICTL_H /* USCI Bx Interrupt Flags Register */
8410 #define OFS_UCBxIV (0x001Eu) /* USCI Bx Interrupt Vector Register */
8411 
8412 #endif
8413 #if (defined(__MSP430_HAS_USCI_Ax__) || defined(__MSP430_HAS_USCI_Bx__))
8414 
8415 // UCAxCTL0 UART-Mode Control Bits
8416 #define UCPEN (0x80) /* Async. Mode: Parity enable */
8417 #define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
8418 #define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
8419 #define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
8420 #define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
8421 #define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
8422 #define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
8423 #define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
8424 
8425 // UCxxCTL0 SPI-Mode Control Bits
8426 #define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
8427 #define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
8428 #define UCMST (0x08) /* Sync. Mode: Master Select */
8429 
8430 // UCBxCTL0 I2C-Mode Control Bits
8431 #define UCA10 (0x80) /* 10-bit Address Mode */
8432 #define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
8433 #define UCMM (0x20) /* Multi-Master Environment */
8434 //#define res (0x10) /* reserved */
8435 #define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
8436 #define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
8437 #define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
8438 #define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
8439 
8440 // UCAxCTL1 UART-Mode Control Bits
8441 #define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
8442 #define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
8443 #define UCRXEIE (0x20) /* RX Error interrupt enable */
8444 #define UCBRKIE (0x10) /* Break interrupt enable */
8445 #define UCDORM (0x08) /* Dormant (Sleep) Mode */
8446 #define UCTXADDR (0x04) /* Send next Data as Address */
8447 #define UCTXBRK (0x02) /* Send next Data as Break */
8448 #define UCSWRST (0x01) /* USCI Software Reset */
8449 
8450 // UCxxCTL1 SPI-Mode Control Bits
8451 //#define res (0x20) /* reserved */
8452 //#define res (0x10) /* reserved */
8453 //#define res (0x08) /* reserved */
8454 //#define res (0x04) /* reserved */
8455 //#define res (0x02) /* reserved */
8456 
8457 // UCBxCTL1 I2C-Mode Control Bits
8458 //#define res (0x20) /* reserved */
8459 #define UCTR (0x10) /* Transmit/Receive Select/Flag */
8460 #define UCTXNACK (0x08) /* Transmit NACK */
8461 #define UCTXSTP (0x04) /* Transmit STOP */
8462 #define UCTXSTT (0x02) /* Transmit START */
8463 #define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
8464 #define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
8465 #define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
8466 #define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
8467 #define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */
8468 #define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */
8469 #define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */
8470 
8471 /* UCAxMCTL Control Bits */
8472 #define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
8473 #define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
8474 #define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
8475 #define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
8476 #define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
8477 #define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
8478 #define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
8479 #define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
8480 
8481 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
8482 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
8483 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
8484 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
8485 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
8486 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
8487 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
8488 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
8489 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
8490 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
8491 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
8492 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
8493 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
8494 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
8495 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
8496 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
8497 
8498 #define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
8499 #define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
8500 #define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
8501 #define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
8502 #define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
8503 #define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
8504 #define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
8505 #define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
8506 
8507 /* UCAxSTAT Control Bits */
8508 #define UCLISTEN (0x80) /* USCI Listen mode */
8509 #define UCFE (0x40) /* USCI Frame Error Flag */
8510 #define UCOE (0x20) /* USCI Overrun Error Flag */
8511 #define UCPE (0x10) /* USCI Parity Error Flag */
8512 #define UCBRK (0x08) /* USCI Break received */
8513 #define UCRXERR (0x04) /* USCI RX Error Flag */
8514 #define UCADDR (0x02) /* USCI Address received Flag */
8515 #define UCBUSY (0x01) /* USCI Busy Flag */
8516 #define UCIDLE (0x02) /* USCI Idle line detected Flag */
8517 
8518 /* UCBxSTAT Control Bits */
8519 #define UCSCLLOW (0x40) /* SCL low */
8520 #define UCGC (0x20) /* General Call address received Flag */
8521 #define UCBBUSY (0x10) /* Bus Busy Flag */
8522 
8523 /* UCAxIRTCTL Control Bits */
8524 #define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
8525 #define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
8526 #define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
8527 #define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
8528 #define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
8529 #define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
8530 #define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
8531 #define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
8532 
8533 /* UCAxIRRCTL Control Bits */
8534 #define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
8535 #define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
8536 #define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
8537 #define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
8538 #define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
8539 #define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
8540 #define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
8541 #define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
8542 
8543 /* UCAxABCTL Control Bits */
8544 //#define res (0x80) /* reserved */
8545 //#define res (0x40) /* reserved */
8546 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
8547 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
8548 #define UCSTOE (0x08) /* Sync-Field Timeout error */
8549 #define UCBTOE (0x04) /* Break Timeout error */
8550 //#define res (0x02) /* reserved */
8551 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */
8552 
8553 /* UCBxI2COA Control Bits */
8554 #define UCGCEN (0x8000u) /* I2C General Call enable */
8555 #define UCOA9 (0x0200u) /* I2C Own Address 9 */
8556 #define UCOA8 (0x0100u) /* I2C Own Address 8 */
8557 #define UCOA7 (0x0080u) /* I2C Own Address 7 */
8558 #define UCOA6 (0x0040u) /* I2C Own Address 6 */
8559 #define UCOA5 (0x0020u) /* I2C Own Address 5 */
8560 #define UCOA4 (0x0010u) /* I2C Own Address 4 */
8561 #define UCOA3 (0x0008u) /* I2C Own Address 3 */
8562 #define UCOA2 (0x0004u) /* I2C Own Address 2 */
8563 #define UCOA1 (0x0002u) /* I2C Own Address 1 */
8564 #define UCOA0 (0x0001u) /* I2C Own Address 0 */
8565 
8566 /* UCBxI2COA Control Bits */
8567 #define UCOA7_L (0x0080u) /* I2C Own Address 7 */
8568 #define UCOA6_L (0x0040u) /* I2C Own Address 6 */
8569 #define UCOA5_L (0x0020u) /* I2C Own Address 5 */
8570 #define UCOA4_L (0x0010u) /* I2C Own Address 4 */
8571 #define UCOA3_L (0x0008u) /* I2C Own Address 3 */
8572 #define UCOA2_L (0x0004u) /* I2C Own Address 2 */
8573 #define UCOA1_L (0x0002u) /* I2C Own Address 1 */
8574 #define UCOA0_L (0x0001u) /* I2C Own Address 0 */
8575 
8576 /* UCBxI2COA Control Bits */
8577 #define UCGCEN_H (0x0080u) /* I2C General Call enable */
8578 #define UCOA9_H (0x0002u) /* I2C Own Address 9 */
8579 #define UCOA8_H (0x0001u) /* I2C Own Address 8 */
8580 
8581 /* UCBxI2CSA Control Bits */
8582 #define UCSA9 (0x0200u) /* I2C Slave Address 9 */
8583 #define UCSA8 (0x0100u) /* I2C Slave Address 8 */
8584 #define UCSA7 (0x0080u) /* I2C Slave Address 7 */
8585 #define UCSA6 (0x0040u) /* I2C Slave Address 6 */
8586 #define UCSA5 (0x0020u) /* I2C Slave Address 5 */
8587 #define UCSA4 (0x0010u) /* I2C Slave Address 4 */
8588 #define UCSA3 (0x0008u) /* I2C Slave Address 3 */
8589 #define UCSA2 (0x0004u) /* I2C Slave Address 2 */
8590 #define UCSA1 (0x0002u) /* I2C Slave Address 1 */
8591 #define UCSA0 (0x0001u) /* I2C Slave Address 0 */
8592 
8593 /* UCBxI2CSA Control Bits */
8594 #define UCSA7_L (0x0080u) /* I2C Slave Address 7 */
8595 #define UCSA6_L (0x0040u) /* I2C Slave Address 6 */
8596 #define UCSA5_L (0x0020u) /* I2C Slave Address 5 */
8597 #define UCSA4_L (0x0010u) /* I2C Slave Address 4 */
8598 #define UCSA3_L (0x0008u) /* I2C Slave Address 3 */
8599 #define UCSA2_L (0x0004u) /* I2C Slave Address 2 */
8600 #define UCSA1_L (0x0002u) /* I2C Slave Address 1 */
8601 #define UCSA0_L (0x0001u) /* I2C Slave Address 0 */
8602 
8603 /* UCBxI2CSA Control Bits */
8604 #define UCSA9_H (0x0002u) /* I2C Slave Address 9 */
8605 #define UCSA8_H (0x0001u) /* I2C Slave Address 8 */
8606 
8607 /* UCAxIE Control Bits */
8608 #define UCTXIE (0x0002u) /* USCI Transmit Interrupt Enable */
8609 #define UCRXIE (0x0001u) /* USCI Receive Interrupt Enable */
8610 
8611 /* UCAxIE Control Bits */
8612 #define UCTXIE_L (0x0002u) /* USCI Transmit Interrupt Enable */
8613 #define UCRXIE_L (0x0001u) /* USCI Receive Interrupt Enable */
8614 
8615 /* UCBxIE Control Bits */
8616 #define UCNACKIE (0x0020u) /* NACK Condition interrupt enable */
8617 #define UCALIE (0x0010u) /* Arbitration Lost interrupt enable */
8618 #define UCSTPIE (0x0008u) /* STOP Condition interrupt enable */
8619 #define UCSTTIE (0x0004u) /* START Condition interrupt enable */
8620 #define UCTXIE (0x0002u) /* USCI Transmit Interrupt Enable */
8621 #define UCRXIE (0x0001u) /* USCI Receive Interrupt Enable */
8622 
8623 /* UCBxIE Control Bits */
8624 #define UCNACKIE_L (0x0020u) /* NACK Condition interrupt enable */
8625 #define UCALIE_L (0x0010u) /* Arbitration Lost interrupt enable */
8626 #define UCSTPIE_L (0x0008u) /* STOP Condition interrupt enable */
8627 #define UCSTTIE_L (0x0004u) /* START Condition interrupt enable */
8628 #define UCTXIE_L (0x0002u) /* USCI Transmit Interrupt Enable */
8629 #define UCRXIE_L (0x0001u) /* USCI Receive Interrupt Enable */
8630 
8631 /* UCAxIFG Control Bits */
8632 #define UCTXIFG (0x0002u) /* USCI Transmit Interrupt Flag */
8633 #define UCRXIFG (0x0001u) /* USCI Receive Interrupt Flag */
8634 
8635 /* UCAxIFG Control Bits */
8636 #define UCTXIFG_L (0x0002u) /* USCI Transmit Interrupt Flag */
8637 #define UCRXIFG_L (0x0001u) /* USCI Receive Interrupt Flag */
8638 
8639 /* UCBxIFG Control Bits */
8640 #define UCNACKIFG (0x0020u) /* NAK Condition interrupt Flag */
8641 #define UCALIFG (0x0010u) /* Arbitration Lost interrupt Flag */
8642 #define UCSTPIFG (0x0008u) /* STOP Condition interrupt Flag */
8643 #define UCSTTIFG (0x0004u) /* START Condition interrupt Flag */
8644 #define UCTXIFG (0x0002u) /* USCI Transmit Interrupt Flag */
8645 #define UCRXIFG (0x0001u) /* USCI Receive Interrupt Flag */
8646 
8647 /* UCBxIFG Control Bits */
8648 #define UCNACKIFG_L (0x0020u) /* NAK Condition interrupt Flag */
8649 #define UCALIFG_L (0x0010u) /* Arbitration Lost interrupt Flag */
8650 #define UCSTPIFG_L (0x0008u) /* STOP Condition interrupt Flag */
8651 #define UCSTTIFG_L (0x0004u) /* START Condition interrupt Flag */
8652 #define UCTXIFG_L (0x0002u) /* USCI Transmit Interrupt Flag */
8653 #define UCRXIFG_L (0x0001u) /* USCI Receive Interrupt Flag */
8654 
8655 /* USCI Definitions */
8656 #define USCI_NONE (0x0000u) /* No Interrupt pending */
8657 #define USCI_UCRXIFG (0x0002u) /* USCI UCRXIFG */
8658 #define USCI_UCTXIFG (0x0004u) /* USCI UCTXIFG */
8659 #define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */
8660 #define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */
8661 #define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/
8662 #define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/
8663 #define USCI_I2C_UCRXIFG (0x000Au) /* USCI I2C Mode: UCRXIFG */
8664 #define USCI_I2C_UCTXIFG (0x000Cu) /* USCI I2C Mode: UCTXIFG */
8665 
8666 #endif
8667 /************************************************************
8668 * USCI Ax
8669 ************************************************************/
8670 #ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */
8671 
8672 #define OFS_UCAxCTLW0 (0x0000u) /* USCI Ax Control Word Register 0 */
8673 #define OFS_UCAxCTLW0_L OFS_UCAxCTLW0
8674 #define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1
8675 #define OFS_UCAxCTL0 (0x0001u)
8676 #define OFS_UCAxCTL1 (0x0000u)
8677 #define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */
8678 #define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */
8679 #define OFS_UCAxCTLW1 (0x0002u) /* USCI Ax Control Word Register 1 */
8680 #define OFS_UCAxCTLW1_L OFS_UCAxCTLW1
8681 #define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1
8682 #define OFS_UCAxBRW (0x0006u) /* USCI Ax Baud Word Rate 0 */
8683 #define OFS_UCAxBRW_L OFS_UCAxBRW
8684 #define OFS_UCAxBRW_H OFS_UCAxBRW+1
8685 #define OFS_UCAxBR0 (0x0006u)
8686 #define OFS_UCAxBR1 (0x0007u)
8687 #define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */
8688 #define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */
8689 #define OFS_UCAxMCTLW (0x0008u) /* USCI Ax Modulation Control */
8690 #define OFS_UCAxMCTLW_L OFS_UCAxMCTLW
8691 #define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1
8692 #define OFS_UCAxSTATW (0x000Au) /* USCI Ax Status Register */
8693 #define OFS_UCAxRXBUF (0x000Cu) /* USCI Ax Receive Buffer */
8694 #define OFS_UCAxRXBUF_L OFS_UCAxRXBUF
8695 #define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1
8696 #define OFS_UCAxTXBUF (0x000Eu) /* USCI Ax Transmit Buffer */
8697 #define OFS_UCAxTXBUF_L OFS_UCAxTXBUF
8698 #define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1
8699 #define OFS_UCAxABCTL (0x0010u) /* USCI Ax LIN Control */
8700 #define OFS_UCAxIRCTL (0x0012u) /* USCI Ax IrDA Transmit Control */
8701 #define OFS_UCAxIRCTL_L OFS_UCAxIRCTL
8702 #define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1
8703 #define OFS_UCAxIRTCTL (0x0012u)
8704 #define OFS_UCAxIRRCTL (0x0013u)
8705 #define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */
8706 #define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */
8707 #define OFS_UCAxIE (0x001Au) /* USCI Ax Interrupt Enable Register */
8708 #define OFS_UCAxIE_L OFS_UCAxIE
8709 #define OFS_UCAxIE_H OFS_UCAxIE+1
8710 #define OFS_UCAxIFG (0x001Cu) /* USCI Ax Interrupt Flags Register */
8711 #define OFS_UCAxIFG_L OFS_UCAxIFG
8712 #define OFS_UCAxIFG_H OFS_UCAxIFG+1
8713 #define OFS_UCAxIE__UART (0x001Au)
8714 #define OFS_UCAxIE__UART_L OFS_UCAxIE__UART
8715 #define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1
8716 #define OFS_UCAxIFG__UART (0x001Cu)
8717 #define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART
8718 #define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1
8719 #define OFS_UCAxIV (0x001Eu) /* USCI Ax Interrupt Vector Register */
8720 
8721 #define OFS_UCAxCTLW0__SPI (0x0000u)
8722 #define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI
8723 #define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1
8724 #define OFS_UCAxCTL0__SPI (0x0001u)
8725 #define OFS_UCAxCTL1__SPI (0x0000u)
8726 #define OFS_UCAxBRW__SPI (0x0006u)
8727 #define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI
8728 #define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1
8729 #define OFS_UCAxBR0__SPI (0x0006u)
8730 #define OFS_UCAxBR1__SPI (0x0007u)
8731 #define OFS_UCAxSTATW__SPI (0x000Au)
8732 #define OFS_UCAxRXBUF__SPI (0x000Cu)
8733 #define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI
8734 #define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1
8735 #define OFS_UCAxTXBUF__SPI (0x000Eu)
8736 #define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI
8737 #define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1
8738 #define OFS_UCAxIE__SPI (0x001Au)
8739 #define OFS_UCAxIFG__SPI (0x001Cu)
8740 #define OFS_UCAxIV__SPI (0x001Eu)
8741 
8742 #endif
8743 /************************************************************
8744 * USCI Bx
8745 ************************************************************/
8746 #ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */
8747 
8748 #define OFS_UCBxCTLW0__SPI (0x0000u)
8749 #define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI
8750 #define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1
8751 #define OFS_UCBxCTL0__SPI (0x0001u)
8752 #define OFS_UCBxCTL1__SPI (0x0000u)
8753 #define OFS_UCBxBRW__SPI (0x0006u)
8754 #define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI
8755 #define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1
8756 #define OFS_UCBxBR0__SPI (0x0006u)
8757 #define OFS_UCBxBR1__SPI (0x0007u)
8758 #define OFS_UCBxSTATW__SPI (0x0008u)
8759 #define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI
8760 #define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1
8761 #define OFS_UCBxRXBUF__SPI (0x000Cu)
8762 #define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI
8763 #define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1
8764 #define OFS_UCBxTXBUF__SPI (0x000Eu)
8765 #define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI
8766 #define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1
8767 #define OFS_UCBxIE__SPI (0x002Au)
8768 #define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI
8769 #define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1
8770 #define OFS_UCBxIFG__SPI (0x002Cu)
8771 #define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI
8772 #define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1
8773 #define OFS_UCBxIV__SPI (0x002Eu)
8774 
8775 #define OFS_UCBxCTLW0 (0x0000u) /* USCI Bx Control Word Register 0 */
8776 #define OFS_UCBxCTLW0_L OFS_UCBxCTLW0
8777 #define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1
8778 #define OFS_UCBxCTL0 (0x0001u)
8779 #define OFS_UCBxCTL1 (0x0000u)
8780 #define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */
8781 #define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */
8782 #define OFS_UCBxCTLW1 (0x0002u) /* USCI Bx Control Word Register 1 */
8783 #define OFS_UCBxCTLW1_L OFS_UCBxCTLW1
8784 #define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1
8785 #define OFS_UCBxBRW (0x0006u) /* USCI Bx Baud Word Rate 0 */
8786 #define OFS_UCBxBRW_L OFS_UCBxBRW
8787 #define OFS_UCBxBRW_H OFS_UCBxBRW+1
8788 #define OFS_UCBxBR0 (0x0006u)
8789 #define OFS_UCBxBR1 (0x0007u)
8790 #define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */
8791 #define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */
8792 #define OFS_UCBxSTATW (0x0008u) /* USCI Bx Status Word Register */
8793 #define OFS_UCBxSTATW_L OFS_UCBxSTATW
8794 #define OFS_UCBxSTATW_H OFS_UCBxSTATW+1
8795 #define OFS_UCBxSTATW__I2C (0x0008u)
8796 #define OFS_UCBxSTAT__I2C (0x0008u)
8797 #define OFS_UCBxBCNT__I2C (0x0009u)
8798 #define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */
8799 #define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */
8800 #define OFS_UCBxTBCNT (0x000Au) /* USCI Bx Byte Counter Threshold Register */
8801 #define OFS_UCBxTBCNT_L OFS_UCBxTBCNT
8802 #define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1
8803 #define OFS_UCBxRXBUF (0x000Cu) /* USCI Bx Receive Buffer */
8804 #define OFS_UCBxRXBUF_L OFS_UCBxRXBUF
8805 #define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1
8806 #define OFS_UCBxTXBUF (0x000Eu) /* USCI Bx Transmit Buffer */
8807 #define OFS_UCBxTXBUF_L OFS_UCBxTXBUF
8808 #define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1
8809 #define OFS_UCBxI2COA0 (0x0014u) /* USCI Bx I2C Own Address 0 */
8810 #define OFS_UCBxI2COA0_L OFS_UCBxI2COA0
8811 #define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1
8812 #define OFS_UCBxI2COA1 (0x0016u) /* USCI Bx I2C Own Address 1 */
8813 #define OFS_UCBxI2COA1_L OFS_UCBxI2COA1
8814 #define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1
8815 #define OFS_UCBxI2COA2 (0x0018u) /* USCI Bx I2C Own Address 2 */
8816 #define OFS_UCBxI2COA2_L OFS_UCBxI2COA2
8817 #define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1
8818 #define OFS_UCBxI2COA3 (0x001Au) /* USCI Bx I2C Own Address 3 */
8819 #define OFS_UCBxI2COA3_L OFS_UCBxI2COA3
8820 #define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1
8821 #define OFS_UCBxADDRX (0x001Cu) /* USCI Bx Received Address Register */
8822 #define OFS_UCBxADDRX_L OFS_UCBxADDRX
8823 #define OFS_UCBxADDRX_H OFS_UCBxADDRX+1
8824 #define OFS_UCBxADDMASK (0x001Eu) /* USCI Bx Address Mask Register */
8825 #define OFS_UCBxADDMASK_L OFS_UCBxADDMASK
8826 #define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1
8827 #define OFS_UCBxI2CSA (0x0020u) /* USCI Bx I2C Slave Address */
8828 #define OFS_UCBxI2CSA_L OFS_UCBxI2CSA
8829 #define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1
8830 #define OFS_UCBxIE (0x002Au) /* USCI Bx Interrupt Enable Register */
8831 #define OFS_UCBxIE_L OFS_UCBxIE
8832 #define OFS_UCBxIE_H OFS_UCBxIE+1
8833 #define OFS_UCBxIFG (0x002Cu) /* USCI Bx Interrupt Flags Register */
8834 #define OFS_UCBxIFG_L OFS_UCBxIFG
8835 #define OFS_UCBxIFG_H OFS_UCBxIFG+1
8836 #define OFS_UCBxIE__I2C (0x002Au)
8837 #define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C
8838 #define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1
8839 #define OFS_UCBxIFG__I2C (0x002Cu)
8840 #define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C
8841 #define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1
8842 #define OFS_UCBxIV (0x002Eu) /* USCI Bx Interrupt Vector Register */
8843 
8844 #endif
8845 #if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__))
8846 
8847 // UCAxCTLW0 UART-Mode Control Bits
8848 #define UCPEN (0x8000u) /* Async. Mode: Parity enable */
8849 #define UCPAR (0x4000u) /* Async. Mode: Parity 0:odd / 1:even */
8850 #define UCMSB (0x2000u) /* Async. Mode: MSB first 0:LSB / 1:MSB */
8851 #define UC7BIT (0x1000u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
8852 #define UCSPB (0x0800u) /* Async. Mode: Stop Bits 0:one / 1: two */
8853 #define UCMODE1 (0x0400u) /* Async. Mode: USCI Mode 1 */
8854 #define UCMODE0 (0x0200u) /* Async. Mode: USCI Mode 0 */
8855 #define UCSYNC (0x0100u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
8856 #define UCSSEL1 (0x0080u) /* USCI 0 Clock Source Select 1 */
8857 #define UCSSEL0 (0x0040u) /* USCI 0 Clock Source Select 0 */
8858 #define UCRXEIE (0x0020u) /* RX Error interrupt enable */
8859 #define UCBRKIE (0x0010u) /* Break interrupt enable */
8860 #define UCDORM (0x0008u) /* Dormant (Sleep) Mode */
8861 #define UCTXADDR (0x0004u) /* Send next Data as Address */
8862 #define UCTXBRK (0x0002u) /* Send next Data as Break */
8863 #define UCSWRST (0x0001u) /* USCI Software Reset */
8864 
8865 // UCAxCTLW0 UART-Mode Control Bits
8866 #define UCSSEL1_L (0x0080u) /* USCI 0 Clock Source Select 1 */
8867 #define UCSSEL0_L (0x0040u) /* USCI 0 Clock Source Select 0 */
8868 #define UCRXEIE_L (0x0020u) /* RX Error interrupt enable */
8869 #define UCBRKIE_L (0x0010u) /* Break interrupt enable */
8870 #define UCDORM_L (0x0008u) /* Dormant (Sleep) Mode */
8871 #define UCTXADDR_L (0x0004u) /* Send next Data as Address */
8872 #define UCTXBRK_L (0x0002u) /* Send next Data as Break */
8873 #define UCSWRST_L (0x0001u) /* USCI Software Reset */
8874 
8875 // UCAxCTLW0 UART-Mode Control Bits
8876 #define UCPEN_H (0x0080u) /* Async. Mode: Parity enable */
8877 #define UCPAR_H (0x0040u) /* Async. Mode: Parity 0:odd / 1:even */
8878 #define UCMSB_H (0x0020u) /* Async. Mode: MSB first 0:LSB / 1:MSB */
8879 #define UC7BIT_H (0x0010u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
8880 #define UCSPB_H (0x0008u) /* Async. Mode: Stop Bits 0:one / 1: two */
8881 #define UCMODE1_H (0x0004u) /* Async. Mode: USCI Mode 1 */
8882 #define UCMODE0_H (0x0002u) /* Async. Mode: USCI Mode 0 */
8883 #define UCSYNC_H (0x0001u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
8884 
8885 // UCxxCTLW0 SPI-Mode Control Bits
8886 #define UCCKPH (0x8000u) /* Sync. Mode: Clock Phase */
8887 #define UCCKPL (0x4000u) /* Sync. Mode: Clock Polarity */
8888 #define UCMST (0x0800u) /* Sync. Mode: Master Select */
8889 //#define res (0x0020u) /* reserved */
8890 //#define res (0x0010u) /* reserved */
8891 //#define res (0x0008u) /* reserved */
8892 //#define res (0x0004u) /* reserved */
8893 #define UCSTEM (0x0002u) /* USCI STE Mode */
8894 
8895 // UCBxCTLW0 I2C-Mode Control Bits
8896 #define UCA10 (0x8000u) /* 10-bit Address Mode */
8897 #define UCSLA10 (0x4000u) /* 10-bit Slave Address Mode */
8898 #define UCMM (0x2000u) /* Multi-Master Environment */
8899 //#define res (0x1000u) /* reserved */
8900 //#define res (0x0100u) /* reserved */
8901 #define UCTXACK (0x0020u) /* Transmit ACK */
8902 #define UCTR (0x0010u) /* Transmit/Receive Select/Flag */
8903 #define UCTXNACK (0x0008u) /* Transmit NACK */
8904 #define UCTXSTP (0x0004u) /* Transmit STOP */
8905 #define UCTXSTT (0x0002u) /* Transmit START */
8906 
8907 // UCBxCTLW0 I2C-Mode Control Bits
8908 //#define res (0x1000u) /* reserved */
8909 //#define res (0x0100u) /* reserved */
8910 #define UCTXACK_L (0x0020u) /* Transmit ACK */
8911 #define UCTR_L (0x0010u) /* Transmit/Receive Select/Flag */
8912 #define UCTXNACK_L (0x0008u) /* Transmit NACK */
8913 #define UCTXSTP_L (0x0004u) /* Transmit STOP */
8914 #define UCTXSTT_L (0x0002u) /* Transmit START */
8915 
8916 // UCBxCTLW0 I2C-Mode Control Bits
8917 #define UCA10_H (0x0080u) /* 10-bit Address Mode */
8918 #define UCSLA10_H (0x0040u) /* 10-bit Slave Address Mode */
8919 #define UCMM_H (0x0020u) /* Multi-Master Environment */
8920 //#define res (0x1000u) /* reserved */
8921 //#define res (0x0100u) /* reserved */
8922 
8923 #define UCMODE_0 (0x0000u) /* Sync. Mode: USCI Mode: 0 */
8924 #define UCMODE_1 (0x0200u) /* Sync. Mode: USCI Mode: 1 */
8925 #define UCMODE_2 (0x0400u) /* Sync. Mode: USCI Mode: 2 */
8926 #define UCMODE_3 (0x0600u) /* Sync. Mode: USCI Mode: 3 */
8927 
8928 #define UCSSEL_0 (0x0000u) /* USCI 0 Clock Source: 0 */
8929 #define UCSSEL_1 (0x0040u) /* USCI 0 Clock Source: 1 */
8930 #define UCSSEL_2 (0x0080u) /* USCI 0 Clock Source: 2 */
8931 #define UCSSEL_3 (0x00C0u) /* USCI 0 Clock Source: 3 */
8932 #define UCSSEL__UCLK (0x0000u) /* USCI 0 Clock Source: UCLK */
8933 #define UCSSEL__ACLK (0x0040u) /* USCI 0 Clock Source: ACLK */
8934 #define UCSSEL__SMCLK (0x0080u) /* USCI 0 Clock Source: SMCLK */
8935 
8936 // UCAxCTLW1 UART-Mode Control Bits
8937 #define UCGLIT1 (0x0002u) /* USCI Deglitch Time Bit 1 */
8938 #define UCGLIT0 (0x0001u) /* USCI Deglitch Time Bit 0 */
8939 
8940 // UCAxCTLW1 UART-Mode Control Bits
8941 #define UCGLIT1_L (0x0002u) /* USCI Deglitch Time Bit 1 */
8942 #define UCGLIT0_L (0x0001u) /* USCI Deglitch Time Bit 0 */
8943 
8944 // UCBxCTLW1 I2C-Mode Control Bits
8945 #define UCETXINT (0x0100u) /* USCI Early UCTXIFG0 */
8946 #define UCCLTO1 (0x0080u) /* USCI Clock low timeout Bit: 1 */
8947 #define UCCLTO0 (0x0040u) /* USCI Clock low timeout Bit: 0 */
8948 #define UCSTPNACK (0x0020u) /* USCI Acknowledge Stop last byte */
8949 #define UCSWACK (0x0010u) /* USCI Software controlled ACK */
8950 #define UCASTP1 (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */
8951 #define UCASTP0 (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */
8952 #define UCGLIT1 (0x0002u) /* USCI Deglitch time Bit: 1 */
8953 #define UCGLIT0 (0x0001u) /* USCI Deglitch time Bit: 0 */
8954 
8955 // UCBxCTLW1 I2C-Mode Control Bits
8956 #define UCCLTO1_L (0x0080u) /* USCI Clock low timeout Bit: 1 */
8957 #define UCCLTO0_L (0x0040u) /* USCI Clock low timeout Bit: 0 */
8958 #define UCSTPNACK_L (0x0020u) /* USCI Acknowledge Stop last byte */
8959 #define UCSWACK_L (0x0010u) /* USCI Software controlled ACK */
8960 #define UCASTP1_L (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */
8961 #define UCASTP0_L (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */
8962 #define UCGLIT1_L (0x0002u) /* USCI Deglitch time Bit: 1 */
8963 #define UCGLIT0_L (0x0001u) /* USCI Deglitch time Bit: 0 */
8964 
8965 // UCBxCTLW1 I2C-Mode Control Bits
8966 #define UCETXINT_H (0x0001u) /* USCI Early UCTXIFG0 */
8967 
8968 #define UCGLIT_0 (0x0000u) /* USCI Deglitch time: 0 */
8969 #define UCGLIT_1 (0x0001u) /* USCI Deglitch time: 1 */
8970 #define UCGLIT_2 (0x0002u) /* USCI Deglitch time: 2 */
8971 #define UCGLIT_3 (0x0003u) /* USCI Deglitch time: 3 */
8972 
8973 #define UCASTP_0 (0x0000u) /* USCI Automatic Stop condition generation: 0 */
8974 #define UCASTP_1 (0x0004u) /* USCI Automatic Stop condition generation: 1 */
8975 #define UCASTP_2 (0x0008u) /* USCI Automatic Stop condition generation: 2 */
8976 #define UCASTP_3 (0x000Cu) /* USCI Automatic Stop condition generation: 3 */
8977 
8978 #define UCCLTO_0 (0x0000u) /* USCI Clock low timeout: 0 */
8979 #define UCCLTO_1 (0x0040u) /* USCI Clock low timeout: 1 */
8980 #define UCCLTO_2 (0x0080u) /* USCI Clock low timeout: 2 */
8981 #define UCCLTO_3 (0x00C0u) /* USCI Clock low timeout: 3 */
8982 
8983 /* UCAxMCTLW Control Bits */
8984 #define UCBRS7 (0x8000u) /* USCI Second Stage Modulation Select 7 */
8985 #define UCBRS6 (0x4000u) /* USCI Second Stage Modulation Select 6 */
8986 #define UCBRS5 (0x2000u) /* USCI Second Stage Modulation Select 5 */
8987 #define UCBRS4 (0x1000u) /* USCI Second Stage Modulation Select 4 */
8988 #define UCBRS3 (0x0800u) /* USCI Second Stage Modulation Select 3 */
8989 #define UCBRS2 (0x0400u) /* USCI Second Stage Modulation Select 2 */
8990 #define UCBRS1 (0x0200u) /* USCI Second Stage Modulation Select 1 */
8991 #define UCBRS0 (0x0100u) /* USCI Second Stage Modulation Select 0 */
8992 #define UCBRF3 (0x0080u) /* USCI First Stage Modulation Select 3 */
8993 #define UCBRF2 (0x0040u) /* USCI First Stage Modulation Select 2 */
8994 #define UCBRF1 (0x0020u) /* USCI First Stage Modulation Select 1 */
8995 #define UCBRF0 (0x0010u) /* USCI First Stage Modulation Select 0 */
8996 #define UCOS16 (0x0001u) /* USCI 16-times Oversampling enable */
8997 
8998 /* UCAxMCTLW Control Bits */
8999 #define UCBRF3_L (0x0080u) /* USCI First Stage Modulation Select 3 */
9000 #define UCBRF2_L (0x0040u) /* USCI First Stage Modulation Select 2 */
9001 #define UCBRF1_L (0x0020u) /* USCI First Stage Modulation Select 1 */
9002 #define UCBRF0_L (0x0010u) /* USCI First Stage Modulation Select 0 */
9003 #define UCOS16_L (0x0001u) /* USCI 16-times Oversampling enable */
9004 
9005 /* UCAxMCTLW Control Bits */
9006 #define UCBRS7_H (0x0080u) /* USCI Second Stage Modulation Select 7 */
9007 #define UCBRS6_H (0x0040u) /* USCI Second Stage Modulation Select 6 */
9008 #define UCBRS5_H (0x0020u) /* USCI Second Stage Modulation Select 5 */
9009 #define UCBRS4_H (0x0010u) /* USCI Second Stage Modulation Select 4 */
9010 #define UCBRS3_H (0x0008u) /* USCI Second Stage Modulation Select 3 */
9011 #define UCBRS2_H (0x0004u) /* USCI Second Stage Modulation Select 2 */
9012 #define UCBRS1_H (0x0002u) /* USCI Second Stage Modulation Select 1 */
9013 #define UCBRS0_H (0x0001u) /* USCI Second Stage Modulation Select 0 */
9014 
9015 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
9016 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
9017 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
9018 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
9019 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
9020 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
9021 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
9022 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
9023 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
9024 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
9025 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
9026 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
9027 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
9028 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
9029 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
9030 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
9031 
9032 /* UCAxSTATW Control Bits */
9033 #define UCLISTEN (0x0080u) /* USCI Listen mode */
9034 #define UCFE (0x0040u) /* USCI Frame Error Flag */
9035 #define UCOE (0x0020u) /* USCI Overrun Error Flag */
9036 #define UCPE (0x0010u) /* USCI Parity Error Flag */
9037 #define UCBRK (0x0008u) /* USCI Break received */
9038 #define UCRXERR (0x0004u) /* USCI RX Error Flag */
9039 #define UCADDR (0x0002u) /* USCI Address received Flag */
9040 #define UCBUSY (0x0001u) /* USCI Busy Flag */
9041 #define UCIDLE (0x0002u) /* USCI Idle line detected Flag */
9042 
9043 /* UCBxSTATW I2C Control Bits */
9044 #define UCBCNT7 (0x8000u) /* USCI Byte Counter Bit 7 */
9045 #define UCBCNT6 (0x4000u) /* USCI Byte Counter Bit 6 */
9046 #define UCBCNT5 (0x2000u) /* USCI Byte Counter Bit 5 */
9047 #define UCBCNT4 (0x1000u) /* USCI Byte Counter Bit 4 */
9048 #define UCBCNT3 (0x0800u) /* USCI Byte Counter Bit 3 */
9049 #define UCBCNT2 (0x0400u) /* USCI Byte Counter Bit 2 */
9050 #define UCBCNT1 (0x0200u) /* USCI Byte Counter Bit 1 */
9051 #define UCBCNT0 (0x0100u) /* USCI Byte Counter Bit 0 */
9052 #define UCSCLLOW (0x0040u) /* SCL low */
9053 #define UCGC (0x0020u) /* General Call address received Flag */
9054 #define UCBBUSY (0x0010u) /* Bus Busy Flag */
9055 
9056 /* UCBxTBCNT I2C Control Bits */
9057 #define UCTBCNT7 (0x0080u) /* USCI Byte Counter Bit 7 */
9058 #define UCTBCNT6 (0x0040u) /* USCI Byte Counter Bit 6 */
9059 #define UCTBCNT5 (0x0020u) /* USCI Byte Counter Bit 5 */
9060 #define UCTBCNT4 (0x0010u) /* USCI Byte Counter Bit 4 */
9061 #define UCTBCNT3 (0x0008u) /* USCI Byte Counter Bit 3 */
9062 #define UCTBCNT2 (0x0004u) /* USCI Byte Counter Bit 2 */
9063 #define UCTBCNT1 (0x0002u) /* USCI Byte Counter Bit 1 */
9064 #define UCTBCNT0 (0x0001u) /* USCI Byte Counter Bit 0 */
9065 
9066 /* UCAxIRCTL Control Bits */
9067 #define UCIRRXFL5 (0x8000u) /* IRDA Receive Filter Length 5 */
9068 #define UCIRRXFL4 (0x4000u) /* IRDA Receive Filter Length 4 */
9069 #define UCIRRXFL3 (0x2000u) /* IRDA Receive Filter Length 3 */
9070 #define UCIRRXFL2 (0x1000u) /* IRDA Receive Filter Length 2 */
9071 #define UCIRRXFL1 (0x0800u) /* IRDA Receive Filter Length 1 */
9072 #define UCIRRXFL0 (0x0400u) /* IRDA Receive Filter Length 0 */
9073 #define UCIRRXPL (0x0200u) /* IRDA Receive Input Polarity */
9074 #define UCIRRXFE (0x0100u) /* IRDA Receive Filter enable */
9075 #define UCIRTXPL5 (0x0080u) /* IRDA Transmit Pulse Length 5 */
9076 #define UCIRTXPL4 (0x0040u) /* IRDA Transmit Pulse Length 4 */
9077 #define UCIRTXPL3 (0x0020u) /* IRDA Transmit Pulse Length 3 */
9078 #define UCIRTXPL2 (0x0010u) /* IRDA Transmit Pulse Length 2 */
9079 #define UCIRTXPL1 (0x0008u) /* IRDA Transmit Pulse Length 1 */
9080 #define UCIRTXPL0 (0x0004u) /* IRDA Transmit Pulse Length 0 */
9081 #define UCIRTXCLK (0x0002u) /* IRDA Transmit Pulse Clock Select */
9082 #define UCIREN (0x0001u) /* IRDA Encoder/Decoder enable */
9083 
9084 /* UCAxIRCTL Control Bits */
9085 #define UCIRTXPL5_L (0x0080u) /* IRDA Transmit Pulse Length 5 */
9086 #define UCIRTXPL4_L (0x0040u) /* IRDA Transmit Pulse Length 4 */
9087 #define UCIRTXPL3_L (0x0020u) /* IRDA Transmit Pulse Length 3 */
9088 #define UCIRTXPL2_L (0x0010u) /* IRDA Transmit Pulse Length 2 */
9089 #define UCIRTXPL1_L (0x0008u) /* IRDA Transmit Pulse Length 1 */
9090 #define UCIRTXPL0_L (0x0004u) /* IRDA Transmit Pulse Length 0 */
9091 #define UCIRTXCLK_L (0x0002u) /* IRDA Transmit Pulse Clock Select */
9092 #define UCIREN_L (0x0001u) /* IRDA Encoder/Decoder enable */
9093 
9094 /* UCAxIRCTL Control Bits */
9095 #define UCIRRXFL5_H (0x0080u) /* IRDA Receive Filter Length 5 */
9096 #define UCIRRXFL4_H (0x0040u) /* IRDA Receive Filter Length 4 */
9097 #define UCIRRXFL3_H (0x0020u) /* IRDA Receive Filter Length 3 */
9098 #define UCIRRXFL2_H (0x0010u) /* IRDA Receive Filter Length 2 */
9099 #define UCIRRXFL1_H (0x0008u) /* IRDA Receive Filter Length 1 */
9100 #define UCIRRXFL0_H (0x0004u) /* IRDA Receive Filter Length 0 */
9101 #define UCIRRXPL_H (0x0002u) /* IRDA Receive Input Polarity */
9102 #define UCIRRXFE_H (0x0001u) /* IRDA Receive Filter enable */
9103 
9104 /* UCAxABCTL Control Bits */
9105 //#define res (0x80) /* reserved */
9106 //#define res (0x40) /* reserved */
9107 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
9108 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
9109 #define UCSTOE (0x08) /* Sync-Field Timeout error */
9110 #define UCBTOE (0x04) /* Break Timeout error */
9111 //#define res (0x02) /* reserved */
9112 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */
9113 
9114 /* UCBxI2COA0 Control Bits */
9115 #define UCGCEN (0x8000u) /* I2C General Call enable */
9116 #define UCOAEN (0x0400u) /* I2C Own Address enable */
9117 #define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */
9118 #define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */
9119 #define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */
9120 #define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */
9121 #define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */
9122 #define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */
9123 #define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */
9124 #define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */
9125 #define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */
9126 #define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */
9127 
9128 /* UCBxI2COA0 Control Bits */
9129 #define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */
9130 #define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */
9131 #define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */
9132 #define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */
9133 #define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */
9134 #define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */
9135 #define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */
9136 #define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */
9137 
9138 /* UCBxI2COA0 Control Bits */
9139 #define UCGCEN_H (0x0080u) /* I2C General Call enable */
9140 #define UCOAEN_H (0x0004u) /* I2C Own Address enable */
9141 #define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */
9142 #define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */
9143 
9144 /* UCBxI2COAx Control Bits */
9145 #define UCOAEN (0x0400u) /* I2C Own Address enable */
9146 #define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */
9147 #define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */
9148 #define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */
9149 #define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */
9150 #define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */
9151 #define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */
9152 #define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */
9153 #define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */
9154 #define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */
9155 #define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */
9156 
9157 /* UCBxI2COAx Control Bits */
9158 #define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */
9159 #define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */
9160 #define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */
9161 #define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */
9162 #define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */
9163 #define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */
9164 #define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */
9165 #define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */
9166 
9167 /* UCBxI2COAx Control Bits */
9168 #define UCOAEN_H (0x0004u) /* I2C Own Address enable */
9169 #define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */
9170 #define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */
9171 
9172 /* UCBxADDRX Control Bits */
9173 #define UCADDRX9 (0x0200u) /* I2C Receive Address Bit 9 */
9174 #define UCADDRX8 (0x0100u) /* I2C Receive Address Bit 8 */
9175 #define UCADDRX7 (0x0080u) /* I2C Receive Address Bit 7 */
9176 #define UCADDRX6 (0x0040u) /* I2C Receive Address Bit 6 */
9177 #define UCADDRX5 (0x0020u) /* I2C Receive Address Bit 5 */
9178 #define UCADDRX4 (0x0010u) /* I2C Receive Address Bit 4 */
9179 #define UCADDRX3 (0x0008u) /* I2C Receive Address Bit 3 */
9180 #define UCADDRX2 (0x0004u) /* I2C Receive Address Bit 2 */
9181 #define UCADDRX1 (0x0002u) /* I2C Receive Address Bit 1 */
9182 #define UCADDRX0 (0x0001u) /* I2C Receive Address Bit 0 */
9183 
9184 /* UCBxADDRX Control Bits */
9185 #define UCADDRX7_L (0x0080u) /* I2C Receive Address Bit 7 */
9186 #define UCADDRX6_L (0x0040u) /* I2C Receive Address Bit 6 */
9187 #define UCADDRX5_L (0x0020u) /* I2C Receive Address Bit 5 */
9188 #define UCADDRX4_L (0x0010u) /* I2C Receive Address Bit 4 */
9189 #define UCADDRX3_L (0x0008u) /* I2C Receive Address Bit 3 */
9190 #define UCADDRX2_L (0x0004u) /* I2C Receive Address Bit 2 */
9191 #define UCADDRX1_L (0x0002u) /* I2C Receive Address Bit 1 */
9192 #define UCADDRX0_L (0x0001u) /* I2C Receive Address Bit 0 */
9193 
9194 /* UCBxADDRX Control Bits */
9195 #define UCADDRX9_H (0x0002u) /* I2C Receive Address Bit 9 */
9196 #define UCADDRX8_H (0x0001u) /* I2C Receive Address Bit 8 */
9197 
9198 /* UCBxADDMASK Control Bits */
9199 #define UCADDMASK9 (0x0200u) /* I2C Address Mask Bit 9 */
9200 #define UCADDMASK8 (0x0100u) /* I2C Address Mask Bit 8 */
9201 #define UCADDMASK7 (0x0080u) /* I2C Address Mask Bit 7 */
9202 #define UCADDMASK6 (0x0040u) /* I2C Address Mask Bit 6 */
9203 #define UCADDMASK5 (0x0020u) /* I2C Address Mask Bit 5 */
9204 #define UCADDMASK4 (0x0010u) /* I2C Address Mask Bit 4 */
9205 #define UCADDMASK3 (0x0008u) /* I2C Address Mask Bit 3 */
9206 #define UCADDMASK2 (0x0004u) /* I2C Address Mask Bit 2 */
9207 #define UCADDMASK1 (0x0002u) /* I2C Address Mask Bit 1 */
9208 #define UCADDMASK0 (0x0001u) /* I2C Address Mask Bit 0 */
9209 
9210 /* UCBxADDMASK Control Bits */
9211 #define UCADDMASK7_L (0x0080u) /* I2C Address Mask Bit 7 */
9212 #define UCADDMASK6_L (0x0040u) /* I2C Address Mask Bit 6 */
9213 #define UCADDMASK5_L (0x0020u) /* I2C Address Mask Bit 5 */
9214 #define UCADDMASK4_L (0x0010u) /* I2C Address Mask Bit 4 */
9215 #define UCADDMASK3_L (0x0008u) /* I2C Address Mask Bit 3 */
9216 #define UCADDMASK2_L (0x0004u) /* I2C Address Mask Bit 2 */
9217 #define UCADDMASK1_L (0x0002u) /* I2C Address Mask Bit 1 */
9218 #define UCADDMASK0_L (0x0001u) /* I2C Address Mask Bit 0 */
9219 
9220 /* UCBxADDMASK Control Bits */
9221 #define UCADDMASK9_H (0x0002u) /* I2C Address Mask Bit 9 */
9222 #define UCADDMASK8_H (0x0001u) /* I2C Address Mask Bit 8 */
9223 
9224 /* UCBxI2CSA Control Bits */
9225 #define UCSA9 (0x0200u) /* I2C Slave Address Bit 9 */
9226 #define UCSA8 (0x0100u) /* I2C Slave Address Bit 8 */
9227 #define UCSA7 (0x0080u) /* I2C Slave Address Bit 7 */
9228 #define UCSA6 (0x0040u) /* I2C Slave Address Bit 6 */
9229 #define UCSA5 (0x0020u) /* I2C Slave Address Bit 5 */
9230 #define UCSA4 (0x0010u) /* I2C Slave Address Bit 4 */
9231 #define UCSA3 (0x0008u) /* I2C Slave Address Bit 3 */
9232 #define UCSA2 (0x0004u) /* I2C Slave Address Bit 2 */
9233 #define UCSA1 (0x0002u) /* I2C Slave Address Bit 1 */
9234 #define UCSA0 (0x0001u) /* I2C Slave Address Bit 0 */
9235 
9236 /* UCBxI2CSA Control Bits */
9237 #define UCSA7_L (0x0080u) /* I2C Slave Address Bit 7 */
9238 #define UCSA6_L (0x0040u) /* I2C Slave Address Bit 6 */
9239 #define UCSA5_L (0x0020u) /* I2C Slave Address Bit 5 */
9240 #define UCSA4_L (0x0010u) /* I2C Slave Address Bit 4 */
9241 #define UCSA3_L (0x0008u) /* I2C Slave Address Bit 3 */
9242 #define UCSA2_L (0x0004u) /* I2C Slave Address Bit 2 */
9243 #define UCSA1_L (0x0002u) /* I2C Slave Address Bit 1 */
9244 #define UCSA0_L (0x0001u) /* I2C Slave Address Bit 0 */
9245 
9246 /* UCBxI2CSA Control Bits */
9247 #define UCSA9_H (0x0002u) /* I2C Slave Address Bit 9 */
9248 #define UCSA8_H (0x0001u) /* I2C Slave Address Bit 8 */
9249 
9250 /* UCAxIE UART Control Bits */
9251 #define UCTXCPTIE (0x0008u) /* UART Transmit Complete Interrupt Enable */
9252 #define UCSTTIE (0x0004u) /* UART Start Bit Interrupt Enalble */
9253 #define UCTXIE (0x0002u) /* UART Transmit Interrupt Enable */
9254 #define UCRXIE (0x0001u) /* UART Receive Interrupt Enable */
9255 
9256 /* UCAxIE/UCBxIE SPI Control Bits */
9257 
9258 /* UCBxIE I2C Control Bits */
9259 #define UCBIT9IE (0x4000u) /* I2C Bit 9 Position Interrupt Enable 3 */
9260 #define UCTXIE3 (0x2000u) /* I2C Transmit Interrupt Enable 3 */
9261 #define UCRXIE3 (0x1000u) /* I2C Receive Interrupt Enable 3 */
9262 #define UCTXIE2 (0x0800u) /* I2C Transmit Interrupt Enable 2 */
9263 #define UCRXIE2 (0x0400u) /* I2C Receive Interrupt Enable 2 */
9264 #define UCTXIE1 (0x0200u) /* I2C Transmit Interrupt Enable 1 */
9265 #define UCRXIE1 (0x0100u) /* I2C Receive Interrupt Enable 1 */
9266 #define UCCLTOIE (0x0080u) /* I2C Clock Low Timeout interrupt enable */
9267 #define UCBCNTIE (0x0040u) /* I2C Automatic stop assertion interrupt enable */
9268 #define UCNACKIE (0x0020u) /* I2C NACK Condition interrupt enable */
9269 #define UCALIE (0x0010u) /* I2C Arbitration Lost interrupt enable */
9270 #define UCSTPIE (0x0008u) /* I2C STOP Condition interrupt enable */
9271 #define UCSTTIE (0x0004u) /* I2C START Condition interrupt enable */
9272 #define UCTXIE0 (0x0002u) /* I2C Transmit Interrupt Enable 0 */
9273 #define UCRXIE0 (0x0001u) /* I2C Receive Interrupt Enable 0 */
9274 
9275 /* UCAxIFG UART Control Bits */
9276 #define UCTXCPTIFG (0x0008u) /* UART Transmit Complete Interrupt Flag */
9277 #define UCSTTIFG (0x0004u) /* UART Start Bit Interrupt Flag */
9278 #define UCTXIFG (0x0002u) /* UART Transmit Interrupt Flag */
9279 #define UCRXIFG (0x0001u) /* UART Receive Interrupt Flag */
9280 
9281 /* UCAxIFG/UCBxIFG SPI Control Bits */
9282 #define UCTXIFG (0x0002u) /* SPI Transmit Interrupt Flag */
9283 #define UCRXIFG (0x0001u) /* SPI Receive Interrupt Flag */
9284 
9285 /* UCBxIFG Control Bits */
9286 #define UCBIT9IFG (0x4000u) /* I2C Bit 9 Possition Interrupt Flag 3 */
9287 #define UCTXIFG3 (0x2000u) /* I2C Transmit Interrupt Flag 3 */
9288 #define UCRXIFG3 (0x1000u) /* I2C Receive Interrupt Flag 3 */
9289 #define UCTXIFG2 (0x0800u) /* I2C Transmit Interrupt Flag 2 */
9290 #define UCRXIFG2 (0x0400u) /* I2C Receive Interrupt Flag 2 */
9291 #define UCTXIFG1 (0x0200u) /* I2C Transmit Interrupt Flag 1 */
9292 #define UCRXIFG1 (0x0100u) /* I2C Receive Interrupt Flag 1 */
9293 #define UCCLTOIFG (0x0080u) /* I2C Clock low Timeout interrupt Flag */
9294 #define UCBCNTIFG (0x0040u) /* I2C Byte counter interrupt flag */
9295 #define UCNACKIFG (0x0020u) /* I2C NACK Condition interrupt Flag */
9296 #define UCALIFG (0x0010u) /* I2C Arbitration Lost interrupt Flag */
9297 #define UCSTPIFG (0x0008u) /* I2C STOP Condition interrupt Flag */
9298 #define UCSTTIFG (0x0004u) /* I2C START Condition interrupt Flag */
9299 #define UCTXIFG0 (0x0002u) /* I2C Transmit Interrupt Flag 0 */
9300 #define UCRXIFG0 (0x0001u) /* I2C Receive Interrupt Flag 0 */
9301 
9302 /* USCI UART Definitions */
9303 #define USCI_NONE (0x0000u) /* No Interrupt pending */
9304 #define USCI_UART_UCRXIFG (0x0002u) /* USCI UCRXIFG */
9305 #define USCI_UART_UCTXIFG (0x0004u) /* USCI UCTXIFG */
9306 #define USCI_UART_UCSTTIFG (0x0006u) /* USCI UCSTTIFG */
9307 #define USCI_UART_UCTXCPTIFG (0x0008u) /* USCI UCTXCPTIFG */
9308 
9309 /* USCI SPI Definitions */
9310 #define USCI_SPI_UCRXIFG (0x0002u) /* USCI UCRXIFG */
9311 #define USCI_SPI_UCTXIFG (0x0004u) /* USCI UCTXIFG */
9312 
9313 /* USCI I2C Definitions */
9314 #define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */
9315 #define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */
9316 #define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/
9317 #define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/
9318 #define USCI_I2C_UCRXIFG3 (0x000Au) /* USCI I2C Mode: UCRXIFG3 */
9319 #define USCI_I2C_UCTXIFG3 (0x000Cu) /* USCI I2C Mode: UCTXIFG3 */
9320 #define USCI_I2C_UCRXIFG2 (0x000Eu) /* USCI I2C Mode: UCRXIFG2 */
9321 #define USCI_I2C_UCTXIFG2 (0x0010u) /* USCI I2C Mode: UCTXIFG2 */
9322 #define USCI_I2C_UCRXIFG1 (0x0012u) /* USCI I2C Mode: UCRXIFG1 */
9323 #define USCI_I2C_UCTXIFG1 (0x0014u) /* USCI I2C Mode: UCTXIFG1 */
9324 #define USCI_I2C_UCRXIFG0 (0x0016u) /* USCI I2C Mode: UCRXIFG0 */
9325 #define USCI_I2C_UCTXIFG0 (0x0018u) /* USCI I2C Mode: UCTXIFG0 */
9326 #define USCI_I2C_UCBCNTIFG (0x001Au) /* USCI I2C Mode: UCBCNTIFG */
9327 #define USCI_I2C_UCCLTOIFG (0x001Cu) /* USCI I2C Mode: UCCLTOIFG */
9328 #define USCI_I2C_UCBIT9IFG (0x001Eu) /* USCI I2C Mode: UCBIT9IFG */
9329 
9330 #endif
9331 /************************************************************
9332 * WATCHDOG TIMER A
9333 ************************************************************/
9334 #ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */
9335 
9336 #define OFS_WDTCTL (0x000Cu) /* Watchdog Timer Control */
9337 #define OFS_WDTCTL_L OFS_WDTCTL
9338 #define OFS_WDTCTL_H OFS_WDTCTL+1
9339 /* The bit names have been prefixed with "WDT" */
9340 /* WDTCTL Control Bits */
9341 #define WDTIS0 (0x0001u) /* WDT - Timer Interval Select 0 */
9342 #define WDTIS1 (0x0002u) /* WDT - Timer Interval Select 1 */
9343 #define WDTIS2 (0x0004u) /* WDT - Timer Interval Select 2 */
9344 #define WDTCNTCL (0x0008u) /* WDT - Timer Clear */
9345 #define WDTTMSEL (0x0010u) /* WDT - Timer Mode Select */
9346 #define WDTSSEL0 (0x0020u) /* WDT - Timer Clock Source Select 0 */
9347 #define WDTSSEL1 (0x0040u) /* WDT - Timer Clock Source Select 1 */
9348 #define WDTHOLD (0x0080u) /* WDT - Timer hold */
9349 
9350 /* WDTCTL Control Bits */
9351 #define WDTIS0_L (0x0001u) /* WDT - Timer Interval Select 0 */
9352 #define WDTIS1_L (0x0002u) /* WDT - Timer Interval Select 1 */
9353 #define WDTIS2_L (0x0004u) /* WDT - Timer Interval Select 2 */
9354 #define WDTCNTCL_L (0x0008u) /* WDT - Timer Clear */
9355 #define WDTTMSEL_L (0x0010u) /* WDT - Timer Mode Select */
9356 #define WDTSSEL0_L (0x0020u) /* WDT - Timer Clock Source Select 0 */
9357 #define WDTSSEL1_L (0x0040u) /* WDT - Timer Clock Source Select 1 */
9358 #define WDTHOLD_L (0x0080u) /* WDT - Timer hold */
9359 
9360 #define WDTPW (0x5A00u)
9361 
9362 #define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */
9363 #define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */
9364 #define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
9365 #define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */
9366 #define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */
9367 #define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
9368 #define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
9369 #define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
9370 #define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */
9371 #define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */
9372 #define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
9373 #define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */
9374 #define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */
9375 #define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
9376 #define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
9377 #define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
9378 
9379 #define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
9380 #define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
9381 #define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
9382 #define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */
9383 #define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
9384 #define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
9385 #define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
9386 
9387 /* WDT-interval times [1ms] coded with Bits 0-2 */
9388 /* WDT is clocked by fSMCLK (assumed 1MHz) */
9389 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
9390 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
9391 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
9392 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
9393 /* WDT is clocked by fACLK (assumed 32KHz) */
9394 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
9395 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
9396 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
9397 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
9398 /* Watchdog mode -> reset after expired time */
9399 /* WDT is clocked by fSMCLK (assumed 1MHz) */
9400 #define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
9401 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
9402 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
9403 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
9404 /* WDT is clocked by fACLK (assumed 32KHz) */
9405 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
9406 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
9407 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
9408 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */
9409 
9410 #endif
9411 
9412 /************************************************************
9413 * TLV Descriptors
9414 ************************************************************/
9415 #define __MSP430_HAS_TLV__ /* Definition to show that Module is available */
9416 #define TLV_BASE __MSP430_BASEADDRESS_TLV__
9417 
9418 #define TLV_START (0x1A08u) /* Start Address of the TLV structure */
9419 #define TLV_END (0x1AFFu) /* End Address of the TLV structure */
9420 
9421 #define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */
9422 #define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
9423 #define TLV_Reserved3 (0x03) /* Future usage */
9424 #define TLV_Reserved4 (0x04) /* Future usage */
9425 #define TLV_BLANK (0x05) /* Blank descriptor */
9426 #define TLV_Reserved6 (0x06) /* Future usage */
9427 #define TLV_Reserved7 (0x07) /* Serial Number */
9428 #define TLV_DIERECORD (0x08) /* Die Record */
9429 #define TLV_ADCCAL (0x11) /* ADC12 calibration */
9430 #define TLV_ADC12CAL (0x11) /* ADC12 calibration */
9431 #define TLV_REFCAL (0x12) /* REF calibration */
9432 #define TLV_ADC10CAL (0x13) /* ADC10 calibration */
9433 #define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */
9434 #define TLV_TAGEXT (0xFE) /* Tag extender */
9435 #define TLV_TAGEND (0xFF) /* Tag End of Table */
9436 
9437 /************************************************************
9438 * Interrupt Vectors (offset from 0xFF80)
9439 ************************************************************/
9440 
9441 
9442 /************************************************************
9443 * End of Modules
9444 ************************************************************/
9445 #pragma language=default
9446 
9447 #endif /* #ifndef __msp430F5XX_F6XXGENERIC */
9448 
Copyright 2013, Texas Instruments Incorporated