CCS/msp430f5xx_6xxgeneric.h
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1 /* ============================================================================ */
2 /* Copyright (c) 2013, Texas Instruments Incorporated */
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31 /* ============================================================================ */
32 
33 /********************************************************************
34 *
35 * Standard register and bit definitions for the Texas Instruments
36 * MSP430 microcontroller.
37 *
38 * This file supports assembler and C development for
39 * MSP430F5XX_F6XXGENERIC device.
40 *
41 * Texas Instruments, Version 1.0
42 *
43 * Rev. 1.0, Setup
44 *
45 *
46 ********************************************************************/
47 
48 #ifndef __msp430F5XX_F6XXGENERIC
49 #define __msp430F5XX_F6XXGENERIC
50 
51 //#define __MSP430_HEADER_VERSION__ 1093
52 
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
56 
57 
58 /*----------------------------------------------------------------------------*/
59 /* PERIPHERAL FILE MAP */
60 /*----------------------------------------------------------------------------*/
61 
62 #ifndef SFR_8BIT
63 /* External references resolved by a device-specific linker command file */
64 #define SFR_8BIT(address) extern volatile unsigned char address
65 #define SFR_16BIT(address) extern volatile unsigned int address
66 //#define SFR_20BIT(address) extern volatile unsigned int address
67 typedef void (* __SFR_FARPTR)();
68 #define SFR_20BIT(address) extern __SFR_FARPTR address
69 #define SFR_32BIT(address) extern volatile unsigned long address
70 
71 #endif
72 
73 
74 /************************************************************
75 * STANDARD BITS
76 ************************************************************/
77 
78 #define BIT0 (0x0001)
79 #define BIT1 (0x0002)
80 #define BIT2 (0x0004)
81 #define BIT3 (0x0008)
82 #define BIT4 (0x0010)
83 #define BIT5 (0x0020)
84 #define BIT6 (0x0040)
85 #define BIT7 (0x0080)
86 #define BIT8 (0x0100)
87 #define BIT9 (0x0200)
88 #define BITA (0x0400)
89 #define BITB (0x0800)
90 #define BITC (0x1000)
91 #define BITD (0x2000)
92 #define BITE (0x4000)
93 #define BITF (0x8000)
94 
95 /************************************************************
96 * STATUS REGISTER BITS
97 ************************************************************/
98 
99 #define C (0x0001)
100 #define Z (0x0002)
101 #define N (0x0004)
102 #define V (0x0100)
103 #define GIE (0x0008)
104 #define CPUOFF (0x0010)
105 #define OSCOFF (0x0020)
106 #define SCG0 (0x0040)
107 #define SCG1 (0x0080)
108 
109 /* Low Power Modes coded with Bits 4-7 in SR */
110 
111 #ifdef __ASM_HEADER__ /* Begin #defines for assembler */
112 #define LPM0 (CPUOFF)
113 #define LPM1 (SCG0+CPUOFF)
114 #define LPM2 (SCG1+CPUOFF)
115 #define LPM3 (SCG1+SCG0+CPUOFF)
116 #define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
117 /* End #defines for assembler */
118 
119 #else /* Begin #defines for C */
120 #define LPM0_bits (CPUOFF)
121 #define LPM1_bits (SCG0+CPUOFF)
122 #define LPM2_bits (SCG1+CPUOFF)
123 #define LPM3_bits (SCG1+SCG0+CPUOFF)
124 #define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
125 
126 #include "in430.h"
127 #include <intrinsics.h>
128 
129 #define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
130 #define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
131 #define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
132 #define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
133 #define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
134 #define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
135 #define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
136 #define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
137 #define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
138 #define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
139 #endif /* End #defines for C */
140 
141 /************************************************************
142 * CPU
143 ************************************************************/
144 #define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */
145 
146 #if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \
147  || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \
148  || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \
149  || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__)
150  #define __MSP430_HAS_TxA7__
151 #endif
152 #if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \
153  || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__)
154  #define __MSP430_HAS_TxB7__
155 #endif
156 #if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \
157  || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__)
158  #define __MSP430_HAS_TxD7__
159 #endif
160 #if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__)
161  #define __MSP430_HAS_USCI_Ax__
162 #endif
163 #if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__)
164  #define __MSP430_HAS_USCI_Bx__
165 #endif
166 #if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__)
167  #define __MSP430_HAS_EUSCI_Ax__
168 #endif
169 #if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__)
170  #define __MSP430_HAS_EUSCI_Bx__
171 #endif
172 #ifdef __MSP430_HAS_EUSCI_B0__
173  #define __MSP430_HAS_EUSCI_Bx__
174 #endif
175 
176 /************************************************************
177 * ADC10_A
178 ************************************************************/
179 #ifdef __MSP430_HAS_ADC10_A__ /* Definition to show that Module is available */
180 
181 #define OFS_ADC10CTL0 (0x0000) /* ADC10 Control 0 */
182 #define OFS_ADC10CTL0_L OFS_ADC10CTL0
183 #define OFS_ADC10CTL0_H OFS_ADC10CTL0+1
184 #define OFS_ADC10CTL1 (0x0002) /* ADC10 Control 1 */
185 #define OFS_ADC10CTL1_L OFS_ADC10CTL1
186 #define OFS_ADC10CTL1_H OFS_ADC10CTL1+1
187 #define OFS_ADC10CTL2 (0x0004) /* ADC10 Control 2 */
188 #define OFS_ADC10CTL2_L OFS_ADC10CTL2
189 #define OFS_ADC10CTL2_H OFS_ADC10CTL2+1
190 #define OFS_ADC10LO (0x0006) /* ADC10 Window Comparator High Threshold */
191 #define OFS_ADC10LO_L OFS_ADC10LO
192 #define OFS_ADC10LO_H OFS_ADC10LO+1
193 #define OFS_ADC10HI (0x0008) /* ADC10 Window Comparator High Threshold */
194 #define OFS_ADC10HI_L OFS_ADC10HI
195 #define OFS_ADC10HI_H OFS_ADC10HI+1
196 #define OFS_ADC10MCTL0 (0x000A) /* ADC10 Memory Control 0 */
197 #define OFS_ADC10MCTL0_L OFS_ADC10MCTL0
198 #define OFS_ADC10MCTL0_H OFS_ADC10MCTL0+1
199 #define OFS_ADC10MEM0 (0x0012) /* ADC10 Conversion Memory 0 */
200 #define OFS_ADC10MEM0_L OFS_ADC10MEM0
201 #define OFS_ADC10MEM0_H OFS_ADC10MEM0+1
202 #define OFS_ADC10IE (0x001A) /* ADC10 Interrupt Enable */
203 #define OFS_ADC10IE_L OFS_ADC10IE
204 #define OFS_ADC10IE_H OFS_ADC10IE+1
205 #define OFS_ADC10IFG (0x001C) /* ADC10 Interrupt Flag */
206 #define OFS_ADC10IFG_L OFS_ADC10IFG
207 #define OFS_ADC10IFG_H OFS_ADC10IFG+1
208 #define OFS_ADC10IV (0x001E) /* ADC10 Interrupt Vector Word */
209 #define OFS_ADC10IV_L OFS_ADC10IV
210 #define OFS_ADC10IV_H OFS_ADC10IV+1
211 
212 /* ADC10CTL0 Control Bits */
213 #define ADC10SC (0x0001) /* ADC10 Start Conversion */
214 #define ADC10ENC (0x0002) /* ADC10 Enable Conversion */
215 #define ADC10ON (0x0010) /* ADC10 On/enable */
216 #define ADC10MSC (0x0080) /* ADC10 Multiple SampleConversion */
217 #define ADC10SHT0 (0x0100) /* ADC10 Sample Hold Select Bit: 0 */
218 #define ADC10SHT1 (0x0200) /* ADC10 Sample Hold Select Bit: 1 */
219 #define ADC10SHT2 (0x0400) /* ADC10 Sample Hold Select Bit: 2 */
220 #define ADC10SHT3 (0x0800) /* ADC10 Sample Hold Select Bit: 3 */
221 
222 /* ADC10CTL0 Control Bits */
223 #define ADC10SC_L (0x0001) /* ADC10 Start Conversion */
224 #define ADC10ENC_L (0x0002) /* ADC10 Enable Conversion */
225 #define ADC10ON_L (0x0010) /* ADC10 On/enable */
226 #define ADC10MSC_L (0x0080) /* ADC10 Multiple SampleConversion */
227 
228 /* ADC10CTL0 Control Bits */
229 #define ADC10SHT0_H (0x0001) /* ADC10 Sample Hold Select Bit: 0 */
230 #define ADC10SHT1_H (0x0002) /* ADC10 Sample Hold Select Bit: 1 */
231 #define ADC10SHT2_H (0x0004) /* ADC10 Sample Hold Select Bit: 2 */
232 #define ADC10SHT3_H (0x0008) /* ADC10 Sample Hold Select Bit: 3 */
233 
234 #define ADC10SHT_0 (0*0x100u) /* ADC10 Sample Hold Select 0 */
235 #define ADC10SHT_1 (1*0x100u) /* ADC10 Sample Hold Select 1 */
236 #define ADC10SHT_2 (2*0x100u) /* ADC10 Sample Hold Select 2 */
237 #define ADC10SHT_3 (3*0x100u) /* ADC10 Sample Hold Select 3 */
238 #define ADC10SHT_4 (4*0x100u) /* ADC10 Sample Hold Select 4 */
239 #define ADC10SHT_5 (5*0x100u) /* ADC10 Sample Hold Select 5 */
240 #define ADC10SHT_6 (6*0x100u) /* ADC10 Sample Hold Select 6 */
241 #define ADC10SHT_7 (7*0x100u) /* ADC10 Sample Hold Select 7 */
242 #define ADC10SHT_8 (8*0x100u) /* ADC10 Sample Hold Select 8 */
243 #define ADC10SHT_9 (9*0x100u) /* ADC10 Sample Hold Select 9 */
244 #define ADC10SHT_10 (10*0x100u) /* ADC10 Sample Hold Select 10 */
245 #define ADC10SHT_11 (11*0x100u) /* ADC10 Sample Hold Select 11 */
246 #define ADC10SHT_12 (12*0x100u) /* ADC10 Sample Hold Select 12 */
247 #define ADC10SHT_13 (13*0x100u) /* ADC10 Sample Hold Select 13 */
248 #define ADC10SHT_14 (14*0x100u) /* ADC10 Sample Hold Select 14 */
249 #define ADC10SHT_15 (15*0x100u) /* ADC10 Sample Hold Select 15 */
250 
251 /* ADC10CTL1 Control Bits */
252 #define ADC10BUSY (0x0001) /* ADC10 Busy */
253 #define ADC10CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */
254 #define ADC10CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */
255 #define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select 0 */
256 #define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select 1 */
257 #define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select 0 */
258 #define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select 1 */
259 #define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select 2 */
260 #define ADC10ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */
261 #define ADC10SHP (0x0200) /* ADC10 Sample/Hold Pulse Mode */
262 #define ADC10SHS0 (0x0400) /* ADC10 Sample/Hold Source 0 */
263 #define ADC10SHS1 (0x0800) /* ADC10 Sample/Hold Source 1 */
264 
265 /* ADC10CTL1 Control Bits */
266 #define ADC10BUSY_L (0x0001) /* ADC10 Busy */
267 #define ADC10CONSEQ0_L (0x0002) /* ADC10 Conversion Sequence Select 0 */
268 #define ADC10CONSEQ1_L (0x0004) /* ADC10 Conversion Sequence Select 1 */
269 #define ADC10SSEL0_L (0x0008) /* ADC10 Clock Source Select 0 */
270 #define ADC10SSEL1_L (0x0010) /* ADC10 Clock Source Select 1 */
271 #define ADC10DIV0_L (0x0020) /* ADC10 Clock Divider Select 0 */
272 #define ADC10DIV1_L (0x0040) /* ADC10 Clock Divider Select 1 */
273 #define ADC10DIV2_L (0x0080) /* ADC10 Clock Divider Select 2 */
274 
275 /* ADC10CTL1 Control Bits */
276 #define ADC10ISSH_H (0x0001) /* ADC10 Invert Sample Hold Signal */
277 #define ADC10SHP_H (0x0002) /* ADC10 Sample/Hold Pulse Mode */
278 #define ADC10SHS0_H (0x0004) /* ADC10 Sample/Hold Source 0 */
279 #define ADC10SHS1_H (0x0008) /* ADC10 Sample/Hold Source 1 */
280 
281 #define ADC10CONSEQ_0 (0*2u) /* ADC10 Conversion Sequence Select: 0 */
282 #define ADC10CONSEQ_1 (1*2u) /* ADC10 Conversion Sequence Select: 1 */
283 #define ADC10CONSEQ_2 (2*2u) /* ADC10 Conversion Sequence Select: 2 */
284 #define ADC10CONSEQ_3 (3*2u) /* ADC10 Conversion Sequence Select: 3 */
285 
286 #define ADC10SSEL_0 (0*8u) /* ADC10 Clock Source Select: 0 */
287 #define ADC10SSEL_1 (1*8u) /* ADC10 Clock Source Select: 1 */
288 #define ADC10SSEL_2 (2*8u) /* ADC10 Clock Source Select: 2 */
289 #define ADC10SSEL_3 (3*8u) /* ADC10 Clock Source Select: 3 */
290 
291 #define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select: 0 */
292 #define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select: 1 */
293 #define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select: 2 */
294 #define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select: 3 */
295 #define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select: 4 */
296 #define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select: 5 */
297 #define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select: 6 */
298 #define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select: 7 */
299 
300 #define ADC10SHS_0 (0*0x400u) /* ADC10 Sample/Hold Source: 0 */
301 #define ADC10SHS_1 (1*0x400u) /* ADC10 Sample/Hold Source: 1 */
302 #define ADC10SHS_2 (2*0x400u) /* ADC10 Sample/Hold Source: 2 */
303 #define ADC10SHS_3 (3*0x400u) /* ADC10 Sample/Hold Source: 3 */
304 
305 /* ADC10CTL2 Control Bits */
306 #define ADC10REFBURST (0x0001) /* ADC10 Reference Burst */
307 #define ADC10SR (0x0004) /* ADC10 Sampling Rate */
308 #define ADC10DF (0x0008) /* ADC10 Data Format */
309 #define ADC10RES (0x0010) /* ADC10 Resolution Bit */
310 #define ADC10PDIV0 (0x0100) /* ADC10 predivider Bit: 0 */
311 #define ADC10PDIV1 (0x0200) /* ADC10 predivider Bit: 1 */
312 
313 /* ADC10CTL2 Control Bits */
314 #define ADC10REFBURST_L (0x0001) /* ADC10 Reference Burst */
315 #define ADC10SR_L (0x0004) /* ADC10 Sampling Rate */
316 #define ADC10DF_L (0x0008) /* ADC10 Data Format */
317 #define ADC10RES_L (0x0010) /* ADC10 Resolution Bit */
318 
319 /* ADC10CTL2 Control Bits */
320 #define ADC10PDIV0_H (0x0001) /* ADC10 predivider Bit: 0 */
321 #define ADC10PDIV1_H (0x0002) /* ADC10 predivider Bit: 1 */
322 
323 #define ADC10PDIV_0 (0x0000) /* ADC10 predivider /1 */
324 #define ADC10PDIV_1 (0x0100) /* ADC10 predivider /2 */
325 #define ADC10PDIV_2 (0x0200) /* ADC10 predivider /64 */
326 #define ADC10PDIV_3 (0x0300) /* ADC10 predivider reserved */
327 
328 #define ADC10PDIV__1 (0x0000) /* ADC10 predivider /1 */
329 #define ADC10PDIV__4 (0x0100) /* ADC10 predivider /2 */
330 #define ADC10PDIV__64 (0x0200) /* ADC10 predivider /64 */
331 
332 /* ADC10MCTL0 Control Bits */
333 #define ADC10INCH0 (0x0001) /* ADC10 Input Channel Select Bit 0 */
334 #define ADC10INCH1 (0x0002) /* ADC10 Input Channel Select Bit 1 */
335 #define ADC10INCH2 (0x0004) /* ADC10 Input Channel Select Bit 2 */
336 #define ADC10INCH3 (0x0008) /* ADC10 Input Channel Select Bit 3 */
337 #define ADC10SREF0 (0x0010) /* ADC10 Select Reference Bit 0 */
338 #define ADC10SREF1 (0x0020) /* ADC10 Select Reference Bit 1 */
339 #define ADC10SREF2 (0x0040) /* ADC10 Select Reference Bit 2 */
340 
341 /* ADC10MCTL0 Control Bits */
342 #define ADC10INCH0_L (0x0001) /* ADC10 Input Channel Select Bit 0 */
343 #define ADC10INCH1_L (0x0002) /* ADC10 Input Channel Select Bit 1 */
344 #define ADC10INCH2_L (0x0004) /* ADC10 Input Channel Select Bit 2 */
345 #define ADC10INCH3_L (0x0008) /* ADC10 Input Channel Select Bit 3 */
346 #define ADC10SREF0_L (0x0010) /* ADC10 Select Reference Bit 0 */
347 #define ADC10SREF1_L (0x0020) /* ADC10 Select Reference Bit 1 */
348 #define ADC10SREF2_L (0x0040) /* ADC10 Select Reference Bit 2 */
349 
350 #define ADC10INCH_0 (0) /* ADC10 Input Channel 0 */
351 #define ADC10INCH_1 (1) /* ADC10 Input Channel 1 */
352 #define ADC10INCH_2 (2) /* ADC10 Input Channel 2 */
353 #define ADC10INCH_3 (3) /* ADC10 Input Channel 3 */
354 #define ADC10INCH_4 (4) /* ADC10 Input Channel 4 */
355 #define ADC10INCH_5 (5) /* ADC10 Input Channel 5 */
356 #define ADC10INCH_6 (6) /* ADC10 Input Channel 6 */
357 #define ADC10INCH_7 (7) /* ADC10 Input Channel 7 */
358 #define ADC10INCH_8 (8) /* ADC10 Input Channel 8 */
359 #define ADC10INCH_9 (9) /* ADC10 Input Channel 9 */
360 #define ADC10INCH_10 (10) /* ADC10 Input Channel 10 */
361 #define ADC10INCH_11 (11) /* ADC10 Input Channel 11 */
362 #define ADC10INCH_12 (12) /* ADC10 Input Channel 12 */
363 #define ADC10INCH_13 (13) /* ADC10 Input Channel 13 */
364 #define ADC10INCH_14 (14) /* ADC10 Input Channel 14 */
365 #define ADC10INCH_15 (15) /* ADC10 Input Channel 15 */
366 
367 #define ADC10SREF_0 (0*0x10u) /* ADC10 Select Reference 0 */
368 #define ADC10SREF_1 (1*0x10u) /* ADC10 Select Reference 1 */
369 #define ADC10SREF_2 (2*0x10u) /* ADC10 Select Reference 2 */
370 #define ADC10SREF_3 (3*0x10u) /* ADC10 Select Reference 3 */
371 #define ADC10SREF_4 (4*0x10u) /* ADC10 Select Reference 4 */
372 #define ADC10SREF_5 (5*0x10u) /* ADC10 Select Reference 5 */
373 #define ADC10SREF_6 (6*0x10u) /* ADC10 Select Reference 6 */
374 #define ADC10SREF_7 (7*0x10u) /* ADC10 Select Reference 7 */
375 
376 /* ADC10IE Interrupt Enable Bits */
377 #define ADC10IE0 (0x0001) /* ADC10_A Interrupt enable */
378 #define ADC10INIE (0x0002) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */
379 #define ADC10LOIE (0x0004) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */
380 #define ADC10HIIE (0x0008) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */
381 #define ADC10OVIE (0x0010) /* ADC10_A ADC10MEM overflow Interrupt enable */
382 #define ADC10TOVIE (0x0020) /* ADC10_A conversion-time-overflow Interrupt enable */
383 
384 /* ADC10IE Interrupt Enable Bits */
385 #define ADC10IE0_L (0x0001) /* ADC10_A Interrupt enable */
386 #define ADC10INIE_L (0x0002) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */
387 #define ADC10LOIE_L (0x0004) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */
388 #define ADC10HIIE_L (0x0008) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */
389 #define ADC10OVIE_L (0x0010) /* ADC10_A ADC10MEM overflow Interrupt enable */
390 #define ADC10TOVIE_L (0x0020) /* ADC10_A conversion-time-overflow Interrupt enable */
391 
392 /* ADC10IFG Interrupt Flag Bits */
393 #define ADC10IFG0 (0x0001) /* ADC10_A Interrupt Flag */
394 #define ADC10INIFG (0x0002) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */
395 #define ADC10LOIFG (0x0004) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */
396 #define ADC10HIIFG (0x0008) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */
397 #define ADC10OVIFG (0x0010) /* ADC10_A ADC10MEM overflow Interrupt Flag */
398 #define ADC10TOVIFG (0x0020) /* ADC10_A conversion-time-overflow Interrupt Flag */
399 
400 /* ADC10IFG Interrupt Flag Bits */
401 #define ADC10IFG0_L (0x0001) /* ADC10_A Interrupt Flag */
402 #define ADC10INIFG_L (0x0002) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */
403 #define ADC10LOIFG_L (0x0004) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */
404 #define ADC10HIIFG_L (0x0008) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */
405 #define ADC10OVIFG_L (0x0010) /* ADC10_A ADC10MEM overflow Interrupt Flag */
406 #define ADC10TOVIFG_L (0x0020) /* ADC10_A conversion-time-overflow Interrupt Flag */
407 
408 /* ADC10IV Definitions */
409 #define ADC10IV_NONE (0x0000) /* No Interrupt pending */
410 #define ADC10IV_ADC10OVIFG (0x0002) /* ADC10OVIFG */
411 #define ADC10IV_ADC10TOVIFG (0x0004) /* ADC10TOVIFG */
412 #define ADC10IV_ADC10HIIFG (0x0006) /* ADC10HIIFG */
413 #define ADC10IV_ADC10LOIFG (0x0008) /* ADC10LOIFG */
414 #define ADC10IV_ADC10INIFG (0x000A) /* ADC10INIFG */
415 #define ADC10IV_ADC10IFG (0x000C) /* ADC10IFG */
416 
417 #endif
418 /************************************************************
419 * ADC12 PLUS
420 ************************************************************/
421 #ifdef __MSP430_HAS_ADC12_PLUS__ /* Definition to show that Module is available */
422 
423 #define OFS_ADC12CTL0 (0x0000) /* ADC12+ Control 0 */
424 #define OFS_ADC12CTL0_L OFS_ADC12CTL0
425 #define OFS_ADC12CTL0_H OFS_ADC12CTL0+1
426 #define OFS_ADC12CTL1 (0x0002) /* ADC12+ Control 1 */
427 #define OFS_ADC12CTL1_L OFS_ADC12CTL1
428 #define OFS_ADC12CTL1_H OFS_ADC12CTL1+1
429 #define OFS_ADC12CTL2 (0x0004) /* ADC12+ Control 2 */
430 #define OFS_ADC12CTL2_L OFS_ADC12CTL2
431 #define OFS_ADC12CTL2_H OFS_ADC12CTL2+1
432 #define OFS_ADC12IFG (0x000A) /* ADC12+ Interrupt Flag */
433 #define OFS_ADC12IFG_L OFS_ADC12IFG
434 #define OFS_ADC12IFG_H OFS_ADC12IFG+1
435 #define OFS_ADC12IE (0x000C) /* ADC12+ Interrupt Enable */
436 #define OFS_ADC12IE_L OFS_ADC12IE
437 #define OFS_ADC12IE_H OFS_ADC12IE+1
438 #define OFS_ADC12IV (0x000E) /* ADC12+ Interrupt Vector Word */
439 #define OFS_ADC12IV_L OFS_ADC12IV
440 #define OFS_ADC12IV_H OFS_ADC12IV+1
441 
442 #define OFS_ADC12MEM0 (0x0020) /* ADC12 Conversion Memory 0 */
443 #define OFS_ADC12MEM0_L OFS_ADC12MEM0
444 #define OFS_ADC12MEM0_H OFS_ADC12MEM0+1
445 #define OFS_ADC12MEM1 (0x0022) /* ADC12 Conversion Memory 1 */
446 #define OFS_ADC12MEM1_L OFS_ADC12MEM1
447 #define OFS_ADC12MEM1_H OFS_ADC12MEM1+1
448 #define OFS_ADC12MEM2 (0x0024) /* ADC12 Conversion Memory 2 */
449 #define OFS_ADC12MEM2_L OFS_ADC12MEM2
450 #define OFS_ADC12MEM2_H OFS_ADC12MEM2+1
451 #define OFS_ADC12MEM3 (0x0026) /* ADC12 Conversion Memory 3 */
452 #define OFS_ADC12MEM3_L OFS_ADC12MEM3
453 #define OFS_ADC12MEM3_H OFS_ADC12MEM3+1
454 #define OFS_ADC12MEM4 (0x0028) /* ADC12 Conversion Memory 4 */
455 #define OFS_ADC12MEM4_L OFS_ADC12MEM4
456 #define OFS_ADC12MEM4_H OFS_ADC12MEM4+1
457 #define OFS_ADC12MEM5 (0x002A) /* ADC12 Conversion Memory 5 */
458 #define OFS_ADC12MEM5_L OFS_ADC12MEM5
459 #define OFS_ADC12MEM5_H OFS_ADC12MEM5+1
460 #define OFS_ADC12MEM6 (0x002C) /* ADC12 Conversion Memory 6 */
461 #define OFS_ADC12MEM6_L OFS_ADC12MEM6
462 #define OFS_ADC12MEM6_H OFS_ADC12MEM6+1
463 #define OFS_ADC12MEM7 (0x002E) /* ADC12 Conversion Memory 7 */
464 #define OFS_ADC12MEM7_L OFS_ADC12MEM7
465 #define OFS_ADC12MEM7_H OFS_ADC12MEM7+1
466 #define OFS_ADC12MEM8 (0x0030) /* ADC12 Conversion Memory 8 */
467 #define OFS_ADC12MEM8_L OFS_ADC12MEM8
468 #define OFS_ADC12MEM8_H OFS_ADC12MEM8+1
469 #define OFS_ADC12MEM9 (0x0032) /* ADC12 Conversion Memory 9 */
470 #define OFS_ADC12MEM9_L OFS_ADC12MEM9
471 #define OFS_ADC12MEM9_H OFS_ADC12MEM9+1
472 #define OFS_ADC12MEM10 (0x0034) /* ADC12 Conversion Memory 10 */
473 #define OFS_ADC12MEM10_L OFS_ADC12MEM10
474 #define OFS_ADC12MEM10_H OFS_ADC12MEM10+1
475 #define OFS_ADC12MEM11 (0x0036) /* ADC12 Conversion Memory 11 */
476 #define OFS_ADC12MEM11_L OFS_ADC12MEM11
477 #define OFS_ADC12MEM11_H OFS_ADC12MEM11+1
478 #define OFS_ADC12MEM12 (0x0038) /* ADC12 Conversion Memory 12 */
479 #define OFS_ADC12MEM12_L OFS_ADC12MEM12
480 #define OFS_ADC12MEM12_H OFS_ADC12MEM12+1
481 #define OFS_ADC12MEM13 (0x003A) /* ADC12 Conversion Memory 13 */
482 #define OFS_ADC12MEM13_L OFS_ADC12MEM13
483 #define OFS_ADC12MEM13_H OFS_ADC12MEM13+1
484 #define OFS_ADC12MEM14 (0x003C) /* ADC12 Conversion Memory 14 */
485 #define OFS_ADC12MEM14_L OFS_ADC12MEM14
486 #define OFS_ADC12MEM14_H OFS_ADC12MEM14+1
487 #define OFS_ADC12MEM15 (0x003E) /* ADC12 Conversion Memory 15 */
488 #define OFS_ADC12MEM15_L OFS_ADC12MEM15
489 #define OFS_ADC12MEM15_H OFS_ADC12MEM15+1
490 #define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */
491 #ifdef __ASM_HEADER__
492 #define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */
493 #else
494 #define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
495 #endif
496 
497 #define OFS_ADC12MCTL0 (0x0010) /* ADC12 Memory Control 0 */
498 #define OFS_ADC12MCTL1 (0x0011) /* ADC12 Memory Control 1 */
499 #define OFS_ADC12MCTL2 (0x0012) /* ADC12 Memory Control 2 */
500 #define OFS_ADC12MCTL3 (0x0013) /* ADC12 Memory Control 3 */
501 #define OFS_ADC12MCTL4 (0x0014) /* ADC12 Memory Control 4 */
502 #define OFS_ADC12MCTL5 (0x0015) /* ADC12 Memory Control 5 */
503 #define OFS_ADC12MCTL6 (0x0016) /* ADC12 Memory Control 6 */
504 #define OFS_ADC12MCTL7 (0x0017) /* ADC12 Memory Control 7 */
505 #define OFS_ADC12MCTL8 (0x0018) /* ADC12 Memory Control 8 */
506 #define OFS_ADC12MCTL9 (0x0019) /* ADC12 Memory Control 9 */
507 #define OFS_ADC12MCTL10 (0x001A) /* ADC12 Memory Control 10 */
508 #define OFS_ADC12MCTL11 (0x001B) /* ADC12 Memory Control 11 */
509 #define OFS_ADC12MCTL12 (0x001C) /* ADC12 Memory Control 12 */
510 #define OFS_ADC12MCTL13 (0x001D) /* ADC12 Memory Control 13 */
511 #define OFS_ADC12MCTL14 (0x001E) /* ADC12 Memory Control 14 */
512 #define OFS_ADC12MCTL15 (0x001F) /* ADC12 Memory Control 15 */
513 #define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */
514 #ifdef __ASM_HEADER__
515 #define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */
516 #else
517 #define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */
518 #endif
519 
520 /* ADC12CTL0 Control Bits */
521 #define ADC12SC (0x0001) /* ADC12 Start Conversion */
522 #define ADC12ENC (0x0002) /* ADC12 Enable Conversion */
523 #define ADC12TOVIE (0x0004) /* ADC12 Timer Overflow interrupt enable */
524 #define ADC12OVIE (0x0008) /* ADC12 Overflow interrupt enable */
525 #define ADC12ON (0x0010) /* ADC12 On/enable */
526 #define ADC12REFON (0x0020) /* ADC12 Reference on */
527 #define ADC12REF2_5V (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */
528 #define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */
529 #define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */
530 #define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */
531 #define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */
532 #define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */
533 #define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */
534 #define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */
535 #define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */
536 #define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */
537 
538 /* ADC12CTL0 Control Bits */
539 #define ADC12SC_L (0x0001) /* ADC12 Start Conversion */
540 #define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */
541 #define ADC12TOVIE_L (0x0004) /* ADC12 Timer Overflow interrupt enable */
542 #define ADC12OVIE_L (0x0008) /* ADC12 Overflow interrupt enable */
543 #define ADC12ON_L (0x0010) /* ADC12 On/enable */
544 #define ADC12REFON_L (0x0020) /* ADC12 Reference on */
545 #define ADC12REF2_5V_L (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */
546 #define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */
547 
548 /* ADC12CTL0 Control Bits */
549 #define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */
550 #define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */
551 #define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */
552 #define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */
553 #define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */
554 #define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */
555 #define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */
556 #define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */
557 
558 #define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
559 #define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */
560 #define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */
561 #define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */
562 #define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */
563 #define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */
564 #define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */
565 #define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */
566 #define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */
567 #define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */
568 #define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */
569 #define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */
570 #define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */
571 #define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */
572 #define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */
573 #define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */
574 
575 #define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
576 #define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
577 #define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
578 #define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
579 #define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */
580 #define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */
581 #define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */
582 #define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */
583 #define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */
584 #define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */
585 #define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */
586 #define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */
587 #define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */
588 #define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */
589 #define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */
590 #define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */
591 
592 /* ADC12CTL1 Control Bits */
593 #define ADC12BUSY (0x0001) /* ADC12 Busy */
594 #define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
595 #define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
596 #define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */
597 #define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */
598 #define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
599 #define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
600 #define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
601 #define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */
602 #define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */
603 #define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */
604 #define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */
605 #define ADC12CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address Bit: 0 */
606 #define ADC12CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address Bit: 1 */
607 #define ADC12CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address Bit: 2 */
608 #define ADC12CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address Bit: 3 */
609 
610 /* ADC12CTL1 Control Bits */
611 #define ADC12BUSY_L (0x0001) /* ADC12 Busy */
612 #define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
613 #define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
614 #define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */
615 #define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */
616 #define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
617 #define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
618 #define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
619 
620 /* ADC12CTL1 Control Bits */
621 #define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */
622 #define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */
623 #define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */
624 #define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */
625 #define ADC12CSTARTADD0_H (0x0010) /* ADC12 Conversion Start Address Bit: 0 */
626 #define ADC12CSTARTADD1_H (0x0020) /* ADC12 Conversion Start Address Bit: 1 */
627 #define ADC12CSTARTADD2_H (0x0040) /* ADC12 Conversion Start Address Bit: 2 */
628 #define ADC12CSTARTADD3_H (0x0080) /* ADC12 Conversion Start Address Bit: 3 */
629 
630 #define ADC12CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */
631 #define ADC12CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */
632 #define ADC12CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */
633 #define ADC12CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */
634 
635 #define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */
636 #define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */
637 #define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */
638 #define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */
639 
640 #define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */
641 #define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */
642 #define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */
643 #define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */
644 #define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */
645 #define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */
646 #define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */
647 #define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */
648 
649 #define ADC12SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */
650 #define ADC12SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */
651 #define ADC12SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */
652 #define ADC12SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */
653 
654 #define ADC12CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */
655 #define ADC12CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */
656 #define ADC12CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */
657 #define ADC12CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */
658 #define ADC12CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */
659 #define ADC12CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */
660 #define ADC12CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */
661 #define ADC12CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */
662 #define ADC12CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */
663 #define ADC12CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */
664 #define ADC12CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */
665 #define ADC12CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */
666 #define ADC12CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */
667 #define ADC12CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */
668 #define ADC12CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */
669 #define ADC12CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 */
670 
671 /* ADC12CTL2 Control Bits */
672 #define ADC12REFBURST (0x0001) /* ADC12+ Reference Burst */
673 #define ADC12REFOUT (0x0002) /* ADC12+ Reference Out */
674 #define ADC12SR (0x0004) /* ADC12+ Sampling Rate */
675 #define ADC12DF (0x0008) /* ADC12+ Data Format */
676 #define ADC12RES0 (0x0010) /* ADC12+ Resolution Bit: 0 */
677 #define ADC12RES1 (0x0020) /* ADC12+ Resolution Bit: 1 */
678 #define ADC12TCOFF (0x0080) /* ADC12+ Temperature Sensor Off */
679 #define ADC12PDIV (0x0100) /* ADC12+ predivider 0:/1 1:/4 */
680 
681 /* ADC12CTL2 Control Bits */
682 #define ADC12REFBURST_L (0x0001) /* ADC12+ Reference Burst */
683 #define ADC12REFOUT_L (0x0002) /* ADC12+ Reference Out */
684 #define ADC12SR_L (0x0004) /* ADC12+ Sampling Rate */
685 #define ADC12DF_L (0x0008) /* ADC12+ Data Format */
686 #define ADC12RES0_L (0x0010) /* ADC12+ Resolution Bit: 0 */
687 #define ADC12RES1_L (0x0020) /* ADC12+ Resolution Bit: 1 */
688 #define ADC12TCOFF_L (0x0080) /* ADC12+ Temperature Sensor Off */
689 
690 /* ADC12CTL2 Control Bits */
691 #define ADC12PDIV_H (0x0001) /* ADC12+ predivider 0:/1 1:/4 */
692 
693 #define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */
694 #define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */
695 #define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */
696 #define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */
697 
698 /* ADC12MCTLx Control Bits */
699 #define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */
700 #define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */
701 #define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */
702 #define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */
703 #define ADC12SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */
704 #define ADC12SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */
705 #define ADC12SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */
706 #define ADC12EOS (0x0080) /* ADC12 End of Sequence */
707 
708 #define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */
709 #define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */
710 #define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */
711 #define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */
712 #define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */
713 #define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */
714 #define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */
715 #define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */
716 #define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */
717 #define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */
718 #define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */
719 #define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */
720 #define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */
721 #define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */
722 #define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */
723 #define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */
724 
725 #define ADC12SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */
726 #define ADC12SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */
727 #define ADC12SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */
728 #define ADC12SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */
729 #define ADC12SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */
730 #define ADC12SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */
731 #define ADC12SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */
732 #define ADC12SREF_7 (7*0x10u) /* ADC12 Select Reference 7 */
733 
734 #define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */
735 #define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */
736 #define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */
737 #define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */
738 #define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */
739 #define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */
740 #define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */
741 #define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */
742 #define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */
743 #define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */
744 #define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */
745 #define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */
746 #define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */
747 #define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */
748 #define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */
749 #define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */
750 
751 #define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */
752 #define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */
753 #define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */
754 #define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */
755 #define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */
756 #define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */
757 #define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */
758 #define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */
759 
760 #define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */
761 #define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */
762 #define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */
763 #define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */
764 #define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */
765 #define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */
766 #define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */
767 #define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */
768 
769 #define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */
770 #define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */
771 #define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */
772 #define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */
773 #define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */
774 #define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */
775 #define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */
776 #define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */
777 #define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */
778 #define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */
779 #define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */
780 #define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */
781 #define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */
782 #define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */
783 #define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */
784 #define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */
785 
786 #define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */
787 #define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */
788 #define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */
789 #define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */
790 #define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */
791 #define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */
792 #define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */
793 #define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */
794 
795 #define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */
796 #define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */
797 #define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */
798 #define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */
799 #define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */
800 #define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */
801 #define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */
802 #define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */
803 
804 /* ADC12IV Definitions */
805 #define ADC12IV_NONE (0x0000) /* No Interrupt pending */
806 #define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */
807 #define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */
808 #define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */
809 #define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */
810 #define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */
811 #define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */
812 #define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */
813 #define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */
814 #define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */
815 #define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */
816 #define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */
817 #define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */
818 #define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */
819 #define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */
820 #define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */
821 #define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */
822 #define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */
823 #define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */
824 
825 #endif
826 /************************************************************
827 * AES Accelerator
828 ************************************************************/
829 #ifdef __MSP430_HAS_AES__ /* Definition to show that Module is available */
830 
831 #define OFS_AESACTL0 (0x0000) /* AES accelerator control register 0 */
832 #define OFS_AESACTL0_L OFS_AESACTL0
833 #define OFS_AESACTL0_H OFS_AESACTL0+1
834 #define OFS_AESASTAT (0x0004) /* AES accelerator status register */
835 #define OFS_AESASTAT_L OFS_AESASTAT
836 #define OFS_AESASTAT_H OFS_AESASTAT+1
837 #define OFS_AESAKEY (0x0006) /* AES accelerator key register */
838 #define OFS_AESAKEY_L OFS_AESAKEY
839 #define OFS_AESAKEY_H OFS_AESAKEY+1
840 #define OFS_AESADIN (0x0008) /* AES accelerator data in register */
841 #define OFS_AESADIN_L OFS_AESADIN
842 #define OFS_AESADIN_H OFS_AESADIN+1
843 #define OFS_AESADOUT (0x000A) /* AES accelerator data out register */
844 #define OFS_AESADOUT_L OFS_AESADOUT
845 #define OFS_AESADOUT_H OFS_AESADOUT+1
846 
847 /* AESACTL0 Control Bits */
848 #define AESOP0 (0x0001) /* AES Operation Bit: 0 */
849 #define AESOP1 (0x0002) /* AES Operation Bit: 1 */
850 #define AESSWRST (0x0080) /* AES Software Reset */
851 #define AESRDYIFG (0x0100) /* AES ready interrupt flag */
852 #define AESERRFG (0x0800) /* AES Error Flag */
853 #define AESRDYIE (0x1000) /* AES ready interrupt enable*/
854 
855 /* AESACTL0 Control Bits */
856 #define AESOP0_L (0x0001) /* AES Operation Bit: 0 */
857 #define AESOP1_L (0x0002) /* AES Operation Bit: 1 */
858 #define AESSWRST_L (0x0080) /* AES Software Reset */
859 
860 /* AESACTL0 Control Bits */
861 #define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */
862 #define AESERRFG_H (0x0008) /* AES Error Flag */
863 #define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/
864 
865 #define AESOP_0 (0x0000) /* AES Operation: Encrypt */
866 #define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */
867 #define AESOP_2 (0x0002) /* AES Operation: Decrypt (frist round Key) */
868 #define AESOP_3 (0x0003) /* AES Operation: Generate first round Key */
869 
870 /* AESASTAT Control Bits */
871 #define AESBUSY (0x0001) /* AES Busy */
872 #define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */
873 #define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */
874 #define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */
875 #define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
876 #define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
877 #define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
878 #define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
879 #define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */
880 #define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */
881 #define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */
882 #define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */
883 #define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */
884 #define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */
885 #define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */
886 #define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */
887 
888 /* AESASTAT Control Bits */
889 #define AESBUSY_L (0x0001) /* AES Busy */
890 #define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */
891 #define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */
892 #define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */
893 #define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
894 #define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
895 #define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
896 #define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
897 
898 /* AESASTAT Control Bits */
899 #define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */
900 #define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */
901 #define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */
902 #define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */
903 #define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */
904 #define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */
905 #define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */
906 #define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */
907 
908 #endif
909 /*************************************************************
910 * Backup RAM Module
911 *************************************************************/
912 #ifdef __MSP430_HAS_BACKUP_RAM__ /* Definition to show that Module is available */
913 
914 #define OFS_BAKMEM0 (0x0000) /* Battery Backup Memory 0 */
915 #define OFS_BAKMEM0_L OFS_BAKMEM0
916 #define OFS_BAKMEM0_H OFS_BAKMEM0+1
917 #define OFS_BAKMEM1 (0x0002) /* Battery Backup Memory 0 */
918 #define OFS_BAKMEM1_L OFS_BAKMEM1
919 #define OFS_BAKMEM1_H OFS_BAKMEM1+1
920 #define OFS_BAKMEM2 (0x0004) /* Battery Backup Memory 0 */
921 #define OFS_BAKMEM2_L OFS_BAKMEM2
922 #define OFS_BAKMEM2_H OFS_BAKMEM2+1
923 #define OFS_BAKMEM3 (0x0006) /* Battery Backup Memory 0 */
924 #define OFS_BAKMEM3_L OFS_BAKMEM3
925 #define OFS_BAKMEM3_H OFS_BAKMEM3+1
926 
927 #endif
928 /*************************************************************
929 * Battery Charger Module
930 *************************************************************/
931 #ifdef __MSP430_HAS_BATTERY_CHARGER__ /* Definition to show that Module is available */
932 
933 #define OFS_BAKCTL (0x0000) /* Battery Backup Control */
934 #define OFS_BAKCTL_L OFS_BAKCTL
935 #define OFS_BAKCTL_H OFS_BAKCTL+1
936 #define OFS_BAKCHCTL (0x0002) /* Battery Charger Control */
937 #define OFS_BAKCHCTL_L OFS_BAKCHCTL
938 #define OFS_BAKCHCTL_H OFS_BAKCHCTL+1
939 
940 /* BAKCTL Control Bits */
941 #define LOCKBAK (0x0001) /* Lock backup sub-system */
942 #define BAKSW (0x0002) /* Manual switch to battery backup supply */
943 #define BAKADC (0x0004) /* Battery backup supply to ADC. */
944 #define BAKDIS (0x0008) /* Disable backup supply switching. */
945 
946 /* BAKCTL Control Bits */
947 #define LOCKBAK_L (0x0001) /* Lock backup sub-system */
948 #define BAKSW_L (0x0002) /* Manual switch to battery backup supply */
949 #define BAKADC_L (0x0004) /* Battery backup supply to ADC. */
950 #define BAKDIS_L (0x0008) /* Disable backup supply switching. */
951 
952 /* BAKCHCTL Control Bits */
953 #define CHEN (0x0001) /* Charger enable */
954 #define CHC0 (0x0002) /* Charger charge current Bit 0 */
955 #define CHC1 (0x0004) /* Charger charge current Bit 1 */
956 #define CHV0 (0x0010) /* Charger end voltage Bit 0 */
957 #define CHV1 (0x0020) /* Charger end voltage Bit 1 */
958 
959 /* BAKCHCTL Control Bits */
960 #define CHEN_L (0x0001) /* Charger enable */
961 #define CHC0_L (0x0002) /* Charger charge current Bit 0 */
962 #define CHC1_L (0x0004) /* Charger charge current Bit 1 */
963 #define CHV0_L (0x0010) /* Charger end voltage Bit 0 */
964 #define CHV1_L (0x0020) /* Charger end voltage Bit 1 */
965 
966 #define CHPWD (0x6900) /* Charger write password. */
967 
968 #endif
969 /************************************************************
970 * Comparator B
971 ************************************************************/
972 #ifdef __MSP430_HAS_COMPB__ /* Definition to show that Module is available */
973 
974 #define OFS_CBCTL0 (0x0000) /* Comparator B Control Register 0 */
975 #define OFS_CBCTL0_L OFS_CBCTL0
976 #define OFS_CBCTL0_H OFS_CBCTL0+1
977 #define OFS_CBCTL1 (0x0002) /* Comparator B Control Register 1 */
978 #define OFS_CBCTL1_L OFS_CBCTL1
979 #define OFS_CBCTL1_H OFS_CBCTL1+1
980 #define OFS_CBCTL2 (0x0004) /* Comparator B Control Register 2 */
981 #define OFS_CBCTL2_L OFS_CBCTL2
982 #define OFS_CBCTL2_H OFS_CBCTL2+1
983 #define OFS_CBCTL3 (0x0006) /* Comparator B Control Register 3 */
984 #define OFS_CBCTL3_L OFS_CBCTL3
985 #define OFS_CBCTL3_H OFS_CBCTL3+1
986 #define OFS_CBINT (0x000C) /* Comparator B Interrupt Register */
987 #define OFS_CBINT_L OFS_CBINT
988 #define OFS_CBINT_H OFS_CBINT+1
989 #define OFS_CBIV (0x000E) /* Comparator B Interrupt Vector Word */
990 
991 /* CBCTL0 Control Bits */
992 #define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */
993 #define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */
994 #define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */
995 #define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */
996 //#define RESERVED (0x0010) /* Comp. B */
997 //#define RESERVED (0x0020) /* Comp. B */
998 //#define RESERVED (0x0040) /* Comp. B */
999 #define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enable */
1000 #define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */
1001 #define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */
1002 #define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */
1003 #define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */
1004 //#define RESERVED (0x1000) /* Comp. B */
1005 //#define RESERVED (0x2000) /* Comp. B */
1006 //#define RESERVED (0x4000) /* Comp. B */
1007 #define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enable */
1008 
1009 /* CBCTL0 Control Bits */
1010 #define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */
1011 #define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */
1012 #define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */
1013 #define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */
1014 //#define RESERVED (0x0010) /* Comp. B */
1015 //#define RESERVED (0x0020) /* Comp. B */
1016 //#define RESERVED (0x0040) /* Comp. B */
1017 #define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enable */
1018 //#define RESERVED (0x1000) /* Comp. B */
1019 //#define RESERVED (0x2000) /* Comp. B */
1020 //#define RESERVED (0x4000) /* Comp. B */
1021 
1022 /* CBCTL0 Control Bits */
1023 //#define RESERVED (0x0010) /* Comp. B */
1024 //#define RESERVED (0x0020) /* Comp. B */
1025 //#define RESERVED (0x0040) /* Comp. B */
1026 #define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */
1027 #define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */
1028 #define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */
1029 #define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */
1030 //#define RESERVED (0x1000) /* Comp. B */
1031 //#define RESERVED (0x2000) /* Comp. B */
1032 //#define RESERVED (0x4000) /* Comp. B */
1033 #define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enable */
1034 
1035 #define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */
1036 #define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */
1037 #define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */
1038 #define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */
1039 #define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */
1040 #define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */
1041 #define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */
1042 #define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */
1043 #define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */
1044 #define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */
1045 #define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */
1046 #define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */
1047 #define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */
1048 #define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */
1049 #define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */
1050 #define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */
1051 
1052 #define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */
1053 #define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */
1054 #define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */
1055 #define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */
1056 #define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */
1057 #define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */
1058 #define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */
1059 #define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */
1060 #define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */
1061 #define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */
1062 #define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */
1063 #define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */
1064 #define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */
1065 #define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */
1066 #define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */
1067 #define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */
1068 
1069 /* CBCTL1 Control Bits */
1070 #define CBOUT (0x0001) /* Comp. B Output */
1071 #define CBOUTPOL (0x0002) /* Comp. B Output Polarity */
1072 #define CBF (0x0004) /* Comp. B Enable Output Filter */
1073 #define CBIES (0x0008) /* Comp. B Interrupt Edge Select */
1074 #define CBSHORT (0x0010) /* Comp. B Input Short */
1075 #define CBEX (0x0020) /* Comp. B Exchange Inputs */
1076 #define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */
1077 #define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */
1078 #define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */
1079 #define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */
1080 #define CBON (0x0400) /* Comp. B enable */
1081 #define CBMRVL (0x0800) /* Comp. B CBMRV Level */
1082 #define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/
1083 //#define RESERVED (0x2000) /* Comp. B */
1084 //#define RESERVED (0x4000) /* Comp. B */
1085 //#define RESERVED (0x8000) /* Comp. B */
1086 
1087 /* CBCTL1 Control Bits */
1088 #define CBOUT_L (0x0001) /* Comp. B Output */
1089 #define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */
1090 #define CBF_L (0x0004) /* Comp. B Enable Output Filter */
1091 #define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */
1092 #define CBSHORT_L (0x0010) /* Comp. B Input Short */
1093 #define CBEX_L (0x0020) /* Comp. B Exchange Inputs */
1094 #define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */
1095 #define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */
1096 //#define RESERVED (0x2000) /* Comp. B */
1097 //#define RESERVED (0x4000) /* Comp. B */
1098 //#define RESERVED (0x8000) /* Comp. B */
1099 
1100 /* CBCTL1 Control Bits */
1101 #define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */
1102 #define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */
1103 #define CBON_H (0x0004) /* Comp. B enable */
1104 #define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */
1105 #define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/
1106 //#define RESERVED (0x2000) /* Comp. B */
1107 //#define RESERVED (0x4000) /* Comp. B */
1108 //#define RESERVED (0x8000) /* Comp. B */
1109 
1110 #define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */
1111 #define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */
1112 #define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */
1113 #define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */
1114 
1115 #define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */
1116 #define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */
1117 #define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/
1118 #define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */
1119 
1120 /* CBCTL2 Control Bits */
1121 #define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
1122 #define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
1123 #define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
1124 #define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
1125 #define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
1126 #define CBRSEL (0x0020) /* Comp. B Reference select */
1127 #define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */
1128 #define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */
1129 #define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */
1130 #define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */
1131 #define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */
1132 #define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */
1133 #define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */
1134 #define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */
1135 #define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */
1136 #define CBREFACC (0x8000) /* Comp. B Reference Accuracy */
1137 
1138 /* CBCTL2 Control Bits */
1139 #define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
1140 #define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
1141 #define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
1142 #define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
1143 #define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
1144 #define CBRSEL_L (0x0020) /* Comp. B Reference select */
1145 #define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */
1146 #define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */
1147 
1148 /* CBCTL2 Control Bits */
1149 #define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */
1150 #define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */
1151 #define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */
1152 #define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */
1153 #define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */
1154 #define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */
1155 #define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */
1156 #define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */
1157 
1158 #define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */
1159 #define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */
1160 #define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */
1161 #define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */
1162 #define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */
1163 #define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */
1164 #define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */
1165 #define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */
1166 #define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */
1167 #define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */
1168 #define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */
1169 #define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */
1170 #define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */
1171 #define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */
1172 #define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */
1173 #define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */
1174 #define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */
1175 #define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */
1176 #define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */
1177 #define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */
1178 #define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */
1179 #define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */
1180 #define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */
1181 #define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */
1182 #define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */
1183 #define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */
1184 #define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */
1185 #define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */
1186 #define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */
1187 #define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */
1188 #define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */
1189 #define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */
1190 
1191 #define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */
1192 #define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */
1193 #define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */
1194 #define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */
1195 
1196 #define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */
1197 #define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */
1198 #define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */
1199 #define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */
1200 #define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */
1201 #define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */
1202 #define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */
1203 #define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */
1204 #define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */
1205 #define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */
1206 #define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */
1207 #define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */
1208 #define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */
1209 #define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */
1210 #define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */
1211 #define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */
1212 #define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */
1213 #define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */
1214 #define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */
1215 #define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */
1216 #define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */
1217 #define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */
1218 #define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */
1219 #define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */
1220 #define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */
1221 #define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */
1222 #define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */
1223 #define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */
1224 #define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */
1225 #define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */
1226 #define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */
1227 #define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */
1228 
1229 #define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */
1230 #define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */
1231 #define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */
1232 #define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */
1233 
1234 #define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
1235 #define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
1236 #define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
1237 #define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
1238 #define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
1239 #define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
1240 #define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
1241 #define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
1242 #define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */
1243 #define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */
1244 #define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */
1245 #define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */
1246 #define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */
1247 #define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */
1248 #define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */
1249 #define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */
1250 
1251 #define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
1252 #define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
1253 #define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
1254 #define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
1255 #define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
1256 #define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
1257 #define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
1258 #define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
1259 
1260 #define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */
1261 #define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */
1262 #define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */
1263 #define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */
1264 #define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */
1265 #define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */
1266 #define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */
1267 #define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */
1268 
1269 /* CBINT Control Bits */
1270 #define CBIFG (0x0001) /* Comp. B Interrupt Flag */
1271 #define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
1272 //#define RESERVED (0x0004) /* Comp. B */
1273 //#define RESERVED (0x0008) /* Comp. B */
1274 //#define RESERVED (0x0010) /* Comp. B */
1275 //#define RESERVED (0x0020) /* Comp. B */
1276 //#define RESERVED (0x0040) /* Comp. B */
1277 //#define RESERVED (0x0080) /* Comp. B */
1278 #define CBIE (0x0100) /* Comp. B Interrupt Enable */
1279 #define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */
1280 //#define RESERVED (0x0400) /* Comp. B */
1281 //#define RESERVED (0x0800) /* Comp. B */
1282 //#define RESERVED (0x1000) /* Comp. B */
1283 //#define RESERVED (0x2000) /* Comp. B */
1284 //#define RESERVED (0x4000) /* Comp. B */
1285 //#define RESERVED (0x8000) /* Comp. B */
1286 
1287 /* CBINT Control Bits */
1288 #define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */
1289 #define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
1290 //#define RESERVED (0x0004) /* Comp. B */
1291 //#define RESERVED (0x0008) /* Comp. B */
1292 //#define RESERVED (0x0010) /* Comp. B */
1293 //#define RESERVED (0x0020) /* Comp. B */
1294 //#define RESERVED (0x0040) /* Comp. B */
1295 //#define RESERVED (0x0080) /* Comp. B */
1296 //#define RESERVED (0x0400) /* Comp. B */
1297 //#define RESERVED (0x0800) /* Comp. B */
1298 //#define RESERVED (0x1000) /* Comp. B */
1299 //#define RESERVED (0x2000) /* Comp. B */
1300 //#define RESERVED (0x4000) /* Comp. B */
1301 //#define RESERVED (0x8000) /* Comp. B */
1302 
1303 /* CBINT Control Bits */
1304 //#define RESERVED (0x0004) /* Comp. B */
1305 //#define RESERVED (0x0008) /* Comp. B */
1306 //#define RESERVED (0x0010) /* Comp. B */
1307 //#define RESERVED (0x0020) /* Comp. B */
1308 //#define RESERVED (0x0040) /* Comp. B */
1309 //#define RESERVED (0x0080) /* Comp. B */
1310 #define CBIE_H (0x0001) /* Comp. B Interrupt Enable */
1311 #define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */
1312 //#define RESERVED (0x0400) /* Comp. B */
1313 //#define RESERVED (0x0800) /* Comp. B */
1314 //#define RESERVED (0x1000) /* Comp. B */
1315 //#define RESERVED (0x2000) /* Comp. B */
1316 //#define RESERVED (0x4000) /* Comp. B */
1317 //#define RESERVED (0x8000) /* Comp. B */
1318 
1319 /* CBIV Definitions */
1320 #define CBIV_NONE (0x0000) /* No Interrupt pending */
1321 #define CBIV_CBIFG (0x0002) /* CBIFG */
1322 #define CBIV_CBIIFG (0x0004) /* CBIIFG */
1323 
1324 #endif
1325 /************************************************************
1326 * CC1101 Radio Interface
1327 ************************************************************/
1328 #ifdef __MSP430_HAS_CC1101__ /* Definition to show that Module is available */
1329 
1330 #define OFS_RF1AIFCTL0 (0x0000) /* Radio interface control register 0 */
1331 #define OFS_RF1AIFCTL0_L OFS_RF1AIFCTL0
1332 #define OFS_RF1AIFCTL0_H OFS_RF1AIFCTL0+1
1333 #define OFS_RF1AIFCTL1 (0x0002) /* Radio interface control register 1 */
1334 #define OFS_RF1AIFCTL1_L OFS_RF1AIFCTL1
1335 #define OFS_RF1AIFCTL1_H OFS_RF1AIFCTL1+1
1336 #define RF1AIFIFG RF1AIFCTL1_L /* Radio interface interrupt flag register */
1337 #define RF1AIFIE RF1AIFCTL1_H /* Radio interface interrupt enable register */
1338 #define OFS_RF1AIFCTL2 (0x0004) /* (Radio interface control register 2) */
1339 #define OFS_RF1AIFCTL2_L OFS_RF1AIFCTL2
1340 #define OFS_RF1AIFCTL2_H OFS_RF1AIFCTL2+1
1341 #define OFS_RF1AIFERR (0x0006) /* Radio interface error flag register */
1342 #define OFS_RF1AIFERR_L OFS_RF1AIFERR
1343 #define OFS_RF1AIFERR_H OFS_RF1AIFERR+1
1344 #define OFS_RF1AIFERRV (0x000C) /* Radio interface error vector word register */
1345 #define OFS_RF1AIFERRV_L OFS_RF1AIFERRV
1346 #define OFS_RF1AIFERRV_H OFS_RF1AIFERRV+1
1347 #define OFS_RF1AIFIV (0x000E) /* Radio interface interrupt vector word register */
1348 #define OFS_RF1AIFIV_L OFS_RF1AIFIV
1349 #define OFS_RF1AIFIV_H OFS_RF1AIFIV+1
1350 #define OFS_RF1AINSTRW (0x0010) /* Radio instruction word register */
1351 #define OFS_RF1AINSTRW_L OFS_RF1AINSTRW
1352 #define OFS_RF1AINSTRW_H OFS_RF1AINSTRW+1
1353 #define RF1ADINB RF1AINSTRW_L /* Radio instruction byte register */
1354 #define RF1AINSTRB RF1AINSTRW_H /* Radio byte data in register */
1355 #define OFS_RF1AINSTR1W (0x0012) /* Radio instruction 1-byte register with autoread */
1356 #define OFS_RF1AINSTR1W_L OFS_RF1AINSTR1W
1357 #define OFS_RF1AINSTR1W_H OFS_RF1AINSTR1W+1
1358 #define RF1AINSTR1B RF1AINSTR1W_H /* Radio instruction 1-byte register with autoread */
1359 #define OFS_RF1AINSTR2W (0x0014) /* Radio instruction 2-byte register with autoread */
1360 #define OFS_RF1AINSTR2W_L OFS_RF1AINSTR2W
1361 #define OFS_RF1AINSTR2W_H OFS_RF1AINSTR2W+1
1362 #define RF1AINSTR2B RF1AINSTR1W_H /* Radio instruction 2-byte register with autoread */
1363 #define OFS_RF1ADINW (0x0016) /* Radio word data in register */
1364 #define OFS_RF1ADINW_L OFS_RF1ADINW
1365 #define OFS_RF1ADINW_H OFS_RF1ADINW+1
1366 
1367 #define OFS_RF1ASTAT0W (0x0020) /* Radio status word register without auto-read */
1368 #define OFS_RF1ASTAT0W_L OFS_RF1ASTAT0W
1369 #define OFS_RF1ASTAT0W_H OFS_RF1ASTAT0W+1
1370 #define RF1ADOUT0B RF1ASTAT0W_L /* Radio byte data out register without auto-read */
1371 #define RF1ASTAT0B RF1ASTAT0W_H /* Radio status byte register without auto-read */
1372 #define RF1ASTATW RF1ASTAT0W /* Radio status word register without auto-read */
1373 #define RF1ADOUTB RF1ASTAT0W_L /* Radio byte data out register without auto-read */
1374 #define RF1ASTATB RF1ASTAT0W_H /* Radio status byte register without auto-read */
1375 #define OFS_RF1ASTAT1W (0x0022) /* Radio status word register with 1-byte auto-read */
1376 #define OFS_RF1ASTAT1W_L OFS_RF1ASTAT1W
1377 #define OFS_RF1ASTAT1W_H OFS_RF1ASTAT1W+1
1378 #define RF1ADOUT1B RF1ASTAT1W_L /* Radio byte data out register with 1-byte auto-read */
1379 #define RF1ASTAT1B RF1ASTAT1W_H /* Radio status byte register with 1-byte auto-read */
1380 #define OFS_RF1ASTAT2W (0x0024) /* Radio status word register with 2-byte auto-read */
1381 #define OFS_RF1ASTAT2W_L OFS_RF1ASTAT2W
1382 #define OFS_RF1ASTAT2W_H OFS_RF1ASTAT2W+1
1383 #define RF1ADOUT2B RF1ASTAT2W_L /* Radio byte data out register with 2-byte auto-read */
1384 #define RF1ASTAT2B RF1ASTAT2W_H /* Radio status byte register with 2-byte auto-read */
1385 #define OFS_RF1ADOUT0W (0x0028) /* Radio core word data out register without auto-read */
1386 #define OFS_RF1ADOUT0W_L OFS_RF1ADOUT0W
1387 #define OFS_RF1ADOUT0W_H OFS_RF1ADOUT0W+1
1388 #define RF1ADOUTW RF1ADOUT0W /* Radio core word data out register without auto-read */
1389 #define RF1ADOUTW_L RF1ADOUT0W_L /* Radio core word data out register without auto-read */
1390 #define RF1ADOUTW_H RF1ADOUT0W_H /* Radio core word data out register without auto-read */
1391 #define OFS_RF1ADOUT1W (0x002A) /* Radio core word data out register with 1-byte auto-read */
1392 #define OFS_RF1ADOUT1W_L OFS_RF1ADOUT1W
1393 #define OFS_RF1ADOUT1W_H OFS_RF1ADOUT1W+1
1394 #define OFS_RF1ADOUT2W (0x002C) /* Radio core word data out register with 2-byte auto-read */
1395 #define OFS_RF1ADOUT2W_L OFS_RF1ADOUT2W
1396 #define OFS_RF1ADOUT2W_H OFS_RF1ADOUT2W+1
1397 #define OFS_RF1AIN (0x0030) /* Radio core signal input register */
1398 #define OFS_RF1AIN_L OFS_RF1AIN
1399 #define OFS_RF1AIN_H OFS_RF1AIN+1
1400 #define OFS_RF1AIFG (0x0032) /* Radio core interrupt flag register */
1401 #define OFS_RF1AIFG_L OFS_RF1AIFG
1402 #define OFS_RF1AIFG_H OFS_RF1AIFG+1
1403 #define OFS_RF1AIES (0x0034) /* Radio core interrupt edge select register */
1404 #define OFS_RF1AIES_L OFS_RF1AIES
1405 #define OFS_RF1AIES_H OFS_RF1AIES+1
1406 #define OFS_RF1AIE (0x0036) /* Radio core interrupt enable register */
1407 #define OFS_RF1AIE_L OFS_RF1AIE
1408 #define OFS_RF1AIE_H OFS_RF1AIE+1
1409 #define OFS_RF1AIV (0x0038) /* Radio core interrupt vector word register */
1410 #define OFS_RF1AIV_L OFS_RF1AIV
1411 #define OFS_RF1AIV_H OFS_RF1AIV+1
1412 #define OFS_RF1ARXFIFO (0x003C) /* Direct receive FIFO access register */
1413 #define OFS_RF1ARXFIFO_L OFS_RF1ARXFIFO
1414 #define OFS_RF1ARXFIFO_H OFS_RF1ARXFIFO+1
1415 #define OFS_RF1ATXFIFO (0x003E) /* Direct transmit FIFO access register */
1416 #define OFS_RF1ATXFIFO_L OFS_RF1ATXFIFO
1417 #define OFS_RF1ATXFIFO_H OFS_RF1ATXFIFO+1
1418 
1419 /* RF1AIFCTL0 Control Bits */
1420 #define RFFIFOEN (0x0001) /* CC1101 Direct FIFO access enable */
1421 #define RFENDIAN (0x0002) /* CC1101 Disable endianness conversion */
1422 
1423 /* RF1AIFCTL0 Control Bits */
1424 #define RFFIFOEN_L (0x0001) /* CC1101 Direct FIFO access enable */
1425 #define RFENDIAN_L (0x0002) /* CC1101 Disable endianness conversion */
1426 
1427 /* RF1AIFCTL1 Control Bits */
1428 #define RFRXIFG (0x0001) /* Radio interface direct FIFO access receive interrupt flag */
1429 #define RFTXIFG (0x0002) /* Radio interface direct FIFO access transmit interrupt flag */
1430 #define RFERRIFG (0x0004) /* Radio interface error interrupt flag */
1431 #define RFINSTRIFG (0x0010) /* Radio interface instruction interrupt flag */
1432 #define RFDINIFG (0x0020) /* Radio interface data in interrupt flag */
1433 #define RFSTATIFG (0x0040) /* Radio interface status interrupt flag */
1434 #define RFDOUTIFG (0x0080) /* Radio interface data out interrupt flag */
1435 #define RFRXIE (0x0100) /* Radio interface direct FIFO access receive interrupt enable */
1436 #define RFTXIE (0x0200) /* Radio interface direct FIFO access transmit interrupt enable */
1437 #define RFERRIE (0x0400) /* Radio interface error interrupt enable */
1438 #define RFINSTRIE (0x1000) /* Radio interface instruction interrupt enable */
1439 #define RFDINIE (0x2000) /* Radio interface data in interrupt enable */
1440 #define RFSTATIE (0x4000) /* Radio interface status interrupt enable */
1441 #define RFDOUTIE (0x8000) /* Radio interface data out interrupt enable */
1442 
1443 /* RF1AIFCTL1 Control Bits */
1444 #define RFRXIFG_L (0x0001) /* Radio interface direct FIFO access receive interrupt flag */
1445 #define RFTXIFG_L (0x0002) /* Radio interface direct FIFO access transmit interrupt flag */
1446 #define RFERRIFG_L (0x0004) /* Radio interface error interrupt flag */
1447 #define RFINSTRIFG_L (0x0010) /* Radio interface instruction interrupt flag */
1448 #define RFDINIFG_L (0x0020) /* Radio interface data in interrupt flag */
1449 #define RFSTATIFG_L (0x0040) /* Radio interface status interrupt flag */
1450 #define RFDOUTIFG_L (0x0080) /* Radio interface data out interrupt flag */
1451 
1452 /* RF1AIFCTL1 Control Bits */
1453 #define RFRXIE_H (0x0001) /* Radio interface direct FIFO access receive interrupt enable */
1454 #define RFTXIE_H (0x0002) /* Radio interface direct FIFO access transmit interrupt enable */
1455 #define RFERRIE_H (0x0004) /* Radio interface error interrupt enable */
1456 #define RFINSTRIE_H (0x0010) /* Radio interface instruction interrupt enable */
1457 #define RFDINIE_H (0x0020) /* Radio interface data in interrupt enable */
1458 #define RFSTATIE_H (0x0040) /* Radio interface status interrupt enable */
1459 #define RFDOUTIE_H (0x0080) /* Radio interface data out interrupt enable */
1460 
1461 /* RF1AIFERR Control Bits */
1462 #define LVERR (0x0001) /* Low Core Voltage Error Flag */
1463 #define OPERR (0x0002) /* Operand Error Flag */
1464 #define OUTERR (0x0004) /* Output data not available Error Flag */
1465 #define OPOVERR (0x0008) /* Operand Overwrite Error Flag */
1466 
1467 /* RF1AIFERR Control Bits */
1468 #define LVERR_L (0x0001) /* Low Core Voltage Error Flag */
1469 #define OPERR_L (0x0002) /* Operand Error Flag */
1470 #define OUTERR_L (0x0004) /* Output data not available Error Flag */
1471 #define OPOVERR_L (0x0008) /* Operand Overwrite Error Flag */
1472 
1473 /* RF1AIFERRV Definitions */
1474 #define RF1AIFERRV_NONE (0x0000) /* No Error pending */
1475 #define RF1AIFERRV_LVERR (0x0002) /* Low core voltage error */
1476 #define RF1AIFERRV_OPERR (0x0004) /* Operand Error */
1477 #define RF1AIFERRV_OUTERR (0x0006) /* Output data not available Error */
1478 #define RF1AIFERRV_OPOVERR (0x0008) /* Operand Overwrite Error */
1479 
1480 /* RF1AIFIV Definitions */
1481 #define RF1AIFIV_NONE (0x0000) /* No Interrupt pending */
1482 #define RF1AIFIV_RFERRIFG (0x0002) /* Radio interface error */
1483 #define RF1AIFIV_RFDOUTIFG (0x0004) /* Radio i/f data out */
1484 #define RF1AIFIV_RFSTATIFG (0x0006) /* Radio i/f status out */
1485 #define RF1AIFIV_RFDINIFG (0x0008) /* Radio i/f data in */
1486 #define RF1AIFIV_RFINSTRIFG (0x000A) /* Radio i/f instruction in */
1487 
1488 /* RF1AIV Definitions */
1489 #define RF1AIV_NONE (0x0000) /* No Interrupt pending */
1490 #define RF1AIV_RFIFG0 (0x0002) /* RFIFG0 */
1491 #define RF1AIV_RFIFG1 (0x0004) /* RFIFG1 */
1492 #define RF1AIV_RFIFG2 (0x0006) /* RFIFG2 */
1493 #define RF1AIV_RFIFG3 (0x0008) /* RFIFG3 */
1494 #define RF1AIV_RFIFG4 (0x000A) /* RFIFG4 */
1495 #define RF1AIV_RFIFG5 (0x000C) /* RFIFG5 */
1496 #define RF1AIV_RFIFG6 (0x000E) /* RFIFG6 */
1497 #define RF1AIV_RFIFG7 (0x0010) /* RFIFG7 */
1498 #define RF1AIV_RFIFG8 (0x0012) /* RFIFG8 */
1499 #define RF1AIV_RFIFG9 (0x0014) /* RFIFG9 */
1500 #define RF1AIV_RFIFG10 (0x0016) /* RFIFG10 */
1501 #define RF1AIV_RFIFG11 (0x0018) /* RFIFG11 */
1502 #define RF1AIV_RFIFG12 (0x001A) /* RFIFG12 */
1503 #define RF1AIV_RFIFG13 (0x001C) /* RFIFG13 */
1504 #define RF1AIV_RFIFG14 (0x001E) /* RFIFG14 */
1505 #define RF1AIV_RFIFG15 (0x0020) /* RFIFG15 */
1506 
1507 // Radio Core Registers
1508 #define IOCFG2 0x00 /* IOCFG2 - GDO2 output pin configuration */
1509 #define IOCFG1 0x01 /* IOCFG1 - GDO1 output pin configuration */
1510 #define IOCFG0 0x02 /* IOCFG1 - GDO0 output pin configuration */
1511 #define FIFOTHR 0x03 /* FIFOTHR - RX FIFO and TX FIFO thresholds */
1512 #define SYNC1 0x04 /* SYNC1 - Sync word, high byte */
1513 #define SYNC0 0x05 /* SYNC0 - Sync word, low byte */
1514 #define PKTLEN 0x06 /* PKTLEN - Packet length */
1515 #define PKTCTRL1 0x07 /* PKTCTRL1 - Packet automation control */
1516 #define PKTCTRL0 0x08 /* PKTCTRL0 - Packet automation control */
1517 #define ADDR 0x09 /* ADDR - Device address */
1518 #define CHANNR 0x0A /* CHANNR - Channel number */
1519 #define FSCTRL1 0x0B /* FSCTRL1 - Frequency synthesizer control */
1520 #define FSCTRL0 0x0C /* FSCTRL0 - Frequency synthesizer control */
1521 #define FREQ2 0x0D /* FREQ2 - Frequency control word, high byte */
1522 #define FREQ1 0x0E /* FREQ1 - Frequency control word, middle byte */
1523 #define FREQ0 0x0F /* FREQ0 - Frequency control word, low byte */
1524 #define MDMCFG4 0x10 /* MDMCFG4 - Modem configuration */
1525 #define MDMCFG3 0x11 /* MDMCFG3 - Modem configuration */
1526 #define MDMCFG2 0x12 /* MDMCFG2 - Modem configuration */
1527 #define MDMCFG1 0x13 /* MDMCFG1 - Modem configuration */
1528 #define MDMCFG0 0x14 /* MDMCFG0 - Modem configuration */
1529 #define DEVIATN 0x15 /* DEVIATN - Modem deviation setting */
1530 #define MCSM2 0x16 /* MCSM2 - Main Radio Control State Machine configuration */
1531 #define MCSM1 0x17 /* MCSM1 - Main Radio Control State Machine configuration */
1532 #define MCSM0 0x18 /* MCSM0 - Main Radio Control State Machine configuration */
1533 #define FOCCFG 0x19 /* FOCCFG - Frequency Offset Compensation configuration */
1534 #define BSCFG 0x1A /* BSCFG - Bit Synchronization configuration */
1535 #define AGCCTRL2 0x1B /* AGCCTRL2 - AGC control */
1536 #define AGCCTRL1 0x1C /* AGCCTRL1 - AGC control */
1537 #define AGCCTRL0 0x1D /* AGCCTRL0 - AGC control */
1538 #define WOREVT1 0x1E /* WOREVT1 - High byte Event0 timeout */
1539 #define WOREVT0 0x1F /* WOREVT0 - Low byte Event0 timeout */
1540 #define WORCTRL 0x20 /* WORCTRL - Wake On Radio control */
1541 #define FREND1 0x21 /* FREND1 - Front end RX configuration */
1542 #define FREND0 0x22 /* FREDN0 - Front end TX configuration */
1543 #define FSCAL3 0x23 /* FSCAL3 - Frequency synthesizer calibration */
1544 #define FSCAL2 0x24 /* FSCAL2 - Frequency synthesizer calibration */
1545 #define FSCAL1 0x25 /* FSCAL1 - Frequency synthesizer calibration */
1546 #define FSCAL0 0x26 /* FSCAL0 - Frequency synthesizer calibration */
1547 //#define RCCTRL1 0x27 /* RCCTRL1 - RC oscillator configuration */
1548 //#define RCCTRL0 0x28 /* RCCTRL0 - RC oscillator configuration */
1549 #define FSTEST 0x29 /* FSTEST - Frequency synthesizer calibration control */
1550 #define PTEST 0x2A /* PTEST - Production test */
1551 #define AGCTEST 0x2B /* AGCTEST - AGC test */
1552 #define TEST2 0x2C /* TEST2 - Various test settings */
1553 #define TEST1 0x2D /* TEST1 - Various test settings */
1554 #define TEST0 0x2E /* TEST0 - Various test settings */
1555 
1556 /* status registers */
1557 #define PARTNUM 0x30 /* PARTNUM - Chip ID */
1558 #define VERSION 0x31 /* VERSION - Chip ID */
1559 #define FREQEST 0x32 /* FREQEST – Frequency Offset Estimate from demodulator */
1560 #define LQI 0x33 /* LQI – Demodulator estimate for Link Quality */
1561 #define RSSI 0x34 /* RSSI – Received signal strength indication */
1562 #define MARCSTATE 0x35 /* MARCSTATE – Main Radio Control State Machine state */
1563 #define WORTIME1 0x36 /* WORTIME1 – High byte of WOR time */
1564 #define WORTIME0 0x37 /* WORTIME0 – Low byte of WOR time */
1565 #define PKTSTATUS 0x38 /* PKTSTATUS – Current GDOx status and packet status */
1566 #define VCO_VC_DAC 0x39 /* VCO_VC_DAC – Current setting from PLL calibration module */
1567 #define TXBYTES 0x3A /* TXBYTES – Underflow and number of bytes */
1568 #define RXBYTES 0x3B /* RXBYTES – Overflow and number of bytes */
1569 
1570 /* burst write registers */
1571 #define PATABLE 0x3E /* PATABLE - PA control settings table */
1572 #define TXFIFO 0x3F /* TXFIFO - Transmit FIFO */
1573 #define RXFIFO 0x3F /* RXFIFO - Receive FIFO */
1574 
1575 /* Radio Core Instructions */
1576 /* command strobes */
1577 #define RF_SRES 0x30 /* SRES - Reset chip. */
1578 #define RF_SFSTXON 0x31 /* SFSTXON - Enable and calibrate frequency synthesizer. */
1579 #define RF_SXOFF 0x32 /* SXOFF - Turn off crystal oscillator. */
1580 #define RF_SCAL 0x33 /* SCAL - Calibrate frequency synthesizer and turn it off. */
1581 #define RF_SRX 0x34 /* SRX - Enable RX. Perform calibration if enabled. */
1582 #define RF_STX 0x35 /* STX - Enable TX. If in RX state, only enable TX if CCA passes. */
1583 #define RF_SIDLE 0x36 /* SIDLE - Exit RX / TX, turn off frequency synthesizer. */
1584 //#define RF_SRSVD 0x37 /* SRVSD - Reserved. Do not use. */
1585 #define RF_SWOR 0x38 /* SWOR - Start automatic RX polling sequence (Wake-on-Radio) */
1586 #define RF_SPWD 0x39 /* SPWD - Enter power down mode when CSn goes high. */
1587 #define RF_SFRX 0x3A /* SFRX - Flush the RX FIFO buffer. */
1588 #define RF_SFTX 0x3B /* SFTX - Flush the TX FIFO buffer. */
1589 #define RF_SWORRST 0x3C /* SWORRST - Reset real time clock. */
1590 #define RF_SNOP 0x3D /* SNOP - No operation. Returns status byte. */
1591 
1592 #define RF_RXSTAT 0x80 /* Used in combination with strobe commands delivers number of availabe bytes in RX FIFO with return status */
1593 #define RF_TXSTAT 0x00 /* Used in combination with strobe commands delivers number of availabe bytes in TX FIFO with return status */
1594 
1595 /* other radio instr */
1596 #define RF_SNGLREGRD 0x80
1597 #define RF_SNGLREGWR 0x00
1598 #define RF_REGRD 0xC0
1599 #define RF_REGWR 0x40
1600 #define RF_STATREGRD 0xC0 /* Read single radio core status register */
1601 #define RF_SNGLPATABRD (RF_SNGLREGRD+PATABLE)
1602 #define RF_SNGLPATABWR (RF_SNGLREGWR+PATABLE)
1603 #define RF_PATABRD (RF_REGRD+PATABLE)
1604 #define RF_PATABWR (RF_REGWR+PATABLE)
1605 #define RF_SNGLRXRD (RF_SNGLREGRD+RXFIFO)
1606 #define RF_SNGLTXWR (RF_SNGLREGWR+TXFIFO)
1607 #define RF_RXFIFORD (RF_REGRD+RXFIFO)
1608 #define RF_TXFIFOWR (RF_REGWR+TXFIFO)
1609 
1610 #endif
1611 /*************************************************************
1612 * CRC Module
1613 *************************************************************/
1614 #ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */
1615 
1616 #define OFS_CRCDI (0x0000) /* CRC Data In Register */
1617 #define OFS_CRCDI_L OFS_CRCDI
1618 #define OFS_CRCDI_H OFS_CRCDI+1
1619 #define OFS_CRCDIRB (0x0002) /* CRC data in reverse byte Register */
1620 #define OFS_CRCDIRB_L OFS_CRCDIRB
1621 #define OFS_CRCDIRB_H OFS_CRCDIRB+1
1622 #define OFS_CRCINIRES (0x0004) /* CRC Initialisation Register and Result Register */
1623 #define OFS_CRCINIRES_L OFS_CRCINIRES
1624 #define OFS_CRCINIRES_H OFS_CRCINIRES+1
1625 #define OFS_CRCRESR (0x0006) /* CRC reverse result Register */
1626 #define OFS_CRCRESR_L OFS_CRCRESR
1627 #define OFS_CRCRESR_H OFS_CRCRESR+1
1628 
1629 #endif
1630 /************************************************************
1631 * DAC12
1632 ************************************************************/
1633 #ifdef __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */
1634 
1635 #define OFS_DAC12_0CTL0 (0x0000) /* DAC12_0 Control Register 0 */
1636 #define OFS_DAC12_0CTL1 (0x0002) /* DAC12_0 Control Register 1 */
1637 #define OFS_DAC12_0DAT (0x0004) /* DAC12_0 Data */
1638 #define OFS_DAC12_0CALCTL (0x0006) /* DAC12_0 Calibration Control Register */
1639 #define OFS_DAC12_0CALDAT (0x0008) /* DAC12_0 Calibration Data Register */
1640 #define OFS_DAC12_1CTL0 (0x0010) /* DAC12_1 Control Register 0 */
1641 #define OFS_DAC12_1CTL1 (0x0012) /* DAC12_1 Control Register 1 */
1642 #define OFS_DAC12_1DAT (0x0014) /* DAC12_1 Data */
1643 #define OFS_DAC12_1CALCTL (0x0016) /* DAC12_1 Calibration Control Register */
1644 #define OFS_DAC12_1CALDAT (0x0018) /* DAC12_1 Calibration Data Register */
1645 #define OFS_DAC12_IV (0x001E) /* DAC12 Interrupt Vector Word */
1646 
1647 /* DAC12_xCTL0 Control Bits */
1648 #define DAC12GRP (0x0001) /* DAC12 group */
1649 #define DAC12ENC (0x0002) /* DAC12 enable conversion */
1650 #define DAC12IFG (0x0004) /* DAC12 interrupt flag */
1651 #define DAC12IE (0x0008) /* DAC12 interrupt enable */
1652 #define DAC12DF (0x0010) /* DAC12 data format */
1653 #define DAC12AMP0 (0x0020) /* DAC12 amplifier bit 0 */
1654 #define DAC12AMP1 (0x0040) /* DAC12 amplifier bit 1 */
1655 #define DAC12AMP2 (0x0080) /* DAC12 amplifier bit 2 */
1656 #define DAC12IR (0x0100) /* DAC12 input reference and output range */
1657 #define DAC12CALON (0x0200) /* DAC12 calibration */
1658 #define DAC12LSEL0 (0x0400) /* DAC12 load select bit 0 */
1659 #define DAC12LSEL1 (0x0800) /* DAC12 load select bit 1 */
1660 #define DAC12RES (0x1000) /* DAC12 resolution */
1661 #define DAC12SREF0 (0x2000) /* DAC12 reference bit 0 */
1662 #define DAC12SREF1 (0x4000) /* DAC12 reference bit 1 */
1663 #define DAC12OPS (0x8000) /* DAC12 Operation Amp. */
1664 
1665 #define DAC12AMP_0 (0*0x0020u) /* DAC12 amplifier 0: off, 3-state */
1666 #define DAC12AMP_1 (1*0x0020u) /* DAC12 amplifier 1: off, off */
1667 #define DAC12AMP_2 (2*0x0020u) /* DAC12 amplifier 2: low, low */
1668 #define DAC12AMP_3 (3*0x0020u) /* DAC12 amplifier 3: low, medium */
1669 #define DAC12AMP_4 (4*0x0020u) /* DAC12 amplifier 4: low, high */
1670 #define DAC12AMP_5 (5*0x0020u) /* DAC12 amplifier 5: medium, medium */
1671 #define DAC12AMP_6 (6*0x0020u) /* DAC12 amplifier 6: medium, high */
1672 #define DAC12AMP_7 (7*0x0020u) /* DAC12 amplifier 7: high, high */
1673 
1674 #define DAC12LSEL_0 (0*0x0400u) /* DAC12 load select 0: direct */
1675 #define DAC12LSEL_1 (1*0x0400u) /* DAC12 load select 1: latched with DAT */
1676 #define DAC12LSEL_2 (2*0x0400u) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */
1677 #define DAC12LSEL_3 (3*0x0400u) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */
1678 
1679 #define DAC12SREF_0 (0*0x2000u) /* DAC12 reference 0: Vref+ */
1680 #define DAC12SREF_1 (1*0x2000u) /* DAC12 reference 1: Vref+ */
1681 #define DAC12SREF_2 (2*0x2000u) /* DAC12 reference 2: Veref+ */
1682 #define DAC12SREF_3 (3*0x2000u) /* DAC12 reference 3: Veref+ */
1683 
1684 /* DAC12_xCTL1 Control Bits */
1685 #define DAC12DFJ (0x0001) /* DAC12 Data Format Justification */
1686 #define DAC12OG (0x0002) /* DAC12 output buffer gain: 0: 3x gain / 1: 2x gain */
1687 
1688 /* DAC12_xCALCTL Control Bits */
1689 #define DAC12LOCK (0x0001) /* DAC12 Calibration Lock */
1690 
1691 #define DAC12PW (0xA500) /* DAC12 Calibration Register write Password */
1692 
1693 /* DACIV Definitions */
1694 #define DACIV_NONE (0x0000) /* No Interrupt pending */
1695 #define DACIV_DAC12IFG_0 (0x0002) /* DAC12IFG_0 */
1696 #define DACIV_DAC12IFG_1 (0x0004) /* DAC12IFG_1 */
1697 
1698 #endif
1699 /************************************************************
1700 * DMA_X
1701 ************************************************************/
1702 #ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
1703 
1704 #define OFS_DMACTL0 (0x0000) /* DMA Module Control 0 */
1705 #define OFS_DMACTL0_L OFS_DMACTL0
1706 #define OFS_DMACTL0_H OFS_DMACTL0+1
1707 #define OFS_DMACTL1 (0x0002) /* DMA Module Control 1 */
1708 #define OFS_DMACTL1_L OFS_DMACTL1
1709 #define OFS_DMACTL1_H OFS_DMACTL1+1
1710 #define OFS_DMACTL2 (0x0004) /* DMA Module Control 2 */
1711 #define OFS_DMACTL2_L OFS_DMACTL2
1712 #define OFS_DMACTL2_H OFS_DMACTL2+1
1713 #define OFS_DMACTL3 (0x0006) /* DMA Module Control 3 */
1714 #define OFS_DMACTL3_L OFS_DMACTL3
1715 #define OFS_DMACTL3_H OFS_DMACTL3+1
1716 #define OFS_DMACTL4 (0x0008) /* DMA Module Control 4 */
1717 #define OFS_DMACTL4_L OFS_DMACTL4
1718 #define OFS_DMACTL4_H OFS_DMACTL4+1
1719 #define OFS_DMAIV (0x000E) /* DMA Interrupt Vector Word */
1720 #define OFS_DMAIV_L OFS_DMAIV
1721 #define OFS_DMAIV_H OFS_DMAIV+1
1722 
1723 #define OFS_DMA0CTL (0x0010) /* DMA Channel 0 Control */
1724 #define OFS_DMA0CTL_L OFS_DMA0CTL
1725 #define OFS_DMA0CTL_H OFS_DMA0CTL+1
1726 #define OFS_DMA0SA (0x0012) /* DMA Channel 0 Source Address */
1727 #define OFS_DMA0DA (0x0016) /* DMA Channel 0 Destination Address */
1728 #define OFS_DMA0SZ (0x001A) /* DMA Channel 0 Transfer Size */
1729 
1730 #define OFS_DMA1CTL (0x0020) /* DMA Channel 1 Control */
1731 #define OFS_DMA1CTL_L OFS_DMA1CTL
1732 #define OFS_DMA1CTL_H OFS_DMA1CTL+1
1733 #define OFS_DMA1SA (0x0022) /* DMA Channel 1 Source Address */
1734 #define OFS_DMA1DA (0x0026) /* DMA Channel 1 Destination Address */
1735 #define OFS_DMA1SZ (0x002A) /* DMA Channel 1 Transfer Size */
1736 
1737 #define OFS_DMA2CTL (0x0030) /* DMA Channel 2 Control */
1738 #define OFS_DMA2CTL_L OFS_DMA2CTL
1739 #define OFS_DMA2CTL_H OFS_DMA2CTL+1
1740 #define OFS_DMA2SA (0x0032) /* DMA Channel 2 Source Address */
1741 #define OFS_DMA2DA (0x0036) /* DMA Channel 2 Destination Address */
1742 #define OFS_DMA2SZ (0x003A) /* DMA Channel 2 Transfer Size */
1743 
1744 /* DMACTL0 Control Bits */
1745 #define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
1746 #define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
1747 #define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
1748 #define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
1749 #define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
1750 #define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
1751 #define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
1752 #define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
1753 #define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
1754 #define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
1755 
1756 /* DMACTL0 Control Bits */
1757 #define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
1758 #define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
1759 #define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
1760 #define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
1761 #define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
1762 
1763 /* DMACTL0 Control Bits */
1764 #define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
1765 #define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
1766 #define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
1767 #define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
1768 #define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
1769 
1770 /* DMACTL01 Control Bits */
1771 #define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
1772 #define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
1773 #define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
1774 #define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
1775 #define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
1776 
1777 /* DMACTL01 Control Bits */
1778 #define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
1779 #define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
1780 #define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
1781 #define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
1782 #define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
1783 
1784 /* DMACTL4 Control Bits */
1785 #define ENNMI (0x0001) /* Enable NMI interruption of DMA */
1786 #define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
1787 #define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
1788 
1789 /* DMACTL4 Control Bits */
1790 #define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
1791 #define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
1792 #define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
1793 
1794 /* DMAxCTL Control Bits */
1795 #define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
1796 #define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
1797 #define DMAIE (0x0004) /* DMA interrupt enable */
1798 #define DMAIFG (0x0008) /* DMA interrupt flag */
1799 #define DMAEN (0x0010) /* DMA enable */
1800 #define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
1801 #define DMASRCBYTE (0x0040) /* DMA source byte */
1802 #define DMADSTBYTE (0x0080) /* DMA destination byte */
1803 #define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
1804 #define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
1805 #define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
1806 #define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
1807 #define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
1808 #define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
1809 #define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
1810 
1811 /* DMAxCTL Control Bits */
1812 #define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
1813 #define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
1814 #define DMAIE_L (0x0004) /* DMA interrupt enable */
1815 #define DMAIFG_L (0x0008) /* DMA interrupt flag */
1816 #define DMAEN_L (0x0010) /* DMA enable */
1817 #define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
1818 #define DMASRCBYTE_L (0x0040) /* DMA source byte */
1819 #define DMADSTBYTE_L (0x0080) /* DMA destination byte */
1820 
1821 /* DMAxCTL Control Bits */
1822 #define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
1823 #define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
1824 #define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
1825 #define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
1826 #define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
1827 #define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
1828 #define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
1829 
1830 #define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
1831 #define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
1832 #define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
1833 #define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
1834 
1835 #define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
1836 #define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
1837 #define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
1838 #define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
1839 
1840 #define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
1841 #define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
1842 #define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
1843 #define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
1844 
1845 #define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
1846 #define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
1847 #define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
1848 #define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
1849 #define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
1850 #define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
1851 #define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
1852 #define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
1853 
1854 /* DMAIV Definitions */
1855 #define DMAIV_NONE (0x0000) /* No Interrupt pending */
1856 #define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
1857 #define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
1858 #define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
1859 
1860 #endif
1861 /************************************************************
1862 * DMA_X
1863 ************************************************************/
1864 #ifdef __MSP430_HAS_DMAX_6__ /* Definition to show that Module is available */
1865 
1866 #define OFS_DMACTL0 (0x0000) /* DMA Module Control 0 */
1867 #define OFS_DMACTL0_L OFS_DMACTL0
1868 #define OFS_DMACTL0_H OFS_DMACTL0+1
1869 #define OFS_DMACTL1 (0x0002) /* DMA Module Control 1 */
1870 #define OFS_DMACTL1_L OFS_DMACTL1
1871 #define OFS_DMACTL1_H OFS_DMACTL1+1
1872 #define OFS_DMACTL2 (0x0004) /* DMA Module Control 2 */
1873 #define OFS_DMACTL2_L OFS_DMACTL2
1874 #define OFS_DMACTL2_H OFS_DMACTL2+1
1875 #define OFS_DMACTL3 (0x0006) /* DMA Module Control 3 */
1876 #define OFS_DMACTL3_L OFS_DMACTL3
1877 #define OFS_DMACTL3_H OFS_DMACTL3+1
1878 #define OFS_DMACTL4 (0x0008) /* DMA Module Control 4 */
1879 #define OFS_DMACTL4_L OFS_DMACTL4
1880 #define OFS_DMACTL4_H OFS_DMACTL4+1
1881 #define OFS_DMAIV (0x000E) /* DMA Interrupt Vector Word */
1882 #define OFS_DMAIV_L OFS_DMAIV
1883 #define OFS_DMAIV_H OFS_DMAIV+1
1884 
1885 #define OFS_DMA0CTL (0x0010) /* DMA Channel 0 Control */
1886 #define OFS_DMA0CTL_L OFS_DMA0CTL
1887 #define OFS_DMA0CTL_H OFS_DMA0CTL+1
1888 #define OFS_DMA0SA (0x0012) /* DMA Channel 0 Source Address */
1889 #define OFS_DMA0DA (0x0016) /* DMA Channel 0 Destination Address */
1890 #define OFS_DMA0SZ (0x001A) /* DMA Channel 0 Transfer Size */
1891 
1892 #define OFS_DMA1CTL (0x0020) /* DMA Channel 1 Control */
1893 #define OFS_DMA1CTL_L OFS_DMA1CTL
1894 #define OFS_DMA1CTL_H OFS_DMA1CTL+1
1895 #define OFS_DMA1SA (0x0022) /* DMA Channel 1 Source Address */
1896 #define OFS_DMA1DA (0x0026) /* DMA Channel 1 Destination Address */
1897 #define OFS_DMA1SZ (0x002A) /* DMA Channel 1 Transfer Size */
1898 
1899 #define OFS_DMA2CTL (0x0030) /* DMA Channel 2 Control */
1900 #define OFS_DMA2CTL_L OFS_DMA2CTL
1901 #define OFS_DMA2CTL_H OFS_DMA2CTL+1
1902 #define OFS_DMA2SA (0x0032) /* DMA Channel 2 Source Address */
1903 #define OFS_DMA2DA (0x0036) /* DMA Channel 2 Destination Address */
1904 #define OFS_DMA2SZ (0x003A) /* DMA Channel 2 Transfer Size */
1905 
1906 #define OFS_DMA3CTL (0x0040) /* DMA Channel 3 Control */
1907 #define OFS_DMA3CTL_L OFS_DMA3CTL
1908 #define OFS_DMA3CTL_H OFS_DMA3CTL+1
1909 #define OFS_DMA3SA (0x0042) /* DMA Channel 3 Source Address */
1910 #define OFS_DMA3DA (0x0046) /* DMA Channel 3 Destination Address */
1911 #define OFS_DMA3SZ (0x004A) /* DMA Channel 3 Transfer Size */
1912 
1913 #define OFS_DMA4CTL (0x0050) /* DMA Channel 4 Control */
1914 #define OFS_DMA4CTL_L OFS_DMA4CTL
1915 #define OFS_DMA4CTL_H OFS_DMA4CTL+1
1916 #define OFS_DMA4SA (0x0052) /* DMA Channel 4 Source Address */
1917 #define OFS_DMA4DA (0x0056) /* DMA Channel 4 Destination Address */
1918 #define OFS_DMA4SZ (0x005A) /* DMA Channel 4 Transfer Size */
1919 
1920 #define OFS_DMA5CTL (0x0060) /* DMA Channel 5 Control */
1921 #define OFS_DMA5CTL_L OFS_DMA5CTL
1922 #define OFS_DMA5CTL_H OFS_DMA5CTL+1
1923 #define OFS_DMA5SA (0x0062) /* DMA Channel 5 Source Address */
1924 #define OFS_DMA5DA (0x0066) /* DMA Channel 5 Destination Address */
1925 #define OFS_DMA5SZ (0x006A) /* DMA Channel 5 Transfer Size */
1926 
1927 /* DMACTL0 Control Bits */
1928 #define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
1929 #define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
1930 #define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
1931 #define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
1932 #define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
1933 #define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
1934 #define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
1935 #define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
1936 #define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
1937 #define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
1938 
1939 /* DMACTL0 Control Bits */
1940 #define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
1941 #define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
1942 #define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
1943 #define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
1944 #define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
1945 
1946 /* DMACTL0 Control Bits */
1947 #define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
1948 #define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
1949 #define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
1950 #define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
1951 #define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
1952 
1953 /* DMACTL01 Control Bits */
1954 #define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
1955 #define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
1956 #define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
1957 #define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
1958 #define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
1959 #define DMA3TSEL0 (0x0100) /* DMA channel 3 transfer select bit 0 */
1960 #define DMA3TSEL1 (0x0200) /* DMA channel 3 transfer select bit 1 */
1961 #define DMA3TSEL2 (0x0400) /* DMA channel 3 transfer select bit 2 */
1962 #define DMA3TSEL3 (0x0800) /* DMA channel 3 transfer select bit 3 */
1963 #define DMA3TSEL4 (0x1000) /* DMA channel 3 transfer select bit 4 */
1964 
1965 /* DMACTL01 Control Bits */
1966 #define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
1967 #define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
1968 #define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
1969 #define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
1970 #define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
1971 
1972 /* DMACTL01 Control Bits */
1973 #define DMA3TSEL0_H (0x0001) /* DMA channel 3 transfer select bit 0 */
1974 #define DMA3TSEL1_H (0x0002) /* DMA channel 3 transfer select bit 1 */
1975 #define DMA3TSEL2_H (0x0004) /* DMA channel 3 transfer select bit 2 */
1976 #define DMA3TSEL3_H (0x0008) /* DMA channel 3 transfer select bit 3 */
1977 #define DMA3TSEL4_H (0x0010) /* DMA channel 3 transfer select bit 4 */
1978 
1979 /* DMACTL0 Control Bits */
1980 #define DMA4TSEL0 (0x0001) /* DMA channel 4 transfer select bit 0 */
1981 #define DMA4TSEL1 (0x0002) /* DMA channel 4 transfer select bit 1 */
1982 #define DMA4TSEL2 (0x0004) /* DMA channel 4 transfer select bit 2 */
1983 #define DMA4TSEL3 (0x0008) /* DMA channel 4 transfer select bit 3 */
1984 #define DMA4TSEL4 (0x0010) /* DMA channel 4 transfer select bit 4 */
1985 #define DMA5TSEL0 (0x0100) /* DMA channel 5 transfer select bit 0 */
1986 #define DMA5TSEL1 (0x0200) /* DMA channel 5 transfer select bit 1 */
1987 #define DMA5TSEL2 (0x0400) /* DMA channel 5 transfer select bit 2 */
1988 #define DMA5TSEL3 (0x0800) /* DMA channel 5 transfer select bit 3 */
1989 #define DMA5TSEL4 (0x1000) /* DMA channel 5 transfer select bit 4 */
1990 
1991 /* DMACTL0 Control Bits */
1992 #define DMA4TSEL0_L (0x0001) /* DMA channel 4 transfer select bit 0 */
1993 #define DMA4TSEL1_L (0x0002) /* DMA channel 4 transfer select bit 1 */
1994 #define DMA4TSEL2_L (0x0004) /* DMA channel 4 transfer select bit 2 */
1995 #define DMA4TSEL3_L (0x0008) /* DMA channel 4 transfer select bit 3 */
1996 #define DMA4TSEL4_L (0x0010) /* DMA channel 4 transfer select bit 4 */
1997 
1998 /* DMACTL0 Control Bits */
1999 #define DMA5TSEL0_H (0x0001) /* DMA channel 5 transfer select bit 0 */
2000 #define DMA5TSEL1_H (0x0002) /* DMA channel 5 transfer select bit 1 */
2001 #define DMA5TSEL2_H (0x0004) /* DMA channel 5 transfer select bit 2 */
2002 #define DMA5TSEL3_H (0x0008) /* DMA channel 5 transfer select bit 3 */
2003 #define DMA5TSEL4_H (0x0010) /* DMA channel 5 transfer select bit 4 */
2004 
2005 /* DMACTL4 Control Bits */
2006 #define ENNMI (0x0001) /* Enable NMI interruption of DMA */
2007 #define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
2008 #define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
2009 
2010 /* DMACTL4 Control Bits */
2011 #define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
2012 #define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
2013 #define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
2014 
2015 /* DMAxCTL Control Bits */
2016 #define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
2017 #define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
2018 #define DMAIE (0x0004) /* DMA interrupt enable */
2019 #define DMAIFG (0x0008) /* DMA interrupt flag */
2020 #define DMAEN (0x0010) /* DMA enable */
2021 #define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
2022 #define DMASRCBYTE (0x0040) /* DMA source byte */
2023 #define DMADSTBYTE (0x0080) /* DMA destination byte */
2024 #define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
2025 #define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
2026 #define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
2027 #define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
2028 #define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
2029 #define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
2030 #define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
2031 
2032 /* DMAxCTL Control Bits */
2033 #define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
2034 #define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
2035 #define DMAIE_L (0x0004) /* DMA interrupt enable */
2036 #define DMAIFG_L (0x0008) /* DMA interrupt flag */
2037 #define DMAEN_L (0x0010) /* DMA enable */
2038 #define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
2039 #define DMASRCBYTE_L (0x0040) /* DMA source byte */
2040 #define DMADSTBYTE_L (0x0080) /* DMA destination byte */
2041 
2042 /* DMAxCTL Control Bits */
2043 #define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
2044 #define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
2045 #define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
2046 #define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
2047 #define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
2048 #define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
2049 #define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
2050 
2051 #define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
2052 #define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
2053 #define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
2054 #define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
2055 
2056 #define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
2057 #define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
2058 #define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
2059 #define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
2060 
2061 #define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
2062 #define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
2063 #define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
2064 #define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
2065 
2066 #define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
2067 #define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
2068 #define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
2069 #define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
2070 #define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
2071 #define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
2072 #define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
2073 #define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
2074 
2075 /* DMAIV Definitions */
2076 #define DMAIV_NONE (0x0000) /* No Interrupt pending */
2077 #define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
2078 #define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
2079 #define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
2080 #define DMAIV_DMA3IFG (0x0008) /* DMA3IFG*/
2081 #define DMAIV_DMA4IFG (0x000A) /* DMA4IFG*/
2082 #define DMAIV_DMA5IFG (0x000C) /* DMA5IFG*/
2083 
2084 #endif
2085 /*************************************************************
2086 * Flash Memory
2087 *************************************************************/
2088 #ifdef __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
2089 
2090 #define OFS_FCTL1 (0x0000) /* FLASH Control 1 */
2091 #define OFS_FCTL1_L OFS_FCTL1
2092 #define OFS_FCTL1_H OFS_FCTL1+1
2093 //#define FCTL2_O (0x0002) /* FLASH Control 2 */
2094 #define OFS_FCTL3 (0x0004) /* FLASH Control 3 */
2095 #define OFS_FCTL3_L OFS_FCTL3
2096 #define OFS_FCTL3_H OFS_FCTL3+1
2097 #define OFS_FCTL4 (0x0006) /* FLASH Control 4 */
2098 #define OFS_FCTL4_L OFS_FCTL4
2099 #define OFS_FCTL4_H OFS_FCTL4+1
2100 
2101 #define FRPW (0x9600) /* Flash password returned by read */
2102 #define FWPW (0xA500) /* Flash password for write */
2103 #define FXPW (0x3300) /* for use with XOR instruction */
2104 #define FRKEY (0x9600) /* (legacy definition) Flash key returned by read */
2105 #define FWKEY (0xA500) /* (legacy definition) Flash key for write */
2106 #define FXKEY (0x3300) /* (legacy definition) for use with XOR instruction */
2107 
2108 /* FCTL1 Control Bits */
2109 //#define RESERVED (0x0001) /* Reserved */
2110 #define ERASE (0x0002) /* Enable bit for Flash segment erase */
2111 #define MERAS (0x0004) /* Enable bit for Flash mass erase */
2112 //#define RESERVED (0x0008) /* Reserved */
2113 //#define RESERVED (0x0010) /* Reserved */
2114 #define SWRT (0x0020) /* Smart Write enable */
2115 #define WRT (0x0040) /* Enable bit for Flash write */
2116 #define BLKWRT (0x0080) /* Enable bit for Flash segment write */
2117 
2118 /* FCTL1 Control Bits */
2119 //#define RESERVED (0x0001) /* Reserved */
2120 #define ERASE_L (0x0002) /* Enable bit for Flash segment erase */
2121 #define MERAS_L (0x0004) /* Enable bit for Flash mass erase */
2122 //#define RESERVED (0x0008) /* Reserved */
2123 //#define RESERVED (0x0010) /* Reserved */
2124 #define SWRT_L (0x0020) /* Smart Write enable */
2125 #define WRT_L (0x0040) /* Enable bit for Flash write */
2126 #define BLKWRT_L (0x0080) /* Enable bit for Flash segment write */
2127 
2128 /* FCTL3 Control Bits */
2129 #define BUSY (0x0001) /* Flash busy: 1 */
2130 #define KEYV (0x0002) /* Flash Key violation flag */
2131 #define ACCVIFG (0x0004) /* Flash Access violation flag */
2132 #define WAIT (0x0008) /* Wait flag for segment write */
2133 #define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
2134 #define EMEX (0x0020) /* Flash Emergency Exit */
2135 #define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
2136 //#define RESERVED (0x0080) /* Reserved */
2137 
2138 /* FCTL3 Control Bits */
2139 #define BUSY_L (0x0001) /* Flash busy: 1 */
2140 #define KEYV_L (0x0002) /* Flash Key violation flag */
2141 #define ACCVIFG_L (0x0004) /* Flash Access violation flag */
2142 #define WAIT_L (0x0008) /* Wait flag for segment write */
2143 #define LOCK_L (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
2144 #define EMEX_L (0x0020) /* Flash Emergency Exit */
2145 #define LOCKA_L (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
2146 //#define RESERVED (0x0080) /* Reserved */
2147 
2148 /* FCTL4 Control Bits */
2149 #define VPE (0x0001) /* Voltage Changed during Program Error Flag */
2150 #define MGR0 (0x0010) /* Marginal read 0 mode. */
2151 #define MGR1 (0x0020) /* Marginal read 1 mode. */
2152 #define LOCKINFO (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
2153 
2154 /* FCTL4 Control Bits */
2155 #define VPE_L (0x0001) /* Voltage Changed during Program Error Flag */
2156 #define MGR0_L (0x0010) /* Marginal read 0 mode. */
2157 #define MGR1_L (0x0020) /* Marginal read 1 mode. */
2158 #define LOCKINFO_L (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
2159 
2160 #endif
2161 /************************************************************
2162 * LCD_B
2163 ************************************************************/
2164 #ifdef __MSP430_HAS_LCD_B__ /* Definition to show that Module is available */
2165 
2166 #define OFS_LCDBCTL0 (0x0000) /* LCD_B Control Register 0 */
2167 #define OFS_LCDBCTL0_L OFS_LCDBCTL0
2168 #define OFS_LCDBCTL0_H OFS_LCDBCTL0+1
2169 #define OFS_LCDBCTL1 (0x0002) /* LCD_B Control Register 1 */
2170 #define OFS_LCDBCTL1_L OFS_LCDBCTL1
2171 #define OFS_LCDBCTL1_H OFS_LCDBCTL1+1
2172 #define OFS_LCDBBLKCTL (0x0004) /* LCD_B blinking control register */
2173 #define OFS_LCDBBLKCTL_L OFS_LCDBBLKCTL
2174 #define OFS_LCDBBLKCTL_H OFS_LCDBBLKCTL+1
2175 #define OFS_LCDBMEMCTL (0x0006) /* LCD_B memory control register */
2176 #define OFS_LCDBMEMCTL_L OFS_LCDBMEMCTL
2177 #define OFS_LCDBMEMCTL_H OFS_LCDBMEMCTL+1
2178 #define OFS_LCDBVCTL (0x0008) /* LCD_B Voltage Control Register */
2179 #define OFS_LCDBVCTL_L OFS_LCDBVCTL
2180 #define OFS_LCDBVCTL_H OFS_LCDBVCTL+1
2181 #define OFS_LCDBPCTL0 (0x000A) /* LCD_B Port Control Register 0 */
2182 #define OFS_LCDBPCTL0_L OFS_LCDBPCTL0
2183 #define OFS_LCDBPCTL0_H OFS_LCDBPCTL0+1
2184 #define OFS_LCDBPCTL1 (0x000C) /* LCD_B Port Control Register 1 */
2185 #define OFS_LCDBPCTL1_L OFS_LCDBPCTL1
2186 #define OFS_LCDBPCTL1_H OFS_LCDBPCTL1+1
2187 #define OFS_LCDBPCTL2 (0x000E) /* LCD_B Port Control Register 2 */
2188 #define OFS_LCDBPCTL2_L OFS_LCDBPCTL2
2189 #define OFS_LCDBPCTL2_H OFS_LCDBPCTL2+1
2190 #define OFS_LCDBPCTL3 (0x0010) /* LCD_B Port Control Register 3 */
2191 #define OFS_LCDBPCTL3_L OFS_LCDBPCTL3
2192 #define OFS_LCDBPCTL3_H OFS_LCDBPCTL3+1
2193 #define OFS_LCDBCPCTL (0x0012) /* LCD_B Charge Pump Control Register 3 */
2194 #define OFS_LCDBCPCTL_L OFS_LCDBCPCTL
2195 #define OFS_LCDBCPCTL_H OFS_LCDBCPCTL+1
2196 #define OFS_LCDBIV (0x001E) /* LCD_B Interrupt Vector Register */
2197 
2198 // LCDBCTL0
2199 #define LCDON (0x0001) /* LCD_B LCD On */
2200 #define LCDSON (0x0004) /* LCD_B LCD Segments On */
2201 #define LCDMX0 (0x0008) /* LCD_B Mux Rate Bit: 0 */
2202 #define LCDMX1 (0x0010) /* LCD_B Mux Rate Bit: 1 */
2203 //#define RESERVED (0x0020) /* LCD_B RESERVED */
2204 //#define RESERVED (0x0040) /* LCD_B RESERVED */
2205 #define LCDSSEL (0x0080) /* LCD_B Clock Select */
2206 #define LCDPRE0 (0x0100) /* LCD_B LCD frequency pre-scaler Bit: 0 */
2207 #define LCDPRE1 (0x0200) /* LCD_B LCD frequency pre-scaler Bit: 1 */
2208 #define LCDPRE2 (0x0400) /* LCD_B LCD frequency pre-scaler Bit: 2 */
2209 #define LCDDIV0 (0x0800) /* LCD_B LCD frequency divider Bit: 0 */
2210 #define LCDDIV1 (0x1000) /* LCD_B LCD frequency divider Bit: 1 */
2211 #define LCDDIV2 (0x2000) /* LCD_B LCD frequency divider Bit: 2 */
2212 #define LCDDIV3 (0x4000) /* LCD_B LCD frequency divider Bit: 3 */
2213 #define LCDDIV4 (0x8000) /* LCD_B LCD frequency divider Bit: 4 */
2214 
2215 // LCDBCTL0
2216 #define LCDON_L (0x0001) /* LCD_B LCD On */
2217 #define LCDSON_L (0x0004) /* LCD_B LCD Segments On */
2218 #define LCDMX0_L (0x0008) /* LCD_B Mux Rate Bit: 0 */
2219 #define LCDMX1_L (0x0010) /* LCD_B Mux Rate Bit: 1 */
2220 //#define RESERVED (0x0020) /* LCD_B RESERVED */
2221 //#define RESERVED (0x0040) /* LCD_B RESERVED */
2222 #define LCDSSEL_L (0x0080) /* LCD_B Clock Select */
2223 
2224 // LCDBCTL0
2225 //#define RESERVED (0x0020) /* LCD_B RESERVED */
2226 //#define RESERVED (0x0040) /* LCD_B RESERVED */
2227 #define LCDPRE0_H (0x0001) /* LCD_B LCD frequency pre-scaler Bit: 0 */
2228 #define LCDPRE1_H (0x0002) /* LCD_B LCD frequency pre-scaler Bit: 1 */
2229 #define LCDPRE2_H (0x0004) /* LCD_B LCD frequency pre-scaler Bit: 2 */
2230 #define LCDDIV0_H (0x0008) /* LCD_B LCD frequency divider Bit: 0 */
2231 #define LCDDIV1_H (0x0010) /* LCD_B LCD frequency divider Bit: 1 */
2232 #define LCDDIV2_H (0x0020) /* LCD_B LCD frequency divider Bit: 2 */
2233 #define LCDDIV3_H (0x0040) /* LCD_B LCD frequency divider Bit: 3 */
2234 #define LCDDIV4_H (0x0080) /* LCD_B LCD frequency divider Bit: 4 */
2235 
2236 #define LCDPRE_0 (0x0000) /* LCD_B LCD frequency pre-scaler: /1 */
2237 #define LCDPRE_1 (0x0100) /* LCD_B LCD frequency pre-scaler: /2 */
2238 #define LCDPRE_2 (0x0200) /* LCD_B LCD frequency pre-scaler: /4 */
2239 #define LCDPRE_3 (0x0300) /* LCD_B LCD frequency pre-scaler: /8 */
2240 #define LCDPRE_4 (0x0400) /* LCD_B LCD frequency pre-scaler: /16 */
2241 #define LCDPRE_5 (0x0500) /* LCD_B LCD frequency pre-scaler: /32 */
2242 #define LCDPRE__1 (0x0000) /* LCD_B LCD frequency pre-scaler: /1 */
2243 #define LCDPRE__2 (0x0100) /* LCD_B LCD frequency pre-scaler: /2 */
2244 #define LCDPRE__4 (0x0200) /* LCD_B LCD frequency pre-scaler: /4 */
2245 #define LCDPRE__8 (0x0300) /* LCD_B LCD frequency pre-scaler: /8 */
2246 #define LCDPRE__16 (0x0400) /* LCD_B LCD frequency pre-scaler: /16 */
2247 #define LCDPRE__32 (0x0500) /* LCD_B LCD frequency pre-scaler: /32 */
2248 
2249 #define LCDDIV_0 (0x0000) /* LCD_B LCD frequency divider: /1 */
2250 #define LCDDIV_1 (0x0800) /* LCD_B LCD frequency divider: /2 */
2251 #define LCDDIV_2 (0x1000) /* LCD_B LCD frequency divider: /3 */
2252 #define LCDDIV_3 (0x1800) /* LCD_B LCD frequency divider: /4 */
2253 #define LCDDIV_4 (0x2000) /* LCD_B LCD frequency divider: /5 */
2254 #define LCDDIV_5 (0x2800) /* LCD_B LCD frequency divider: /6 */
2255 #define LCDDIV_6 (0x3000) /* LCD_B LCD frequency divider: /7 */
2256 #define LCDDIV_7 (0x3800) /* LCD_B LCD frequency divider: /8 */
2257 #define LCDDIV_8 (0x4000) /* LCD_B LCD frequency divider: /9 */
2258 #define LCDDIV_9 (0x4800) /* LCD_B LCD frequency divider: /10 */
2259 #define LCDDIV_10 (0x5000) /* LCD_B LCD frequency divider: /11 */
2260 #define LCDDIV_11 (0x5800) /* LCD_B LCD frequency divider: /12 */
2261 #define LCDDIV_12 (0x6000) /* LCD_B LCD frequency divider: /13 */
2262 #define LCDDIV_13 (0x6800) /* LCD_B LCD frequency divider: /14 */
2263 #define LCDDIV_14 (0x7000) /* LCD_B LCD frequency divider: /15 */
2264 #define LCDDIV_15 (0x7800) /* LCD_B LCD frequency divider: /16 */
2265 #define LCDDIV_16 (0x8000) /* LCD_B LCD frequency divider: /17 */
2266 #define LCDDIV_17 (0x8800) /* LCD_B LCD frequency divider: /18 */
2267 #define LCDDIV_18 (0x9000) /* LCD_B LCD frequency divider: /19 */
2268 #define LCDDIV_19 (0x9800) /* LCD_B LCD frequency divider: /20 */
2269 #define LCDDIV_20 (0xA000) /* LCD_B LCD frequency divider: /21 */
2270 #define LCDDIV_21 (0xA800) /* LCD_B LCD frequency divider: /22 */
2271 #define LCDDIV_22 (0xB000) /* LCD_B LCD frequency divider: /23 */
2272 #define LCDDIV_23 (0xB800) /* LCD_B LCD frequency divider: /24 */
2273 #define LCDDIV_24 (0xC000) /* LCD_B LCD frequency divider: /25 */
2274 #define LCDDIV_25 (0xC800) /* LCD_B LCD frequency divider: /26 */
2275 #define LCDDIV_26 (0xD000) /* LCD_B LCD frequency divider: /27 */
2276 #define LCDDIV_27 (0xD800) /* LCD_B LCD frequency divider: /28 */
2277 #define LCDDIV_28 (0xE000) /* LCD_B LCD frequency divider: /29 */
2278 #define LCDDIV_29 (0xE800) /* LCD_B LCD frequency divider: /30 */
2279 #define LCDDIV_30 (0xF000) /* LCD_B LCD frequency divider: /31 */
2280 #define LCDDIV_31 (0xF800) /* LCD_B LCD frequency divider: /32 */
2281 #define LCDDIV__1 (0x0000) /* LCD_B LCD frequency divider: /1 */
2282 #define LCDDIV__2 (0x0800) /* LCD_B LCD frequency divider: /2 */
2283 #define LCDDIV__3 (0x1000) /* LCD_B LCD frequency divider: /3 */
2284 #define LCDDIV__4 (0x1800) /* LCD_B LCD frequency divider: /4 */
2285 #define LCDDIV__5 (0x2000) /* LCD_B LCD frequency divider: /5 */
2286 #define LCDDIV__6 (0x2800) /* LCD_B LCD frequency divider: /6 */
2287 #define LCDDIV__7 (0x3000) /* LCD_B LCD frequency divider: /7 */
2288 #define LCDDIV__8 (0x3800) /* LCD_B LCD frequency divider: /8 */
2289 #define LCDDIV__9 (0x4000) /* LCD_B LCD frequency divider: /9 */
2290 #define LCDDIV__10 (0x4800) /* LCD_B LCD frequency divider: /10 */
2291 #define LCDDIV__11 (0x5000) /* LCD_B LCD frequency divider: /11 */
2292 #define LCDDIV__12 (0x5800) /* LCD_B LCD frequency divider: /12 */
2293 #define LCDDIV__13 (0x6000) /* LCD_B LCD frequency divider: /13 */
2294 #define LCDDIV__14 (0x6800) /* LCD_B LCD frequency divider: /14 */
2295 #define LCDDIV__15 (0x7000) /* LCD_B LCD frequency divider: /15 */
2296 #define LCDDIV__16 (0x7800) /* LCD_B LCD frequency divider: /16 */
2297 #define LCDDIV__17 (0x8000) /* LCD_B LCD frequency divider: /17 */
2298 #define LCDDIV__18 (0x8800) /* LCD_B LCD frequency divider: /18 */
2299 #define LCDDIV__19 (0x9000) /* LCD_B LCD frequency divider: /19 */
2300 #define LCDDIV__20 (0x9800) /* LCD_B LCD frequency divider: /20 */
2301 #define LCDDIV__21 (0xA000) /* LCD_B LCD frequency divider: /21 */
2302 #define LCDDIV__22 (0xA800) /* LCD_B LCD frequency divider: /22 */
2303 #define LCDDIV__23 (0xB000) /* LCD_B LCD frequency divider: /23 */
2304 #define LCDDIV__24 (0xB800) /* LCD_B LCD frequency divider: /24 */
2305 #define LCDDIV__25 (0xC000) /* LCD_B LCD frequency divider: /25 */
2306 #define LCDDIV__26 (0xC800) /* LCD_B LCD frequency divider: /26 */
2307 #define LCDDIV__27 (0xD000) /* LCD_B LCD frequency divider: /27 */
2308 #define LCDDIV__28 (0xD800) /* LCD_B LCD frequency divider: /28 */
2309 #define LCDDIV__29 (0xE000) /* LCD_B LCD frequency divider: /29 */
2310 #define LCDDIV__30 (0xE800) /* LCD_B LCD frequency divider: /30 */
2311 #define LCDDIV__31 (0xF000) /* LCD_B LCD frequency divider: /31 */
2312 #define LCDDIV__32 (0xF800) /* LCD_B LCD frequency divider: /32 */
2313 
2314 /* Display modes coded with Bits 2-4 */
2315 #define LCDSTATIC (LCDSON)
2316 #define LCD2MUX (LCDMX0+LCDSON)
2317 #define LCD3MUX (LCDMX1+LCDSON)
2318 #define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
2319 
2320 // LCDBCTL1
2321 #define LCDFRMIFG (0x0001) /* LCD_B LCD frame interrupt flag */
2322 #define LCDBLKOFFIFG (0x0002) /* LCD_B LCD blinking off interrupt flag, */
2323 #define LCDBLKONIFG (0x0004) /* LCD_B LCD blinking on interrupt flag, */
2324 #define LCDNOCAPIFG (0x0008) /* LCD_B No cpacitance connected interrupt flag */
2325 #define LCDFRMIE (0x0100) /* LCD_B LCD frame interrupt enable */
2326 #define LCDBLKOFFIE (0x0200) /* LCD_B LCD blinking off interrupt flag, */
2327 #define LCDBLKONIE (0x0400) /* LCD_B LCD blinking on interrupt flag, */
2328 #define LCDNOCAPIE (0x0800) /* LCD_B No cpacitance connected interrupt enable */
2329 
2330 // LCDBCTL1
2331 #define LCDFRMIFG_L (0x0001) /* LCD_B LCD frame interrupt flag */
2332 #define LCDBLKOFFIFG_L (0x0002) /* LCD_B LCD blinking off interrupt flag, */
2333 #define LCDBLKONIFG_L (0x0004) /* LCD_B LCD blinking on interrupt flag, */
2334 #define LCDNOCAPIFG_L (0x0008) /* LCD_B No cpacitance connected interrupt flag */
2335 
2336 // LCDBCTL1
2337 #define LCDFRMIE_H (0x0001) /* LCD_B LCD frame interrupt enable */
2338 #define LCDBLKOFFIE_H (0x0002) /* LCD_B LCD blinking off interrupt flag, */
2339 #define LCDBLKONIE_H (0x0004) /* LCD_B LCD blinking on interrupt flag, */
2340 #define LCDNOCAPIE_H (0x0008) /* LCD_B No cpacitance connected interrupt enable */
2341 
2342 // LCDBBLKCTL
2343 #define LCDBLKMOD0 (0x0001) /* LCD_B Blinking mode Bit: 0 */
2344 #define LCDBLKMOD1 (0x0002) /* LCD_B Blinking mode Bit: 1 */
2345 #define LCDBLKPRE0 (0x0004) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */
2346 #define LCDBLKPRE1 (0x0008) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */
2347 #define LCDBLKPRE2 (0x0010) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */
2348 #define LCDBLKDIV0 (0x0020) /* LCD_B Clock divider for blinking frequency Bit: 0 */
2349 #define LCDBLKDIV1 (0x0040) /* LCD_B Clock divider for blinking frequency Bit: 1 */
2350 #define LCDBLKDIV2 (0x0080) /* LCD_B Clock divider for blinking frequency Bit: 2 */
2351 
2352 // LCDBBLKCTL
2353 #define LCDBLKMOD0_L (0x0001) /* LCD_B Blinking mode Bit: 0 */
2354 #define LCDBLKMOD1_L (0x0002) /* LCD_B Blinking mode Bit: 1 */
2355 #define LCDBLKPRE0_L (0x0004) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */
2356 #define LCDBLKPRE1_L (0x0008) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */
2357 #define LCDBLKPRE2_L (0x0010) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */
2358 #define LCDBLKDIV0_L (0x0020) /* LCD_B Clock divider for blinking frequency Bit: 0 */
2359 #define LCDBLKDIV1_L (0x0040) /* LCD_B Clock divider for blinking frequency Bit: 1 */
2360 #define LCDBLKDIV2_L (0x0080) /* LCD_B Clock divider for blinking frequency Bit: 2 */
2361 
2362 #define LCDBLKMOD_0 (0x0000) /* LCD_B Blinking mode: Off */
2363 #define LCDBLKMOD_1 (0x0001) /* LCD_B Blinking mode: Individual */
2364 #define LCDBLKMOD_2 (0x0002) /* LCD_B Blinking mode: All */
2365 #define LCDBLKMOD_3 (0x0003) /* LCD_B Blinking mode: Switching */
2366 
2367 // LCDBMEMCTL
2368 #define LCDDISP (0x0001) /* LCD_B LCD memory registers for display */
2369 #define LCDCLRM (0x0002) /* LCD_B Clear LCD memory */
2370 #define LCDCLRBM (0x0004) /* LCD_B Clear LCD blinking memory */
2371 
2372 // LCDBMEMCTL
2373 #define LCDDISP_L (0x0001) /* LCD_B LCD memory registers for display */
2374 #define LCDCLRM_L (0x0002) /* LCD_B Clear LCD memory */
2375 #define LCDCLRBM_L (0x0004) /* LCD_B Clear LCD blinking memory */
2376 
2377 // LCDBVCTL
2378 #define LCD2B (0x0001) /* Selects 1/2 bias. */
2379 #define VLCDREF0 (0x0002) /* Selects reference voltage for regulated charge pump: 0 */
2380 #define VLCDREF1 (0x0004) /* Selects reference voltage for regulated charge pump: 1 */
2381 #define LCDCPEN (0x0008) /* LCD Voltage Charge Pump Enable. */
2382 #define VLCDEXT (0x0010) /* Select external source for VLCD. */
2383 #define LCDEXTBIAS (0x0020) /* V2 - V4 voltage select. */
2384 #define R03EXT (0x0040) /* Selects external connections for LCD mid voltages. */
2385 #define LCDREXT (0x0080) /* Selects external connection for lowest LCD voltage. */
2386 #define VLCD0 (0x0200) /* VLCD select: 0 */
2387 #define VLCD1 (0x0400) /* VLCD select: 1 */
2388 #define VLCD2 (0x0800) /* VLCD select: 2 */
2389 #define VLCD3 (0x1000) /* VLCD select: 3 */
2390 
2391 // LCDBVCTL
2392 #define LCD2B_L (0x0001) /* Selects 1/2 bias. */
2393 #define VLCDREF0_L (0x0002) /* Selects reference voltage for regulated charge pump: 0 */
2394 #define VLCDREF1_L (0x0004) /* Selects reference voltage for regulated charge pump: 1 */
2395 #define LCDCPEN_L (0x0008) /* LCD Voltage Charge Pump Enable. */
2396 #define VLCDEXT_L (0x0010) /* Select external source for VLCD. */
2397 #define LCDEXTBIAS_L (0x0020) /* V2 - V4 voltage select. */
2398 #define R03EXT_L (0x0040) /* Selects external connections for LCD mid voltages. */
2399 #define LCDREXT_L (0x0080) /* Selects external connection for lowest LCD voltage. */
2400 
2401 // LCDBVCTL
2402 #define VLCD0_H (0x0002) /* VLCD select: 0 */
2403 #define VLCD1_H (0x0004) /* VLCD select: 1 */
2404 #define VLCD2_H (0x0008) /* VLCD select: 2 */
2405 #define VLCD3_H (0x0010) /* VLCD select: 3 */
2406 
2407 /* Reference voltage source select for the regulated charge pump */
2408 #define VLCDREF_0 (0<<1) /* Internal */
2409 #define VLCDREF_1 (1<<1) /* External */
2410 #define VLCDREF_2 (2<<1) /* Reserved */
2411 #define VLCDREF_3 (3<<1) /* Reserved */
2412 
2413 /* Charge pump voltage selections */
2414 #define VLCD_0 (0<<9) /* Charge pump disabled */
2415 #define VLCD_1 (1<<9) /* VLCD = 2.60V */
2416 #define VLCD_2 (2<<9) /* VLCD = 2.66V */
2417 #define VLCD_3 (3<<9) /* VLCD = 2.72V */
2418 #define VLCD_4 (4<<9) /* VLCD = 2.78V */
2419 #define VLCD_5 (5<<9) /* VLCD = 2.84V */
2420 #define VLCD_6 (6<<9) /* VLCD = 2.90V */
2421 #define VLCD_7 (7<<9) /* VLCD = 2.96V */
2422 #define VLCD_8 (8<<9) /* VLCD = 3.02V */
2423 #define VLCD_9 (9<<9) /* VLCD = 3.08V */
2424 #define VLCD_10 (10<<9) /* VLCD = 3.14V */
2425 #define VLCD_11 (11<<9) /* VLCD = 3.20V */
2426 #define VLCD_12 (12<<9) /* VLCD = 3.26V */
2427 #define VLCD_13 (13<<9) /* VLCD = 3.32V */
2428 #define VLCD_14 (14<<9) /* VLCD = 3.38V */
2429 #define VLCD_15 (15<<9) /* VLCD = 3.44V */
2430 
2431 #define VLCD_DISABLED (0<<9) /* Charge pump disabled */
2432 #define VLCD_2_60 (1<<9) /* VLCD = 2.60V */
2433 #define VLCD_2_66 (2<<9) /* VLCD = 2.66V */
2434 #define VLCD_2_72 (3<<9) /* VLCD = 2.72V */
2435 #define VLCD_2_78 (4<<9) /* VLCD = 2.78V */
2436 #define VLCD_2_84 (5<<9) /* VLCD = 2.84V */
2437 #define VLCD_2_90 (6<<9) /* VLCD = 2.90V */
2438 #define VLCD_2_96 (7<<9) /* VLCD = 2.96V */
2439 #define VLCD_3_02 (8<<9) /* VLCD = 3.02V */
2440 #define VLCD_3_08 (9<<9) /* VLCD = 3.08V */
2441 #define VLCD_3_14 (10<<9) /* VLCD = 3.14V */
2442 #define VLCD_3_20 (11<<9) /* VLCD = 3.20V */
2443 #define VLCD_3_26 (12<<9) /* VLCD = 3.26V */
2444 #define VLCD_3_32 (13<<9) /* VLCD = 3.32V */
2445 #define VLCD_3_38 (14<<9) /* VLCD = 3.38V */
2446 #define VLCD_3_44 (15<<9) /* VLCD = 3.44V */
2447 
2448 // LCDBPCTL0
2449 #define LCDS0 (0x0001) /* LCD Segment 0 enable. */
2450 #define LCDS1 (0x0002) /* LCD Segment 1 enable. */
2451 #define LCDS2 (0x0004) /* LCD Segment 2 enable. */
2452 #define LCDS3 (0x0008) /* LCD Segment 3 enable. */
2453 #define LCDS4 (0x0010) /* LCD Segment 4 enable. */
2454 #define LCDS5 (0x0020) /* LCD Segment 5 enable. */
2455 #define LCDS6 (0x0040) /* LCD Segment 6 enable. */
2456 #define LCDS7 (0x0080) /* LCD Segment 7 enable. */
2457 #define LCDS8 (0x0100) /* LCD Segment 8 enable. */
2458 #define LCDS9 (0x0200) /* LCD Segment 9 enable. */
2459 #define LCDS10 (0x0400) /* LCD Segment 10 enable. */
2460 #define LCDS11 (0x0800) /* LCD Segment 11 enable. */
2461 #define LCDS12 (0x1000) /* LCD Segment 12 enable. */
2462 #define LCDS13 (0x2000) /* LCD Segment 13 enable. */
2463 #define LCDS14 (0x4000) /* LCD Segment 14 enable. */
2464 #define LCDS15 (0x8000) /* LCD Segment 15 enable. */
2465 
2466 // LCDBPCTL0
2467 #define LCDS0_L (0x0001) /* LCD Segment 0 enable. */
2468 #define LCDS1_L (0x0002) /* LCD Segment 1 enable. */
2469 #define LCDS2_L (0x0004) /* LCD Segment 2 enable. */
2470 #define LCDS3_L (0x0008) /* LCD Segment 3 enable. */
2471 #define LCDS4_L (0x0010) /* LCD Segment 4 enable. */
2472 #define LCDS5_L (0x0020) /* LCD Segment 5 enable. */
2473 #define LCDS6_L (0x0040) /* LCD Segment 6 enable. */
2474 #define LCDS7_L (0x0080) /* LCD Segment 7 enable. */
2475 
2476 // LCDBPCTL0
2477 #define LCDS8_H (0x0001) /* LCD Segment 8 enable. */
2478 #define LCDS9_H (0x0002) /* LCD Segment 9 enable. */
2479 #define LCDS10_H (0x0004) /* LCD Segment 10 enable. */
2480 #define LCDS11_H (0x0008) /* LCD Segment 11 enable. */
2481 #define LCDS12_H (0x0010) /* LCD Segment 12 enable. */
2482 #define LCDS13_H (0x0020) /* LCD Segment 13 enable. */
2483 #define LCDS14_H (0x0040) /* LCD Segment 14 enable. */
2484 #define LCDS15_H (0x0080) /* LCD Segment 15 enable. */
2485 
2486 // LCDBPCTL1
2487 #define LCDS16 (0x0001) /* LCD Segment 16 enable. */
2488 #define LCDS17 (0x0002) /* LCD Segment 17 enable. */
2489 #define LCDS18 (0x0004) /* LCD Segment 18 enable. */
2490 #define LCDS19 (0x0008) /* LCD Segment 19 enable. */
2491 #define LCDS20 (0x0010) /* LCD Segment 20 enable. */
2492 #define LCDS21 (0x0020) /* LCD Segment 21 enable. */
2493 #define LCDS22 (0x0040) /* LCD Segment 22 enable. */
2494 #define LCDS23 (0x0080) /* LCD Segment 23 enable. */
2495 #define LCDS24 (0x0100) /* LCD Segment 24 enable. */
2496 #define LCDS25 (0x0200) /* LCD Segment 25 enable. */
2497 #define LCDS26 (0x0400) /* LCD Segment 26 enable. */
2498 #define LCDS27 (0x0800) /* LCD Segment 27 enable. */
2499 #define LCDS28 (0x1000) /* LCD Segment 28 enable. */
2500 #define LCDS29 (0x2000) /* LCD Segment 29 enable. */
2501 #define LCDS30 (0x4000) /* LCD Segment 30 enable. */
2502 #define LCDS31 (0x8000) /* LCD Segment 31 enable. */
2503 
2504 // LCDBPCTL1
2505 #define LCDS16_L (0x0001) /* LCD Segment 16 enable. */
2506 #define LCDS17_L (0x0002) /* LCD Segment 17 enable. */
2507 #define LCDS18_L (0x0004) /* LCD Segment 18 enable. */
2508 #define LCDS19_L (0x0008) /* LCD Segment 19 enable. */
2509 #define LCDS20_L (0x0010) /* LCD Segment 20 enable. */
2510 #define LCDS21_L (0x0020) /* LCD Segment 21 enable. */
2511 #define LCDS22_L (0x0040) /* LCD Segment 22 enable. */
2512 #define LCDS23_L (0x0080) /* LCD Segment 23 enable. */
2513 
2514 // LCDBPCTL1
2515 #define LCDS24_H (0x0001) /* LCD Segment 24 enable. */
2516 #define LCDS25_H (0x0002) /* LCD Segment 25 enable. */
2517 #define LCDS26_H (0x0004) /* LCD Segment 26 enable. */
2518 #define LCDS27_H (0x0008) /* LCD Segment 27 enable. */
2519 #define LCDS28_H (0x0010) /* LCD Segment 28 enable. */
2520 #define LCDS29_H (0x0020) /* LCD Segment 29 enable. */
2521 #define LCDS30_H (0x0040) /* LCD Segment 30 enable. */
2522 #define LCDS31_H (0x0080) /* LCD Segment 31 enable. */
2523 
2524 // LCDBPCTL2
2525 #define LCDS32 (0x0001) /* LCD Segment 32 enable. */
2526 #define LCDS33 (0x0002) /* LCD Segment 33 enable. */
2527 #define LCDS34 (0x0004) /* LCD Segment 34 enable. */
2528 #define LCDS35 (0x0008) /* LCD Segment 35 enable. */
2529 #define LCDS36 (0x0010) /* LCD Segment 36 enable. */
2530 #define LCDS37 (0x0020) /* LCD Segment 37 enable. */
2531 #define LCDS38 (0x0040) /* LCD Segment 38 enable. */
2532 #define LCDS39 (0x0080) /* LCD Segment 39 enable. */
2533 #define LCDS40 (0x0100) /* LCD Segment 40 enable. */
2534 #define LCDS41 (0x0200) /* LCD Segment 41 enable. */
2535 #define LCDS42 (0x0400) /* LCD Segment 42 enable. */
2536 #define LCDS43 (0x0800) /* LCD Segment 43 enable. */
2537 #define LCDS44 (0x1000) /* LCD Segment 44 enable. */
2538 #define LCDS45 (0x2000) /* LCD Segment 45 enable. */
2539 #define LCDS46 (0x4000) /* LCD Segment 46 enable. */
2540 #define LCDS47 (0x8000) /* LCD Segment 47 enable. */
2541 
2542 // LCDBPCTL2
2543 #define LCDS32_L (0x0001) /* LCD Segment 32 enable. */
2544 #define LCDS33_L (0x0002) /* LCD Segment 33 enable. */
2545 #define LCDS34_L (0x0004) /* LCD Segment 34 enable. */
2546 #define LCDS35_L (0x0008) /* LCD Segment 35 enable. */
2547 #define LCDS36_L (0x0010) /* LCD Segment 36 enable. */
2548 #define LCDS37_L (0x0020) /* LCD Segment 37 enable. */
2549 #define LCDS38_L (0x0040) /* LCD Segment 38 enable. */
2550 #define LCDS39_L (0x0080) /* LCD Segment 39 enable. */
2551 
2552 // LCDBPCTL2
2553 #define LCDS40_H (0x0001) /* LCD Segment 40 enable. */
2554 #define LCDS41_H (0x0002) /* LCD Segment 41 enable. */
2555 #define LCDS42_H (0x0004) /* LCD Segment 42 enable. */
2556 #define LCDS43_H (0x0008) /* LCD Segment 43 enable. */
2557 #define LCDS44_H (0x0010) /* LCD Segment 44 enable. */
2558 #define LCDS45_H (0x0020) /* LCD Segment 45 enable. */
2559 #define LCDS46_H (0x0040) /* LCD Segment 46 enable. */
2560 #define LCDS47_H (0x0080) /* LCD Segment 47 enable. */
2561 
2562 // LCDBPCTL3
2563 #define LCDS48 (0x0001) /* LCD Segment 48 enable. */
2564 #define LCDS49 (0x0002) /* LCD Segment 49 enable. */
2565 #define LCDS50 (0x0004) /* LCD Segment 50 enable. */
2566 
2567 // LCDBPCTL3
2568 #define LCDS48_L (0x0001) /* LCD Segment 48 enable. */
2569 #define LCDS49_L (0x0002) /* LCD Segment 49 enable. */
2570 #define LCDS50_L (0x0004) /* LCD Segment 50 enable. */
2571 
2572 // LCDBCPCTL
2573 #define LCDCPDIS0 (0x0001) /* LCD charge pump disable */
2574 #define LCDCPDIS1 (0x0002) /* LCD charge pump disable */
2575 #define LCDCPDIS2 (0x0004) /* LCD charge pump disable */
2576 #define LCDCPDIS3 (0x0008) /* LCD charge pump disable */
2577 #define LCDCPDIS4 (0x0010) /* LCD charge pump disable */
2578 #define LCDCPDIS5 (0x0020) /* LCD charge pump disable */
2579 #define LCDCPDIS6 (0x0040) /* LCD charge pump disable */
2580 #define LCDCPDIS7 (0x0080) /* LCD charge pump disable */
2581 #define LCDCPCLKSYNC (0x8000) /* LCD charge pump clock synchronization */
2582 
2583 // LCDBCPCTL
2584 #define LCDCPDIS0_L (0x0001) /* LCD charge pump disable */
2585 #define LCDCPDIS1_L (0x0002) /* LCD charge pump disable */
2586 #define LCDCPDIS2_L (0x0004) /* LCD charge pump disable */
2587 #define LCDCPDIS3_L (0x0008) /* LCD charge pump disable */
2588 #define LCDCPDIS4_L (0x0010) /* LCD charge pump disable */
2589 #define LCDCPDIS5_L (0x0020) /* LCD charge pump disable */
2590 #define LCDCPDIS6_L (0x0040) /* LCD charge pump disable */
2591 #define LCDCPDIS7_L (0x0080) /* LCD charge pump disable */
2592 
2593 // LCDBCPCTL
2594 #define LCDCPCLKSYNC_H (0x0080) /* LCD charge pump clock synchronization */
2595 
2596 #define OFS_LCDM1 (0x0020) /* LCD Memory 1 */
2597 #define LCDMEM_ LCDM1 /* LCD Memory */
2598 #ifdef __ASM_HEADER__
2599 #define LCDMEM LCDM1 /* LCD Memory (for assembler) */
2600 #else
2601 #define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */
2602 #endif
2603 #define OFS_LCDM2 (0x0021) /* LCD Memory 2 */
2604 #define OFS_LCDM3 (0x0022) /* LCD Memory 3 */
2605 #define OFS_LCDM4 (0x0023) /* LCD Memory 4 */
2606 #define OFS_LCDM5 (0x0024) /* LCD Memory 5 */
2607 #define OFS_LCDM6 (0x0025) /* LCD Memory 6 */
2608 #define OFS_LCDM7 (0x0026) /* LCD Memory 7 */
2609 #define OFS_LCDM8 (0x0027) /* LCD Memory 8 */
2610 #define OFS_LCDM9 (0x0028) /* LCD Memory 9 */
2611 #define OFS_LCDM10 (0x0029) /* LCD Memory 10 */
2612 #define OFS_LCDM11 (0x002A) /* LCD Memory 11 */
2613 #define OFS_LCDM12 (0x002B) /* LCD Memory 12 */
2614 #define OFS_LCDM13 (0x002C) /* LCD Memory 13 */
2615 #define OFS_LCDM14 (0x002D) /* LCD Memory 14 */
2616 #define OFS_LCDM15 (0x002E) /* LCD Memory 15 */
2617 #define OFS_LCDM16 (0x002F) /* LCD Memory 16 */
2618 #define OFS_LCDM17 (0x0030) /* LCD Memory 17 */
2619 #define OFS_LCDM18 (0x0031) /* LCD Memory 18 */
2620 #define OFS_LCDM19 (0x0032) /* LCD Memory 19 */
2621 #define OFS_LCDM20 (0x0033) /* LCD Memory 20 */
2622 #define OFS_LCDM21 (0x0034) /* LCD Memory 21 */
2623 #define OFS_LCDM22 (0x0035) /* LCD Memory 22 */
2624 #define OFS_LCDM23 (0x0036) /* LCD Memory 23 */
2625 #define OFS_LCDM24 (0x0037) /* LCD Memory 24 */
2626 
2627 #define OFS_LCDBM1 (0x0040) /* LCD Blinking Memory 1 */
2628 #define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */
2629 #ifdef __ASM_HEADER__
2630 #define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */
2631 #else
2632 #define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */
2633 #endif
2634 #define OFS_LCDBM2 (0x0041) /* LCD Blinking Memory 2 */
2635 #define OFS_LCDBM3 (0x0042) /* LCD Blinking Memory 3 */
2636 #define OFS_LCDBM4 (0x0043) /* LCD Blinking Memory 4 */
2637 #define OFS_LCDBM5 (0x0044) /* LCD Blinking Memory 5 */
2638 #define OFS_LCDBM6 (0x0045) /* LCD Blinking Memory 6 */
2639 #define OFS_LCDBM7 (0x0046) /* LCD Blinking Memory 7 */
2640 #define OFS_LCDBM8 (0x0047) /* LCD Blinking Memory 8 */
2641 #define OFS_LCDBM9 (0x0048) /* LCD Blinking Memory 9 */
2642 #define OFS_LCDBM10 (0x0049) /* LCD Blinking Memory 10 */
2643 #define OFS_LCDBM11 (0x004A) /* LCD Blinking Memory 11 */
2644 #define OFS_LCDBM12 (0x004B) /* LCD Blinking Memory 12 */
2645 #define OFS_LCDBM13 (0x004C) /* LCD Blinking Memory 13 */
2646 #define OFS_LCDBM14 (0x004D) /* LCD Blinking Memory 14 */
2647 #define OFS_LCDBM15 (0x004E) /* LCD Blinking Memory 15 */
2648 #define OFS_LCDBM16 (0x004F) /* LCD Blinking Memory 16 */
2649 #define OFS_LCDBM17 (0x0050) /* LCD Blinking Memory 17 */
2650 #define OFS_LCDBM18 (0x0051) /* LCD Blinking Memory 18 */
2651 #define OFS_LCDBM19 (0x0052) /* LCD Blinking Memory 19 */
2652 #define OFS_LCDBM20 (0x0053) /* LCD Blinking Memory 20 */
2653 #define OFS_LCDBM21 (0x0054) /* LCD Blinking Memory 21 */
2654 #define OFS_LCDBM22 (0x0055) /* LCD Blinking Memory 22 */
2655 #define OFS_LCDBM23 (0x0056) /* LCD Blinking Memory 23 */
2656 #define OFS_LCDBM24 (0x0057) /* LCD Blinking Memory 24 */
2657 
2658 /* LCDBIV Definitions */
2659 #define LCDBIV_NONE (0x0000) /* No Interrupt pending */
2660 #define LCDBIV_LCDNOCAPIFG (0x0002) /* No capacitor connected */
2661 #define LCDBIV_LCDBLKOFFIFG (0x0004) /* Blink, segments off */
2662 #define LCDBIV_LCDBLKONIFG (0x0006) /* Blink, segments on */
2663 #define LCDBIV_LCDFRMIFG (0x0008) /* Frame interrupt */
2664 
2665 #endif
2666 /************************************************************
2667 * HARDWARE MULTIPLIER 32Bit
2668 ************************************************************/
2669 #ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */
2670 
2671 #define OFS_MPY (0x0000) /* Multiply Unsigned/Operand 1 */
2672 #define OFS_MPY_L OFS_MPY
2673 #define OFS_MPY_H OFS_MPY+1
2674 #define OFS_MPYS (0x0002) /* Multiply Signed/Operand 1 */
2675 #define OFS_MPYS_L OFS_MPYS
2676 #define OFS_MPYS_H OFS_MPYS+1
2677 #define OFS_MAC (0x0004) /* Multiply Unsigned and Accumulate/Operand 1 */
2678 #define OFS_MAC_L OFS_MAC
2679 #define OFS_MAC_H OFS_MAC+1
2680 #define OFS_MACS (0x0006) /* Multiply Signed and Accumulate/Operand 1 */
2681 #define OFS_MACS_L OFS_MACS
2682 #define OFS_MACS_H OFS_MACS+1
2683 #define OFS_OP2 (0x0008) /* Operand 2 */
2684 #define OFS_OP2_L OFS_OP2
2685 #define OFS_OP2_H OFS_OP2+1
2686 #define OFS_RESLO (0x000A) /* Result Low Word */
2687 #define OFS_RESLO_L OFS_RESLO
2688 #define OFS_RESLO_H OFS_RESLO+1
2689 #define OFS_RESHI (0x000C) /* Result High Word */
2690 #define OFS_RESHI_L OFS_RESHI
2691 #define OFS_RESHI_H OFS_RESHI+1
2692 #define OFS_SUMEXT (0x000E) /* Sum Extend */
2693 #define OFS_SUMEXT_L OFS_SUMEXT
2694 #define OFS_SUMEXT_H OFS_SUMEXT+1
2695 #define OFS_MPY32CTL0 (0x002C)
2696 #define OFS_MPY32CTL0_L OFS_MPY32CTL0
2697 #define OFS_MPY32CTL0_H OFS_MPY32CTL0+1
2698 
2699 #define OFS_MPY32L (0x0010) /* 32-bit operand 1 - multiply - low word */
2700 #define OFS_MPY32L_L OFS_MPY32L
2701 #define OFS_MPY32L_H OFS_MPY32L+1
2702 #define OFS_MPY32H (0x0012) /* 32-bit operand 1 - multiply - high word */
2703 #define OFS_MPY32H_L OFS_MPY32H
2704 #define OFS_MPY32H_H OFS_MPY32H+1
2705 #define OFS_MPYS32L (0x0014) /* 32-bit operand 1 - signed multiply - low word */
2706 #define OFS_MPYS32L_L OFS_MPYS32L
2707 #define OFS_MPYS32L_H OFS_MPYS32L+1
2708 #define OFS_MPYS32H (0x0016) /* 32-bit operand 1 - signed multiply - high word */
2709 #define OFS_MPYS32H_L OFS_MPYS32H
2710 #define OFS_MPYS32H_H OFS_MPYS32H+1
2711 #define OFS_MAC32L (0x0018) /* 32-bit operand 1 - multiply accumulate - low word */
2712 #define OFS_MAC32L_L OFS_MAC32L
2713 #define OFS_MAC32L_H OFS_MAC32L+1
2714 #define OFS_MAC32H (0x001A) /* 32-bit operand 1 - multiply accumulate - high word */
2715 #define OFS_MAC32H_L OFS_MAC32H
2716 #define OFS_MAC32H_H OFS_MAC32H+1
2717 #define OFS_MACS32L (0x001C) /* 32-bit operand 1 - signed multiply accumulate - low word */
2718 #define OFS_MACS32L_L OFS_MACS32L
2719 #define OFS_MACS32L_H OFS_MACS32L+1
2720 #define OFS_MACS32H (0x001E) /* 32-bit operand 1 - signed multiply accumulate - high word */
2721 #define OFS_MACS32H_L OFS_MACS32H
2722 #define OFS_MACS32H_H OFS_MACS32H+1
2723 #define OFS_OP2L (0x0020) /* 32-bit operand 2 - low word */
2724 #define OFS_OP2L_L OFS_OP2L
2725 #define OFS_OP2L_H OFS_OP2L+1
2726 #define OFS_OP2H (0x0022) /* 32-bit operand 2 - high word */
2727 #define OFS_OP2H_L OFS_OP2H
2728 #define OFS_OP2H_H OFS_OP2H+1
2729 #define OFS_RES0 (0x0024) /* 32x32-bit result 0 - least significant word */
2730 #define OFS_RES0_L OFS_RES0
2731 #define OFS_RES0_H OFS_RES0+1
2732 #define OFS_RES1 (0x0026) /* 32x32-bit result 1 */
2733 #define OFS_RES1_L OFS_RES1
2734 #define OFS_RES1_H OFS_RES1+1
2735 #define OFS_RES2 (0x0028) /* 32x32-bit result 2 */
2736 #define OFS_RES2_L OFS_RES2
2737 #define OFS_RES2_H OFS_RES2+1
2738 #define OFS_RES3 (0x002A) /* 32x32-bit result 3 - most significant word */
2739 #define OFS_RES3_L OFS_RES3
2740 #define OFS_RES3_H OFS_RES3+1
2741 #define OFS_SUMEXT (0x000E)
2742 #define OFS_SUMEXT_L OFS_SUMEXT
2743 #define OFS_SUMEXT_H OFS_SUMEXT+1
2744 #define OFS_MPY32CTL0 (0x002C) /* MPY32 Control Register 0 */
2745 #define OFS_MPY32CTL0_L OFS_MPY32CTL0
2746 #define OFS_MPY32CTL0_H OFS_MPY32CTL0+1
2747 
2748 #define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
2749 #define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
2750 #define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
2751 #define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
2752 #define OP2_B OP2_L /* Operand 2 (Byte Access) */
2753 #define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
2754 #define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
2755 #define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
2756 #define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
2757 #define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
2758 #define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
2759 #define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
2760 #define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
2761 #define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
2762 #define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */
2763 
2764 /* MPY32CTL0 Control Bits */
2765 #define MPYC (0x0001) /* Carry of the multiplier */
2766 //#define RESERVED (0x0002) /* Reserved */
2767 #define MPYFRAC (0x0004) /* Fractional mode */
2768 #define MPYSAT (0x0008) /* Saturation mode */
2769 #define MPYM0 (0x0010) /* Multiplier mode Bit:0 */
2770 #define MPYM1 (0x0020) /* Multiplier mode Bit:1 */
2771 #define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
2772 #define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
2773 #define MPYDLYWRTEN (0x0100) /* Delayed write enable */
2774 #define MPYDLY32 (0x0200) /* Delayed write mode */
2775 
2776 /* MPY32CTL0 Control Bits */
2777 #define MPYC_L (0x0001) /* Carry of the multiplier */
2778 //#define RESERVED (0x0002) /* Reserved */
2779 #define MPYFRAC_L (0x0004) /* Fractional mode */
2780 #define MPYSAT_L (0x0008) /* Saturation mode */
2781 #define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */
2782 #define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */
2783 #define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
2784 #define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
2785 
2786 /* MPY32CTL0 Control Bits */
2787 //#define RESERVED (0x0002) /* Reserved */
2788 #define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */
2789 #define MPYDLY32_H (0x0002) /* Delayed write mode */
2790 
2791 #define MPYM_0 (0x0000) /* Multiplier mode: MPY */
2792 #define MPYM_1 (0x0010) /* Multiplier mode: MPYS */
2793 #define MPYM_2 (0x0020) /* Multiplier mode: MAC */
2794 #define MPYM_3 (0x0030) /* Multiplier mode: MACS */
2795 #define MPYM__MPY (0x0000) /* Multiplier mode: MPY */
2796 #define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */
2797 #define MPYM__MAC (0x0020) /* Multiplier mode: MAC */
2798 #define MPYM__MACS (0x0030) /* Multiplier mode: MACS */
2799 
2800 #endif
2801 /************************************************************
2802 * DIGITAL I/O Port1/2 Pull up / Pull down Resistors
2803 ************************************************************/
2804 #ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
2805 #ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
2806 #ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */
2807 
2808 #define OFS_PAIN (0x0000) /* Port A Input */
2809 #define OFS_PAIN_L OFS_PAIN
2810 #define OFS_PAIN_H OFS_PAIN+1
2811 #define OFS_PAOUT (0x0002) /* Port A Output */
2812 #define OFS_PAOUT_L OFS_PAOUT
2813 #define OFS_PAOUT_H OFS_PAOUT+1
2814 #define OFS_PADIR (0x0004) /* Port A Direction */
2815 #define OFS_PADIR_L OFS_PADIR
2816 #define OFS_PADIR_H OFS_PADIR+1
2817 #define OFS_PAREN (0x0006) /* Port A Resistor Enable */
2818 #define OFS_PAREN_L OFS_PAREN
2819 #define OFS_PAREN_H OFS_PAREN+1
2820 #define OFS_PADS (0x0008) /* Port A Drive Strenght */
2821 #define OFS_PADS_L OFS_PADS
2822 #define OFS_PADS_H OFS_PADS+1
2823 #define OFS_PASEL (0x000A) /* Port A Selection */
2824 #define OFS_PASEL_L OFS_PASEL
2825 #define OFS_PASEL_H OFS_PASEL+1
2826 #define OFS_PAIES (0x0018) /* Port A Interrupt Edge Select */
2827 #define OFS_PAIES_L OFS_PAIES
2828 #define OFS_PAIES_H OFS_PAIES+1
2829 #define OFS_PAIE (0x001A) /* Port A Interrupt Enable */
2830 #define OFS_PAIE_L OFS_PAIE
2831 #define OFS_PAIE_H OFS_PAIE+1
2832 #define OFS_PAIFG (0x001C) /* Port A Interrupt Flag */
2833 #define OFS_PAIFG_L OFS_PAIFG
2834 #define OFS_PAIFG_H OFS_PAIFG+1
2835 
2836 
2837 #define OFS_P1IN (0x0000)
2838 #define OFS_P1OUT (0x0002)
2839 #define OFS_P1DIR (0x0004)
2840 #define OFS_P1REN (0x0006)
2841 #define OFS_P1DS (0x0008)
2842 #define OFS_P1SEL (0x000A)
2843 #define OFS_P1IV (0x000E) /* Port 1 Interrupt Vector Word */
2844 #define OFS_P1IES (0x0018)
2845 #define OFS_P1IE (0x001A)
2846 #define OFS_P1IFG (0x001C)
2847 #define OFS_P2IN (0x0001)
2848 #define OFS_P2OUT (0x0003)
2849 #define OFS_P2DIR (0x0005)
2850 #define OFS_P2REN (0x0007)
2851 #define OFS_P2DS (0x0009)
2852 #define OFS_P2SEL (0x000B)
2853 #define OFS_P2IV (0x001E) /* Port 2 Interrupt Vector Word */
2854 #define OFS_P2IES (0x0019)
2855 #define OFS_P2IE (0x001B)
2856 #define OFS_P2IFG (0x001d)
2857 #define P1IN (PAIN_L) /* Port 1 Input */
2858 #define P1OUT (PAOUT_L) /* Port 1 Output */
2859 #define P1DIR (PADIR_L) /* Port 1 Direction */
2860 #define P1REN (PAREN_L) /* Port 1 Resistor Enable */
2861 #define P1DS (PADS_L) /* Port 1 Drive Strenght */
2862 #define P1SEL (PASEL_L) /* Port 1 Selection */
2863 #define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
2864 #define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
2865 #define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */
2866 
2867 //Definitions for P1IV
2868 #define P1IV_NONE (0x0000) /* No Interrupt pending */
2869 #define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */
2870 #define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */
2871 #define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */
2872 #define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */
2873 #define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */
2874 #define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */
2875 #define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */
2876 #define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */
2877 
2878 #define P2IN (PAIN_H) /* Port 2 Input */
2879 #define P2OUT (PAOUT_H) /* Port 2 Output */
2880 #define P2DIR (PADIR_H) /* Port 2 Direction */
2881 #define P2REN (PAREN_H) /* Port 2 Resistor Enable */
2882 #define P2DS (PADS_H) /* Port 2 Drive Strenght */
2883 #define P2SEL (PASEL_H) /* Port 2 Selection */
2884 #define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
2885 #define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
2886 #define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */
2887 
2888 //Definitions for P2IV
2889 #define P2IV_NONE (0x0000) /* No Interrupt pending */
2890 #define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */
2891 #define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */
2892 #define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */
2893 #define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */
2894 #define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */
2895 #define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */
2896 #define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */
2897 #define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */
2898 
2899 
2900 #endif
2901 #endif
2902 #endif
2903 /************************************************************
2904 * DIGITAL I/O Port3/4 Pull up / Pull down Resistors
2905 ************************************************************/
2906 #ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
2907 #ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */
2908 #ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */
2909 
2910 #define OFS_PBIN (0x0000) /* Port B Input */
2911 #define OFS_PBIN_L OFS_PBIN
2912 #define OFS_PBIN_H OFS_PBIN+1
2913 #define OFS_PBOUT (0x0002) /* Port B Output */
2914 #define OFS_PBOUT_L OFS_PBOUT
2915 #define OFS_PBOUT_H OFS_PBOUT+1
2916 #define OFS_PBDIR (0x0004) /* Port B Direction */
2917 #define OFS_PBDIR_L OFS_PBDIR
2918 #define OFS_PBDIR_H OFS_PBDIR+1
2919 #define OFS_PBREN (0x0006) /* Port B Resistor Enable */
2920 #define OFS_PBREN_L OFS_PBREN
2921 #define OFS_PBREN_H OFS_PBREN+1
2922 #define OFS_PBDS (0x0008) /* Port B Drive Strenght */
2923 #define OFS_PBDS_L OFS_PBDS
2924 #define OFS_PBDS_H OFS_PBDS+1
2925 #define OFS_PBSEL (0x000A) /* Port B Selection */
2926 #define OFS_PBSEL_L OFS_PBSEL
2927 #define OFS_PBSEL_H OFS_PBSEL+1
2928 #define OFS_PBIES (0x0018) /* Port B Interrupt Edge Select */
2929 #define OFS_PBIES_L OFS_PBIES
2930 #define OFS_PBIES_H OFS_PBIES+1
2931 #define OFS_PBIE (0x001A) /* Port B Interrupt Enable */
2932 #define OFS_PBIE_L OFS_PBIE
2933 #define OFS_PBIE_H OFS_PBIE+1
2934 #define OFS_PBIFG (0x001C) /* Port B Interrupt Flag */
2935 #define OFS_PBIFG_L OFS_PBIFG
2936 #define OFS_PBIFG_H OFS_PBIFG+1
2937 
2938 
2939 #define OFS_P3IN (0x0000)
2940 #define OFS_P3OUT (0x0002)
2941 #define OFS_P3DIR (0x0004)
2942 #define OFS_P3REN (0x0006)
2943 #define OFS_P3DS (0x0008)
2944 #define OFS_P3SEL (0x000A)
2945 #define OFS_P3IV (0x000E) /* Port 3 Interrupt Vector Word */
2946 #define OFS_P3IES (0x0018)
2947 #define OFS_P3IE (0x001A)
2948 #define OFS_P3IFG (0x001C)
2949 #define OFS_P4IN (0x0001)
2950 #define OFS_P4OUT (0x0003)
2951 #define OFS_P4DIR (0x0005)
2952 #define OFS_P4REN (0x0007)
2953 #define OFS_P4DS (0x0009)
2954 #define OFS_P4SEL (0x000B)
2955 #define OFS_P4IV (0x001E) /* Port 4 Interrupt Vector Word */
2956 #define OFS_P4IES (0x0019)
2957 #define OFS_P4IE (0x001B)
2958 #define OFS_P4IFG (0x001d)
2959 #define P3IN (PBIN_L) /* Port 3 Input */
2960 #define P3OUT (PBOUT_L) /* Port 3 Output */
2961 #define P3DIR (PBDIR_L) /* Port 3 Direction */
2962 #define P3REN (PBREN_L) /* Port 3 Resistor Enable */
2963 #define P3DS (PBDS_L) /* Port 3 Drive Strenght */
2964 #define P3SEL (PBSEL_L) /* Port 3 Selection */
2965 #define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */
2966 #define P3IE (PBIE_L) /* Port 3 Interrupt Enable */
2967 #define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */
2968 
2969 //Definitions for P3IV
2970 #define P3IV_NONE (0x0000) /* No Interrupt pending */
2971 #define P3IV_P3IFG0 (0x0002) /* P3IV P3IFG.0 */
2972 #define P3IV_P3IFG1 (0x0004) /* P3IV P3IFG.1 */
2973 #define P3IV_P3IFG2 (0x0006) /* P3IV P3IFG.2 */
2974 #define P3IV_P3IFG3 (0x0008) /* P3IV P3IFG.3 */
2975 #define P3IV_P3IFG4 (0x000A) /* P3IV P3IFG.4 */
2976 #define P3IV_P3IFG5 (0x000C) /* P3IV P3IFG.5 */
2977 #define P3IV_P3IFG6 (0x000E) /* P3IV P3IFG.6 */
2978 #define P3IV_P3IFG7 (0x0010) /* P3IV P3IFG.7 */
2979 
2980 #define P4IN (PBIN_H) /* Port 4 Input */
2981 #define P4OUT (PBOUT_H) /* Port 4 Output */
2982 #define P4DIR (PBDIR_H) /* Port 4 Direction */
2983 #define P4REN (PBREN_H) /* Port 4 Resistor Enable */
2984 #define P4DS (PBDS_H) /* Port 4 Drive Strenght */
2985 #define P4SEL (PBSEL_H) /* Port 4 Selection */
2986 #define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */
2987 #define P4IE (PBIE_H) /* Port 4 Interrupt Enable */
2988 #define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */
2989 
2990 //Definitions for P4IV
2991 #define P4IV_NONE (0x0000) /* No Interrupt pending */
2992 #define P4IV_P4IFG0 (0x0002) /* P4IV P4IFG.0 */
2993 #define P4IV_P4IFG1 (0x0004) /* P4IV P4IFG.1 */
2994 #define P4IV_P4IFG2 (0x0006) /* P4IV P4IFG.2 */
2995 #define P4IV_P4IFG3 (0x0008) /* P4IV P4IFG.3 */
2996 #define P4IV_P4IFG4 (0x000A) /* P4IV P4IFG.4 */
2997 #define P4IV_P4IFG5 (0x000C) /* P4IV P4IFG.5 */
2998 #define P4IV_P4IFG6 (0x000E) /* P4IV P4IFG.6 */
2999 #define P4IV_P4IFG7 (0x0010) /* P4IV P4IFG.7 */
3000 
3001 
3002 #endif
3003 #endif
3004 #endif
3005 /************************************************************
3006 * DIGITAL I/O Port5/6 Pull up / Pull down Resistors
3007 ************************************************************/
3008 #ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */
3009 #ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */
3010 #ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */
3011 
3012 #define OFS_PCIN (0x0000) /* Port C Input */
3013 #define OFS_PCIN_L OFS_PCIN
3014 #define OFS_PCIN_H OFS_PCIN+1
3015 #define OFS_PCOUT (0x0002) /* Port C Output */
3016 #define OFS_PCOUT_L OFS_PCOUT
3017 #define OFS_PCOUT_H OFS_PCOUT+1
3018 #define OFS_PCDIR (0x0004) /* Port C Direction */
3019 #define OFS_PCDIR_L OFS_PCDIR
3020 #define OFS_PCDIR_H OFS_PCDIR+1
3021 #define OFS_PCREN (0x0006) /* Port C Resistor Enable */
3022 #define OFS_PCREN_L OFS_PCREN
3023 #define OFS_PCREN_H OFS_PCREN+1
3024 #define OFS_PCDS (0x0008) /* Port C Drive Strenght */
3025 #define OFS_PCDS_L OFS_PCDS
3026 #define OFS_PCDS_H OFS_PCDS+1
3027 #define OFS_PCSEL (0x000A) /* Port C Selection */
3028 #define OFS_PCSEL_L OFS_PCSEL
3029 #define OFS_PCSEL_H OFS_PCSEL+1
3030 #define OFS_PCIES (0x0018) /* Port C Interrupt Edge Select */
3031 #define OFS_PCIES_L OFS_PCIES
3032 #define OFS_PCIES_H OFS_PCIES+1
3033 #define OFS_PCIE (0x001A) /* Port C Interrupt Enable */
3034 #define OFS_PCIE_L OFS_PCIE
3035 #define OFS_PCIE_H OFS_PCIE+1
3036 #define OFS_PCIFG (0x001C) /* Port C Interrupt Flag */
3037 #define OFS_PCIFG_L OFS_PCIFG
3038 #define OFS_PCIFG_H OFS_PCIFG+1
3039 
3040 
3041 #define OFS_P5IN (0x0000)
3042 #define OFS_P5OUT (0x0002)
3043 #define OFS_P5DIR (0x0004)
3044 #define OFS_P5REN (0x0006)
3045 #define OFS_P5DS (0x0008)
3046 #define OFS_P5SEL (0x000A)
3047 #define OFS_P5IV (0x000E) /* Port 5 Interrupt Vector Word */
3048 #define OFS_P5IES (0x0018)
3049 #define OFS_P5IE (0x001A)
3050 #define OFS_P5IFG (0x001C)
3051 #define OFS_P6IN (0x0001)
3052 #define OFS_P6OUT (0x0003)
3053 #define OFS_P6DIR (0x0005)
3054 #define OFS_P6REN (0x0007)
3055 #define OFS_P6DS (0x0009)
3056 #define OFS_P6SEL (0x000B)
3057 #define OFS_P6IV (0x001E) /* Port 6 Interrupt Vector Word */
3058 #define OFS_P6IES (0x0019)
3059 #define OFS_P6IE (0x001B)
3060 #define OFS_P6IFG (0x001d)
3061 #define P5IN (PCIN_L) /* Port 5 Input */
3062 #define P5OUT (PCOUT_L) /* Port 5 Output */
3063 #define P5DIR (PCDIR_L) /* Port 5 Direction */
3064 #define P5REN (PCREN_L) /* Port 5 Resistor Enable */
3065 #define P5DS (PCDS_L) /* Port 5 Drive Strenght */
3066 #define P5SEL (PCSEL_L) /* Port 5 Selection */
3067 #define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */
3068 #define P5IE (PCIE_L) /* Port 5 Interrupt Enable */
3069 #define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */
3070 
3071 //Definitions for P5IV
3072 #define P5IV_NONE (0x0000) /* No Interrupt pending */
3073 #define P5IV_P5IFG0 (0x0002) /* P5IV P5IFG.0 */
3074 #define P5IV_P5IFG1 (0x0004) /* P5IV P5IFG.1 */
3075 #define P5IV_P5IFG2 (0x0006) /* P5IV P5IFG.2 */
3076 #define P5IV_P5IFG3 (0x0008) /* P5IV P5IFG.3 */
3077 #define P5IV_P5IFG4 (0x000A) /* P5IV P5IFG.4 */
3078 #define P5IV_P5IFG5 (0x000C) /* P5IV P5IFG.5 */
3079 #define P5IV_P5IFG6 (0x000E) /* P5IV P5IFG.6 */
3080 #define P5IV_P5IFG7 (0x0010) /* P5IV P5IFG.7 */
3081 
3082 #define P6IN (PCIN_H) /* Port 6 Input */
3083 #define P6OUT (PCOUT_H) /* Port 6 Output */
3084 #define P6DIR (PCDIR_H) /* Port 6 Direction */
3085 #define P6REN (PCREN_H) /* Port 6 Resistor Enable */
3086 #define P6DS (PCDS_H) /* Port 6 Drive Strenght */
3087 #define P6SEL (PCSEL_H) /* Port 6 Selection */
3088 #define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */
3089 #define P6IE (PCIE_H) /* Port 6 Interrupt Enable */
3090 #define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */
3091 
3092 //Definitions for P6IV
3093 #define P6IV_NONE (0x0000) /* No Interrupt pending */
3094 #define P6IV_P6IFG0 (0x0002) /* P6IV P6IFG.0 */
3095 #define P6IV_P6IFG1 (0x0004) /* P6IV P6IFG.1 */
3096 #define P6IV_P6IFG2 (0x0006) /* P6IV P6IFG.2 */
3097 #define P6IV_P6IFG3 (0x0008) /* P6IV P6IFG.3 */
3098 #define P6IV_P6IFG4 (0x000A) /* P6IV P6IFG.4 */
3099 #define P6IV_P6IFG5 (0x000C) /* P6IV P6IFG.5 */
3100 #define P6IV_P6IFG6 (0x000E) /* P6IV P6IFG.6 */
3101 #define P6IV_P6IFG7 (0x0010) /* P6IV P6IFG.7 */
3102 
3103 
3104 #endif
3105 #endif
3106 #endif
3107 /************************************************************
3108 * DIGITAL I/O Port7/8 Pull up / Pull down Resistors
3109 ************************************************************/
3110 #ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */
3111 #ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */
3112 #ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */
3113 
3114 #define OFS_PDIN (0x0000) /* Port D Input */
3115 #define OFS_PDIN_L OFS_PDIN
3116 #define OFS_PDIN_H OFS_PDIN+1
3117 #define OFS_PDOUT (0x0002) /* Port D Output */
3118 #define OFS_PDOUT_L OFS_PDOUT
3119 #define OFS_PDOUT_H OFS_PDOUT+1
3120 #define OFS_PDDIR (0x0004) /* Port D Direction */
3121 #define OFS_PDDIR_L OFS_PDDIR
3122 #define OFS_PDDIR_H OFS_PDDIR+1
3123 #define OFS_PDREN (0x0006) /* Port D Resistor Enable */
3124 #define OFS_PDREN_L OFS_PDREN
3125 #define OFS_PDREN_H OFS_PDREN+1
3126 #define OFS_PDDS (0x0008) /* Port D Drive Strenght */
3127 #define OFS_PDDS_L OFS_PDDS
3128 #define OFS_PDDS_H OFS_PDDS+1
3129 #define OFS_PDSEL (0x000A) /* Port D Selection */
3130 #define OFS_PDSEL_L OFS_PDSEL
3131 #define OFS_PDSEL_H OFS_PDSEL+1
3132 #define OFS_PDIES (0x0018) /* Port D Interrupt Edge Select */
3133 #define OFS_PDIES_L OFS_PDIES
3134 #define OFS_PDIES_H OFS_PDIES+1
3135 #define OFS_PDIE (0x001A) /* Port D Interrupt Enable */
3136 #define OFS_PDIE_L OFS_PDIE
3137 #define OFS_PDIE_H OFS_PDIE+1
3138 #define OFS_PDIFG (0x001C) /* Port D Interrupt Flag */
3139 #define OFS_PDIFG_L OFS_PDIFG
3140 #define OFS_PDIFG_H OFS_PDIFG+1
3141 
3142 
3143 #define OFS_P7IN (0x0000)
3144 #define OFS_P7OUT (0x0002)
3145 #define OFS_P7DIR (0x0004)
3146 #define OFS_P7REN (0x0006)
3147 #define OFS_P7DS (0x0008)
3148 #define OFS_P7SEL (0x000A)
3149 #define OFS_P7IV (0x000E) /* Port 7 Interrupt Vector Word */
3150 #define OFS_P7IES (0x0018)
3151 #define OFS_P7IE (0x001A)
3152 #define OFS_P7IFG (0x001C)
3153 #define OFS_P8IN (0x0001)
3154 #define OFS_P8OUT (0x0003)
3155 #define OFS_P8DIR (0x0005)
3156 #define OFS_P8REN (0x0007)
3157 #define OFS_P8DS (0x0009)
3158 #define OFS_P8SEL (0x000B)
3159 #define OFS_P8IV (0x001E) /* Port 8 Interrupt Vector Word */
3160 #define OFS_P8IES (0x0019)
3161 #define OFS_P8IE (0x001B)
3162 #define OFS_P8IFG (0x001d)
3163 #define P7IN (PDIN_L) /* Port 7 Input */
3164 #define P7OUT (PDOUT_L) /* Port 7 Output */
3165 #define P7DIR (PDDIR_L) /* Port 7 Direction */
3166 #define P7REN (PDREN_L) /* Port 7 Resistor Enable */
3167 #define P7DS (PDDS_L) /* Port 7 Drive Strenght */
3168 #define P7SEL (PDSEL_L) /* Port 7 Selection */
3169 #define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */
3170 #define P7IE (PDIE_L) /* Port 7 Interrupt Enable */
3171 #define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */
3172 
3173 //Definitions for P7IV
3174 #define P7IV_NONE (0x0000) /* No Interrupt pending */
3175 #define P7IV_P7IFG0 (0x0002) /* P7IV P7IFG.0 */
3176 #define P7IV_P7IFG1 (0x0004) /* P7IV P7IFG.1 */
3177 #define P7IV_P7IFG2 (0x0006) /* P7IV P7IFG.2 */
3178 #define P7IV_P7IFG3 (0x0008) /* P7IV P7IFG.3 */
3179 #define P7IV_P7IFG4 (0x000A) /* P7IV P7IFG.4 */
3180 #define P7IV_P7IFG5 (0x000C) /* P7IV P7IFG.5 */
3181 #define P7IV_P7IFG6 (0x000E) /* P7IV P7IFG.6 */
3182 #define P7IV_P7IFG7 (0x0010) /* P7IV P7IFG.7 */
3183 
3184 #define P8IN (PDIN_H) /* Port 8 Input */
3185 #define P8OUT (PDOUT_H) /* Port 8 Output */
3186 #define P8DIR (PDDIR_H) /* Port 8 Direction */
3187 #define P8REN (PDREN_H) /* Port 8 Resistor Enable */
3188 #define P8DS (PDDS_H) /* Port 8 Drive Strenght */
3189 #define P8SEL (PDSEL_H) /* Port 8 Selection */
3190 #define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */
3191 #define P8IE (PDIE_H) /* Port 8 Interrupt Enable */
3192 #define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */
3193 
3194 //Definitions for P8IV
3195 #define P8IV_NONE (0x0000) /* No Interrupt pending */
3196 #define P8IV_P8IFG0 (0x0002) /* P8IV P8IFG.0 */
3197 #define P8IV_P8IFG1 (0x0004) /* P8IV P8IFG.1 */
3198 #define P8IV_P8IFG2 (0x0006) /* P8IV P8IFG.2 */
3199 #define P8IV_P8IFG3 (0x0008) /* P8IV P8IFG.3 */
3200 #define P8IV_P8IFG4 (0x000A) /* P8IV P8IFG.4 */
3201 #define P8IV_P8IFG5 (0x000C) /* P8IV P8IFG.5 */
3202 #define P8IV_P8IFG6 (0x000E) /* P8IV P8IFG.6 */
3203 #define P8IV_P8IFG7 (0x0010) /* P8IV P8IFG.7 */
3204 
3205 
3206 #endif
3207 #endif
3208 #endif
3209 /************************************************************
3210 * DIGITAL I/O Port9/10 Pull up / Pull down Resistors
3211 ************************************************************/
3212 #ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */
3213 #ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */
3214 #ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */
3215 
3216 #define OFS_PEIN (0x0000) /* Port E Input */
3217 #define OFS_PEIN_L OFS_PEIN
3218 #define OFS_PEIN_H OFS_PEIN+1
3219 #define OFS_PEOUT (0x0002) /* Port E Output */
3220 #define OFS_PEOUT_L OFS_PEOUT
3221 #define OFS_PEOUT_H OFS_PEOUT+1
3222 #define OFS_PEDIR (0x0004) /* Port E Direction */
3223 #define OFS_PEDIR_L OFS_PEDIR
3224 #define OFS_PEDIR_H OFS_PEDIR+1
3225 #define OFS_PEREN (0x0006) /* Port E Resistor Enable */
3226 #define OFS_PEREN_L OFS_PEREN
3227 #define OFS_PEREN_H OFS_PEREN+1
3228 #define OFS_PEDS (0x0008) /* Port E Drive Strenght */
3229 #define OFS_PEDS_L OFS_PEDS
3230 #define OFS_PEDS_H OFS_PEDS+1
3231 #define OFS_PESEL (0x000A) /* Port E Selection */
3232 #define OFS_PESEL_L OFS_PESEL
3233 #define OFS_PESEL_H OFS_PESEL+1
3234 #define OFS_PEIES (0x0018) /* Port E Interrupt Edge Select */
3235 #define OFS_PEIES_L OFS_PEIES
3236 #define OFS_PEIES_H OFS_PEIES+1
3237 #define OFS_PEIE (0x001A) /* Port E Interrupt Enable */
3238 #define OFS_PEIE_L OFS_PEIE
3239 #define OFS_PEIE_H OFS_PEIE+1
3240 #define OFS_PEIFG (0x001C) /* Port E Interrupt Flag */
3241 #define OFS_PEIFG_L OFS_PEIFG
3242 #define OFS_PEIFG_H OFS_PEIFG+1
3243 
3244 
3245 #define OFS_P9IN (0x0000)
3246 #define OFS_P9OUT (0x0002)
3247 #define OFS_P9DIR (0x0004)
3248 #define OFS_P9REN (0x0006)
3249 #define OFS_P9DS (0x0008)
3250 #define OFS_P9SEL (0x000A)
3251 #define OFS_P9IV (0x000E) /* Port 9 Interrupt Vector Word */
3252 #define OFS_P9IES (0x0018)
3253 #define OFS_P9IE (0x001A)
3254 #define OFS_P9IFG (0x001C)
3255 #define OFS_P10IN (0x0001)
3256 #define OFS_P10OUT (0x0003)
3257 #define OFS_P10DIR (0x0005)
3258 #define OFS_P10REN (0x0007)
3259 #define OFS_P10DS (0x0009)
3260 #define OFS_P10SEL (0x000B)
3261 #define OFS_P10IV (0x001E) /* Port 10 Interrupt Vector Word */
3262 #define OFS_P10IES (0x0019)
3263 #define OFS_P10IE (0x001B)
3264 #define OFS_P10IFG (0x001d)
3265 #define P9IN (PEIN_L) /* Port 9 Input */
3266 #define P9OUT (PEOUT_L) /* Port 9 Output */
3267 #define P9DIR (PEDIR_L) /* Port 9 Direction */
3268 #define P9REN (PEREN_L) /* Port 9 Resistor Enable */
3269 #define P9DS (PEDS_L) /* Port 9 Drive Strenght */
3270 #define P9SEL (PESEL_L) /* Port 9 Selection */
3271 #define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */
3272 #define P9IE (PEIE_L) /* Port 9 Interrupt Enable */
3273 #define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */
3274 
3275 //Definitions for P9IV
3276 #define P9IV_NONE (0x0000) /* No Interrupt pending */
3277 #define P9IV_P9IFG0 (0x0002) /* P9IV P9IFG.0 */
3278 #define P9IV_P9IFG1 (0x0004) /* P9IV P9IFG.1 */
3279 #define P9IV_P9IFG2 (0x0006) /* P9IV P9IFG.2 */
3280 #define P9IV_P9IFG3 (0x0008) /* P9IV P9IFG.3 */
3281 #define P9IV_P9IFG4 (0x000A) /* P9IV P9IFG.4 */
3282 #define P9IV_P9IFG5 (0x000C) /* P9IV P9IFG.5 */
3283 #define P9IV_P9IFG6 (0x000E) /* P9IV P9IFG.6 */
3284 #define P9IV_P9IFG7 (0x0010) /* P9IV P9IFG.7 */
3285 
3286 #define P10IN (PEIN_H) /* Port 10 Input */
3287 #define P10OUT (PEOUT_H) /* Port 10 Output */
3288 #define P10DIR (PEDIR_H) /* Port 10 Direction */
3289 #define P10REN (PEREN_H) /* Port 10 Resistor Enable */
3290 #define P10DS (PEDS_H) /* Port 10 Drive Strenght */
3291 #define P10SEL (PESEL_H) /* Port 10 Selection */
3292 #define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */
3293 #define P10IE (PEIE_H) /* Port 10 Interrupt Enable */
3294 #define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */
3295 
3296 //Definitions for P10IV
3297 #define P10IV_NONE (0x0000) /* No Interrupt pending */
3298 #define P10IV_P10IFG0 (0x0002) /* P10IV P10IFG.0 */
3299 #define P10IV_P10IFG1 (0x0004) /* P10IV P10IFG.1 */
3300 #define P10IV_P10IFG2 (0x0006) /* P10IV P10IFG.2 */
3301 #define P10IV_P10IFG3 (0x0008) /* P10IV P10IFG.3 */
3302 #define P10IV_P10IFG4 (0x000A) /* P10IV P10IFG.4 */
3303 #define P10IV_P10IFG5 (0x000C) /* P10IV P10IFG.5 */
3304 #define P10IV_P10IFG6 (0x000E) /* P10IV P10IFG.6 */
3305 #define P10IV_P10IFG7 (0x0010) /* P10IV P10IFG.7 */
3306 
3307 
3308 #endif
3309 #endif
3310 #endif
3311 /************************************************************
3312 * DIGITAL I/O Port11 Pull up / Pull down Resistors
3313 ************************************************************/
3314 #ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */
3315 #ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */
3316 
3317 #define OFS_PFIN (0x0000) /* Port F Input */
3318 #define OFS_PFIN_L OFS_PFIN
3319 #define OFS_PFIN_H OFS_PFIN+1
3320 #define OFS_PFOUT (0x0002) /* Port F Output */
3321 #define OFS_PFOUT_L OFS_PFOUT
3322 #define OFS_PFOUT_H OFS_PFOUT+1
3323 #define OFS_PFDIR (0x0004) /* Port F Direction */
3324 #define OFS_PFDIR_L OFS_PFDIR
3325 #define OFS_PFDIR_H OFS_PFDIR+1
3326 #define OFS_PFREN (0x0006) /* Port F Resistor Enable */
3327 #define OFS_PFREN_L OFS_PFREN
3328 #define OFS_PFREN_H OFS_PFREN+1
3329 #define OFS_PFDS (0x0008) /* Port F Drive Strenght */
3330 #define OFS_PFDS_L OFS_PFDS
3331 #define OFS_PFDS_H OFS_PFDS+1
3332 #define OFS_PFSEL (0x000A) /* Port F Selection */
3333 #define OFS_PFSEL_L OFS_PFSEL
3334 #define OFS_PFSEL_H OFS_PFSEL+1
3335 #define OFS_PFIES (0x0018) /* Port F Interrupt Edge Select */
3336 #define OFS_PFIES_L OFS_PFIES
3337 #define OFS_PFIES_H OFS_PFIES+1
3338 #define OFS_PFIE (0x001A) /* Port F Interrupt Enable */
3339 #define OFS_PFIE_L OFS_PFIE
3340 #define OFS_PFIE_H OFS_PFIE+1
3341 #define OFS_PFIFG (0x001C) /* Port F Interrupt Flag */
3342 #define OFS_PFIFG_L OFS_PFIFG
3343 #define OFS_PFIFG_H OFS_PFIFG+1
3344 
3345 
3346 #define OFS_P11IN (0x0000)
3347 #define OFS_P11OUT (0x0002)
3348 #define OFS_P11DIR (0x0004)
3349 #define OFS_P11REN (0x0006)
3350 #define OFS_P11DS (0x0008)
3351 #define OFS_P11SEL (0x000A)
3352 #define OFS_P11IV (0x000E) /* Port 11 Interrupt Vector Word */
3353 #define OFS_P11IES (0x0018)
3354 #define OFS_P11IE (0x001A)
3355 #define OFS_P11IFG (0x001C)
3356 #define P11IN (PFIN_L) /* Port 11 Input */
3357 #define P11OUT (PFOUT_L) /* Port 11 Output */
3358 #define P11DIR (PFDIR_L) /* Port 11 Direction */
3359 #define P11REN (PFREN_L) /* Port 11 Resistor Enable */
3360 #define P11DS (PFDS_L) /* Port 11 Drive Strenght */
3361 #define P11SEL (PFSEL_L) /* Port 11 Selection */
3362 
3363 #define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */
3364 #define P11IE (PFIE_L) /* Port 11 Interrupt Enable */
3365 #define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */
3366 
3367 //Definitions for P11IV
3368 #define P11IV_NONE (0x0000) /* No Interrupt pending */
3369 #define P11IV_P11IFG0 (0x0002) /* P11IV P11IFG.0 */
3370 #define P11IV_P11IFG1 (0x0004) /* P11IV P11IFG.1 */
3371 #define P11IV_P11IFG2 (0x0006) /* P11IV P11IFG.2 */
3372 #define P11IV_P11IFG3 (0x0008) /* P11IV P11IFG.3 */
3373 #define P11IV_P11IFG4 (0x000A) /* P11IV P11IFG.4 */
3374 #define P11IV_P11IFG5 (0x000C) /* P11IV P11IFG.5 */
3375 #define P11IV_P11IFG6 (0x000E) /* P11IV P11IFG.6 */
3376 #define P11IV_P11IFG7 (0x0010) /* P11IV P11IFG.7 */
3377 
3378 
3379 #endif
3380 #endif
3381 /************************************************************
3382 * DIGITAL I/O PortJ Pull up / Pull down Resistors
3383 ************************************************************/
3384 #ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */
3385 
3386 #define OFS_PJIN (0x0000) /* Port J Input */
3387 #define OFS_PJIN_L OFS_PJIN
3388 #define OFS_PJIN_H OFS_PJIN+1
3389 #define OFS_PJOUT (0x0002) /* Port J Output */
3390 #define OFS_PJOUT_L OFS_PJOUT
3391 #define OFS_PJOUT_H OFS_PJOUT+1
3392 #define OFS_PJDIR (0x0004) /* Port J Direction */
3393 #define OFS_PJDIR_L OFS_PJDIR
3394 #define OFS_PJDIR_H OFS_PJDIR+1
3395 #define OFS_PJREN (0x0006) /* Port J Resistor Enable */
3396 #define OFS_PJREN_L OFS_PJREN
3397 #define OFS_PJREN_H OFS_PJREN+1
3398 #define OFS_PJDS (0x0008) /* Port J Drive Strenght */
3399 #define OFS_PJDS_L OFS_PJDS
3400 #define OFS_PJDS_H OFS_PJDS+1
3401 #define OFS_PJSEL (0x000A) /* Port J Selection */
3402 #define OFS_PJSEL_L OFS_PJSEL
3403 #define OFS_PJSEL_H OFS_PJSEL+1
3404 
3405 #endif
3406 /************************************************************
3407 * PORT MAPPING CONTROLLER
3408 ************************************************************/
3409 #ifdef __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */
3410 
3411 #define OFS_PMAPKEYID (0x0000) /* Port Mapping Key register */
3412 #define OFS_PMAPKEYID_L OFS_PMAPKEYID
3413 #define OFS_PMAPKEYID_H OFS_PMAPKEYID+1
3414 #define OFS_PMAPCTL (0x0002) /* Port Mapping control register */
3415 #define OFS_PMAPCTL_L OFS_PMAPCTL
3416 #define OFS_PMAPCTL_H OFS_PMAPCTL+1
3417 
3418 #define PMAPKEY (0x2D52) /* Port Mapping Key */
3419 #define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */
3420 #define PMAPPW (0x2D52) /* Legacy Definition: Port Mapping Password */
3421 
3422 /* PMAPCTL Control Bits */
3423 #define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */
3424 #define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */
3425 
3426 /* PMAPCTL Control Bits */
3427 #define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */
3428 #define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */
3429 
3430 #endif
3431 /************************************************************
3432 * PORT 2 MAPPING CONTROLLER
3433 ************************************************************/
3434 #ifdef __MSP430_HAS_PORT2_MAPPING__ /* Definition to show that Module is available */
3435 
3436 #define OFS_P2MAP01 (0x0000) /* Port P2.0/1 mapping register */
3437 #define OFS_P2MAP01_L OFS_P2MAP01
3438 #define OFS_P2MAP01_H OFS_P2MAP01+1
3439 #define OFS_P2MAP23 (0x0002) /* Port P2.2/3 mapping register */
3440 #define OFS_P2MAP23_L OFS_P2MAP23
3441 #define OFS_P2MAP23_H OFS_P2MAP23+1
3442 #define OFS_P2MAP45 (0x0004) /* Port P2.4/5 mapping register */
3443 #define OFS_P2MAP45_L OFS_P2MAP45
3444 #define OFS_P2MAP45_H OFS_P2MAP45+1
3445 #define OFS_P2MAP67 (0x0006) /* Port P2.6/7 mapping register */
3446 #define OFS_P2MAP67_L OFS_P2MAP67
3447 #define OFS_P2MAP67_H OFS_P2MAP67+1
3448 #define OFS_P2MAP0 (0x0000)
3449 #define OFS_P2MAP1 (0x0001)
3450 #define OFS_P2MAP2 (0x0002)
3451 #define OFS_P2MAP3 (0x0003)
3452 #define OFS_P2MAP4 (0x0004)
3453 #define OFS_P2MAP5 (0x0005)
3454 #define OFS_P2MAP6 (0x0006)
3455 #define OFS_P2MAP7 (0x0007)
3456 
3457 #define P2MAP0 P2MAP01_L /* Port P2.0 mapping register */
3458 #define P2MAP1 P2MAP01_H /* Port P2.1 mapping register */
3459 #define P2MAP2 P2MAP23_L /* Port P2.2 mapping register */
3460 #define P2MAP3 P2MAP23_H /* Port P2.3 mapping register */
3461 #define P2MAP4 P2MAP45_L /* Port P2.4 mapping register */
3462 #define P2MAP5 P2MAP45_H /* Port P2.5 mapping register */
3463 #define P2MAP6 P2MAP67_L /* Port P2.6 mapping register */
3464 #define P2MAP7 P2MAP67_H /* Port P2.7 mapping register */
3465 
3466 #endif
3467 /************************************************************
3468 * PMM - Power Management System
3469 ************************************************************/
3470 #ifdef __MSP430_HAS_PMM__ /* Definition to show that Module is available */
3471 
3472 #define OFS_PMMCTL0 (0x0000) /* PMM Control 0 */
3473 #define OFS_PMMCTL0_L OFS_PMMCTL0
3474 #define OFS_PMMCTL0_H OFS_PMMCTL0+1
3475 #define OFS_PMMCTL1 (0x0002) /* PMM Control 1 */
3476 #define OFS_PMMCTL1_L OFS_PMMCTL1
3477 #define OFS_PMMCTL1_H OFS_PMMCTL1+1
3478 #define OFS_SVSMHCTL (0x0004) /* SVS and SVM high side control register */
3479 #define OFS_SVSMHCTL_L OFS_SVSMHCTL
3480 #define OFS_SVSMHCTL_H OFS_SVSMHCTL+1
3481 #define OFS_SVSMLCTL (0x0006) /* SVS and SVM low side control register */
3482 #define OFS_SVSMLCTL_L OFS_SVSMLCTL
3483 #define OFS_SVSMLCTL_H OFS_SVSMLCTL+1
3484 #define OFS_SVSMIO (0x0008) /* SVSIN and SVSOUT control register */
3485 #define OFS_SVSMIO_L OFS_SVSMIO
3486 #define OFS_SVSMIO_H OFS_SVSMIO+1
3487 #define OFS_PMMIFG (0x000C) /* PMM Interrupt Flag */
3488 #define OFS_PMMIFG_L OFS_PMMIFG
3489 #define OFS_PMMIFG_H OFS_PMMIFG+1
3490 #define OFS_PMMRIE (0x000E) /* PMM and RESET Interrupt Enable */
3491 #define OFS_PMMRIE_L OFS_PMMRIE
3492 #define OFS_PMMRIE_H OFS_PMMRIE+1
3493 
3494 #define PMMPW (0xA500) /* PMM Register Write Password */
3495 #define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */
3496 
3497 /* PMMCTL0 Control Bits */
3498 #define PMMCOREV0 (0x0001) /* PMM Core Voltage Bit: 0 */
3499 #define PMMCOREV1 (0x0002) /* PMM Core Voltage Bit: 1 */
3500 #define PMMSWBOR (0x0004) /* PMM Software BOR */
3501 #define PMMSWPOR (0x0008) /* PMM Software POR */
3502 #define PMMREGOFF (0x0010) /* PMM Turn Regulator off */
3503 #define PMMHPMRE (0x0080) /* PMM Global High Power Module Request Enable */
3504 
3505 /* PMMCTL0 Control Bits */
3506 #define PMMCOREV0_L (0x0001) /* PMM Core Voltage Bit: 0 */
3507 #define PMMCOREV1_L (0x0002) /* PMM Core Voltage Bit: 1 */
3508 #define PMMSWBOR_L (0x0004) /* PMM Software BOR */
3509 #define PMMSWPOR_L (0x0008) /* PMM Software POR */
3510 #define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */
3511 #define PMMHPMRE_L (0x0080) /* PMM Global High Power Module Request Enable */
3512 
3513 #define PMMCOREV_0 (0x0000) /* PMM Core Voltage 0 (1.35V) */
3514 #define PMMCOREV_1 (0x0001) /* PMM Core Voltage 1 (1.55V) */
3515 #define PMMCOREV_2 (0x0002) /* PMM Core Voltage 2 (1.75V) */
3516 #define PMMCOREV_3 (0x0003) /* PMM Core Voltage 3 (1.85V) */
3517 
3518 /* PMMCTL1 Control Bits */
3519 #define PMMREFMD (0x0001) /* PMM Reference Mode */
3520 #define PMMCMD0 (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */
3521 #define PMMCMD1 (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */
3522 
3523 /* PMMCTL1 Control Bits */
3524 #define PMMREFMD_L (0x0001) /* PMM Reference Mode */
3525 #define PMMCMD0_L (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */
3526 #define PMMCMD1_L (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */
3527 
3528 /* SVSMHCTL Control Bits */
3529 #define SVSMHRRL0 (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
3530 #define SVSMHRRL1 (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
3531 #define SVSMHRRL2 (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
3532 #define SVSMHDLYST (0x0008) /* SVS and SVM high side delay status */
3533 #define SVSHMD (0x0010) /* SVS high side mode */
3534 #define SVSMHEVM (0x0040) /* SVS and SVM high side event mask */
3535 #define SVSMHACE (0x0080) /* SVS and SVM high side auto control enable */
3536 #define SVSHRVL0 (0x0100) /* SVS high side reset voltage level Bit: 0 */
3537 #define SVSHRVL1 (0x0200) /* SVS high side reset voltage level Bit: 1 */
3538 #define SVSHE (0x0400) /* SVS high side enable */
3539 #define SVSHFP (0x0800) /* SVS high side full performace mode */
3540 #define SVMHOVPE (0x1000) /* SVM high side over-voltage enable */
3541 #define SVMHE (0x4000) /* SVM high side enable */
3542 #define SVMHFP (0x8000) /* SVM high side full performace mode */
3543 
3544 /* SVSMHCTL Control Bits */
3545 #define SVSMHRRL0_L (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
3546 #define SVSMHRRL1_L (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
3547 #define SVSMHRRL2_L (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
3548 #define SVSMHDLYST_L (0x0008) /* SVS and SVM high side delay status */
3549 #define SVSHMD_L (0x0010) /* SVS high side mode */
3550 #define SVSMHEVM_L (0x0040) /* SVS and SVM high side event mask */
3551 #define SVSMHACE_L (0x0080) /* SVS and SVM high side auto control enable */
3552 
3553 /* SVSMHCTL Control Bits */
3554 #define SVSHRVL0_H (0x0001) /* SVS high side reset voltage level Bit: 0 */
3555 #define SVSHRVL1_H (0x0002) /* SVS high side reset voltage level Bit: 1 */
3556 #define SVSHE_H (0x0004) /* SVS high side enable */
3557 #define SVSHFP_H (0x0008) /* SVS high side full performace mode */
3558 #define SVMHOVPE_H (0x0010) /* SVM high side over-voltage enable */
3559 #define SVMHE_H (0x0040) /* SVM high side enable */
3560 #define SVMHFP_H (0x0080) /* SVM high side full performace mode */
3561 
3562 #define SVSMHRRL_0 (0x0000) /* SVS and SVM high side Reset Release Voltage Level 0 */
3563 #define SVSMHRRL_1 (0x0001) /* SVS and SVM high side Reset Release Voltage Level 1 */
3564 #define SVSMHRRL_2 (0x0002) /* SVS and SVM high side Reset Release Voltage Level 2 */
3565 #define SVSMHRRL_3 (0x0003) /* SVS and SVM high side Reset Release Voltage Level 3 */
3566 #define SVSMHRRL_4 (0x0004) /* SVS and SVM high side Reset Release Voltage Level 4 */
3567 #define SVSMHRRL_5 (0x0005) /* SVS and SVM high side Reset Release Voltage Level 5 */
3568 #define SVSMHRRL_6 (0x0006) /* SVS and SVM high side Reset Release Voltage Level 6 */
3569 #define SVSMHRRL_7 (0x0007) /* SVS and SVM high side Reset Release Voltage Level 7 */
3570 
3571 #define SVSHRVL_0 (0x0000) /* SVS high side Reset Release Voltage Level 0 */
3572 #define SVSHRVL_1 (0x0100) /* SVS high side Reset Release Voltage Level 1 */
3573 #define SVSHRVL_2 (0x0200) /* SVS high side Reset Release Voltage Level 2 */
3574 #define SVSHRVL_3 (0x0300) /* SVS high side Reset Release Voltage Level 3 */
3575 
3576 /* SVSMLCTL Control Bits */
3577 #define SVSMLRRL0 (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
3578 #define SVSMLRRL1 (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
3579 #define SVSMLRRL2 (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
3580 #define SVSMLDLYST (0x0008) /* SVS and SVM low side delay status */
3581 #define SVSLMD (0x0010) /* SVS low side mode */
3582 #define SVSMLEVM (0x0040) /* SVS and SVM low side event mask */
3583 #define SVSMLACE (0x0080) /* SVS and SVM low side auto control enable */
3584 #define SVSLRVL0 (0x0100) /* SVS low side reset voltage level Bit: 0 */
3585 #define SVSLRVL1 (0x0200) /* SVS low side reset voltage level Bit: 1 */
3586 #define SVSLE (0x0400) /* SVS low side enable */
3587 #define SVSLFP (0x0800) /* SVS low side full performace mode */
3588 #define SVMLOVPE (0x1000) /* SVM low side over-voltage enable */
3589 #define SVMLE (0x4000) /* SVM low side enable */
3590 #define SVMLFP (0x8000) /* SVM low side full performace mode */
3591 
3592 /* SVSMLCTL Control Bits */
3593 #define SVSMLRRL0_L (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
3594 #define SVSMLRRL1_L (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
3595 #define SVSMLRRL2_L (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
3596 #define SVSMLDLYST_L (0x0008) /* SVS and SVM low side delay status */
3597 #define SVSLMD_L (0x0010) /* SVS low side mode */
3598 #define SVSMLEVM_L (0x0040) /* SVS and SVM low side event mask */
3599 #define SVSMLACE_L (0x0080) /* SVS and SVM low side auto control enable */
3600 
3601 /* SVSMLCTL Control Bits */
3602 #define SVSLRVL0_H (0x0001) /* SVS low side reset voltage level Bit: 0 */
3603 #define SVSLRVL1_H (0x0002) /* SVS low side reset voltage level Bit: 1 */
3604 #define SVSLE_H (0x0004) /* SVS low side enable */
3605 #define SVSLFP_H (0x0008) /* SVS low side full performace mode */
3606 #define SVMLOVPE_H (0x0010) /* SVM low side over-voltage enable */
3607 #define SVMLE_H (0x0040) /* SVM low side enable */
3608 #define SVMLFP_H (0x0080) /* SVM low side full performace mode */
3609 
3610 #define SVSMLRRL_0 (0x0000) /* SVS and SVM low side Reset Release Voltage Level 0 */
3611 #define SVSMLRRL_1 (0x0001) /* SVS and SVM low side Reset Release Voltage Level 1 */
3612 #define SVSMLRRL_2 (0x0002) /* SVS and SVM low side Reset Release Voltage Level 2 */
3613 #define SVSMLRRL_3 (0x0003) /* SVS and SVM low side Reset Release Voltage Level 3 */
3614 #define SVSMLRRL_4 (0x0004) /* SVS and SVM low side Reset Release Voltage Level 4 */
3615 #define SVSMLRRL_5 (0x0005) /* SVS and SVM low side Reset Release Voltage Level 5 */
3616 #define SVSMLRRL_6 (0x0006) /* SVS and SVM low side Reset Release Voltage Level 6 */
3617 #define SVSMLRRL_7 (0x0007) /* SVS and SVM low side Reset Release Voltage Level 7 */
3618 
3619 #define SVSLRVL_0 (0x0000) /* SVS low side Reset Release Voltage Level 0 */
3620 #define SVSLRVL_1 (0x0100) /* SVS low side Reset Release Voltage Level 1 */
3621 #define SVSLRVL_2 (0x0200) /* SVS low side Reset Release Voltage Level 2 */
3622 #define SVSLRVL_3 (0x0300) /* SVS low side Reset Release Voltage Level 3 */
3623 
3624 /* SVSMIO Control Bits */
3625 #define SVMLOE (0x0008) /* SVM low side output enable */
3626 #define SVMLVLROE (0x0010) /* SVM low side voltage level reached output enable */
3627 #define SVMOUTPOL (0x0020) /* SVMOUT pin polarity */
3628 #define SVMHOE (0x0800) /* SVM high side output enable */
3629 #define SVMHVLROE (0x1000) /* SVM high side voltage level reached output enable */
3630 
3631 /* SVSMIO Control Bits */
3632 #define SVMLOE_L (0x0008) /* SVM low side output enable */
3633 #define SVMLVLROE_L (0x0010) /* SVM low side voltage level reached output enable */
3634 #define SVMOUTPOL_L (0x0020) /* SVMOUT pin polarity */
3635 
3636 /* SVSMIO Control Bits */
3637 #define SVMHOE_H (0x0008) /* SVM high side output enable */
3638 #define SVMHVLROE_H (0x0010) /* SVM high side voltage level reached output enable */
3639 
3640 /* PMMIFG Control Bits */
3641 #define SVSMLDLYIFG (0x0001) /* SVS and SVM low side Delay expired interrupt flag */
3642 #define SVMLIFG (0x0002) /* SVM low side interrupt flag */
3643 #define SVMLVLRIFG (0x0004) /* SVM low side Voltage Level Reached interrupt flag */
3644 #define SVSMHDLYIFG (0x0010) /* SVS and SVM high side Delay expired interrupt flag */
3645 #define SVMHIFG (0x0020) /* SVM high side interrupt flag */
3646 #define SVMHVLRIFG (0x0040) /* SVM high side Voltage Level Reached interrupt flag */
3647 #define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */
3648 #define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */
3649 #define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */
3650 #define SVSHIFG (0x1000) /* SVS low side interrupt flag */
3651 #define SVSLIFG (0x2000) /* SVS high side interrupt flag */
3652 #define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */
3653 
3654 /* PMMIFG Control Bits */
3655 #define SVSMLDLYIFG_L (0x0001) /* SVS and SVM low side Delay expired interrupt flag */
3656 #define SVMLIFG_L (0x0002) /* SVM low side interrupt flag */
3657 #define SVMLVLRIFG_L (0x0004) /* SVM low side Voltage Level Reached interrupt flag */
3658 #define SVSMHDLYIFG_L (0x0010) /* SVS and SVM high side Delay expired interrupt flag */
3659 #define SVMHIFG_L (0x0020) /* SVM high side interrupt flag */
3660 #define SVMHVLRIFG_L (0x0040) /* SVM high side Voltage Level Reached interrupt flag */
3661 
3662 /* PMMIFG Control Bits */
3663 #define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */
3664 #define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */
3665 #define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */
3666 #define SVSHIFG_H (0x0010) /* SVS low side interrupt flag */
3667 #define SVSLIFG_H (0x0020) /* SVS high side interrupt flag */
3668 #define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */
3669 
3670 #define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */
3671 
3672 /* PMMIE and RESET Control Bits */
3673 #define SVSMLDLYIE (0x0001) /* SVS and SVM low side Delay expired interrupt enable */
3674 #define SVMLIE (0x0002) /* SVM low side interrupt enable */
3675 #define SVMLVLRIE (0x0004) /* SVM low side Voltage Level Reached interrupt enable */
3676 #define SVSMHDLYIE (0x0010) /* SVS and SVM high side Delay expired interrupt enable */
3677 #define SVMHIE (0x0020) /* SVM high side interrupt enable */
3678 #define SVMHVLRIE (0x0040) /* SVM high side Voltage Level Reached interrupt enable */
3679 #define SVSLPE (0x0100) /* SVS low side POR enable */
3680 #define SVMLVLRPE (0x0200) /* SVM low side Voltage Level reached POR enable */
3681 #define SVSHPE (0x1000) /* SVS high side POR enable */
3682 #define SVMHVLRPE (0x2000) /* SVM high side Voltage Level reached POR enable */
3683 
3684 /* PMMIE and RESET Control Bits */
3685 #define SVSMLDLYIE_L (0x0001) /* SVS and SVM low side Delay expired interrupt enable */
3686 #define SVMLIE_L (0x0002) /* SVM low side interrupt enable */
3687 #define SVMLVLRIE_L (0x0004) /* SVM low side Voltage Level Reached interrupt enable */
3688 #define SVSMHDLYIE_L (0x0010) /* SVS and SVM high side Delay expired interrupt enable */
3689 #define SVMHIE_L (0x0020) /* SVM high side interrupt enable */
3690 #define SVMHVLRIE_L (0x0040) /* SVM high side Voltage Level Reached interrupt enable */
3691 
3692 /* PMMIE and RESET Control Bits */
3693 #define SVSLPE_H (0x0001) /* SVS low side POR enable */
3694 #define SVMLVLRPE_H (0x0002) /* SVM low side Voltage Level reached POR enable */
3695 #define SVSHPE_H (0x0010) /* SVS high side POR enable */
3696 #define SVMHVLRPE_H (0x0020) /* SVM high side Voltage Level reached POR enable */
3697 
3698 #endif
3699 /************************************************************
3700 * Port U
3701 ************************************************************/
3702 #ifdef __MSP430_HAS_PU__ /* Definition to show that Module is available */
3703 
3704 /* ========================================================================= */
3705 /* Port U and LDO Control Registers */
3706 /* ========================================================================= */
3707 #define OFS_LDOKEYPID (0x0000) /* LDO Controller peripheral ID and key register */
3708 #define OFS_LDOKEYPID_L OFS_LDOKEYPID
3709 #define OFS_LDOKEYPID_H OFS_LDOKEYPID+1
3710 #define OFS_PUCTL (0x0004) /* PU Control register */
3711 #define OFS_PUCTL_L OFS_PUCTL
3712 #define OFS_PUCTL_H OFS_PUCTL+1
3713 #define OFS_LDOPWRCTL (0x0008) /* LDO Power control register */
3714 #define OFS_LDOPWRCTL_L OFS_LDOPWRCTL
3715 #define OFS_LDOPWRCTL_H OFS_LDOPWRCTL+1
3716 
3717 #define LDOKEY (0x9628) /* LDO Control Register key */
3718 #define LDOKEYID LDOKEYPID /* Legacy Definiton */
3719 
3720 /* PUCTL Control Bits */
3721 #define PUOUT0 (0x0001) /* PU - PU Output Signal Bit 0 */
3722 #define PUOUT1 (0x0002) /* PU - PU Output Signal Bit 1 */
3723 #define PUIN0 (0x0004) /* PU - PU0/DP Input Data */
3724 #define PUIN1 (0x0008) /* PU - PU1/DM Input Data */
3725 #define PUOPE (0x0020) /* PU - Port Output Enable */
3726 #define PUIPE (0x0100) /* PU - PHY Single Ended Input enable */
3727 
3728 /* PUCTL Control Bits */
3729 #define PUOUT0_L (0x0001) /* PU - PU Output Signal Bit 0 */
3730 #define PUOUT1_L (0x0002) /* PU - PU Output Signal Bit 1 */
3731 #define PUIN0_L (0x0004) /* PU - PU0/DP Input Data */
3732 #define PUIN1_L (0x0008) /* PU - PU1/DM Input Data */
3733 #define PUOPE_L (0x0020) /* PU - Port Output Enable */
3734 
3735 /* PUCTL Control Bits */
3736 #define PUIPE_H (0x0001) /* PU - PHY Single Ended Input enable */
3737 
3738 #define PUDIR (0x0020) /* Legacy Definiton */
3739 #define PSEIEN (0x0100) /* Legacy Definiton */
3740 
3741 /* LDOPWRCTL Control Bits */
3742 #define LDOOVLIFG (0x0001) /* PU - LDOO Overload Interrupt Flag */
3743 #define LDOONIFG (0x0002) /* PU - LDOI "Coming ON" Interrupt Flag */
3744 #define LDOOFFIFG (0x0004) /* PU - LDOI "Going OFF" Interrupt Flag */
3745 #define LDOBGVBV (0x0008) /* PU - LDO Bandgap and LDOI valid */
3746 #define OVLAOFF (0x0020) /* PU - LDO overload auto off enable */
3747 #define LDOOVLIE (0x0100) /* PU - Overload indication Interrupt Enable */
3748 #define LDOONIE (0x0200) /* PU - LDOI "Coming ON" Interrupt Enable */
3749 #define LDOOFFIE (0x0400) /* PU - LDOI "Going OFF" Interrupt Enable */
3750 #define LDOEN (0x0800) /* PU - LDO Enable (3.3V) */
3751 
3752 /* LDOPWRCTL Control Bits */
3753 #define LDOOVLIFG_L (0x0001) /* PU - LDOO Overload Interrupt Flag */
3754 #define LDOONIFG_L (0x0002) /* PU - LDOI "Coming ON" Interrupt Flag */
3755 #define LDOOFFIFG_L (0x0004) /* PU - LDOI "Going OFF" Interrupt Flag */
3756 #define LDOBGVBV_L (0x0008) /* PU - LDO Bandgap and LDOI valid */
3757 #define OVLAOFF_L (0x0020) /* PU - LDO overload auto off enable */
3758 
3759 /* LDOPWRCTL Control Bits */
3760 #define LDOOVLIE_H (0x0001) /* PU - Overload indication Interrupt Enable */
3761 #define LDOONIE_H (0x0002) /* PU - LDOI "Coming ON" Interrupt Enable */
3762 #define LDOOFFIE_H (0x0004) /* PU - LDOI "Going OFF" Interrupt Enable */
3763 #define LDOEN_H (0x0008) /* PU - LDO Enable (3.3V) */
3764 #define LDOOEN_H (0x0008) /* Deprecated PU - LDO Enable (3.3V) */
3765 #define LDOOEN LDOEN /* Deprecated support for LDO Enable (3.3V) */
3766 
3767 #define VUOVLIFG (0x0001) /* PU - Legacy Definiton: LDOO Overload Interrupt Flag */
3768 #define VBONIFG (0x0002) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Flag */
3769 #define VBOFFIFG (0x0004) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Flag */
3770 #define VUOVLIE (0x0100) /* PU - Legacy Definiton: Overload indication Interrupt Enable */
3771 #define VBONIE (0x0200) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Enable */
3772 #define VBOFFIE (0x0400) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Enable */
3773 
3774 
3775 #endif
3776 /*************************************************************
3777 * RAM Control Module
3778 *************************************************************/
3779 #ifdef __MSP430_HAS_RC__ /* Definition to show that Module is available */
3780 
3781 #define OFS_RCCTL0 (0x0000) /* Ram Controller Control Register */
3782 #define OFS_RCCTL0_L OFS_RCCTL0
3783 #define OFS_RCCTL0_H OFS_RCCTL0+1
3784 
3785 /* RCCTL0 Control Bits */
3786 #define RCRS0OFF (0x0001) /* RAM Controller RAM Sector 0 Off */
3787 #define RCRS1OFF (0x0002) /* RAM Controller RAM Sector 1 Off */
3788 #define RCRS2OFF (0x0004) /* RAM Controller RAM Sector 2 Off */
3789 #define RCRS3OFF (0x0008) /* RAM Controller RAM Sector 3 Off */
3790 #define RCRS4OFF (0x0010) /* RAM Controller RAM Sector 4 Off */
3791 #define RCRS5OFF (0x0020) /* RAM Controller RAM Sector 5 Off */
3792 #define RCRS6OFF (0x0040) /* RAM Controller RAM Sector 6 Off */
3793 #define RCRS7OFF (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */
3794 
3795 /* RCCTL0 Control Bits */
3796 #define RCRS0OFF_L (0x0001) /* RAM Controller RAM Sector 0 Off */
3797 #define RCRS1OFF_L (0x0002) /* RAM Controller RAM Sector 1 Off */
3798 #define RCRS2OFF_L (0x0004) /* RAM Controller RAM Sector 2 Off */
3799 #define RCRS3OFF_L (0x0008) /* RAM Controller RAM Sector 3 Off */
3800 #define RCRS4OFF_L (0x0010) /* RAM Controller RAM Sector 4 Off */
3801 #define RCRS5OFF_L (0x0020) /* RAM Controller RAM Sector 5 Off */
3802 #define RCRS6OFF_L (0x0040) /* RAM Controller RAM Sector 6 Off */
3803 #define RCRS7OFF_L (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */
3804 
3805 #define RCKEY (0x5A00)
3806 
3807 #endif
3808 /************************************************************
3809 * Shared Reference
3810 ************************************************************/
3811 #ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */
3812 
3813 #define OFS_REFCTL0 (0x0000) /* REF Shared Reference control register 0 */
3814 #define OFS_REFCTL0_L OFS_REFCTL0
3815 #define OFS_REFCTL0_H OFS_REFCTL0+1
3816 
3817 /* REFCTL0 Control Bits */
3818 #define REFON (0x0001) /* REF Reference On */
3819 #define REFOUT (0x0002) /* REF Reference output Buffer On */
3820 //#define RESERVED (0x0004) /* Reserved */
3821 #define REFTCOFF (0x0008) /* REF Temp.Sensor off */
3822 #define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
3823 #define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
3824 //#define RESERVED (0x0040) /* Reserved */
3825 #define REFMSTR (0x0080) /* REF Master Control */
3826 #define REFGENACT (0x0100) /* REF Reference generator active */
3827 #define REFBGACT (0x0200) /* REF Reference bandgap active */
3828 #define REFGENBUSY (0x0400) /* REF Reference generator busy */
3829 #define BGMODE (0x0800) /* REF Bandgap mode */
3830 //#define RESERVED (0x1000) /* Reserved */
3831 //#define RESERVED (0x2000) /* Reserved */
3832 //#define RESERVED (0x4000) /* Reserved */
3833 //#define RESERVED (0x8000) /* Reserved */
3834 
3835 /* REFCTL0 Control Bits */
3836 #define REFON_L (0x0001) /* REF Reference On */
3837 #define REFOUT_L (0x0002) /* REF Reference output Buffer On */
3838 //#define RESERVED (0x0004) /* Reserved */
3839 #define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
3840 #define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
3841 #define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
3842 //#define RESERVED (0x0040) /* Reserved */
3843 #define REFMSTR_L (0x0080) /* REF Master Control */
3844 //#define RESERVED (0x1000) /* Reserved */
3845 //#define RESERVED (0x2000) /* Reserved */
3846 //#define RESERVED (0x4000) /* Reserved */
3847 //#define RESERVED (0x8000) /* Reserved */
3848 
3849 /* REFCTL0 Control Bits */
3850 //#define RESERVED (0x0004) /* Reserved */
3851 //#define RESERVED (0x0040) /* Reserved */
3852 #define REFGENACT_H (0x0001) /* REF Reference generator active */
3853 #define REFBGACT_H (0x0002) /* REF Reference bandgap active */
3854 #define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
3855 #define BGMODE_H (0x0008) /* REF Bandgap mode */
3856 //#define RESERVED (0x1000) /* Reserved */
3857 //#define RESERVED (0x2000) /* Reserved */
3858 //#define RESERVED (0x4000) /* Reserved */
3859 //#define RESERVED (0x8000) /* Reserved */
3860 
3861 #define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */
3862 #define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
3863 #define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
3864 #define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
3865 
3866 #endif
3867 /************************************************************
3868 * Shared Reference
3869 ************************************************************/
3870 #ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */
3871 
3872 #define OFS_REFCTL0 (0x0000) /* REF Shared Reference control register 0 */
3873 #define OFS_REFCTL0_L OFS_REFCTL0
3874 #define OFS_REFCTL0_H OFS_REFCTL0+1
3875 
3876 /* REFCTL0 Control Bits */
3877 #define REFON (0x0001) /* REF Reference On */
3878 //#define RESERVED (0x0002) /* Reserved */
3879 //#define RESERVED (0x0004) /* Reserved */
3880 #define REFTCOFF (0x0008) /* REF Temp.Sensor off */
3881 #define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
3882 #define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
3883 //#define RESERVED (0x0040) /* Reserved */
3884 //#define RESERVED (0x0080) /* Reserved */
3885 #define REFGENACT (0x0100) /* REF Reference generator active */
3886 #define REFBGACT (0x0200) /* REF Reference bandgap active */
3887 #define REFGENBUSY (0x0400) /* REF Reference generator busy */
3888 #define BGMODE (0x0800) /* REF Bandgap mode */
3889 //#define RESERVED (0x1000) /* Reserved */
3890 //#define RESERVED (0x2000) /* Reserved */
3891 //#define RESERVED (0x4000) /* Reserved */
3892 //#define RESERVED (0x8000) /* Reserved */
3893 
3894 /* REFCTL0 Control Bits */
3895 #define REFON_L (0x0001) /* REF Reference On */
3896 //#define RESERVED (0x0002) /* Reserved */
3897 //#define RESERVED (0x0004) /* Reserved */
3898 #define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
3899 #define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
3900 #define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
3901 //#define RESERVED (0x0040) /* Reserved */
3902 //#define RESERVED (0x0080) /* Reserved */
3903 //#define RESERVED (0x1000) /* Reserved */
3904 //#define RESERVED (0x2000) /* Reserved */
3905 //#define RESERVED (0x4000) /* Reserved */
3906 //#define RESERVED (0x8000) /* Reserved */
3907 
3908 /* REFCTL0 Control Bits */
3909 //#define RESERVED (0x0002) /* Reserved */
3910 //#define RESERVED (0x0004) /* Reserved */
3911 //#define RESERVED (0x0040) /* Reserved */
3912 //#define RESERVED (0x0080) /* Reserved */
3913 #define REFGENACT_H (0x0001) /* REF Reference generator active */
3914 #define REFBGACT_H (0x0002) /* REF Reference bandgap active */
3915 #define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
3916 #define BGMODE_H (0x0008) /* REF Bandgap mode */
3917 //#define RESERVED (0x1000) /* Reserved */
3918 //#define RESERVED (0x2000) /* Reserved */
3919 //#define RESERVED (0x4000) /* Reserved */
3920 //#define RESERVED (0x8000) /* Reserved */
3921 
3922 #define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */
3923 #define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
3924 #define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
3925 #define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
3926 
3927 #endif
3928 /************************************************************
3929 * Real Time Clock
3930 ************************************************************/
3931 #ifdef __MSP430_HAS_RTC__ /* Definition to show that Module is available */
3932 
3933 #define OFS_RTCCTL01 (0x0000) /* Real Timer Control 0/1 */
3934 #define OFS_RTCCTL01_L OFS_RTCCTL01
3935 #define OFS_RTCCTL01_H OFS_RTCCTL01+1
3936 #define OFS_RTCCTL23 (0x0002) /* Real Timer Control 2/3 */
3937 #define OFS_RTCCTL23_L OFS_RTCCTL23
3938 #define OFS_RTCCTL23_H OFS_RTCCTL23+1
3939 #define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */
3940 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
3941 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
3942 #define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */
3943 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
3944 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
3945 #define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */
3946 #define OFS_RTCPS_L OFS_RTCPS
3947 #define OFS_RTCPS_H OFS_RTCPS+1
3948 #define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */
3949 #define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */
3950 #define OFS_RTCTIM0_L OFS_RTCTIM0
3951 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
3952 #define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */
3953 #define OFS_RTCTIM1_L OFS_RTCTIM1
3954 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
3955 #define OFS_RTCDATE (0x0014) /* Real Time Clock Date */
3956 #define OFS_RTCDATE_L OFS_RTCDATE
3957 #define OFS_RTCDATE_H OFS_RTCDATE+1
3958 #define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */
3959 #define OFS_RTCYEAR_L OFS_RTCYEAR
3960 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
3961 #define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */
3962 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
3963 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
3964 #define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */
3965 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
3966 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
3967 #define OFS_RTCSEC (0x0010)
3968 #define OFS_RTCMIN (0x0011)
3969 #define OFS_RTCHOUR (0x0012)
3970 #define OFS_RTCDOW (0x0013)
3971 #define OFS_RTCDAY (0x0014)
3972 #define OFS_RTCMON (0x0015)
3973 #define OFS_RTCAMIN (0x0018)
3974 #define OFS_RTCAHOUR (0x0019)
3975 #define OFS_RTCADOW (0x001A)
3976 #define OFS_RTCADAY (0x001B)
3977 
3978 #define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
3979 #define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
3980 #define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
3981 #define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
3982 #define RTCNT12 RTCTIM0
3983 #define RTCNT34 RTCTIM1
3984 #define RTCNT1 RTCTIM0_L
3985 #define RTCNT2 RTCTIM0_H
3986 #define RTCNT3 RTCTIM1_L
3987 #define RTCNT4 RTCTIM1_H
3988 #define RTCSEC RTCTIM0_L
3989 #define RTCMIN RTCTIM0_H
3990 #define RTCHOUR RTCTIM1_L
3991 #define RTCDOW RTCTIM1_H
3992 #define RTCDAY RTCDATE_L
3993 #define RTCMON RTCDATE_H
3994 #define RTCYEARL RTCYEAR_L
3995 #define RTCYEARH RTCYEAR_H
3996 #define RT0PS RTCPS_L
3997 #define RT1PS RTCPS_H
3998 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
3999 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
4000 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
4001 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
4002 
4003 /* RTCCTL01 Control Bits */
4004 #define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */
4005 #define RTCHOLD (0x4000) /* RTC Hold */
4006 #define RTCMODE (0x2000) /* RTC Mode 0:Counter / 1: Calendar */
4007 #define RTCRDY (0x1000) /* RTC Ready */
4008 #define RTCSSEL1 (0x0800) /* RTC Source Select 1 */
4009 #define RTCSSEL0 (0x0400) /* RTC Source Select 0 */
4010 #define RTCTEV1 (0x0200) /* RTC Time Event 1 */
4011 #define RTCTEV0 (0x0100) /* RTC Time Event 0 */
4012 //#define Reserved (0x0080)
4013 #define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
4014 #define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
4015 #define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
4016 //#define Reserved (0x0008)
4017 #define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
4018 #define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
4019 #define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
4020 
4021 /* RTCCTL01 Control Bits */
4022 //#define Reserved (0x0080)
4023 #define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
4024 #define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
4025 #define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
4026 //#define Reserved (0x0008)
4027 #define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
4028 #define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
4029 #define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
4030 
4031 /* RTCCTL01 Control Bits */
4032 #define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */
4033 #define RTCHOLD_H (0x0040) /* RTC Hold */
4034 #define RTCMODE_H (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
4035 #define RTCRDY_H (0x0010) /* RTC Ready */
4036 #define RTCSSEL1_H (0x0008) /* RTC Source Select 1 */
4037 #define RTCSSEL0_H (0x0004) /* RTC Source Select 0 */
4038 #define RTCTEV1_H (0x0002) /* RTC Time Event 1 */
4039 #define RTCTEV0_H (0x0001) /* RTC Time Event 0 */
4040 //#define Reserved (0x0080)
4041 //#define Reserved (0x0008)
4042 
4043 #define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */
4044 #define RTCSSEL_1 (0x0400) /* RTC Source Select SMCLK */
4045 #define RTCSSEL_2 (0x0800) /* RTC Source Select RT1PS */
4046 #define RTCSSEL_3 (0x0C00) /* RTC Source Select RT1PS */
4047 #define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */
4048 #define RTCSSEL__SMCLK (0x0400) /* RTC Source Select SMCLK */
4049 #define RTCSSEL__RT1PS (0x0800) /* RTC Source Select RT1PS */
4050 #define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
4051 #define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */
4052 #define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */
4053 #define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */
4054 #define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
4055 #define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */
4056 #define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */
4057 #define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */
4058 
4059 /* RTCCTL23 Control Bits */
4060 #define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
4061 #define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
4062 #define RTCCALS (0x0080) /* RTC Calibration Sign */
4063 //#define Reserved (0x0040)
4064 #define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */
4065 #define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */
4066 #define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */
4067 #define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */
4068 #define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */
4069 #define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */
4070 
4071 /* RTCCTL23 Control Bits */
4072 #define RTCCALS_L (0x0080) /* RTC Calibration Sign */
4073 //#define Reserved (0x0040)
4074 #define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */
4075 #define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */
4076 #define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */
4077 #define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */
4078 #define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */
4079 #define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */
4080 
4081 /* RTCCTL23 Control Bits */
4082 #define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
4083 #define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
4084 //#define Reserved (0x0040)
4085 
4086 #define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
4087 #define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
4088 #define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
4089 #define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
4090 
4091 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
4092 
4093 /* RTCPS0CTL Control Bits */
4094 //#define Reserved (0x8000)
4095 #define RT0SSEL (0x4000) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
4096 #define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
4097 #define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
4098 #define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
4099 //#define Reserved (0x0400)
4100 //#define Reserved (0x0200)
4101 #define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */
4102 //#define Reserved (0x0080)
4103 //#define Reserved (0x0040)
4104 //#define Reserved (0x0020)
4105 #define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4106 #define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4107 #define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4108 #define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4109 #define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
4110 
4111 /* RTCPS0CTL Control Bits */
4112 //#define Reserved (0x8000)
4113 //#define Reserved (0x0400)
4114 //#define Reserved (0x0200)
4115 //#define Reserved (0x0080)
4116 //#define Reserved (0x0040)
4117 //#define Reserved (0x0020)
4118 #define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4119 #define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4120 #define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4121 #define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4122 #define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
4123 
4124 /* RTCPS0CTL Control Bits */
4125 //#define Reserved (0x8000)
4126 #define RT0SSEL_H (0x0040) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
4127 #define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
4128 #define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
4129 #define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
4130 //#define Reserved (0x0400)
4131 //#define Reserved (0x0200)
4132 #define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */
4133 //#define Reserved (0x0080)
4134 //#define Reserved (0x0040)
4135 //#define Reserved (0x0020)
4136 
4137 #define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4138 #define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4139 #define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4140 #define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4141 #define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4142 #define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4143 #define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4144 #define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4145 
4146 #define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide /2 */
4147 #define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide /4 */
4148 #define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide /8 */
4149 #define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide /16 */
4150 #define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide /32 */
4151 #define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide /64 */
4152 #define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide /128 */
4153 #define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide /256 */
4154 
4155 /* RTCPS1CTL Control Bits */
4156 #define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */
4157 #define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */
4158 #define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
4159 #define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
4160 #define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
4161 //#define Reserved (0x0400)
4162 //#define Reserved (0x0200)
4163 #define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */
4164 //#define Reserved (0x0080)
4165 //#define Reserved (0x0040)
4166 //#define Reserved (0x0020)
4167 #define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4168 #define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4169 #define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4170 #define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4171 #define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
4172 
4173 /* RTCPS1CTL Control Bits */
4174 //#define Reserved (0x0400)
4175 //#define Reserved (0x0200)
4176 //#define Reserved (0x0080)
4177 //#define Reserved (0x0040)
4178 //#define Reserved (0x0020)
4179 #define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4180 #define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4181 #define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4182 #define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4183 #define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
4184 
4185 /* RTCPS1CTL Control Bits */
4186 #define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */
4187 #define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */
4188 #define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
4189 #define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
4190 #define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
4191 //#define Reserved (0x0400)
4192 //#define Reserved (0x0200)
4193 #define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */
4194 //#define Reserved (0x0080)
4195 //#define Reserved (0x0040)
4196 //#define Reserved (0x0020)
4197 
4198 #define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4199 #define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4200 #define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4201 #define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4202 #define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4203 #define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4204 #define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
4205 #define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
4206 
4207 #define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide /2 */
4208 #define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide /4 */
4209 #define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide /8 */
4210 #define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide /16 */
4211 #define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide /32 */
4212 #define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide /64 */
4213 #define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide /128 */
4214 #define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide /256 */
4215 
4216 #define RT1SSEL_0 (0x0000) /* RTC Prescale Timer Source Select ACLK */
4217 #define RT1SSEL_1 (0x4000) /* RTC Prescale Timer Source Select SMCLK */
4218 #define RT1SSEL_2 (0x8000) /* RTC Prescale Timer Source Select RT0PS */
4219 #define RT1SSEL_3 (0xC000) /* RTC Prescale Timer Source Select RT0PS */
4220 
4221 /* RTC Definitions */
4222 #define RTCIV_NONE (0x0000) /* No Interrupt pending */
4223 #define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
4224 #define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
4225 #define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
4226 #define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
4227 #define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
4228 
4229 /* Legacy Definitions */
4230 #define RTC_NONE (0x0000) /* No Interrupt pending */
4231 #define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
4232 #define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
4233 #define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
4234 #define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
4235 #define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
4236 
4237 #endif
4238 /************************************************************
4239 * Real Time Clock
4240 ************************************************************/
4241 #ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */
4242 
4243 #define OFS_RTCCTL01 (0x0000) /* Real Timer Control 0/1 */
4244 #define OFS_RTCCTL01_L OFS_RTCCTL01
4245 #define OFS_RTCCTL01_H OFS_RTCCTL01+1
4246 #define OFS_RTCCTL23 (0x0002) /* Real Timer Control 2/3 */
4247 #define OFS_RTCCTL23_L OFS_RTCCTL23
4248 #define OFS_RTCCTL23_H OFS_RTCCTL23+1
4249 #define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */
4250 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
4251 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
4252 #define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */
4253 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
4254 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
4255 #define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */
4256 #define OFS_RTCPS_L OFS_RTCPS
4257 #define OFS_RTCPS_H OFS_RTCPS+1
4258 #define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */
4259 #define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */
4260 #define OFS_RTCTIM0_L OFS_RTCTIM0
4261 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
4262 #define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */
4263 #define OFS_RTCTIM1_L OFS_RTCTIM1
4264 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
4265 #define OFS_RTCDATE (0x0014) /* Real Time Clock Date */
4266 #define OFS_RTCDATE_L OFS_RTCDATE
4267 #define OFS_RTCDATE_H OFS_RTCDATE+1
4268 #define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */
4269 #define OFS_RTCYEAR_L OFS_RTCYEAR
4270 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
4271 #define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */
4272 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
4273 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
4274 #define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */
4275 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
4276 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
4277 #define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */
4278 #define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */
4279 #define OFS_RTCSEC (0x0010)
4280 #define OFS_RTCMIN (0x0011)
4281 #define OFS_RTCHOUR (0x0012)
4282 #define OFS_RTCDOW (0x0013)
4283 #define OFS_RTCDAY (0x0014)
4284 #define OFS_RTCMON (0x0015)
4285 #define OFS_RTCAMIN (0x0018)
4286 #define OFS_RTCAHOUR (0x0019)
4287 #define OFS_RTCADOW (0x001A)
4288 #define OFS_RTCADAY (0x001B)
4289 
4290 #define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
4291 #define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
4292 #define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
4293 #define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
4294 #define RTCNT12 RTCTIM0
4295 #define RTCNT34 RTCTIM1
4296 #define RTCNT1 RTCTIM0_L
4297 #define RTCNT2 RTCTIM0_H
4298 #define RTCNT3 RTCTIM1_L
4299 #define RTCNT4 RTCTIM1_H
4300 #define RTCSEC RTCTIM0_L
4301 #define RTCMIN RTCTIM0_H
4302 #define RTCHOUR RTCTIM1_L
4303 #define RTCDOW RTCTIM1_H
4304 #define RTCDAY RTCDATE_L
4305 #define RTCMON RTCDATE_H
4306 #define RTCYEARL RTCYEAR_L
4307 #define RTCYEARH RTCYEAR_H
4308 #define RT0PS RTCPS_L
4309 #define RT1PS RTCPS_H
4310 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
4311 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
4312 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
4313 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
4314 
4315 /* RTCCTL01 Control Bits */
4316 #define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */
4317 #define RTCHOLD (0x4000) /* RTC Hold */
4318 //#define RESERVED (0x2000) /* RESERVED */
4319 #define RTCRDY (0x1000) /* RTC Ready */
4320 //#define RESERVED (0x0800) /* RESERVED */
4321 //#define RESERVED (0x0400) /* RESERVED */
4322 #define RTCTEV1 (0x0200) /* RTC Time Event 1 */
4323 #define RTCTEV0 (0x0100) /* RTC Time Event 0 */
4324 #define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4325 #define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
4326 #define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
4327 #define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
4328 #define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4329 #define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
4330 #define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
4331 #define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
4332 
4333 /* RTCCTL01 Control Bits */
4334 //#define RESERVED (0x2000) /* RESERVED */
4335 //#define RESERVED (0x0800) /* RESERVED */
4336 //#define RESERVED (0x0400) /* RESERVED */
4337 #define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4338 #define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
4339 #define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
4340 #define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
4341 #define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4342 #define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
4343 #define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
4344 #define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
4345 
4346 /* RTCCTL01 Control Bits */
4347 #define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */
4348 #define RTCHOLD_H (0x0040) /* RTC Hold */
4349 //#define RESERVED (0x2000) /* RESERVED */
4350 #define RTCRDY_H (0x0010) /* RTC Ready */
4351 //#define RESERVED (0x0800) /* RESERVED */
4352 //#define RESERVED (0x0400) /* RESERVED */
4353 #define RTCTEV1_H (0x0002) /* RTC Time Event 1 */
4354 #define RTCTEV0_H (0x0001) /* RTC Time Event 0 */
4355 
4356 #define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
4357 #define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */
4358 #define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */
4359 #define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */
4360 #define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
4361 #define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */
4362 #define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */
4363 #define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */
4364 
4365 /* RTCCTL23 Control Bits */
4366 #define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
4367 #define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
4368 #define RTCCALS (0x0080) /* RTC Calibration Sign */
4369 //#define Reserved (0x0040)
4370 #define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */
4371 #define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */
4372 #define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */
4373 #define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */
4374 #define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */
4375 #define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */
4376 
4377 /* RTCCTL23 Control Bits */
4378 #define RTCCALS_L (0x0080) /* RTC Calibration Sign */
4379 //#define Reserved (0x0040)
4380 #define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */
4381 #define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */
4382 #define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */
4383 #define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */
4384 #define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */
4385 #define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */
4386 
4387 /* RTCCTL23 Control Bits */
4388 #define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
4389 #define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
4390 //#define Reserved (0x0040)
4391 
4392 #define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
4393 #define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
4394 #define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
4395 #define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
4396 
4397 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
4398 
4399 /* RTCPS0CTL Control Bits */
4400 //#define Reserved (0x0080)
4401 //#define Reserved (0x0040)
4402 //#define Reserved (0x0020)
4403 #define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4404 #define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4405 #define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4406 #define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4407 #define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
4408 
4409 /* RTCPS0CTL Control Bits */
4410 //#define Reserved (0x0080)
4411 //#define Reserved (0x0040)
4412 //#define Reserved (0x0020)
4413 #define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4414 #define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4415 #define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4416 #define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4417 #define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
4418 
4419 #define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4420 #define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4421 #define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4422 #define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4423 #define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4424 #define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4425 #define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4426 #define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4427 
4428 #define RT0IP__2 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4429 #define RT0IP__4 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4430 #define RT0IP__8 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4431 #define RT0IP__16 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4432 #define RT0IP__32 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4433 #define RT0IP__64 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4434 #define RT0IP__128 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4435 #define RT0IP__256 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4436 
4437 /* RTCPS1CTL Control Bits */
4438 //#define Reserved (0x0080)
4439 //#define Reserved (0x0040)
4440 //#define Reserved (0x0020)
4441 #define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4442 #define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4443 #define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4444 #define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4445 #define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
4446 
4447 /* RTCPS1CTL Control Bits */
4448 //#define Reserved (0x0080)
4449 //#define Reserved (0x0040)
4450 //#define Reserved (0x0020)
4451 #define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4452 #define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4453 #define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4454 #define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4455 #define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
4456 
4457 #define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4458 #define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4459 #define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4460 #define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4461 #define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4462 #define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4463 #define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
4464 #define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
4465 
4466 #define RT1IP__2 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4467 #define RT1IP__4 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4468 #define RT1IP__8 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4469 #define RT1IP__16 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4470 #define RT1IP__32 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4471 #define RT1IP__64 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4472 #define RT1IP__128 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
4473 #define RT1IP__256 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
4474 
4475 /* RTC Definitions */
4476 #define RTCIV_NONE (0x0000) /* No Interrupt pending */
4477 #define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
4478 #define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
4479 #define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
4480 #define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
4481 #define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
4482 #define RTCIV_RTCOFIFG (0x000C) /* RTC Oscillator fault */
4483 
4484 /* Legacy Definitions */
4485 #define RTC_NONE (0x0000) /* No Interrupt pending */
4486 #define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
4487 #define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
4488 #define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
4489 #define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
4490 #define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
4491 #define RTC_RTCOFIFG (0x000C) /* RTC Oscillator fault */
4492 
4493 #endif
4494 /************************************************************
4495 * Real Time Clock
4496 ************************************************************/
4497 #ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */
4498 
4499 #define OFS_RTCCTL0 (0x0000) /* Real Timer Clock Control 0/Key */
4500 #define OFS_RTCCTL0_L OFS_RTCCTL0
4501 #define OFS_RTCCTL0_H OFS_RTCCTL0+1
4502 #define OFS_RTCCTL13 (0x0002) /* Real Timer Clock Control 1/3 */
4503 #define OFS_RTCCTL13_L OFS_RTCCTL13
4504 #define OFS_RTCCTL13_H OFS_RTCCTL13+1
4505 #define RTCCTL1 RTCCTL13_L
4506 #define RTCCTL3 RTCCTL13_H
4507 #define OFS_RTCOCAL (0x0004) /* Real Timer Clock Offset Calibartion */
4508 #define OFS_RTCOCAL_L OFS_RTCOCAL
4509 #define OFS_RTCOCAL_H OFS_RTCOCAL+1
4510 #define OFS_RTCTCMP (0x0006) /* Real Timer Temperature Compensation */
4511 #define OFS_RTCTCMP_L OFS_RTCTCMP
4512 #define OFS_RTCTCMP_H OFS_RTCTCMP+1
4513 #define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */
4514 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
4515 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
4516 #define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */
4517 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
4518 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
4519 #define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */
4520 #define OFS_RTCPS_L OFS_RTCPS
4521 #define OFS_RTCPS_H OFS_RTCPS+1
4522 #define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */
4523 #define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */
4524 #define OFS_RTCTIM0_L OFS_RTCTIM0
4525 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
4526 #define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */
4527 #define OFS_RTCTIM1_L OFS_RTCTIM1
4528 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
4529 #define OFS_RTCDATE (0x0014) /* Real Time Clock Date */
4530 #define OFS_RTCDATE_L OFS_RTCDATE
4531 #define OFS_RTCDATE_H OFS_RTCDATE+1
4532 #define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */
4533 #define OFS_RTCYEAR_L OFS_RTCYEAR
4534 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
4535 #define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */
4536 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
4537 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
4538 #define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */
4539 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
4540 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
4541 #define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */
4542 #define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */
4543 #define OFS_RTCSEC (0x0010)
4544 #define OFS_RTCMIN (0x0011)
4545 #define OFS_RTCHOUR (0x0012)
4546 #define OFS_RTCDOW (0x0013)
4547 #define OFS_RTCDAY (0x0014)
4548 #define OFS_RTCMON (0x0015)
4549 #define OFS_RTCAMIN (0x0018)
4550 #define OFS_RTCAHOUR (0x0019)
4551 #define OFS_RTCADOW (0x001A)
4552 #define OFS_RTCADAY (0x001B)
4553 
4554 #define RTCSEC RTCTIM0_L
4555 #define RTCMIN RTCTIM0_H
4556 #define RTCHOUR RTCTIM1_L
4557 #define RTCDOW RTCTIM1_H
4558 #define RTCDAY RTCDATE_L
4559 #define RTCMON RTCDATE_H
4560 #define RTCYEARL RTCYEAR_L
4561 #define RT0PS RTCPS_L
4562 #define RT1PS RTCPS_H
4563 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
4564 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
4565 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
4566 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
4567 
4568 /* RTCCTL0 Control Bits */
4569 #define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4570 #define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
4571 #define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
4572 #define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
4573 #define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4574 #define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
4575 #define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
4576 #define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
4577 
4578 /* RTCCTL0 Control Bits */
4579 #define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4580 #define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
4581 #define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
4582 #define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
4583 #define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4584 #define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
4585 #define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
4586 #define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
4587 
4588 #define RTCKEY (0xA500) /* RTC Key for RTC write access */
4589 #define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */
4590 
4591 /* RTCCTL13 Control Bits */
4592 #define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
4593 #define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
4594 #define RTCBCD (0x0080) /* RTC BCD 0:Binary / 1:BCD */
4595 #define RTCHOLD (0x0040) /* RTC Hold */
4596 #define RTCMODE (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
4597 #define RTCRDY (0x0010) /* RTC Ready */
4598 #define RTCSSEL1 (0x0008) /* RTC Source Select 1 */
4599 #define RTCSSEL0 (0x0004) /* RTC Source Select 0 */
4600 #define RTCTEV1 (0x0002) /* RTC Time Event 1 */
4601 #define RTCTEV0 (0x0001) /* RTC Time Event 0 */
4602 
4603 /* RTCCTL13 Control Bits */
4604 #define RTCBCD_L (0x0080) /* RTC BCD 0:Binary / 1:BCD */
4605 #define RTCHOLD_L (0x0040) /* RTC Hold */
4606 #define RTCMODE_L (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
4607 #define RTCRDY_L (0x0010) /* RTC Ready */
4608 #define RTCSSEL1_L (0x0008) /* RTC Source Select 1 */
4609 #define RTCSSEL0_L (0x0004) /* RTC Source Select 0 */
4610 #define RTCTEV1_L (0x0002) /* RTC Time Event 1 */
4611 #define RTCTEV0_L (0x0001) /* RTC Time Event 0 */
4612 
4613 /* RTCCTL13 Control Bits */
4614 #define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
4615 #define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
4616 
4617 #define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */
4618 #define RTCSSEL_1 (0x0004) /* RTC Source Select SMCLK */
4619 #define RTCSSEL_2 (0x0008) /* RTC Source Select RT1PS */
4620 #define RTCSSEL_3 (0x000C) /* RTC Source Select RT1PS */
4621 #define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */
4622 #define RTCSSEL__SMCLK (0x0004) /* RTC Source Select SMCLK */
4623 #define RTCSSEL__RT1PS (0x0008) /* RTC Source Select RT1PS */
4624 
4625 #define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
4626 #define RTCTEV_1 (0x0001) /* RTC Time Event: 1 (Hour changed) */
4627 #define RTCTEV_2 (0x0002) /* RTC Time Event: 2 (12:00 changed) */
4628 #define RTCTEV_3 (0x0003) /* RTC Time Event: 3 (00:00 changed) */
4629 #define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
4630 #define RTCTEV__HOUR (0x0001) /* RTC Time Event: 1 (Hour changed) */
4631 #define RTCTEV__0000 (0x0002) /* RTC Time Event: 2 (00:00 changed) */
4632 #define RTCTEV__1200 (0x0003) /* RTC Time Event: 3 (12:00 changed) */
4633 
4634 #define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
4635 #define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
4636 #define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
4637 #define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
4638 
4639 /* RTCOCAL Control Bits */
4640 #define RTCOCALS (0x8000) /* RTC Offset Calibration Sign */
4641 #define RTCOCAL7 (0x0080) /* RTC Offset Calibration Bit 7 */
4642 #define RTCOCAL6 (0x0040) /* RTC Offset Calibration Bit 6 */
4643 #define RTCOCAL5 (0x0020) /* RTC Offset Calibration Bit 5 */
4644 #define RTCOCAL4 (0x0010) /* RTC Offset Calibration Bit 4 */
4645 #define RTCOCAL3 (0x0008) /* RTC Offset Calibration Bit 3 */
4646 #define RTCOCAL2 (0x0004) /* RTC Offset Calibration Bit 2 */
4647 #define RTCOCAL1 (0x0002) /* RTC Offset Calibration Bit 1 */
4648 #define RTCOCAL0 (0x0001) /* RTC Offset Calibration Bit 0 */
4649 
4650 /* RTCOCAL Control Bits */
4651 #define RTCOCAL7_L (0x0080) /* RTC Offset Calibration Bit 7 */
4652 #define RTCOCAL6_L (0x0040) /* RTC Offset Calibration Bit 6 */
4653 #define RTCOCAL5_L (0x0020) /* RTC Offset Calibration Bit 5 */
4654 #define RTCOCAL4_L (0x0010) /* RTC Offset Calibration Bit 4 */
4655 #define RTCOCAL3_L (0x0008) /* RTC Offset Calibration Bit 3 */
4656 #define RTCOCAL2_L (0x0004) /* RTC Offset Calibration Bit 2 */
4657 #define RTCOCAL1_L (0x0002) /* RTC Offset Calibration Bit 1 */
4658 #define RTCOCAL0_L (0x0001) /* RTC Offset Calibration Bit 0 */
4659 
4660 /* RTCOCAL Control Bits */
4661 #define RTCOCALS_H (0x0080) /* RTC Offset Calibration Sign */
4662 
4663 /* RTCTCMP Control Bits */
4664 #define RTCTCMPS (0x8000) /* RTC Temperature Compensation Sign */
4665 #define RTCTCRDY (0x4000) /* RTC Temperature compensation ready */
4666 #define RTCTCOK (0x2000) /* RTC Temperature compensation write OK */
4667 #define RTCTCMP7 (0x0080) /* RTC Temperature Compensation Bit 7 */
4668 #define RTCTCMP6 (0x0040) /* RTC Temperature Compensation Bit 6 */
4669 #define RTCTCMP5 (0x0020) /* RTC Temperature Compensation Bit 5 */
4670 #define RTCTCMP4 (0x0010) /* RTC Temperature Compensation Bit 4 */
4671 #define RTCTCMP3 (0x0008) /* RTC Temperature Compensation Bit 3 */
4672 #define RTCTCMP2 (0x0004) /* RTC Temperature Compensation Bit 2 */
4673 #define RTCTCMP1 (0x0002) /* RTC Temperature Compensation Bit 1 */
4674 #define RTCTCMP0 (0x0001) /* RTC Temperature Compensation Bit 0 */
4675 
4676 /* RTCTCMP Control Bits */
4677 #define RTCTCMP7_L (0x0080) /* RTC Temperature Compensation Bit 7 */
4678 #define RTCTCMP6_L (0x0040) /* RTC Temperature Compensation Bit 6 */
4679 #define RTCTCMP5_L (0x0020) /* RTC Temperature Compensation Bit 5 */
4680 #define RTCTCMP4_L (0x0010) /* RTC Temperature Compensation Bit 4 */
4681 #define RTCTCMP3_L (0x0008) /* RTC Temperature Compensation Bit 3 */
4682 #define RTCTCMP2_L (0x0004) /* RTC Temperature Compensation Bit 2 */
4683 #define RTCTCMP1_L (0x0002) /* RTC Temperature Compensation Bit 1 */
4684 #define RTCTCMP0_L (0x0001) /* RTC Temperature Compensation Bit 0 */
4685 
4686 /* RTCTCMP Control Bits */
4687 #define RTCTCMPS_H (0x0080) /* RTC Temperature Compensation Sign */
4688 #define RTCTCRDY_H (0x0040) /* RTC Temperature compensation ready */
4689 #define RTCTCOK_H (0x0020) /* RTC Temperature compensation write OK */
4690 
4691 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
4692 
4693 /* RTCPS0CTL Control Bits */
4694 //#define Reserved (0x8000)
4695 //#define Reserved (0x4000)
4696 #define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
4697 #define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
4698 #define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
4699 //#define Reserved (0x0400)
4700 //#define Reserved (0x0200)
4701 #define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */
4702 //#define Reserved (0x0080)
4703 //#define Reserved (0x0040)
4704 //#define Reserved (0x0020)
4705 #define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4706 #define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4707 #define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4708 #define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4709 #define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
4710 
4711 /* RTCPS0CTL Control Bits */
4712 //#define Reserved (0x8000)
4713 //#define Reserved (0x4000)
4714 //#define Reserved (0x0400)
4715 //#define Reserved (0x0200)
4716 //#define Reserved (0x0080)
4717 //#define Reserved (0x0040)
4718 //#define Reserved (0x0020)
4719 #define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
4720 #define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
4721 #define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
4722 #define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
4723 #define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
4724 
4725 /* RTCPS0CTL Control Bits */
4726 //#define Reserved (0x8000)
4727 //#define Reserved (0x4000)
4728 #define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
4729 #define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
4730 #define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
4731 //#define Reserved (0x0400)
4732 //#define Reserved (0x0200)
4733 #define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */
4734 //#define Reserved (0x0080)
4735 //#define Reserved (0x0040)
4736 //#define Reserved (0x0020)
4737 
4738 #define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
4739 #define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
4740 #define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
4741 #define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
4742 #define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
4743 #define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
4744 #define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
4745 #define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
4746 
4747 /* RTCPS1CTL Control Bits */
4748 #define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */
4749 #define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */
4750 #define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
4751 #define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
4752 #define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
4753 //#define Reserved (0x0400)
4754 //#define Reserved (0x0200)
4755 #define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */
4756 //#define Reserved (0x0080)
4757 //#define Reserved (0x0040)
4758 //#define Reserved (0x0020)
4759 #define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4760 #define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4761 #define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4762 #define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4763 #define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
4764 
4765 /* RTCPS1CTL Control Bits */
4766 //#define Reserved (0x0400)
4767 //#define Reserved (0x0200)
4768 //#define Reserved (0x0080)
4769 //#define Reserved (0x0040)
4770 //#define Reserved (0x0020)
4771 #define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
4772 #define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
4773 #define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
4774 #define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
4775 #define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
4776 
4777 /* RTCPS1CTL Control Bits */
4778 #define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */
4779 #define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */
4780 #define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
4781 #define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
4782 #define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
4783 //#define Reserved (0x0400)
4784 //#define Reserved (0x0200)
4785 #define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */
4786 //#define Reserved (0x0080)
4787 //#define Reserved (0x0040)
4788 //#define Reserved (0x0020)
4789 
4790 #define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
4791 #define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
4792 #define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
4793 #define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
4794 #define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
4795 #define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
4796 #define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
4797 #define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
4798 
4799 /* RTC Definitions */
4800 #define RTCIV_NONE (0x0000) /* No Interrupt pending */
4801 #define RTCIV_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */
4802 #define RTCIV_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */
4803 #define RTCIV_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */
4804 #define RTCIV_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */
4805 #define RTCIV_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */
4806 #define RTCIV_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */
4807 
4808 /* Legacy Definitions */
4809 #define RTC_NONE (0x0000) /* No Interrupt pending */
4810 #define RTC_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */
4811 #define RTC_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */
4812 #define RTC_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */
4813 #define RTC_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */
4814 #define RTC_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */
4815 #define RTC_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */
4816 
4817 #endif
4818 /************************************************************
4819 * Real Time Clock
4820 ************************************************************/
4821 #ifdef __MSP430_HAS_RTC_CE__ /* Definition to show that Module is available */
4822 
4823 #define OFS_RTCCTL0 (0x0000) /* Real Timer Clock Control 0/Key */
4824 #define OFS_RTCCTL0_L OFS_RTCCTL0
4825 #define OFS_RTCCTL0_H OFS_RTCCTL0+1
4826 #define OFS_RTCCTL13 (0x0002) /* Real Timer Clock Control 1/3 */
4827 #define OFS_RTCCTL13_L OFS_RTCCTL13
4828 #define OFS_RTCCTL13_H OFS_RTCCTL13+1
4829 #define RTCCTL1 RTCCTL13_L
4830 #define RTCCTL3 RTCCTL13_H
4831 #define OFS_RTCOCAL (0x0004) /* Real Timer Clock Offset Calibartion */
4832 #define OFS_RTCOCAL_L OFS_RTCOCAL
4833 #define OFS_RTCOCAL_H OFS_RTCOCAL+1
4834 #define OFS_RTCTCMP (0x0006) /* Real Timer Temperature Compensation */
4835 #define OFS_RTCTCMP_L OFS_RTCTCMP
4836 #define OFS_RTCTCMP_H OFS_RTCTCMP+1
4837 #define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */
4838 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL
4839 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1
4840 #define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */
4841 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL
4842 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1
4843 #define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */
4844 #define OFS_RTCPS_L OFS_RTCPS
4845 #define OFS_RTCPS_H OFS_RTCPS+1
4846 #define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */
4847 #define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */
4848 #define OFS_RTCTIM0_L OFS_RTCTIM0
4849 #define OFS_RTCTIM0_H OFS_RTCTIM0+1
4850 #define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */
4851 #define OFS_RTCTIM1_L OFS_RTCTIM1
4852 #define OFS_RTCTIM1_H OFS_RTCTIM1+1
4853 #define OFS_RTCDATE (0x0014) /* Real Time Clock Date */
4854 #define OFS_RTCDATE_L OFS_RTCDATE
4855 #define OFS_RTCDATE_H OFS_RTCDATE+1
4856 #define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */
4857 #define OFS_RTCYEAR_L OFS_RTCYEAR
4858 #define OFS_RTCYEAR_H OFS_RTCYEAR+1
4859 #define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */
4860 #define OFS_RTCAMINHR_L OFS_RTCAMINHR
4861 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1
4862 #define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */
4863 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY
4864 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1
4865 #define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */
4866 #define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */
4867 #define OFS_RTCSEC (0x0010)
4868 #define OFS_RTCMIN (0x0011)
4869 #define OFS_RTCHOUR (0x0012)
4870 #define OFS_RTCDOW (0x0013)
4871 #define OFS_RTCDAY (0x0014)
4872 #define OFS_RTCMON (0x0015)
4873 #define OFS_RTCAMIN (0x0018)
4874 #define OFS_RTCAHOUR (0x0019)
4875 #define OFS_RTCADOW (0x001A)
4876 #define OFS_RTCADAY (0x001B)
4877 
4878 #define OFS_RTCTCCTL0 (0x0020) /* Real-Time Clock Time Capture Control Register 0 */
4879 #define OFS_RTCTCCTL1 (0x0021) /* Real-Time Clock Time Capture Control Register 1 */
4880 #define OFS_RTCCAP0CTL (0x0022) /* Tamper Detect Pin 0 Control Register */
4881 #define OFS_RTCCAP1CTL (0x0023) /* Tamper Detect Pin 1 Control Register */
4882 #define OFS_RTCSECBAK0 (0x0030) /* Real-Time Clock Seconds Backup Register 0 */
4883 #define OFS_RTCMINBAK0 (0x0031) /* Real-Time Clock Minutes Backup Register 0 */
4884 #define OFS_RTCHOURBAK0 (0x0032) /* Real-Time Clock Hours Backup Register 0 */
4885 #define OFS_RTCDAYBAK0 (0x0033) /* Real-Time Clock Days Backup Register 0 */
4886 #define OFS_RTCMONBAK0 (0x0034) /* Real-Time Clock Months Backup Register 0 */
4887 #define OFS_RTCYEARBAK0 (0x0036) /* Real-Time Clock year Backup Register 0 */
4888 #define OFS_RTCSECBAK1 (0x0038) /* Real-Time Clock Seconds Backup Register 1 */
4889 #define OFS_RTCMINBAK1 (0x0039) /* Real-Time Clock Minutes Backup Register 1 */
4890 #define OFS_RTCHOURBAK1 (0x003A) /* Real-Time Clock Hours Backup Register 1 */
4891 #define OFS_RTCDAYBAK1 (0x003B) /* Real-Time Clock Days Backup Register 1 */
4892 #define OFS_RTCMONBAK1 (0x003C) /* Real-Time Clock Months Backup Register 1 */
4893 #define OFS_RTCYEARBAK1 (0x003E) /* Real-Time Clock Year Backup Register 1 */
4894 
4895 #define RTCSEC RTCTIM0_L
4896 #define RTCMIN RTCTIM0_H
4897 #define RTCHOUR RTCTIM1_L
4898 #define RTCDOW RTCTIM1_H
4899 #define RTCDAY RTCDATE_L
4900 #define RTCMON RTCDATE_H
4901 #define RTCYEARL RTCYEAR_L
4902 #define RT0PS RTCPS_L
4903 #define RT1PS RTCPS_H
4904 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
4905 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
4906 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
4907 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
4908 
4909 /* RTCCTL0 Control Bits */
4910 #define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4911 #define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
4912 #define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
4913 #define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
4914 #define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4915 #define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
4916 #define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
4917 #define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
4918 
4919 /* RTCCTL0 Control Bits */
4920 #define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
4921 #define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
4922 #define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
4923 #define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
4924 #define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
4925 #define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
4926 #define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
4927 #define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
4928 
4929 #define RTCKEY (0xA500) /* RTC Key for RTC write access */
4930 #define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */
4931 
4932 /* RTCCTL13 Control Bits */
4933 #define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
4934 #define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
4935 #define RTCBCD (0x0080) /* RTC BCD 0:Binary / 1:BCD */
4936 #define RTCHOLD (0x0040) /* RTC Hold */
4937 #define RTCMODE (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
4938 #define RTCRDY (0x0010) /* RTC Ready */
4939 #define RTCSSEL1 (0x0008) /* RTC Source Select 1 */
4940 #define RTCSSEL0 (0x0004) /* RTC Source Select 0 */
4941 #define RTCTEV1 (0x0002) /* RTC Time Event 1 */
4942 #define RTCTEV0 (0x0001) /* RTC Time Event 0 */
4943 
4944 /* RTCCTL13 Control Bits */
4945 #define RTCBCD_L (0x0080) /* RTC BCD 0:Binary / 1:BCD */
4946 #define RTCHOLD_L (0x0040) /* RTC Hold */
4947 #define RTCMODE_L (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
4948 #define RTCRDY_L (0x0010) /* RTC Ready */
4949 #define RTCSSEL1_L (0x0008) /* RTC Source Select 1 */
4950 #define RTCSSEL0_L (0x0004) /* RTC Source Select 0 */
4951 #define RTCTEV1_L (0x0002) /* RTC Time Event 1 */
4952 #define RTCTEV0_L (0x0001) /* RTC Time Event 0 */
4953 
4954 /* RTCCTL13 Control Bits */
4955 #define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
4956 #define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
4957 
4958 #define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */
4959 #define RTCSSEL_1 (0x0004) /* RTC Source Select SMCLK */
4960 #define RTCSSEL_2 (0x0008) /* RTC Source Select RT1PS */
4961 #define RTCSSEL_3 (0x000C) /* RTC Source Select RT1PS */
4962 #define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */
4963 #define RTCSSEL__SMCLK (0x0004) /* RTC Source Select SMCLK */
4964 #define RTCSSEL__RT1PS (0x0008) /* RTC Source Select RT1PS */
4965 
4966 #define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
4967 #define RTCTEV_1 (0x0001) /* RTC Time Event: 1 (Hour changed) */
4968 #define RTCTEV_2 (0x0002) /* RTC Time Event: 2 (12:00 changed) */
4969 #define RTCTEV_3 (0x0003) /* RTC Time Event: 3 (00:00 changed) */
4970 #define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
4971 #define RTCTEV__HOUR (0x0001) /* RTC Time Event: 1 (Hour changed) */
4972 #define RTCTEV__0000 (0x0002) /* RTC Time Event: 2 (00:00 changed) */
4973 #define RTCTEV__1200 (0x0003) /* RTC Time Event: 3 (12:00 changed) */
4974 
4975 #define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
4976 #define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
4977 #define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
4978 #define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
4979 
4980 /* RTCOCAL Control Bits */
4981 #define RTCOCALS (0x8000) /* RTC Offset Calibration Sign */
4982 #define RTCOCAL7 (0x0080) /* RTC Offset Calibration Bit 7 */
4983 #define RTCOCAL6 (0x0040) /* RTC Offset Calibration Bit 6 */
4984 #define RTCOCAL5 (0x0020) /* RTC Offset Calibration Bit 5 */
4985 #define RTCOCAL4 (0x0010) /* RTC Offset Calibration Bit 4 */
4986 #define RTCOCAL3 (0x0008) /* RTC Offset Calibration Bit 3 */
4987 #define RTCOCAL2 (0x0004) /* RTC Offset Calibration Bit 2 */
4988 #define RTCOCAL1 (0x0002) /* RTC Offset Calibration Bit 1 */
4989 #define RTCOCAL0 (0x0001) /* RTC Offset Calibration Bit 0 */
4990 
4991 /* RTCOCAL Control Bits */
4992 #define RTCOCAL7_L (0x0080) /* RTC Offset Calibration Bit 7 */
4993 #define RTCOCAL6_L (0x0040) /* RTC Offset Calibration Bit 6 */
4994 #define RTCOCAL5_L (0x0020) /* RTC Offset Calibration Bit 5 */
4995 #define RTCOCAL4_L (0x0010) /* RTC Offset Calibration Bit 4 */
4996 #define RTCOCAL3_L (0x0008) /* RTC Offset Calibration Bit 3 */
4997 #define RTCOCAL2_L (0x0004) /* RTC Offset Calibration Bit 2 */
4998 #define RTCOCAL1_L (0x0002) /* RTC Offset Calibration Bit 1 */
4999 #define RTCOCAL0_L (0x0001) /* RTC Offset Calibration Bit 0 */
5000 
5001 /* RTCOCAL Control Bits */
5002 #define RTCOCALS_H (0x0080) /* RTC Offset Calibration Sign */
5003 
5004 /* RTCTCMP Control Bits */
5005 #define RTCTCMPS (0x8000) /* RTC Temperature Compensation Sign */
5006 #define RTCTCRDY (0x4000) /* RTC Temperature compensation ready */
5007 #define RTCTCOK (0x2000) /* RTC Temperature compensation write OK */
5008 #define RTCTCMP7 (0x0080) /* RTC Temperature Compensation Bit 7 */
5009 #define RTCTCMP6 (0x0040) /* RTC Temperature Compensation Bit 6 */
5010 #define RTCTCMP5 (0x0020) /* RTC Temperature Compensation Bit 5 */
5011 #define RTCTCMP4 (0x0010) /* RTC Temperature Compensation Bit 4 */
5012 #define RTCTCMP3 (0x0008) /* RTC Temperature Compensation Bit 3 */
5013 #define RTCTCMP2 (0x0004) /* RTC Temperature Compensation Bit 2 */
5014 #define RTCTCMP1 (0x0002) /* RTC Temperature Compensation Bit 1 */
5015 #define RTCTCMP0 (0x0001) /* RTC Temperature Compensation Bit 0 */
5016 
5017 /* RTCTCMP Control Bits */
5018 #define RTCTCMP7_L (0x0080) /* RTC Temperature Compensation Bit 7 */
5019 #define RTCTCMP6_L (0x0040) /* RTC Temperature Compensation Bit 6 */
5020 #define RTCTCMP5_L (0x0020) /* RTC Temperature Compensation Bit 5 */
5021 #define RTCTCMP4_L (0x0010) /* RTC Temperature Compensation Bit 4 */
5022 #define RTCTCMP3_L (0x0008) /* RTC Temperature Compensation Bit 3 */
5023 #define RTCTCMP2_L (0x0004) /* RTC Temperature Compensation Bit 2 */
5024 #define RTCTCMP1_L (0x0002) /* RTC Temperature Compensation Bit 1 */
5025 #define RTCTCMP0_L (0x0001) /* RTC Temperature Compensation Bit 0 */
5026 
5027 /* RTCTCMP Control Bits */
5028 #define RTCTCMPS_H (0x0080) /* RTC Temperature Compensation Sign */
5029 #define RTCTCRDY_H (0x0040) /* RTC Temperature compensation ready */
5030 #define RTCTCOK_H (0x0020) /* RTC Temperature compensation write OK */
5031 
5032 #define RTCAE (0x80) /* Real Time Clock Alarm enable */
5033 
5034 /* RTCPS0CTL Control Bits */
5035 //#define Reserved (0x8000)
5036 //#define Reserved (0x4000)
5037 #define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
5038 #define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
5039 #define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
5040 //#define Reserved (0x0400)
5041 //#define Reserved (0x0200)
5042 #define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */
5043 //#define Reserved (0x0080)
5044 //#define Reserved (0x0040)
5045 //#define Reserved (0x0020)
5046 #define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
5047 #define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
5048 #define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
5049 #define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
5050 #define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
5051 
5052 /* RTCPS0CTL Control Bits */
5053 //#define Reserved (0x8000)
5054 //#define Reserved (0x4000)
5055 //#define Reserved (0x0400)
5056 //#define Reserved (0x0200)
5057 //#define Reserved (0x0080)
5058 //#define Reserved (0x0040)
5059 //#define Reserved (0x0020)
5060 #define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
5061 #define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
5062 #define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
5063 #define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
5064 #define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
5065 
5066 /* RTCPS0CTL Control Bits */
5067 //#define Reserved (0x8000)
5068 //#define Reserved (0x4000)
5069 #define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
5070 #define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
5071 #define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
5072 //#define Reserved (0x0400)
5073 //#define Reserved (0x0200)
5074 #define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */
5075 //#define Reserved (0x0080)
5076 //#define Reserved (0x0040)
5077 //#define Reserved (0x0020)
5078 
5079 #define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
5080 #define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
5081 #define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
5082 #define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
5083 #define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
5084 #define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
5085 #define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
5086 #define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
5087 
5088 /* RTCPS1CTL Control Bits */
5089 #define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */
5090 #define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */
5091 #define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
5092 #define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
5093 #define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
5094 //#define Reserved (0x0400)
5095 //#define Reserved (0x0200)
5096 #define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */
5097 //#define Reserved (0x0080)
5098 //#define Reserved (0x0040)
5099 //#define Reserved (0x0020)
5100 #define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
5101 #define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
5102 #define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
5103 #define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
5104 #define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
5105 
5106 /* RTCPS1CTL Control Bits */
5107 //#define Reserved (0x0400)
5108 //#define Reserved (0x0200)
5109 //#define Reserved (0x0080)
5110 //#define Reserved (0x0040)
5111 //#define Reserved (0x0020)
5112 #define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
5113 #define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
5114 #define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
5115 #define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
5116 #define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
5117 
5118 /* RTCPS1CTL Control Bits */
5119 #define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */
5120 #define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */
5121 #define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
5122 #define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
5123 #define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
5124 //#define Reserved (0x0400)
5125 //#define Reserved (0x0200)
5126 #define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */
5127 //#define Reserved (0x0080)
5128 //#define Reserved (0x0040)
5129 //#define Reserved (0x0020)
5130 
5131 #define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
5132 #define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
5133 #define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
5134 #define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
5135 #define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
5136 #define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
5137 #define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
5138 #define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
5139 
5140 /* RTCTCCTL0 Control Bits */
5141 #define TCEN (0x0001) /* RTC Enable for RTC Tamper Detection with Time Stamp */
5142 #define AUX3RST (0x0002) /* RTC Indication of power cycle on AUXVCC3 */
5143 
5144 /* RTCTCCTL1 Control Bits */
5145 #define RTCCAPIFG (0x0001) /* RTC Tamper Event Interrupt Flag */
5146 #define RTCCAPIE (0x0002) /* RTC Tamper Event Interrupt Enable */
5147 
5148 /* RTCCAPxCTL Control Bits */
5149 #define CAPEV (0x0001) /* RTC Tamper Event Flag */
5150 #define CAPES (0x0004) /* RTC Event Edge Select */
5151 #define RTCREN (0x0008) /* RTC RTCCAPx pin pullup/pulldown resistor enable */
5152 #define RTCCAPIN (0x0010) /* RTC RTCCAPx input */
5153 #define RTCCAPDIR (0x0020) /* RTC RTCCAPx Pin direction */
5154 #define RTCCAPOUT (0x0040) /* RTC RTCCAPx Output */
5155 
5156 /* RTCIV Definitions */
5157 #define RTCIV_NONE (0x0000) /* No Interrupt pending */
5158 #define RTCIV_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */
5159 #define RTCIV_RTCCAPIFG (0x0004) /* RTC RTC Tamper Event: RTCCAPIFG */
5160 #define RTCIV_RTCRDYIFG (0x0006) /* RTC ready: RTCRDYIFG */
5161 #define RTCIV_RTCTEVIFG (0x0008) /* RTC interval timer: RTCTEVIFG */
5162 #define RTCIV_RTCAIFG (0x000A) /* RTC user alarm: RTCAIFG */
5163 #define RTCIV_RT0PSIFG (0x000C) /* RTC prescaler 0: RT0PSIFG */
5164 #define RTCIV_RT1PSIFG (0x000E) /* RTC prescaler 1: RT1PSIFG */
5165 
5166 /* Legacy RTCIV Definitions */
5167 #define RTC_NONE (0x0000) /* No Interrupt pending */
5168 #define RTC_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */
5169 #define RTC_RTCRDYIFG (0x0006) /* RTC ready: RTCRDYIFG */
5170 #define RTC_RTCTEVIFG (0x0008) /* RTC interval timer: RTCTEVIFG */
5171 #define RTC_RTCAIFG (0x000A) /* RTC user alarm: RTCAIFG */
5172 #define RTC_RT0PSIFG (0x000C) /* RTC prescaler 0: RT0PSIFG */
5173 #define RTC_RT1PSIFG (0x000E) /* RTC prescaler 1: RT1PSIFG */
5174 
5175 #endif
5176 /************************************************************
5177 * SD24_B - Sigma Delta 24 Bit
5178 ************************************************************/
5179 #ifdef __MSP430_HAS_SD24_B__ /* Definition to show that Module is available */
5180 
5181 #define OFS_SD24BCTL0 (0x0000) /* SD24B Control Register 0 */
5182 #define OFS_SD24BCTL0_L OFS_SD24BCTL0
5183 #define OFS_SD24BCTL0_H OFS_SD24BCTL0+1
5184 #define OFS_SD24BCTL1 (0x0002) /* SD24B Control Register 1 */
5185 #define OFS_SD24BCTL1_L OFS_SD24BCTL1
5186 #define OFS_SD24BCTL1_H OFS_SD24BCTL1+1
5187 #define OFS_SD24BTRGCTL (0x0004) /* SD24B Trigger Control Register */
5188 #define OFS_SD24BTRGCTL_L OFS_SD24BTRGCTL
5189 #define OFS_SD24BTRGCTL_H OFS_SD24BTRGCTL+1
5190 #define OFS_SD24BTRGOSR (0x0006) /* SD24B Trigger OSR Control Register */
5191 #define OFS_SD24BTRGOSR_L OFS_SD24BTRGOSR
5192 #define OFS_SD24BTRGOSR_H OFS_SD24BTRGOSR+1
5193 #define OFS_SD24BTRGPRE (0x0008) /* SD24B Trigger Preload Register */
5194 #define OFS_SD24BTRGPRE_L OFS_SD24BTRGPRE
5195 #define OFS_SD24BTRGPRE_H OFS_SD24BTRGPRE+1
5196 #define OFS_SD24BIFG (0x000A) /* SD24B Interrupt Flag Register */
5197 #define OFS_SD24BIFG_L OFS_SD24BIFG
5198 #define OFS_SD24BIFG_H OFS_SD24BIFG+1
5199 #define OFS_SD24BIE (0x000C) /* SD24B Interrupt Enable Register */
5200 #define OFS_SD24BIE_L OFS_SD24BIE
5201 #define OFS_SD24BIE_H OFS_SD24BIE+1
5202 #define OFS_SD24BIV (0x000E) /* SD24B Interrupt Vector Register */
5203 #define OFS_SD24BIV_L OFS_SD24BIV
5204 #define OFS_SD24BIV_H OFS_SD24BIV+1
5205 
5206 #define OFS_SD24BCCTL0 (0x0010) /* SD24B Channel 0 Control Register */
5207 #define OFS_SD24BCCTL0_L OFS_SD24BCCTL0
5208 #define OFS_SD24BCCTL0_H OFS_SD24BCCTL0+1
5209 #define OFS_SD24BINCTL0 (0x0012) /* SD24B Channel 0 Input Control Register */
5210 #define OFS_SD24BINCTL0_L OFS_SD24BINCTL0
5211 #define OFS_SD24BINCTL0_H OFS_SD24BINCTL0+1
5212 #define OFS_SD24BOSR0 (0x0014) /* SD24B Channel 0 OSR Control Register */
5213 #define OFS_SD24BOSR0_L OFS_SD24BOSR0
5214 #define OFS_SD24BOSR0_H OFS_SD24BOSR0+1
5215 #define OFS_SD24BPRE0 (0x0016) /* SD24B Channel 0 Preload Register */
5216 #define OFS_SD24BPRE0_L OFS_SD24BPRE0
5217 #define OFS_SD24BPRE0_H OFS_SD24BPRE0+1
5218 
5219 #define OFS_SD24BMEML0 (0x0050) /* SD24B Channel 0 Conversion Memory Low word */
5220 #define OFS_SD24BMEML0_L OFS_SD24BMEML0
5221 #define OFS_SD24BMEML0_H OFS_SD24BMEML0+1
5222 #define OFS_SD24BMEMH0 (0x0052) /* SD24B Channel 0 Conversion Memory High Word */
5223 #define OFS_SD24BMEMH0_L OFS_SD24BMEMH0
5224 #define OFS_SD24BMEMH0_H OFS_SD24BMEMH0+1
5225 
5226 /* SD24BCTL0 */
5227 #define SD24OV32 (0x0002) /* SD24B Overflow Control */
5228 #define SD24REFS (0x0004) /* SD24B Reference Select */
5229 #define SD24SSEL0 (0x0010) /* SD24B Clock Source Select 0 */
5230 #define SD24SSEL1 (0x0020) /* SD24B Clock Source Select 1 */
5231 #define SD24M4 (0x0040) /* SD24B Modulator clock to Manchester decoder clock ratio */
5232 #define SD24CLKOS (0x0080) /* SD24B Clock Output Select */
5233 #define SD24PDIV0 (0x0100) /* SD24B Frequency pre-scaler Bit 0 */
5234 #define SD24PDIV1 (0x0200) /* SD24B Frequency pre-scaler Bit 1 */
5235 #define SD24PDIV2 (0x0400) /* SD24B Frequency pre-scaler Bit 2 */
5236 #define SD24DIV0 (0x0800) /* SD24B Frequency Divider Bit 0 */
5237 #define SD24DIV1 (0x1000) /* SD24B Frequency Divider Bit 1 */
5238 #define SD24DIV2 (0x2000) /* SD24B Frequency Divider Bit 2 */
5239 #define SD24DIV3 (0x4000) /* SD24B Frequency Divider Bit 3 */
5240 #define SD24DIV4 (0x8000) /* SD24B Frequency Divider Bit 4 */
5241 
5242 #define SD24OV32_L (0x0002) /* SD24B Overflow Control */
5243 #define SD24REFS_L (0x0004) /* SD24B Reference Select */
5244 #define SD24SSEL0_L (0x0010) /* SD24B Clock Source Select 0 */
5245 #define SD24SSEL1_L (0x0020) /* SD24B Clock Source Select 1 */
5246 #define SD24M4_L (0x0040) /* SD24B Modulator clock to Manchester decoder clock ratio */
5247 #define SD24CLKOS_L (0x0080) /* SD24B Clock Output Select */
5248 
5249 #define SD24PDIV0_H (0x0001) /* SD24B Frequency pre-scaler Bit 0 */
5250 #define SD24PDIV1_H (0x0002) /* SD24B Frequency pre-scaler Bit 1 */
5251 #define SD24PDIV2_H (0x0004) /* SD24B Frequency pre-scaler Bit 2 */
5252 #define SD24DIV0_H (0x0008) /* SD24B Frequency Divider Bit 0 */
5253 #define SD24DIV1_H (0x0010) /* SD24B Frequency Divider Bit 1 */
5254 #define SD24DIV2_H (0x0020) /* SD24B Frequency Divider Bit 2 */
5255 #define SD24DIV3_H (0x0040) /* SD24B Frequency Divider Bit 3 */
5256 #define SD24DIV4_H (0x0080) /* SD24B Frequency Divider Bit 4 */
5257 
5258 #define SD24SSEL_0 (0x0000) /* SD24B Clock Source Select MCLK */
5259 #define SD24SSEL_1 (0x0010) /* SD24B Clock Source Select SMCLK */
5260 #define SD24SSEL_2 (0x0020) /* SD24B Clock Source Select ACLK */
5261 #define SD24SSEL_3 (0x0030) /* SD24B Clock Source Select TACLK */
5262 #define SD24SSEL__MCLK (0x0000) /* SD24B Clock Source Select MCLK */
5263 #define SD24SSEL__SMCLK (0x0010) /* SD24B Clock Source Select SMCLK */
5264 #define SD24SSEL__ACLK (0x0020) /* SD24B Clock Source Select ACLK */
5265 #define SD24SSEL__SD24CLK (0x0030) /* SD24B Clock Source Select SD24CLK */
5266 
5267 #define SD24PDIV_0 (0x0000) /* SD24B Frequency pre-scaler /1 */
5268 #define SD24PDIV_1 (0x0100) /* SD24B Frequency pre-scaler /2 */
5269 #define SD24PDIV_2 (0x0200) /* SD24B Frequency pre-scaler /4 */
5270 #define SD24PDIV_3 (0x0300) /* SD24B Frequency pre-scaler /8 */
5271 #define SD24PDIV_4 (0x0400) /* SD24B Frequency pre-scaler /16 */
5272 #define SD24PDIV_5 (0x0500) /* SD24B Frequency pre-scaler /32 */
5273 #define SD24PDIV_6 (0x0600) /* SD24B Frequency pre-scaler /64 */
5274 #define SD24PDIV_7 (0x0700) /* SD24B Frequency pre-scaler /128 */
5275 
5276 /* SD24BCTL1 */
5277 #define SD24GRP0SC (0x0001) /* SD24B Group 0 Start Conversion */
5278 #define SD24GRP1SC (0x0002) /* SD24B Group 1 Start Conversion */
5279 #define SD24GRP2SC (0x0004) /* SD24B Group 2 Start Conversion */
5280 #define SD24GRP3SC (0x0008) /* SD24B Group 3 Start Conversion */
5281 #define SD24DMA0 (0x0100) /* SD24B DMA Trigger Select Bit 0 */
5282 #define SD24DMA1 (0x0200) /* SD24B DMA Trigger Select Bit 1 */
5283 #define SD24DMA2 (0x0400) /* SD24B DMA Trigger Select Bit 2 */
5284 #define SD24DMA3 (0x0800) /* SD24B DMA Trigger Select Bit 3 */
5285 
5286 #define SD24GRP0SC_L (0x0001) /* SD24B Group 0 Start Conversion */
5287 #define SD24GRP1SC_L (0x0002) /* SD24B Group 1 Start Conversion */
5288 #define SD24GRP2SC_L (0x0004) /* SD24B Group 2 Start Conversion */
5289 #define SD24GRP3SC_L (0x0008) /* SD24B Group 3 Start Conversion */
5290 
5291 #define SD24DMA0_H (0x0001) /* SD24B DMA Trigger Select Bit 0 */
5292 #define SD24DMA1_H (0x0002) /* SD24B DMA Trigger Select Bit 1 */
5293 #define SD24DMA2_H (0x0004) /* SD24B DMA Trigger Select Bit 2 */
5294 #define SD24DMA3_H (0x0008) /* SD24B DMA Trigger Select Bit 3 */
5295 
5296 #define SD24DMA_0 (0x0000) /* SD24B DMA Trigger: 0 */
5297 #define SD24DMA_1 (0x0100) /* SD24B DMA Trigger: 1 */
5298 #define SD24DMA_2 (0x0200) /* SD24B DMA Trigger: 2 */
5299 #define SD24DMA_3 (0x0300) /* SD24B DMA Trigger: 3 */
5300 #define SD24DMA_4 (0x0400) /* SD24B DMA Trigger: 4 */
5301 #define SD24DMA_5 (0x0500) /* SD24B DMA Trigger: 5 */
5302 #define SD24DMA_6 (0x0600) /* SD24B DMA Trigger: 6 */
5303 #define SD24DMA_7 (0x0700) /* SD24B DMA Trigger: 7 */
5304 #define SD24DMA_8 (0x0800) /* SD24B DMA Trigger: 8 */
5305 
5306 /* SD24BTRGCTL */
5307 #define SD24SC (0x0001) /* SD24B Start Conversion */
5308 #define SD24SCS0 (0x0002) /* SD24B Start Conversion Select Bit 0 */
5309 #define SD24SCS1 (0x0004) /* SD24B Start Conversion Select Bit 1 */
5310 #define SD24SCS2 (0x0008) /* SD24B Start Conversion Select Bit 2 */
5311 #define SD24SNGL (0x0100) /* SD24B Single Trigger Mode */
5312 #define SD24TRGIFG (0x0400) /* SD24B Trigger Interrupt Flag */
5313 #define SD24TRGIE (0x0800) /* SD24B Trigger Interrupt Enable */
5314 
5315 #define SD24SC_L (0x0001) /* SD24B Start Conversion */
5316 #define SD24SCS0_L (0x0002) /* SD24B Start Conversion Select Bit 0 */
5317 #define SD24SCS1_L (0x0004) /* SD24B Start Conversion Select Bit 1 */
5318 #define SD24SCS2_L (0x0008) /* SD24B Start Conversion Select Bit 2 */
5319 
5320 #define SD24SNGL_H (0x0001) /* SD24B Single Trigger Mode */
5321 #define SD24TRGIFG_H (0x0004) /* SD24B Trigger Interrupt Flag */
5322 #define SD24TRGIE_H (0x0008) /* SD24B Trigger Interrupt Enable */
5323 
5324 #define SD24SCS_0 (0x0000) /* SD24B Start Conversion Select: 0 */
5325 #define SD24SCS_1 (0x0002) /* SD24B Start Conversion Select: 1 */
5326 #define SD24SCS_2 (0x0004) /* SD24B Start Conversion Select: 2 */
5327 #define SD24SCS_3 (0x0006) /* SD24B Start Conversion Select: 3 */
5328 #define SD24SCS_4 (0x0008) /* SD24B Start Conversion Select: 4 */
5329 #define SD24SCS_5 (0x000A) /* SD24B Start Conversion Select: 5 */
5330 #define SD24SCS_6 (0x000C) /* SD24B Start Conversion Select: 6 */
5331 #define SD24SCS_7 (0x000E) /* SD24B Start Conversion Select: 7 */
5332 #define SD24SCS__SD24SC (0x0000) /* SD24B Start Conversion Select: SD24SC */
5333 #define SD24SCS__EXT1 (0x0002) /* SD24B Start Conversion Select: EXT1 */
5334 #define SD24SCS__EXT2 (0x0004) /* SD24B Start Conversion Select: EXT2 */
5335 #define SD24SCS__EXT3 (0x0006) /* SD24B Start Conversion Select: EXT3 */
5336 #define SD24SCS__GROUP0 (0x0008) /* SD24B Start Conversion Select: GROUP0 */
5337 #define SD24SCS__GROUP1 (0x000A) /* SD24B Start Conversion Select: GROUP1 */
5338 #define SD24SCS__GROUP2 (0x000C) /* SD24B Start Conversion Select: GROUP2 */
5339 #define SD24SCS__GROUP3 (0x000E) /* SD24B Start Conversion Select: GROUP3 */
5340 
5341 /* SD24BIFG */
5342 #define SD24IFG0 (0x0001) /* SD24B Channel 0 Interrupt Flag */
5343 #define SD24OVIFG0 (0x0100) /* SD24B Channel 0 Overflow Interrupt Flag */
5344 
5345 #define SD24IFG0_L (0x0001) /* SD24B Channel 0 Interrupt Flag */
5346 
5347 #define SD24OVIFG0_H (0x0001) /* SD24B Channel 0 Overflow Interrupt Flag */
5348 
5349 /* SD24BIE */
5350 #define SD24IE0 (0x0001) /* SD24B Channel 0 Interrupt Enable */
5351 #define SD24OVIE0 (0x0100) /* SD24B Channel 0 Overflow Interrupt Enable */
5352 
5353 #define SD24IE0_L (0x0001) /* SD24B Channel 0 Interrupt Enable */
5354 
5355 #define SD24OVIE0_H (0x0001) /* SD24B Channel 0 Overflow Interrupt Enable */
5356 
5357 /* SD24BIV Definitions */
5358 #define SD24BIV_NONE (0x0000) /* No Interrupt pending */
5359 #define SD24BIV_SD24OVIFG (0x0002) /* SD24OVIFG */
5360 #define SD24BIV_SD24TRGIFG (0x0004) /* SD24TRGIFG */
5361 #define SD24BIV_SD24IFG0 (0x0006) /* SD24IFG0 */
5362 
5363 /* SD24BCCTLx */
5364 #define SD24DF0 (0x0010) /* SD24B Data Format Bit: 0 */
5365 #define SD24DF1 (0x0020) /* SD24B Data Format Bit: 1 */
5366 #define SD24ALGN (0x0040) /* SD24B Data Alignment */
5367 #define SD24CAL (0x0200) /* SD24B Calibration */
5368 #define SD24DFS0 (0x0400) /* SD24B Digital Filter Bit: 0 */
5369 #define SD24DFS1 (0x0800) /* SD24B Digital Filter Bit: 1 */
5370 #define SD24DI (0x1000) /* SD24B Digital Bitstream Input */
5371 #define SD24MC0 (0x2000) /* SD24B Manchaster Encoding Bit: 0 */
5372 #define SD24MC1 (0x4000) /* SD24B Manchaster Encoding Bit: 1 */
5373 
5374 #define SD24DF0_L (0x0010) /* SD24B Data Format Bit: 0 */
5375 #define SD24DF1_L (0x0020) /* SD24B Data Format Bit: 1 */
5376 #define SD24ALGN_L (0x0040) /* SD24B Data Alignment */
5377 
5378 #define SD24CAL_H (0x0002) /* SD24B Calibration */
5379 #define SD24DFS0_H (0x0004) /* SD24B Digital Filter Bit: 0 */
5380 #define SD24DFS1_H (0x0008) /* SD24B Digital Filter Bit: 1 */
5381 #define SD24DI_H (0x0010) /* SD24B Digital Bitstream Input */
5382 #define SD24MC0_H (0x0020) /* SD24B Manchaster Encoding Bit: 0 */
5383 #define SD24MC1_H (0x0040) /* SD24B Manchaster Encoding Bit: 1 */
5384 
5385 #define SD24DF_0 (0x0000) /* SD24B Data Format: Offset Binary */
5386 #define SD24DF_1 (0x0010) /* SD24B Data Format: 2's complement */
5387 
5388 #define SD24DFS_0 (0x0000) /* SD24B Digital Filter 0 */
5389 #define SD24DFS_1 (0x0400) /* SD24B Digital Filter 1 */
5390 #define SD24DFS_2 (0x0800) /* SD24B Digital Filter 2 */
5391 #define SD24DFS_3 (0x0C00) /* SD24B Digital Filter 3 */
5392 
5393 #define SD24MC_0 (0x0000) /* SD24B Manchaster Encoding 0 */
5394 #define SD24MC_1 (0x2000) /* SD24B Manchaster Encoding 1 */
5395 #define SD24MC_2 (0x4000) /* SD24B Manchaster Encoding 2 */
5396 #define SD24MC_3 (0x6000) /* SD24B Manchaster Encoding 3 */
5397 
5398 /* SD24BINCTLx */
5399 #define SD24GAIN0 (0x0008) /* SD24B Input Pre-Amplifier Gain Select 0 */
5400 #define SD24GAIN1 (0x0010) /* SD24B Input Pre-Amplifier Gain Select 1 */
5401 #define SD24GAIN2 (0x0020) /* SD24B Input Pre-Amplifier Gain Select 2 */
5402 #define SD24INTDLY0 (0x0040) /* SD24B Interrupt Delay after 1.Conversion 0 */
5403 #define SD24INTDLY1 (0x0080) /* SD24B Interrupt Delay after 1.Conversion 1 */
5404 
5405 #define SD24GAIN0_L (0x0008) /* SD24B Input Pre-Amplifier Gain Select 0 */
5406 #define SD24GAIN1_L (0x0010) /* SD24B Input Pre-Amplifier Gain Select 1 */
5407 #define SD24GAIN2_L (0x0020) /* SD24B Input Pre-Amplifier Gain Select 2 */
5408 #define SD24INTDLY0_L (0x0040) /* SD24B Interrupt Delay after 1.Conversion 0 */
5409 #define SD24INTDLY1_L (0x0080) /* SD24B Interrupt Delay after 1.Conversion 1 */
5410 
5411 #define SD24GAIN_1 (0x0000) /* SD24B Input Pre-Amplifier Gain Select *1 */
5412 #define SD24GAIN_2 (0x0008) /* SD24B Input Pre-Amplifier Gain Select *2 */
5413 #define SD24GAIN_4 (0x0010) /* SD24B Input Pre-Amplifier Gain Select *4 */
5414 #define SD24GAIN_8 (0x0018) /* SD24B Input Pre-Amplifier Gain Select *8 */
5415 #define SD24GAIN_16 (0x0020) /* SD24B Input Pre-Amplifier Gain Select *16 */
5416 #define SD24GAIN_32 (0x0028) /* SD24B Input Pre-Amplifier Gain Select *32 */
5417 #define SD24GAIN_64 (0x0030) /* SD24B Input Pre-Amplifier Gain Select *64 */
5418 #define SD24GAIN_128 (0x0038) /* SD24B Input Pre-Amplifier Gain Select *128 */
5419 
5420 #define SD24INTDLY_0 (0x0000) /* SD24B Interrupt Delay: Int. after 4.Conversion */
5421 #define SD24INTDLY_1 (0x0040) /* SD24B Interrupt Delay: Int. after 3.Conversion */
5422 #define SD24INTDLY_2 (0x0080) /* SD24B Interrupt Delay: Int. after 2.Conversion */
5423 #define SD24INTDLY_3 (0x00C0) /* SD24B Interrupt Delay: Int. after 1.Conversion */
5424 
5425 /* SD24BOSRx */
5426 #define OSR0 (0x0001) /* SD24B Oversampling Rate Bit: 0 */
5427 #define OSR1 (0x0002) /* SD24B Oversampling Rate Bit: 1 */
5428 #define OSR2 (0x0004) /* SD24B Oversampling Rate Bit: 2 */
5429 #define OSR3 (0x0008) /* SD24B Oversampling Rate Bit: 3 */
5430 #define OSR4 (0x0010) /* SD24B Oversampling Rate Bit: 4 */
5431 #define OSR5 (0x0020) /* SD24B Oversampling Rate Bit: 5 */
5432 #define OSR6 (0x0040) /* SD24B Oversampling Rate Bit: 6 */
5433 #define OSR7 (0x0080) /* SD24B Oversampling Rate Bit: 7 */
5434 #define OSR8 (0x0100) /* SD24B Oversampling Rate Bit: 8 */
5435 #define OSR9 (0x0200) /* SD24B Oversampling Rate Bit: 9 */
5436 #define OSR10 (0x0400) /* SD24B Oversampling Rate Bit: 10 */
5437 
5438 #define OSR0_L (0x0001) /* SD24B Oversampling Rate Bit: 0 */
5439 #define OSR1_L (0x0002) /* SD24B Oversampling Rate Bit: 1 */
5440 #define OSR2_L (0x0004) /* SD24B Oversampling Rate Bit: 2 */
5441 #define OSR3_L (0x0008) /* SD24B Oversampling Rate Bit: 3 */
5442 #define OSR4_L (0x0010) /* SD24B Oversampling Rate Bit: 4 */
5443 #define OSR5_L (0x0020) /* SD24B Oversampling Rate Bit: 5 */
5444 #define OSR6_L (0x0040) /* SD24B Oversampling Rate Bit: 6 */
5445 #define OSR7_L (0x0080) /* SD24B Oversampling Rate Bit: 7 */
5446 
5447 #define OSR8_H (0x0001) /* SD24B Oversampling Rate Bit: 8 */
5448 #define OSR9_H (0x0002) /* SD24B Oversampling Rate Bit: 9 */
5449 #define OSR10_H (0x0004) /* SD24B Oversampling Rate Bit: 10 */
5450 
5451 /* SD24BTRGOSR */
5452 
5453 #define OSR__32 (32-1) /* SD24B Oversampling Rate: 32 */
5454 #define OSR__64 (64-1) /* SD24B Oversampling Rate: 64 */
5455 #define OSR__128 (128-1) /* SD24B Oversampling Rate: 128 */
5456 #define OSR__256 (256-1) /* SD24B Oversampling Rate: 256 */
5457 #define OSR__512 (512-1) /* SD24B Oversampling Rate: 512 */
5458 #define OSR__1024 (1024-1) /* SD24B Oversampling Rate: 1024 */
5459 
5460 
5461 #endif
5462 /************************************************************
5463 * SFR - Special Function Register Module
5464 ************************************************************/
5465 #ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */
5466 
5467 #define OFS_SFRIE1 (0x0000) /* Interrupt Enable 1 */
5468 #define OFS_SFRIE1_L OFS_SFRIE1
5469 #define OFS_SFRIE1_H OFS_SFRIE1+1
5470 
5471 /* SFRIE1 Control Bits */
5472 #define WDTIE (0x0001) /* WDT Interrupt Enable */
5473 #define OFIE (0x0002) /* Osc Fault Enable */
5474 //#define Reserved (0x0004)
5475 #define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */
5476 #define NMIIE (0x0010) /* NMI Interrupt Enable */
5477 #ifndef ACCVIE
5478 #define ACCVIE (0x0020) /* Flash Access Violation Interrupt Enable */
5479 #endif
5480 #define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */
5481 #define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */
5482 
5483 #define WDTIE_L (0x0001) /* WDT Interrupt Enable */
5484 #define OFIE_L (0x0002) /* Osc Fault Enable */
5485 //#define Reserved (0x0004)
5486 #define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */
5487 #define NMIIE_L (0x0010) /* NMI Interrupt Enable */
5488 #ifndef ACCVIE
5489 #define ACCVIE_L (0x0020) /* Flash Access Violation Interrupt Enable */
5490 #endif
5491 #define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */
5492 #define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */
5493 
5494 #define OFS_SFRIFG1 (0x0002) /* Interrupt Flag 1 */
5495 #define OFS_SFRIFG1_L OFS_SFRIFG1
5496 #define OFS_SFRIFG1_H OFS_SFRIFG1+1
5497 /* SFRIFG1 Control Bits */
5498 #define WDTIFG (0x0001) /* WDT Interrupt Flag */
5499 #define OFIFG (0x0002) /* Osc Fault Flag */
5500 //#define Reserved (0x0004)
5501 #define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */
5502 #define NMIIFG (0x0010) /* NMI Interrupt Flag */
5503 //#define Reserved (0x0020)
5504 #define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */
5505 #define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */
5506 
5507 #define WDTIFG_L (0x0001) /* WDT Interrupt Flag */
5508 #define OFIFG_L (0x0002) /* Osc Fault Flag */
5509 //#define Reserved (0x0004)
5510 #define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */
5511 #define NMIIFG_L (0x0010) /* NMI Interrupt Flag */
5512 //#define Reserved (0x0020)
5513 #define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */
5514 #define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */
5515 
5516 #define OFS_SFRRPCR (0x0004) /* RESET Pin Control Register */
5517 #define OFS_SFRRPCR_L OFS_SFRRPCR
5518 #define OFS_SFRRPCR_H OFS_SFRRPCR+1
5519 /* SFRRPCR Control Bits */
5520 #define SYSNMI (0x0001) /* NMI select */
5521 #define SYSNMIIES (0x0002) /* NMI edge select */
5522 #define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */
5523 #define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */
5524 
5525 #define SYSNMI_L (0x0001) /* NMI select */
5526 #define SYSNMIIES_L (0x0002) /* NMI edge select */
5527 #define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */
5528 #define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */
5529 
5530 #endif
5531 /************************************************************
5532 * SYS - System Module
5533 ************************************************************/
5534 #ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */
5535 
5536 #define OFS_SYSCTL (0x0000) /* System control */
5537 #define OFS_SYSCTL_L OFS_SYSCTL
5538 #define OFS_SYSCTL_H OFS_SYSCTL+1
5539 #define OFS_SYSBSLC (0x0002) /* Boot strap configuration area */
5540 #define OFS_SYSBSLC_L OFS_SYSBSLC
5541 #define OFS_SYSBSLC_H OFS_SYSBSLC+1
5542 #define OFS_SYSJMBC (0x0006) /* JTAG mailbox control */
5543 #define OFS_SYSJMBC_L OFS_SYSJMBC
5544 #define OFS_SYSJMBC_H OFS_SYSJMBC+1
5545 #define OFS_SYSJMBI0 (0x0008) /* JTAG mailbox input 0 */
5546 #define OFS_SYSJMBI0_L OFS_SYSJMBI0
5547 #define OFS_SYSJMBI0_H OFS_SYSJMBI0+1
5548 #define OFS_SYSJMBI1 (0x000A) /* JTAG mailbox input 1 */
5549 #define OFS_SYSJMBI1_L OFS_SYSJMBI1
5550 #define OFS_SYSJMBI1_H OFS_SYSJMBI1+1
5551 #define OFS_SYSJMBO0 (0x000C) /* JTAG mailbox output 0 */
5552 #define OFS_SYSJMBO0_L OFS_SYSJMBO0
5553 #define OFS_SYSJMBO0_H OFS_SYSJMBO0+1
5554 #define OFS_SYSJMBO1 (0x000E) /* JTAG mailbox output 1 */
5555 #define OFS_SYSJMBO1_L OFS_SYSJMBO1
5556 #define OFS_SYSJMBO1_H OFS_SYSJMBO1+1
5557 
5558 #define OFS_SYSBERRIV (0x0018) /* Bus Error vector generator */
5559 #define OFS_SYSBERRIV_L OFS_SYSBERRIV
5560 #define OFS_SYSBERRIV_H OFS_SYSBERRIV+1
5561 #define OFS_SYSUNIV (0x001A) /* User NMI vector generator */
5562 #define OFS_SYSUNIV_L OFS_SYSUNIV
5563 #define OFS_SYSUNIV_H OFS_SYSUNIV+1
5564 #define OFS_SYSSNIV (0x001C) /* System NMI vector generator */
5565 #define OFS_SYSSNIV_L OFS_SYSSNIV
5566 #define OFS_SYSSNIV_H OFS_SYSSNIV+1
5567 #define OFS_SYSRSTIV (0x001E) /* Reset vector generator */
5568 #define OFS_SYSRSTIV_L OFS_SYSRSTIV
5569 #define OFS_SYSRSTIV_H OFS_SYSRSTIV+1
5570 
5571 /* SYSCTL Control Bits */
5572 #define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */
5573 //#define RESERVED (0x0002) /* SYS - Reserved */
5574 #define SYSPMMPE (0x0004) /* SYS - PMM access protect */
5575 //#define RESERVED (0x0008) /* SYS - Reserved */
5576 #define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */
5577 #define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */
5578 //#define RESERVED (0x0040) /* SYS - Reserved */
5579 //#define RESERVED (0x0080) /* SYS - Reserved */
5580 //#define RESERVED (0x0100) /* SYS - Reserved */
5581 //#define RESERVED (0x0200) /* SYS - Reserved */
5582 //#define RESERVED (0x0400) /* SYS - Reserved */
5583 //#define RESERVED (0x0800) /* SYS - Reserved */
5584 //#define RESERVED (0x1000) /* SYS - Reserved */
5585 //#define RESERVED (0x2000) /* SYS - Reserved */
5586 //#define RESERVED (0x4000) /* SYS - Reserved */
5587 //#define RESERVED (0x8000) /* SYS - Reserved */
5588 
5589 /* SYSCTL Control Bits */
5590 #define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */
5591 //#define RESERVED (0x0002) /* SYS - Reserved */
5592 #define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */
5593 //#define RESERVED (0x0008) /* SYS - Reserved */
5594 #define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */
5595 #define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */
5596 //#define RESERVED (0x0040) /* SYS - Reserved */
5597 //#define RESERVED (0x0080) /* SYS - Reserved */
5598 //#define RESERVED (0x0100) /* SYS - Reserved */
5599 //#define RESERVED (0x0200) /* SYS - Reserved */
5600 //#define RESERVED (0x0400) /* SYS - Reserved */
5601 //#define RESERVED (0x0800) /* SYS - Reserved */
5602 //#define RESERVED (0x1000) /* SYS - Reserved */
5603 //#define RESERVED (0x2000) /* SYS - Reserved */
5604 //#define RESERVED (0x4000) /* SYS - Reserved */
5605 //#define RESERVED (0x8000) /* SYS - Reserved */
5606 
5607 /* SYSBSLC Control Bits */
5608 #define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */
5609 #define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */
5610 #define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */
5611 //#define RESERVED (0x0008) /* SYS - Reserved */
5612 //#define RESERVED (0x0010) /* SYS - Reserved */
5613 //#define RESERVED (0x0020) /* SYS - Reserved */
5614 //#define RESERVED (0x0040) /* SYS - Reserved */
5615 //#define RESERVED (0x0080) /* SYS - Reserved */
5616 //#define RESERVED (0x0100) /* SYS - Reserved */
5617 //#define RESERVED (0x0200) /* SYS - Reserved */
5618 //#define RESERVED (0x0400) /* SYS - Reserved */
5619 //#define RESERVED (0x0800) /* SYS - Reserved */
5620 //#define RESERVED (0x1000) /* SYS - Reserved */
5621 //#define RESERVED (0x2000) /* SYS - Reserved */
5622 #define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */
5623 #define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */
5624 
5625 /* SYSBSLC Control Bits */
5626 #define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */
5627 #define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */
5628 #define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */
5629 //#define RESERVED (0x0008) /* SYS - Reserved */
5630 //#define RESERVED (0x0010) /* SYS - Reserved */
5631 //#define RESERVED (0x0020) /* SYS - Reserved */
5632 //#define RESERVED (0x0040) /* SYS - Reserved */
5633 //#define RESERVED (0x0080) /* SYS - Reserved */
5634 //#define RESERVED (0x0100) /* SYS - Reserved */
5635 //#define RESERVED (0x0200) /* SYS - Reserved */
5636 //#define RESERVED (0x0400) /* SYS - Reserved */
5637 //#define RESERVED (0x0800) /* SYS - Reserved */
5638 //#define RESERVED (0x1000) /* SYS - Reserved */
5639 //#define RESERVED (0x2000) /* SYS - Reserved */
5640 
5641 /* SYSBSLC Control Bits */
5642 //#define RESERVED (0x0008) /* SYS - Reserved */
5643 //#define RESERVED (0x0010) /* SYS - Reserved */
5644 //#define RESERVED (0x0020) /* SYS - Reserved */
5645 //#define RESERVED (0x0040) /* SYS - Reserved */
5646 //#define RESERVED (0x0080) /* SYS - Reserved */
5647 //#define RESERVED (0x0100) /* SYS - Reserved */
5648 //#define RESERVED (0x0200) /* SYS - Reserved */
5649 //#define RESERVED (0x0400) /* SYS - Reserved */
5650 //#define RESERVED (0x0800) /* SYS - Reserved */
5651 //#define RESERVED (0x1000) /* SYS - Reserved */
5652 //#define RESERVED (0x2000) /* SYS - Reserved */
5653 #define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */
5654 #define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */
5655 
5656 /* SYSJMBC Control Bits */
5657 #define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
5658 #define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
5659 #define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
5660 #define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
5661 #define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */
5662 //#define RESERVED (0x0020) /* SYS - Reserved */
5663 #define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
5664 #define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
5665 //#define RESERVED (0x0100) /* SYS - Reserved */
5666 //#define RESERVED (0x0200) /* SYS - Reserved */
5667 //#define RESERVED (0x0400) /* SYS - Reserved */
5668 //#define RESERVED (0x0800) /* SYS - Reserved */
5669 //#define RESERVED (0x1000) /* SYS - Reserved */
5670 //#define RESERVED (0x2000) /* SYS - Reserved */
5671 //#define RESERVED (0x4000) /* SYS - Reserved */
5672 //#define RESERVED (0x8000) /* SYS - Reserved */
5673 
5674 /* SYSJMBC Control Bits */
5675 #define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
5676 #define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
5677 #define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
5678 #define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
5679 #define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */
5680 //#define RESERVED (0x0020) /* SYS - Reserved */
5681 #define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
5682 #define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
5683 //#define RESERVED (0x0100) /* SYS - Reserved */
5684 //#define RESERVED (0x0200) /* SYS - Reserved */
5685 //#define RESERVED (0x0400) /* SYS - Reserved */
5686 //#define RESERVED (0x0800) /* SYS - Reserved */
5687 //#define RESERVED (0x1000) /* SYS - Reserved */
5688 //#define RESERVED (0x2000) /* SYS - Reserved */
5689 //#define RESERVED (0x4000) /* SYS - Reserved */
5690 //#define RESERVED (0x8000) /* SYS - Reserved */
5691 
5692 #endif
5693 /************************************************************
5694 * Timerx_A7
5695 ************************************************************/
5696 #ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */
5697 
5698 #define OFS_TAxCTL (0x0000) /* Timerx_A7 Control */
5699 #define OFS_TAxCCTL0 (0x0002) /* Timerx_A7 Capture/Compare Control 0 */
5700 #define OFS_TAxCCTL1 (0x0004) /* Timerx_A7 Capture/Compare Control 1 */
5701 #define OFS_TAxCCTL2 (0x0006) /* Timerx_A7 Capture/Compare Control 2 */
5702 #define OFS_TAxCCTL3 (0x0008) /* Timerx_A7 Capture/Compare Control 3 */
5703 #define OFS_TAxCCTL4 (0x000A) /* Timerx_A7 Capture/Compare Control 4 */
5704 #define OFS_TAxCCTL5 (0x000C) /* Timerx_A7 Capture/Compare Control 5 */
5705 #define OFS_TAxCCTL6 (0x000E) /* Timerx_A7 Capture/Compare Control 6 */
5706 #define OFS_TAxR (0x0010) /* Timerx_A7 */
5707 #define OFS_TAxCCR0 (0x0012) /* Timerx_A7 Capture/Compare 0 */
5708 #define OFS_TAxCCR1 (0x0014) /* Timerx_A7 Capture/Compare 1 */
5709 #define OFS_TAxCCR2 (0x0016) /* Timerx_A7 Capture/Compare 2 */
5710 #define OFS_TAxCCR3 (0x0018) /* Timerx_A7 Capture/Compare 3 */
5711 #define OFS_TAxCCR4 (0x001A) /* Timerx_A7 Capture/Compare 4 */
5712 #define OFS_TAxCCR5 (0x001C) /* Timerx_A7 Capture/Compare 5 */
5713 #define OFS_TAxCCR6 (0x001E) /* Timerx_A7 Capture/Compare 6 */
5714 #define OFS_TAxIV (0x002E) /* Timerx_A7 Interrupt Vector Word */
5715 #define OFS_TAxEX0 (0x0020) /* Timerx_A7 Expansion Register 0 */
5716 
5717 /* Bits are already defined within the Timer0_Ax */
5718 
5719 /* TAxIV Definitions */
5720 #define TAxIV_NONE (0x0000) /* No Interrupt pending */
5721 #define TAxIV_TACCR1 (0x0002) /* TAxCCR1_CCIFG */
5722 #define TAxIV_TACCR2 (0x0004) /* TAxCCR2_CCIFG */
5723 #define TAxIV_TACCR3 (0x0006) /* TAxCCR3_CCIFG */
5724 #define TAxIV_TACCR4 (0x0008) /* TAxCCR4_CCIFG */
5725 #define TAxIV_TACCR5 (0x000A) /* TAxCCR5_CCIFG */
5726 #define TAxIV_TACCR6 (0x000C) /* TAxCCR6_CCIFG */
5727 #define TAxIV_TAIFG (0x000E) /* TAxIFG */
5728 
5729 /* Legacy Defines */
5730 #define TAxIV_TAxCCR1 (0x0002) /* TAxCCR1_CCIFG */
5731 #define TAxIV_TAxCCR2 (0x0004) /* TAxCCR2_CCIFG */
5732 #define TAxIV_TAxCCR3 (0x0006) /* TAxCCR3_CCIFG */
5733 #define TAxIV_TAxCCR4 (0x0008) /* TAxCCR4_CCIFG */
5734 #define TAxIV_TAxCCR5 (0x000A) /* TAxCCR5_CCIFG */
5735 #define TAxIV_TAxCCR6 (0x000C) /* TAxCCR6_CCIFG */
5736 #define TAxIV_TAxIFG (0x000E) /* TAxIFG */
5737 
5738 /* TAxCTL Control Bits */
5739 #define TASSEL1 (0x0200) /* Timer A clock source select 1 */
5740 #define TASSEL0 (0x0100) /* Timer A clock source select 0 */
5741 #define ID1 (0x0080) /* Timer A clock input divider 1 */
5742 #define ID0 (0x0040) /* Timer A clock input divider 0 */
5743 #define MC1 (0x0020) /* Timer A mode control 1 */
5744 #define MC0 (0x0010) /* Timer A mode control 0 */
5745 #define TACLR (0x0004) /* Timer A counter clear */
5746 #define TAIE (0x0002) /* Timer A counter interrupt enable */
5747 #define TAIFG (0x0001) /* Timer A counter interrupt flag */
5748 
5749 #define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
5750 #define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
5751 #define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */
5752 #define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
5753 #define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
5754 #define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
5755 #define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
5756 #define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
5757 #define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
5758 #define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
5759 #define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
5760 #define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
5761 #define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */
5762 #define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
5763 #define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */
5764 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
5765 #define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */
5766 #define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */
5767 #define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */
5768 #define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */
5769 #define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */
5770 #define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */
5771 #define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */
5772 #define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
5773 #define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */
5774 
5775 /* TAxCCTLx Control Bits */
5776 #define CM1 (0x8000) /* Capture mode 1 */
5777 #define CM0 (0x4000) /* Capture mode 0 */
5778 #define CCIS1 (0x2000) /* Capture input select 1 */
5779 #define CCIS0 (0x1000) /* Capture input select 0 */
5780 #define SCS (0x0800) /* Capture sychronize */
5781 #define SCCI (0x0400) /* Latched capture signal (read) */
5782 #define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
5783 #define OUTMOD2 (0x0080) /* Output mode 2 */
5784 #define OUTMOD1 (0x0040) /* Output mode 1 */
5785 #define OUTMOD0 (0x0020) /* Output mode 0 */
5786 #define CCIE (0x0010) /* Capture/compare interrupt enable */
5787 #define CCI (0x0008) /* Capture input signal (read) */
5788 #define OUT (0x0004) /* PWM Output signal if output mode 0 */
5789 #define COV (0x0002) /* Capture/compare overflow flag */
5790 #define CCIFG (0x0001) /* Capture/compare interrupt flag */
5791 
5792 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
5793 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
5794 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
5795 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
5796 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
5797 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
5798 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
5799 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
5800 #define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
5801 #define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
5802 #define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
5803 #define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
5804 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
5805 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
5806 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
5807 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
5808 
5809 /* TAxEX0 Control Bits */
5810 #define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */
5811 #define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */
5812 #define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */
5813 
5814 #define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */
5815 #define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */
5816 #define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */
5817 #define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */
5818 #define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */
5819 #define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */
5820 #define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */
5821 #define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */
5822 
5823 #endif
5824 /************************************************************
5825 * Timerx_B7
5826 ************************************************************/
5827 #ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */
5828 
5829 #define OFS_TBxCTL (0x0000) /* Timerx_B7 Control */
5830 #define OFS_TBxCCTL0 (0x0002) /* Timerx_B7 Capture/Compare Control 0 */
5831 #define OFS_TBxCCTL1 (0x0004) /* Timerx_B7 Capture/Compare Control 1 */
5832 #define OFS_TBxCCTL2 (0x0006) /* Timerx_B7 Capture/Compare Control 2 */
5833 #define OFS_TBxCCTL3 (0x0008) /* Timerx_B7 Capture/Compare Control 3 */
5834 #define OFS_TBxCCTL4 (0x000A) /* Timerx_B7 Capture/Compare Control 4 */
5835 #define OFS_TBxCCTL5 (0x000C) /* Timerx_B7 Capture/Compare Control 5 */
5836 #define OFS_TBxCCTL6 (0x000E) /* Timerx_B7 Capture/Compare Control 6 */
5837 #define OFS_TBxR (0x0010) /* Timerx_B7 */
5838 #define OFS_TBxCCR0 (0x0012) /* Timerx_B7 Capture/Compare 0 */
5839 #define OFS_TBxCCR1 (0x0014) /* Timerx_B7 Capture/Compare 1 */
5840 #define OFS_TBxCCR2 (0x0016) /* Timerx_B7 Capture/Compare 2 */
5841 #define OFS_TBxCCR3 (0x0018) /* Timerx_B7 Capture/Compare 3 */
5842 #define OFS_TBxCCR4 (0x001A) /* Timerx_B7 Capture/Compare 4 */
5843 #define OFS_TBxCCR5 (0x001C) /* Timerx_B7 Capture/Compare 5 */
5844 #define OFS_TBxCCR6 (0x001E) /* Timerx_B7 Capture/Compare 6 */
5845 #define OFS_TBxIV (0x002E) /* Timerx_B7 Interrupt Vector Word */
5846 #define OFS_TBxEX0 (0x0020) /* Timerx_B7 Expansion Register 0 */
5847 
5848 /* Bits are already defined within the Timer0_Ax */
5849 
5850 /* TBxIV Definitions */
5851 #define TBxIV_NONE (0x0000) /* No Interrupt pending */
5852 #define TBxIV_TBCCR1 (0x0002) /* TBxCCR1_CCIFG */
5853 #define TBxIV_TBCCR2 (0x0004) /* TBxCCR2_CCIFG */
5854 #define TBxIV_TBCCR3 (0x0006) /* TBxCCR3_CCIFG */
5855 #define TBxIV_TBCCR4 (0x0008) /* TBxCCR4_CCIFG */
5856 #define TBxIV_TBCCR5 (0x000A) /* TBxCCR5_CCIFG */
5857 #define TBxIV_TBCCR6 (0x000C) /* TBxCCR6_CCIFG */
5858 #define TBxIV_TBIFG (0x000E) /* TBxIFG */
5859 
5860 /* Legacy Defines */
5861 #define TBxIV_TBxCCR1 (0x0002) /* TBxCCR1_CCIFG */
5862 #define TBxIV_TBxCCR2 (0x0004) /* TBxCCR2_CCIFG */
5863 #define TBxIV_TBxCCR3 (0x0006) /* TBxCCR3_CCIFG */
5864 #define TBxIV_TBxCCR4 (0x0008) /* TBxCCR4_CCIFG */
5865 #define TBxIV_TBxCCR5 (0x000A) /* TBxCCR5_CCIFG */
5866 #define TBxIV_TBxCCR6 (0x000C) /* TBxCCR6_CCIFG */
5867 #define TBxIV_TBxIFG (0x000E) /* TBxIFG */
5868 
5869 /* TBxCTL Control Bits */
5870 #define TBCLGRP1 (0x4000) /* Timer_B7 Compare latch load group 1 */
5871 #define TBCLGRP0 (0x2000) /* Timer_B7 Compare latch load group 0 */
5872 #define CNTL1 (0x1000) /* Counter lenght 1 */
5873 #define CNTL0 (0x0800) /* Counter lenght 0 */
5874 #define TBSSEL1 (0x0200) /* Clock source 1 */
5875 #define TBSSEL0 (0x0100) /* Clock source 0 */
5876 #define TBCLR (0x0004) /* Timer_B7 counter clear */
5877 #define TBIE (0x0002) /* Timer_B7 interrupt enable */
5878 #define TBIFG (0x0001) /* Timer_B7 interrupt flag */
5879 
5880 #define SHR1 (0x4000) /* Timer_B7 Compare latch load group 1 */
5881 #define SHR0 (0x2000) /* Timer_B7 Compare latch load group 0 */
5882 
5883 #define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */
5884 #define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
5885 #define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
5886 #define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
5887 #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
5888 #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
5889 #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
5890 #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
5891 #define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */
5892 #define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
5893 #define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/
5894 #define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */
5895 #define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */
5896 #define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
5897 #define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/
5898 #define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */
5899 #define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */
5900 #define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */
5901 #define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */
5902 #define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */
5903 #define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */
5904 #define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */
5905 #define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */
5906 #define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */
5907 #define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */
5908 
5909 /* Additional Timer B Control Register bits are defined in Timer A */
5910 /* TBxCCTLx Control Bits */
5911 #define CLLD1 (0x0400) /* Compare latch load source 1 */
5912 #define CLLD0 (0x0200) /* Compare latch load source 0 */
5913 
5914 #define SLSHR1 (0x0400) /* Compare latch load source 1 */
5915 #define SLSHR0 (0x0200) /* Compare latch load source 0 */
5916 
5917 #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
5918 #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
5919 #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
5920 #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
5921 
5922 #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
5923 #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
5924 #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
5925 #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
5926 
5927 /* TBxEX0 Control Bits */
5928 #define TBIDEX0 (0x0001) /* Timer_B7 Input divider expansion Bit: 0 */
5929 #define TBIDEX1 (0x0002) /* Timer_B7 Input divider expansion Bit: 1 */
5930 #define TBIDEX2 (0x0004) /* Timer_B7 Input divider expansion Bit: 2 */
5931 
5932 #define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */
5933 #define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */
5934 #define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */
5935 #define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */
5936 #define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */
5937 #define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */
5938 #define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */
5939 #define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */
5940 #define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */
5941 #define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */
5942 #define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */
5943 #define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */
5944 #define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */
5945 #define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */
5946 #define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */
5947 #define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */
5948 
5949 
5950 #define ID1 (0x0080) /* Timer B clock input divider 1 */
5951 #define ID0 (0x0040) /* Timer B clock input divider 0 */
5952 #define MC1 (0x0020) /* Timer B mode control 1 */
5953 #define MC0 (0x0010) /* Timer B mode control 0 */
5954 #define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */
5955 #define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */
5956 #define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */
5957 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
5958 #define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */
5959 #define CM1 (0x8000) /* Capture mode 1 */
5960 #define CM0 (0x4000) /* Capture mode 0 */
5961 #define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */
5962 #define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */
5963 #define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */
5964 #define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */
5965 #define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
5966 #define CCIE (0x0010) /* Capture/compare interrupt enable */
5967 #define CCIFG (0x0001) /* Capture/compare interrupt flag */
5968 #define CCIS_0 (0*0x1000u)
5969 #define CCIS_1 (1*0x1000u)
5970 #define CCIS_2 (2*0x1000u)
5971 #define CCIS_3 (3*0x1000u)
5972 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
5973 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
5974 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
5975 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
5976 #define OUT (0x0004) /* PWM Output signal if output mode 0 */
5977 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
5978 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
5979 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
5980 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
5981 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
5982 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
5983 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
5984 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
5985 #define SCCI (0x0400) /* Latched capture signal (read) */
5986 #define SCS (0x0800) /* Capture sychronize */
5987 #define CCI (0x0008) /* Capture input signal (read) */
5988 #define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */
5989 #define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */
5990 #define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */
5991 #define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */
5992 #define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */
5993 #define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */
5994 #define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */
5995 #define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */
5996 
5997 #endif
5998 /************************************************************
5999 * Timerx_D7
6000 ************************************************************/
6001 #ifdef __MSP430_HAS_TxD7__ /* Definition to show that Module is available */
6002 
6003 #define OFS_TDxCTL0 (0x0000) /* Timerx_D7 Control 0 */
6004 #define OFS_TDxCTL1 (0x0002) /* Timerx_D7 Control 1 */
6005 #define OFS_TDxCTL2 (0x0004) /* Timerx_D7 Control 2 */
6006 #define OFS_TDxR (0x0006) /* Timerx_D7 Counter */
6007 #define OFS_TDxCCTL0 (0x0008) /* Timerx_D7 Capture/Compare Control 0 */
6008 #define OFS_TDxCCR0 (0x000A) /* Timerx_D7 Capture/Compare 0 */
6009 #define OFS_TDxCL0 (0x000C) /* Timerx_D7 Capture/Compare Latch 0 */
6010 #define OFS_TDxCCTL1 (0x000E) /* Timerx_D7 Capture/Compare Control 1 */
6011 #define OFS_TDxCCR1 (0x0010) /* Timerx_D7 Capture/Compare 1 */
6012 #define OFS_TDxCL1 (0x0012) /* Timerx_D7 Capture/Compare Latch 1 */
6013 #define OFS_TDxCCTL2 (0x0014) /* Timerx_D7 Capture/Compare Control 2 */
6014 #define OFS_TDxCCR2 (0x0016) /* Timerx_D7 Capture/Compare 2 */
6015 #define OFS_TDxCL2 (0x0018) /* Timerx_D7 Capture/Compare Latch 2 */
6016 #define OFS_TDxCCTL3 (0x001A) /* Timerx_D7 Capture/Compare Control 3 */
6017 #define OFS_TDxCCR3 (0x001C) /* Timerx_D7 Capture/Compare 3 */
6018 #define OFS_TDxCL3 (0x001E) /* Timerx_D7 Capture/Compare Latch 3 */
6019 #define OFS_TDxCCTL4 (0x0020) /* Timerx_D7 Capture/Compare Control 4 */
6020 #define OFS_TDxCCR4 (0x0022) /* Timerx_D7 Capture/Compare 4 */
6021 #define OFS_TDxCL4 (0x0024) /* Timerx_D7 Capture/Compare Latch 4 */
6022 #define OFS_TDxCCTL5 (0x0026) /* Timerx_D7 Capture/Compare Control 5 */
6023 #define OFS_TDxCCR5 (0x0028) /* Timerx_D7 Capture/Compare 5 */
6024 #define OFS_TDxCL5 (0x002A) /* Timerx_D7 Capture/Compare Latch 5 */
6025 #define OFS_TDxCCTL6 (0x002C) /* Timerx_D7 Capture/Compare Control 6 */
6026 #define OFS_TDxCCR6 (0x002E) /* Timerx_D7 Capture/Compare 6 */
6027 #define OFS_TDxCL6 (0x0030) /* Timerx_D7 Capture/Compare Latch 6 */
6028 #define OFS_TDxHCTL0 (0x0038) /* Timerx_D7 High-resolution Control Register 0 */
6029 #define OFS_TDxHCTL1 (0x003A) /* Timerx_D7 High-resolution Control Register 1 */
6030 #define OFS_TDxHINT (0x003C) /* Timerx_D7 High-resolution Interrupt Register */
6031 #define OFS_TDxIV (0x003E) /* Timerx_D7 Interrupt Vector Word */
6032 
6033 /* Bits are already defined within the Timer0_Dx */
6034 
6035 /* TDxIV Definitions */
6036 #define TDxIV_NONE (0x0000) /* No Interrupt pending */
6037 #define TDxIV_TDCCR1 (0x0002) /* TDxCCR1_CCIFG */
6038 #define TDxIV_TDCCR2 (0x0004) /* TDxCCR2_CCIFG */
6039 #define TDxIV_TDCCR3 (0x0006) /* TDxCCR3_CCIFG */
6040 #define TDxIV_TDCCR4 (0x0008) /* TDxCCR4_CCIFG */
6041 #define TDxIV_TDCCR5 (0x000A) /* TDxCCR5_CCIFG */
6042 #define TDxIV_TDCCR6 (0x000C) /* TDxCCR6_CCIFG */
6043 #define TDxIV_RES_14 (0x000E) /* Reserverd */
6044 #define TDxIV_TDIFG (0x0010) /* TDxIFG */
6045 #define TDxIV_TDHFLIFG (0x0012) /* TDHFLIFG Clock fail low */
6046 #define TDxIV_TDHFHIFG (0x0014) /* TDHFLIFG Clock fail high */
6047 #define TDxIV_TDHLKIFG (0x0016) /* TDHLKIE Clock lock*/
6048 #define TDxIV_TDHUNLKIFG (0x0018) /* TDHUNLKIE Clock unlock */
6049 
6050 /* Legacy Defines */
6051 #define TDxIV_TDxCCR1 (0x0002) /* TDxCCR1_CCIFG */
6052 #define TDxIV_TDxCCR2 (0x0004) /* TDxCCR2_CCIFG */
6053 #define TDxIV_TDxCCR3 (0x0006) /* TDxCCR3_CCIFG */
6054 #define TDxIV_TDxCCR4 (0x0008) /* TDxCCR4_CCIFG */
6055 #define TDxIV_TDxCCR5 (0x000A) /* TDxCCR5_CCIFG */
6056 #define TDxIV_TDxCCR6 (0x000C) /* TDxCCR6_CCIFG */
6057 #define TDxIV_TDxIFG (0x0010) /* TDxIFG */
6058 
6059 /* TDxCTL0 Control Bits */
6060 #define TDCLGRP1 (0x4000) /* Timer_D7 Compare latch load group 1 */
6061 #define TDCLGRP0 (0x2000) /* Timer_D7 Compare latch load group 0 */
6062 #define CNTL1 (0x1000) /* Counter lenght 1 */
6063 #define CNTL0 (0x0800) /* Counter lenght 0 */
6064 #define TDSSEL1 (0x0200) /* Clock source 1 */
6065 #define TDSSEL0 (0x0100) /* Clock source 0 */
6066 #define TDCLR (0x0004) /* Timer_D7 counter clear */
6067 #define TDIE (0x0002) /* Timer_D7 interrupt enable */
6068 #define TDIFG (0x0001) /* Timer_D7 interrupt flag */
6069 
6070 #define SHR1 (0x4000) /* Timer_D7 Compare latch load group 1 */
6071 #define SHR0 (0x2000) /* Timer_D7 Compare latch load group 0 */
6072 
6073 #define TDSSEL_0 (0*0x0100u) /* Clock Source: TDCLK */
6074 #define TDSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
6075 #define TDSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
6076 #define TDSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
6077 #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
6078 #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
6079 #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
6080 #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
6081 #define SHR_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */
6082 #define SHR_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
6083 #define SHR_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/
6084 #define SHR_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */
6085 #define TDCLGRP_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */
6086 #define TDCLGRP_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
6087 #define TDCLGRP_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/
6088 #define TDCLGRP_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */
6089 #define TDSSEL__TACLK (0*0x0100u) /* Timer_D7 clock source select: 0 - TACLK */
6090 #define TDSSEL__ACLK (1*0x0100u) /* Timer_D7 clock source select: 1 - ACLK */
6091 #define TDSSEL__SMCLK (2*0x0100u) /* Timer_D7 clock source select: 2 - SMCLK */
6092 #define TDSSEL__INCLK (3*0x0100u) /* Timer_D7 clock source select: 3 - INCLK */
6093 #define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */
6094 #define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */
6095 #define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */
6096 #define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */
6097 
6098 /* Additional Timer B Control Register bits are defined in Timer A */
6099 
6100 /* TDxCTL1 Control Bits */
6101 #define TDCLKM0 (0x0001) /* Timer_D7 Clocking Mode Bit: 0 */
6102 #define TDCLKM1 (0x0002) /* Timer_D7 Clocking Mode Bit: 1 */
6103 #define TD2CMB (0x0010) /* Timer_D7 TD0CCR Combination in TD2 */
6104 #define TD4CMB (0x0020) /* Timer_D7 TD0CCR Combination in TD4 */
6105 #define TD6CMB (0x0040) /* Timer_D7 TD0CCR Combination in TD6 */
6106 #define TDIDEX0 (0x0100) /* Timer_D7 Input divider expansion Bit: 0 */
6107 #define TDIDEX1 (0x0200) /* Timer_D7 Input divider expansion Bit: 1 */
6108 #define TDIDEX2 (0x0400) /* Timer_D7 Input divider expansion Bit: 2 */
6109 
6110 #define TDCLKM_0 (0x0000) /* Timer_D7 Clocking Mode: External */
6111 #define TDCLKM_1 (0x0001) /* Timer_D7 Clocking Mode: High-Res. local clock */
6112 #define TDCLKM_2 (0x0002) /* Timer_D7 Clocking Mode: Aux Clock */
6113 #define TDCLKM__EXT (0x0000) /* Timer_D7 Clocking Mode: External */
6114 #define TDCLKM__HIGHRES (0x0001) /* Timer_D7 Clocking Mode: High-Res. local clock */
6115 #define TDCLKM__AUX (0x0002) /* Timer_D7 Clocking Mode: Aux Clock */
6116 
6117 #define TDIDEX_0 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */
6118 #define TDIDEX_1 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */
6119 #define TDIDEX_2 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */
6120 #define TDIDEX_3 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */
6121 #define TDIDEX_4 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */
6122 #define TDIDEX_5 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */
6123 #define TDIDEX_6 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */
6124 #define TDIDEX_7 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */
6125 #define TDIDEX__1 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */
6126 #define TDIDEX__2 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */
6127 #define TDIDEX__3 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */
6128 #define TDIDEX__4 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */
6129 #define TDIDEX__5 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */
6130 #define TDIDEX__6 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */
6131 #define TDIDEX__7 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */
6132 #define TDIDEX__8 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */
6133 
6134 /* TDxCTL2 Control Bits */
6135 #define TDCAPM0 (0x0001) /* Timer_D7 Capture Mode of Channel 0 */
6136 #define TDCAPM1 (0x0002) /* Timer_D7 Capture Mode of Channel 1 */
6137 #define TDCAPM2 (0x0004) /* Timer_D7 Capture Mode of Channel 2 */
6138 #define TDCAPM3 (0x0008) /* Timer_D7 Capture Mode of Channel 3 */
6139 #define TDCAPM4 (0x0010) /* Timer_D7 Capture Mode of Channel 4 */
6140 #define TDCAPM5 (0x0020) /* Timer_D7 Capture Mode of Channel 5 */
6141 #define TDCAPM6 (0x0040) /* Timer_D7 Capture Mode of Channel 6 */
6142 
6143 /* TDxCCTLx Control Bits */
6144 #define CLLD1 (0x0400) /* Compare latch load source 1 */
6145 #define CLLD0 (0x0200) /* Compare latch load source 0 */
6146 
6147 #define SLSHR1 (0x0400) /* Compare latch load source 1 */
6148 #define SLSHR0 (0x0200) /* Compare latch load source 0 */
6149 
6150 #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
6151 #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */
6152 #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
6153 #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */
6154 
6155 #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
6156 #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */
6157 #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
6158 #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */
6159 
6160 /* TDxHCTL0 Control Bits */
6161 #define TDHEN (0x0001) /* Timer_D7 High-Resolution Enable */
6162 #define TDHREGEN (0x0002) /* Timer_D7 High-Resolution Regulatied Mode */
6163 #define TDHEAEN (0x0004) /* Timer_D7 High-Resolution clock error accum. enable */
6164 #define TDHRON (0x0008) /* Timer_D7 High-Resolution Generator forced on*/
6165 #define TDHM0 (0x0010) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 0 */
6166 #define TDHM1 (0x0020) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 1 */
6167 #define TDHD0 (0x0040) /* Timer_D7 High-Resolution clock divider Bit: 0 */
6168 #define TDHD1 (0x0080) /* Timer_D7 High-Resolution clock divider Bit: 1 */
6169 #define TDHFW (0x0100) /* Timer_D7 High-resolution generator fast wakeup enable */
6170 
6171 #define TDHCALEN TDHREGEN /* Timer_D7 Lagacy Definition */
6172 
6173 #define TDHM_0 (0x0000) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */
6174 #define TDHM_1 (0x0010) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */
6175 #define TDHM__8 (0x0000) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */
6176 #define TDHM__16 (0x0010) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */
6177 #define TDHD_0 (0x0000) /* Timer_D7 High-Resolution clock divider: /1 */
6178 #define TDHD_1 (0x0040) /* Timer_D7 High-Resolution clock divider: /2 */
6179 #define TDHD_2 (0x0080) /* Timer_D7 High-Resolution clock divider: /4 */
6180 #define TDHD_3 (0x00C0) /* Timer_D7 High-Resolution clock divider: /8 */
6181 #define TDHD__1 (0x0000) /* Timer_D7 High-Resolution clock divider: /1 */
6182 #define TDHD__2 (0x0040) /* Timer_D7 High-Resolution clock divider: /2 */
6183 #define TDHD__4 (0x0080) /* Timer_D7 High-Resolution clock divider: /4 */
6184 #define TDHD__8 (0x00C0) /* Timer_D7 High-Resolution clock divider: /8 */
6185 
6186 /* TDxHCTL1 Control Bits */
6187 #define TDHCLKTRIM0 (0x0002) /* Timer_D7 High-Resolution Clock Trim Bit: 0 */
6188 #define TDHCLKTRIM1 (0x0004) /* Timer_D7 High-Resolution Clock Trim Bit: 1 */
6189 #define TDHCLKTRIM2 (0x0008) /* Timer_D7 High-Resolution Clock Trim Bit: 2 */
6190 #define TDHCLKTRIM3 (0x0010) /* Timer_D7 High-Resolution Clock Trim Bit: 3 */
6191 #define TDHCLKTRIM4 (0x0020) /* Timer_D7 High-Resolution Clock Trim Bit: 4 */
6192 #define TDHCLKTRIM5 (0x0040) /* Timer_D7 High-Resolution Clock Trim Bit: 5 */
6193 #define TDHCLKTRIM6 (0x0080) /* Timer_D7 High-Resolution Clock Trim Bit: 6 */
6194 #define TDHCLKSR0 (0x0100) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 0 */
6195 #define TDHCLKSR1 (0x0200) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 1 */
6196 #define TDHCLKSR2 (0x0400) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 2 */
6197 #define TDHCLKSR3 (0x0800) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 3 */
6198 #define TDHCLKSR4 (0x1000) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 4 */
6199 #define TDHCLKR0 (0x2000) /* Timer_D7 High-Resolution Clock Range Bit: 0 */
6200 #define TDHCLKR1 (0x4000) /* Timer_D7 High-Resolution Clock Range Bit: 1 */
6201 #define TDHCLKCR (0x8000) /* Timer_D7 High-Resolution Coarse Clock Range */
6202 
6203 /* TDxHINT Control Bits */
6204 #define TDHFLIFG (0x0001) /* Timer_D7 High-Res. fail low Interrupt Flag */
6205 #define TDHFHIFG (0x0002) /* Timer_D7 High-Res. fail high Interrupt Flag */
6206 #define TDHLKIFG (0x0004) /* Timer_D7 High-Res. frequency lock Interrupt Flag */
6207 #define TDHUNLKIFG (0x0008) /* Timer_D7 High-Res. frequency unlock Interrupt Flag */
6208 #define TDHFLIE (0x0100) /* Timer_D7 High-Res. fail low Interrupt Enable */
6209 #define TDHFHIE (0x0200) /* Timer_D7 High-Res. fail high Interrupt Enable */
6210 #define TDHLKIE (0x0400) /* Timer_D7 High-Res. frequency lock Interrupt Enable */
6211 #define TDHUNLKIE (0x0800) /* Timer_D7 High-Res. frequency unlock Interrupt Enable */
6212 
6213 #define ID1 (0x0080) /* Timer D clock input divider 1 */
6214 #define ID0 (0x0040) /* Timer D clock input divider 0 */
6215 #define MC1 (0x0020) /* Timer D mode control 1 */
6216 #define MC0 (0x0010) /* Timer D mode control 0 */
6217 #define MC__STOP (0*0x10u) /* Timer D mode control: 0 - Stop */
6218 #define MC__UP (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */
6219 #define MC__CONTINUOUS (2*0x10u) /* Timer D mode control: 2 - Continuous up */
6220 #define MC__CONTINOUS (2*0x10u) /* Legacy define */
6221 #define MC__UPDOWN (3*0x10u) /* Timer D mode control: 3 - Up/Down */
6222 #define CM1 (0x8000) /* Capture mode 1 */
6223 #define CM0 (0x4000) /* Capture mode 0 */
6224 #define MC_0 (0*0x10u) /* Timer D mode control: 0 - Stop */
6225 #define MC_1 (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */
6226 #define MC_2 (2*0x10u) /* Timer D mode control: 2 - Continuous up */
6227 #define MC_3 (3*0x10u) /* Timer D mode control: 3 - Up/Down */
6228 #define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
6229 #define CCIE (0x0010) /* Capture/compare interrupt enable */
6230 #define CCIFG (0x0001) /* Capture/compare interrupt flag */
6231 #define CCIS_0 (0*0x1000u)
6232 #define CCIS_1 (1*0x1000u)
6233 #define CCIS_2 (2*0x1000u)
6234 #define CCIS_3 (3*0x1000u)
6235 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
6236 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
6237 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
6238 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
6239 #define OUT (0x0004) /* PWM Output signal if output mode 0 */
6240 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
6241 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
6242 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
6243 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
6244 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
6245 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
6246 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
6247 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
6248 #define SCCI (0x0400) /* Latched capture signal (read) */
6249 #define SCS (0x0800) /* Capture sychronize */
6250 #define CCI (0x0008) /* Capture input signal (read) */
6251 #define ID__1 (0*0x40u) /* Timer D input divider: 0 - /1 */
6252 #define ID__2 (1*0x40u) /* Timer D input divider: 1 - /2 */
6253 #define ID__4 (2*0x40u) /* Timer D input divider: 2 - /4 */
6254 #define ID__8 (3*0x40u) /* Timer D input divider: 3 - /8 */
6255 #define ID_0 (0*0x40u) /* Timer D input divider: 0 - /1 */
6256 #define ID_1 (1*0x40u) /* Timer D input divider: 1 - /2 */
6257 #define ID_2 (2*0x40u) /* Timer D input divider: 2 - /4 */
6258 #define ID_3 (3*0x40u) /* Timer D input divider: 3 - /8 */
6259 
6260 #endif
6261 /************************************************************
6262 * Timer Event Control 0
6263 ************************************************************/
6264 #ifdef __MSP430_HAS_TEV0__ /* Definition to show that Module is available */
6265 
6266 #define OFS_TEC0XCTL0 (0x0000) /* Timer Event Control 0 External Control 0 */
6267 #define OFS_TEC0XCTL0_L OFS_TEC0XCTL0
6268 #define OFS_TEC0XCTL0_H OFS_TEC0XCTL0+1
6269 #define OFS_TEC0XCTL1 (0x0002) /* Timer Event Control 0 External Control 1 */
6270 #define OFS_TEC0XCTL1_L OFS_TEC0XCTL1
6271 #define OFS_TEC0XCTL1_H OFS_TEC0XCTL1+1
6272 #define OFS_TEC0XCTL2 (0x0004) /* Timer Event Control 0 External Control 2 */
6273 #define OFS_TEC0XCTL2_L OFS_TEC0XCTL2
6274 #define OFS_TEC0XCTL2_H OFS_TEC0XCTL2+1
6275 #define OFS_TEC0STA (0x0006) /* Timer Event Control 0 Status */
6276 #define OFS_TEC0STA_L OFS_TEC0STA
6277 #define OFS_TEC0STA_H OFS_TEC0STA+1
6278 #define OFS_TEC0XINT (0x0008) /* Timer Event Control 0 External Interrupt */
6279 #define OFS_TEC0XINT_L OFS_TEC0XINT
6280 #define OFS_TEC0XINT_H OFS_TEC0XINT+1
6281 #define OFS_TEC0IV (0x000A) /* Timer Event Control 0 Interrupt Vector */
6282 #define OFS_TEC0IV_L OFS_TEC0IV
6283 #define OFS_TEC0IV_H OFS_TEC0IV+1
6284 
6285 /* TECxXCTL0 Control Bits */
6286 #define TECXFLTHLD0 (0x0001) /* TEV Ext. fault signal hold for CE0 */
6287 #define TECXFLTHLD1 (0x0002) /* TEV Ext. fault signal hold for CE1 */
6288 #define TECXFLTHLD2 (0x0004) /* TEV Ext. fault signal hold for CE2 */
6289 #define TECXFLTHLD3 (0x0008) /* TEV Ext. fault signal hold for CE3 */
6290 #define TECXFLTHLD4 (0x0010) /* TEV Ext. fault signal hold for CE4 */
6291 #define TECXFLTHLD5 (0x0020) /* TEV Ext. fault signal hold for CE5 */
6292 #define TECXFLTHLD6 (0x0040) /* TEV Ext. fault signal hold for CE6 */
6293 #define TECXFLTEN0 (0x0100) /* TEV Ext. fault signal enable for CE0 */
6294 #define TECXFLTEN1 (0x0200) /* TEV Ext. fault signal enable for CE1 */
6295 #define TECXFLTEN2 (0x0400) /* TEV Ext. fault signal enable for CE2 */
6296 #define TECXFLTEN3 (0x0800) /* TEV Ext. fault signal enable for CE3 */
6297 #define TECXFLTEN4 (0x1000) /* TEV Ext. fault signal enable for CE4 */
6298 #define TECXFLTEN5 (0x2000) /* TEV Ext. fault signal enable for CE5 */
6299 #define TECXFLTEN6 (0x4000) /* TEV Ext. fault signal enable for CE6 */
6300 
6301 /* TECxXCTL0 Control Bits */
6302 #define TECXFLTHLD0_L (0x0001) /* TEV Ext. fault signal hold for CE0 */
6303 #define TECXFLTHLD1_L (0x0002) /* TEV Ext. fault signal hold for CE1 */
6304 #define TECXFLTHLD2_L (0x0004) /* TEV Ext. fault signal hold for CE2 */
6305 #define TECXFLTHLD3_L (0x0008) /* TEV Ext. fault signal hold for CE3 */
6306 #define TECXFLTHLD4_L (0x0010) /* TEV Ext. fault signal hold for CE4 */
6307 #define TECXFLTHLD5_L (0x0020) /* TEV Ext. fault signal hold for CE5 */
6308 #define TECXFLTHLD6_L (0x0040) /* TEV Ext. fault signal hold for CE6 */
6309 
6310 /* TECxXCTL0 Control Bits */
6311 #define TECXFLTEN0_H (0x0001) /* TEV Ext. fault signal enable for CE0 */
6312 #define TECXFLTEN1_H (0x0002) /* TEV Ext. fault signal enable for CE1 */
6313 #define TECXFLTEN2_H (0x0004) /* TEV Ext. fault signal enable for CE2 */
6314 #define TECXFLTEN3_H (0x0008) /* TEV Ext. fault signal enable for CE3 */
6315 #define TECXFLTEN4_H (0x0010) /* TEV Ext. fault signal enable for CE4 */
6316 #define TECXFLTEN5_H (0x0020) /* TEV Ext. fault signal enable for CE5 */
6317 #define TECXFLTEN6_H (0x0040) /* TEV Ext. fault signal enable for CE6 */
6318 
6319 /* TECxXCTL1 Control Bits */
6320 #define TECXFLTPOL0 (0x0001) /* TEV Polarity Bit of ext. fault 0 */
6321 #define TECXFLTPOL1 (0x0002) /* TEV Polarity Bit of ext. fault 1 */
6322 #define TECXFLTPOL2 (0x0004) /* TEV Polarity Bit of ext. fault 2 */
6323 #define TECXFLTPOL3 (0x0008) /* TEV Polarity Bit of ext. fault 3 */
6324 #define TECXFLTPOL4 (0x0010) /* TEV Polarity Bit of ext. fault 4 */
6325 #define TECXFLTPOL5 (0x0020) /* TEV Polarity Bit of ext. fault 5 */
6326 #define TECXFLTPOL6 (0x0040) /* TEV Polarity Bit of ext. fault 6 */
6327 #define TECXFLTLVS0 (0x0100) /* TEV Signal Type of Ext. fault 0 */
6328 #define TECXFLTLVS1 (0x0200) /* TEV Signal Type of Ext. fault 1 */
6329 #define TECXFLTLVS2 (0x0400) /* TEV Signal Type of Ext. fault 2 */
6330 #define TECXFLTLVS3 (0x0800) /* TEV Signal Type of Ext. fault 3 */
6331 #define TECXFLTLVS4 (0x1000) /* TEV Signal Type of Ext. fault 4 */
6332 #define TECXFLTLVS5 (0x2000) /* TEV Signal Type of Ext. fault 5 */
6333 #define TECXFLTLVS6 (0x4000) /* TEV Signal Type of Ext. fault 6 */
6334 
6335 /* TECxXCTL1 Control Bits */
6336 #define TECXFLTPOL0_L (0x0001) /* TEV Polarity Bit of ext. fault 0 */
6337 #define TECXFLTPOL1_L (0x0002) /* TEV Polarity Bit of ext. fault 1 */
6338 #define TECXFLTPOL2_L (0x0004) /* TEV Polarity Bit of ext. fault 2 */
6339 #define TECXFLTPOL3_L (0x0008) /* TEV Polarity Bit of ext. fault 3 */
6340 #define TECXFLTPOL4_L (0x0010) /* TEV Polarity Bit of ext. fault 4 */
6341 #define TECXFLTPOL5_L (0x0020) /* TEV Polarity Bit of ext. fault 5 */
6342 #define TECXFLTPOL6_L (0x0040) /* TEV Polarity Bit of ext. fault 6 */
6343 
6344 /* TECxXCTL1 Control Bits */
6345 #define TECXFLTLVS0_H (0x0001) /* TEV Signal Type of Ext. fault 0 */
6346 #define TECXFLTLVS1_H (0x0002) /* TEV Signal Type of Ext. fault 1 */
6347 #define TECXFLTLVS2_H (0x0004) /* TEV Signal Type of Ext. fault 2 */
6348 #define TECXFLTLVS3_H (0x0008) /* TEV Signal Type of Ext. fault 3 */
6349 #define TECXFLTLVS4_H (0x0010) /* TEV Signal Type of Ext. fault 4 */
6350 #define TECXFLTLVS5_H (0x0020) /* TEV Signal Type of Ext. fault 5 */
6351 #define TECXFLTLVS6_H (0x0040) /* TEV Signal Type of Ext. fault 6 */
6352 
6353 /* TECxXCTL2 Control Bits */
6354 #define TECCLKSEL0 (0x0001) /* TEV Aux. Clock Select Bit: 0 */
6355 #define TECCLKSEL1 (0x0002) /* TEV Aux. Clock Select Bit: 1 */
6356 #define TECAXCLREN (0x0004) /* TEV Auxilary clear signal control */
6357 #define TECEXCLREN (0x0008) /* TEV Ext. clear signal control */
6358 #define TECEXCLRHLD (0x0010) /* TEV External clear signal hold bit */
6359 #define TECEXCLRPOL (0x0020) /* TEV Polarity Bit of ext. clear */
6360 #define TECEXCLRLVS (0x0040) /* TEV Signal Type of Ext. clear */
6361 
6362 /* TECxXCTL2 Control Bits */
6363 #define TECCLKSEL0_L (0x0001) /* TEV Aux. Clock Select Bit: 0 */
6364 #define TECCLKSEL1_L (0x0002) /* TEV Aux. Clock Select Bit: 1 */
6365 #define TECAXCLREN_L (0x0004) /* TEV Auxilary clear signal control */
6366 #define TECEXCLREN_L (0x0008) /* TEV Ext. clear signal control */
6367 #define TECEXCLRHLD_L (0x0010) /* TEV External clear signal hold bit */
6368 #define TECEXCLRPOL_L (0x0020) /* TEV Polarity Bit of ext. clear */
6369 #define TECEXCLRLVS_L (0x0040) /* TEV Signal Type of Ext. clear */
6370 
6371 #define TECCLKSEL_0 (0x0000) /* TEV Aux. Clock Select: CLK0 */
6372 #define TECCLKSEL_1 (0x0001) /* TEV Aux. Clock Select: CLK1 */
6373 #define TECCLKSEL_2 (0x0002) /* TEV Aux. Clock Select: CLK2 */
6374 #define TECCLKSEL_3 (0x0003) /* TEV Aux. Clock Select: CLK3 */
6375 
6376 /* TECxSTA Control Bits */
6377 #define TECXFLT0STA (0x0001) /* TEV External fault status flag for CE0 */
6378 #define TECXFLT1STA (0x0002) /* TEV External fault status flag for CE1 */
6379 #define TECXFLT2STA (0x0004) /* TEV External fault status flag for CE2 */
6380 #define TECXFLT3STA (0x0008) /* TEV External fault status flag for CE3 */
6381 #define TECXFLT4STA (0x0010) /* TEV External fault status flag for CE4 */
6382 #define TECXFLT5STA (0x0020) /* TEV External fault status flag for CE5 */
6383 #define TECXFLT6STA (0x0040) /* TEV External fault status flag for CE6 */
6384 #define TECXCLRSTA (0x0100) /* TEC External clear status flag */
6385 
6386 /* TECxSTA Control Bits */
6387 #define TECXFLT0STA_L (0x0001) /* TEV External fault status flag for CE0 */
6388 #define TECXFLT1STA_L (0x0002) /* TEV External fault status flag for CE1 */
6389 #define TECXFLT2STA_L (0x0004) /* TEV External fault status flag for CE2 */
6390 #define TECXFLT3STA_L (0x0008) /* TEV External fault status flag for CE3 */
6391 #define TECXFLT4STA_L (0x0010) /* TEV External fault status flag for CE4 */
6392 #define TECXFLT5STA_L (0x0020) /* TEV External fault status flag for CE5 */
6393 #define TECXFLT6STA_L (0x0040) /* TEV External fault status flag for CE6 */
6394 
6395 /* TECxSTA Control Bits */
6396 #define TECXCLRSTA_H (0x0001) /* TEC External clear status flag */
6397 
6398 /* TECxXINT Control Bits */
6399 #define TECAXCLRIFG (0x0001) /* TEC Aux. Clear Interrupt Flag */
6400 #define TECEXCLRIFG (0x0002) /* TEC External Clear Interrupt Flag */
6401 #define TECXFLTIFG (0x0004) /* TEC External Fault Interrupt Flag */
6402 #define TECAXCLRIE (0x0100) /* TEC Aux. Clear Interrupt Enable */
6403 #define TECEXCLRIE (0x0200) /* TEC External Clear Interrupt Enable */
6404 #define TECXFLTIE (0x0400) /* TEC External Fault Interrupt Enable */
6405 
6406 /* TECxXINT Control Bits */
6407 #define TECAXCLRIFG_L (0x0001) /* TEC Aux. Clear Interrupt Flag */
6408 #define TECEXCLRIFG_L (0x0002) /* TEC External Clear Interrupt Flag */
6409 #define TECXFLTIFG_L (0x0004) /* TEC External Fault Interrupt Flag */
6410 
6411 /* TECxXINT Control Bits */
6412 #define TECAXCLRIE_H (0x0001) /* TEC Aux. Clear Interrupt Enable */
6413 #define TECEXCLRIE_H (0x0002) /* TEC External Clear Interrupt Enable */
6414 #define TECXFLTIE_H (0x0004) /* TEC External Fault Interrupt Enable */
6415 
6416 /* TEC0IV Definitions */
6417 #define TEC0IV_NONE (0x0000) /* No Interrupt pending */
6418 #define TEC0IV_TECXFLTIFG (0x0002) /* TEC0XFLTIFG */
6419 #define TEC0IV_TECEXCLRIFG (0x0004) /* TEC0EXCLRIFG */
6420 #define TEC0IV_TECAXCLRIFG (0x0006) /* TEC0AXCLRIFG */
6421 
6422 #endif
6423 /************************************************************
6424 * Timer Event Control x
6425 ************************************************************/
6426 #ifdef __MSP430_HAS_TEVx__ /* Definition to show that Module is available */
6427 
6428 #define OFS_TECxXCTL0 (0x0000) /* Timer Event Control x External Control 0 */
6429 #define OFS_TECxXCTL0_L OFS_TECxXCTL0
6430 #define OFS_TECxXCTL0_H OFS_TECxXCTL0+1
6431 #define OFS_TECxXCTL1 (0x0002) /* Timer Event Control x External Control 1 */
6432 #define OFS_TECxXCTL1_L OFS_TECxXCTL1
6433 #define OFS_TECxXCTL1_H OFS_TECxXCTL1+1
6434 #define OFS_TECxXCTL2 (0x0004) /* Timer Event Control x External Control 2 */
6435 #define OFS_TECxXCTL2_L OFS_TECxXCTL2
6436 #define OFS_TECxXCTL2_H OFS_TECxXCTL2+1
6437 #define OFS_TECxSTA (0x0006) /* Timer Event Control x Status */
6438 #define OFS_TECxSTA_L OFS_TECxSTA
6439 #define OFS_TECxSTA_H OFS_TECxSTA+1
6440 #define OFS_TECxXINT (0x0008) /* Timer Event Control x External Interrupt */
6441 #define OFS_TECxXINT_L OFS_TECxXINT
6442 #define OFS_TECxXINT_H OFS_TECxXINT+1
6443 #define OFS_TECxIV (0x000A) /* Timer Event Control x Interrupt Vector */
6444 #define OFS_TECxIV_L OFS_TECxIV
6445 #define OFS_TECxIV_H OFS_TECxIV+1
6446 
6447 /* TECIV Definitions */
6448 #define TECxIV_NONE (0x0000) /* No Interrupt pending */
6449 #define TECxIV_TECXFLTIFG (0x0002) /* TECxXFLTIFG */
6450 #define TECxIV_TECEXCLRIFG (0x0004) /* TECxEXCLRIFG */
6451 #define TECxIV_TECAXCLRIFG (0x0006) /* TECxAXCLRIFG */
6452 
6453 
6454 #endif
6455 
6456 /************************************************************
6457 * UNIFIED CLOCK SYSTEM
6458 ************************************************************/
6459 #ifdef __MSP430_HAS_UCS__ /* Definition to show that Module is available */
6460 
6461 #define OFS_UCSCTL0 (0x0000) /* UCS Control Register 0 */
6462 #define OFS_UCSCTL0_L OFS_UCSCTL0
6463 #define OFS_UCSCTL0_H OFS_UCSCTL0+1
6464 #define OFS_UCSCTL1 (0x0002) /* UCS Control Register 1 */
6465 #define OFS_UCSCTL1_L OFS_UCSCTL1
6466 #define OFS_UCSCTL1_H OFS_UCSCTL1+1
6467 #define OFS_UCSCTL2 (0x0004) /* UCS Control Register 2 */
6468 #define OFS_UCSCTL2_L OFS_UCSCTL2
6469 #define OFS_UCSCTL2_H OFS_UCSCTL2+1
6470 #define OFS_UCSCTL3 (0x0006) /* UCS Control Register 3 */
6471 #define OFS_UCSCTL3_L OFS_UCSCTL3
6472 #define OFS_UCSCTL3_H OFS_UCSCTL3+1
6473 #define OFS_UCSCTL4 (0x0008) /* UCS Control Register 4 */
6474 #define OFS_UCSCTL4_L OFS_UCSCTL4
6475 #define OFS_UCSCTL4_H OFS_UCSCTL4+1
6476 #define OFS_UCSCTL5 (0x000A) /* UCS Control Register 5 */
6477 #define OFS_UCSCTL5_L OFS_UCSCTL5
6478 #define OFS_UCSCTL5_H OFS_UCSCTL5+1
6479 #define OFS_UCSCTL6 (0x000C) /* UCS Control Register 6 */
6480 #define OFS_UCSCTL6_L OFS_UCSCTL6
6481 #define OFS_UCSCTL6_H OFS_UCSCTL6+1
6482 #define OFS_UCSCTL7 (0x000E) /* UCS Control Register 7 */
6483 #define OFS_UCSCTL7_L OFS_UCSCTL7
6484 #define OFS_UCSCTL7_H OFS_UCSCTL7+1
6485 #define OFS_UCSCTL8 (0x0010) /* UCS Control Register 8 */
6486 #define OFS_UCSCTL8_L OFS_UCSCTL8
6487 #define OFS_UCSCTL8_H OFS_UCSCTL8+1
6488 
6489 /* UCSCTL0 Control Bits */
6490 //#define RESERVED (0x0001) /* RESERVED */
6491 //#define RESERVED (0x0002) /* RESERVED */
6492 //#define RESERVED (0x0004) /* RESERVED */
6493 #define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */
6494 #define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */
6495 #define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */
6496 #define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */
6497 #define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */
6498 #define DCO0 (0x0100) /* DCO TAP Bit : 0 */
6499 #define DCO1 (0x0200) /* DCO TAP Bit : 1 */
6500 #define DCO2 (0x0400) /* DCO TAP Bit : 2 */
6501 #define DCO3 (0x0800) /* DCO TAP Bit : 3 */
6502 #define DCO4 (0x1000) /* DCO TAP Bit : 4 */
6503 //#define RESERVED (0x2000) /* RESERVED */
6504 //#define RESERVED (0x4000) /* RESERVED */
6505 //#define RESERVED (0x8000) /* RESERVED */
6506 
6507 /* UCSCTL0 Control Bits */
6508 //#define RESERVED (0x0001) /* RESERVED */
6509 //#define RESERVED (0x0002) /* RESERVED */
6510 //#define RESERVED (0x0004) /* RESERVED */
6511 #define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */
6512 #define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */
6513 #define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */
6514 #define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */
6515 #define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */
6516 //#define RESERVED (0x2000) /* RESERVED */
6517 //#define RESERVED (0x4000) /* RESERVED */
6518 //#define RESERVED (0x8000) /* RESERVED */
6519 
6520 /* UCSCTL0 Control Bits */
6521 //#define RESERVED (0x0001) /* RESERVED */
6522 //#define RESERVED (0x0002) /* RESERVED */
6523 //#define RESERVED (0x0004) /* RESERVED */
6524 #define DCO0_H (0x0001) /* DCO TAP Bit : 0 */
6525 #define DCO1_H (0x0002) /* DCO TAP Bit : 1 */
6526 #define DCO2_H (0x0004) /* DCO TAP Bit : 2 */
6527 #define DCO3_H (0x0008) /* DCO TAP Bit : 3 */
6528 #define DCO4_H (0x0010) /* DCO TAP Bit : 4 */
6529 //#define RESERVED (0x2000) /* RESERVED */
6530 //#define RESERVED (0x4000) /* RESERVED */
6531 //#define RESERVED (0x8000) /* RESERVED */
6532 
6533 /* UCSCTL1 Control Bits */
6534 #define DISMOD (0x0001) /* Disable Modulation */
6535 //#define RESERVED (0x0002) /* RESERVED */
6536 //#define RESERVED (0x0004) /* RESERVED */
6537 //#define RESERVED (0x0008) /* RESERVED */
6538 #define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */
6539 #define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */
6540 #define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */
6541 //#define RESERVED (0x0080) /* RESERVED */
6542 //#define RESERVED (0x0100) /* RESERVED */
6543 //#define RESERVED (0x0200) /* RESERVED */
6544 //#define RESERVED (0x0400) /* RESERVED */
6545 //#define RESERVED (0x0800) /* RESERVED */
6546 //#define RESERVED (0x1000) /* RESERVED */
6547 //#define RESERVED (0x2000) /* RESERVED */
6548 //#define RESERVED (0x4000) /* RESERVED */
6549 //#define RESERVED (0x8000) /* RESERVED */
6550 
6551 /* UCSCTL1 Control Bits */
6552 #define DISMOD_L (0x0001) /* Disable Modulation */
6553 //#define RESERVED (0x0002) /* RESERVED */
6554 //#define RESERVED (0x0004) /* RESERVED */
6555 //#define RESERVED (0x0008) /* RESERVED */
6556 #define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */
6557 #define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */
6558 #define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */
6559 //#define RESERVED (0x0080) /* RESERVED */
6560 //#define RESERVED (0x0100) /* RESERVED */
6561 //#define RESERVED (0x0200) /* RESERVED */
6562 //#define RESERVED (0x0400) /* RESERVED */
6563 //#define RESERVED (0x0800) /* RESERVED */
6564 //#define RESERVED (0x1000) /* RESERVED */
6565 //#define RESERVED (0x2000) /* RESERVED */
6566 //#define RESERVED (0x4000) /* RESERVED */
6567 //#define RESERVED (0x8000) /* RESERVED */
6568 
6569 #define DCORSEL_0 (0x0000) /* DCO RSEL 0 */
6570 #define DCORSEL_1 (0x0010) /* DCO RSEL 1 */
6571 #define DCORSEL_2 (0x0020) /* DCO RSEL 2 */
6572 #define DCORSEL_3 (0x0030) /* DCO RSEL 3 */
6573 #define DCORSEL_4 (0x0040) /* DCO RSEL 4 */
6574 #define DCORSEL_5 (0x0050) /* DCO RSEL 5 */
6575 #define DCORSEL_6 (0x0060) /* DCO RSEL 6 */
6576 #define DCORSEL_7 (0x0070) /* DCO RSEL 7 */
6577 
6578 /* UCSCTL2 Control Bits */
6579 #define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */
6580 #define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */
6581 #define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */
6582 #define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */
6583 #define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */
6584 #define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */
6585 #define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */
6586 #define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */
6587 #define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */
6588 #define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */
6589 //#define RESERVED (0x0400) /* RESERVED */
6590 //#define RESERVED (0x0800) /* RESERVED */
6591 #define FLLD0 (0x1000) /* Loop Divider Bit : 0 */
6592 #define FLLD1 (0x2000) /* Loop Divider Bit : 1 */
6593 #define FLLD2 (0x4000) /* Loop Divider Bit : 1 */
6594 //#define RESERVED (0x8000) /* RESERVED */
6595 
6596 /* UCSCTL2 Control Bits */
6597 #define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */
6598 #define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */
6599 #define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */
6600 #define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */
6601 #define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */
6602 #define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */
6603 #define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */
6604 #define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */
6605 //#define RESERVED (0x0400) /* RESERVED */
6606 //#define RESERVED (0x0800) /* RESERVED */
6607 //#define RESERVED (0x8000) /* RESERVED */
6608 
6609 /* UCSCTL2 Control Bits */
6610 #define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */
6611 #define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */
6612 //#define RESERVED (0x0400) /* RESERVED */
6613 //#define RESERVED (0x0800) /* RESERVED */
6614 #define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */
6615 #define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */
6616 #define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */
6617 //#define RESERVED (0x8000) /* RESERVED */
6618 
6619 #define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */
6620 #define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */
6621 #define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */
6622 #define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */
6623 #define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */
6624 #define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */
6625 #define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */
6626 #define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */
6627 #define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */
6628 #define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */
6629 #define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */
6630 #define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */
6631 #define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */
6632 #define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */
6633 
6634 /* UCSCTL3 Control Bits */
6635 #define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */
6636 #define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */
6637 #define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */
6638 //#define RESERVED (0x0008) /* RESERVED */
6639 #define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */
6640 #define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */
6641 #define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */
6642 //#define RESERVED (0x0080) /* RESERVED */
6643 //#define RESERVED (0x0100) /* RESERVED */
6644 //#define RESERVED (0x0200) /* RESERVED */
6645 //#define RESERVED (0x0400) /* RESERVED */
6646 //#define RESERVED (0x0800) /* RESERVED */
6647 //#define RESERVED (0x1000) /* RESERVED */
6648 //#define RESERVED (0x2000) /* RESERVED */
6649 //#define RESERVED (0x4000) /* RESERVED */
6650 //#define RESERVED (0x8000) /* RESERVED */
6651 
6652 /* UCSCTL3 Control Bits */
6653 #define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */
6654 #define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */
6655 #define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */
6656 //#define RESERVED (0x0008) /* RESERVED */
6657 #define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */
6658 #define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */
6659 #define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */
6660 //#define RESERVED (0x0080) /* RESERVED */
6661 //#define RESERVED (0x0100) /* RESERVED */
6662 //#define RESERVED (0x0200) /* RESERVED */
6663 //#define RESERVED (0x0400) /* RESERVED */
6664 //#define RESERVED (0x0800) /* RESERVED */
6665 //#define RESERVED (0x1000) /* RESERVED */
6666 //#define RESERVED (0x2000) /* RESERVED */
6667 //#define RESERVED (0x4000) /* RESERVED */
6668 //#define RESERVED (0x8000) /* RESERVED */
6669 
6670 #define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */
6671 #define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */
6672 #define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */
6673 #define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */
6674 #define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */
6675 #define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */
6676 #define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */
6677 #define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */
6678 #define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */
6679 #define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */
6680 #define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */
6681 #define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */
6682 #define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */
6683 #define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */
6684 #define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */
6685 #define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */
6686 #define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */
6687 #define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */
6688 #define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */
6689 #define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */
6690 #define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */
6691 #define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */
6692 #define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */
6693 #define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */
6694 #define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */
6695 
6696 /* UCSCTL4 Control Bits */
6697 #define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
6698 #define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
6699 #define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
6700 //#define RESERVED (0x0008) /* RESERVED */
6701 #define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
6702 #define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
6703 #define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
6704 //#define RESERVED (0x0080) /* RESERVED */
6705 #define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
6706 #define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
6707 #define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
6708 //#define RESERVED (0x0800) /* RESERVED */
6709 //#define RESERVED (0x1000) /* RESERVED */
6710 //#define RESERVED (0x2000) /* RESERVED */
6711 //#define RESERVED (0x4000) /* RESERVED */
6712 //#define RESERVED (0x8000) /* RESERVED */
6713 
6714 /* UCSCTL4 Control Bits */
6715 #define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
6716 #define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
6717 #define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
6718 //#define RESERVED (0x0008) /* RESERVED */
6719 #define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
6720 #define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
6721 #define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
6722 //#define RESERVED (0x0080) /* RESERVED */
6723 //#define RESERVED (0x0800) /* RESERVED */
6724 //#define RESERVED (0x1000) /* RESERVED */
6725 //#define RESERVED (0x2000) /* RESERVED */
6726 //#define RESERVED (0x4000) /* RESERVED */
6727 //#define RESERVED (0x8000) /* RESERVED */
6728 
6729 /* UCSCTL4 Control Bits */
6730 //#define RESERVED (0x0008) /* RESERVED */
6731 //#define RESERVED (0x0080) /* RESERVED */
6732 #define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
6733 #define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
6734 #define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
6735 //#define RESERVED (0x0800) /* RESERVED */
6736 //#define RESERVED (0x1000) /* RESERVED */
6737 //#define RESERVED (0x2000) /* RESERVED */
6738 //#define RESERVED (0x4000) /* RESERVED */
6739 //#define RESERVED (0x8000) /* RESERVED */
6740 
6741 #define SELM_0 (0x0000) /* MCLK Source Select 0 */
6742 #define SELM_1 (0x0001) /* MCLK Source Select 1 */
6743 #define SELM_2 (0x0002) /* MCLK Source Select 2 */
6744 #define SELM_3 (0x0003) /* MCLK Source Select 3 */
6745 #define SELM_4 (0x0004) /* MCLK Source Select 4 */
6746 #define SELM_5 (0x0005) /* MCLK Source Select 5 */
6747 #define SELM_6 (0x0006) /* MCLK Source Select 6 */
6748 #define SELM_7 (0x0007) /* MCLK Source Select 7 */
6749 #define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */
6750 #define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
6751 #define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */
6752 #define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
6753 #define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */
6754 #define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */
6755 
6756 #define SELS_0 (0x0000) /* SMCLK Source Select 0 */
6757 #define SELS_1 (0x0010) /* SMCLK Source Select 1 */
6758 #define SELS_2 (0x0020) /* SMCLK Source Select 2 */
6759 #define SELS_3 (0x0030) /* SMCLK Source Select 3 */
6760 #define SELS_4 (0x0040) /* SMCLK Source Select 4 */
6761 #define SELS_5 (0x0050) /* SMCLK Source Select 5 */
6762 #define SELS_6 (0x0060) /* SMCLK Source Select 6 */
6763 #define SELS_7 (0x0070) /* SMCLK Source Select 7 */
6764 #define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */
6765 #define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
6766 #define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */
6767 #define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
6768 #define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */
6769 #define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */
6770 
6771 #define SELA_0 (0x0000) /* ACLK Source Select 0 */
6772 #define SELA_1 (0x0100) /* ACLK Source Select 1 */
6773 #define SELA_2 (0x0200) /* ACLK Source Select 2 */
6774 #define SELA_3 (0x0300) /* ACLK Source Select 3 */
6775 #define SELA_4 (0x0400) /* ACLK Source Select 4 */
6776 #define SELA_5 (0x0500) /* ACLK Source Select 5 */
6777 #define SELA_6 (0x0600) /* ACLK Source Select 6 */
6778 #define SELA_7 (0x0700) /* ACLK Source Select 7 */
6779 #define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */
6780 #define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
6781 #define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */
6782 #define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */
6783 #define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */
6784 #define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */
6785 
6786 /* UCSCTL5 Control Bits */
6787 #define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
6788 #define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
6789 #define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
6790 //#define RESERVED (0x0008) /* RESERVED */
6791 #define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
6792 #define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
6793 #define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
6794 //#define RESERVED (0x0080) /* RESERVED */
6795 #define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
6796 #define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
6797 #define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
6798 //#define RESERVED (0x0800) /* RESERVED */
6799 #define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */
6800 #define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */
6801 #define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */
6802 //#define RESERVED (0x8000) /* RESERVED */
6803 
6804 /* UCSCTL5 Control Bits */
6805 #define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
6806 #define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
6807 #define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
6808 //#define RESERVED (0x0008) /* RESERVED */
6809 #define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
6810 #define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
6811 #define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
6812 //#define RESERVED (0x0080) /* RESERVED */
6813 //#define RESERVED (0x0800) /* RESERVED */
6814 //#define RESERVED (0x8000) /* RESERVED */
6815 
6816 /* UCSCTL5 Control Bits */
6817 //#define RESERVED (0x0008) /* RESERVED */
6818 //#define RESERVED (0x0080) /* RESERVED */
6819 #define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
6820 #define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
6821 #define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
6822 //#define RESERVED (0x0800) /* RESERVED */
6823 #define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */
6824 #define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */
6825 #define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */
6826 //#define RESERVED (0x8000) /* RESERVED */
6827 
6828 #define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
6829 #define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
6830 #define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
6831 #define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
6832 #define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
6833 #define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
6834 #define DIVM_6 (0x0006) /* MCLK Source Divider 6 */
6835 #define DIVM_7 (0x0007) /* MCLK Source Divider 7 */
6836 #define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
6837 #define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
6838 #define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
6839 #define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
6840 #define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
6841 #define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
6842 
6843 #define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
6844 #define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
6845 #define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
6846 #define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
6847 #define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
6848 #define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
6849 #define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */
6850 #define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */
6851 #define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
6852 #define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
6853 #define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
6854 #define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
6855 #define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
6856 #define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
6857 
6858 #define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
6859 #define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
6860 #define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
6861 #define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
6862 #define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
6863 #define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
6864 #define DIVA_6 (0x0600) /* ACLK Source Divider 6 */
6865 #define DIVA_7 (0x0700) /* ACLK Source Divider 7 */
6866 #define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
6867 #define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
6868 #define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
6869 #define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
6870 #define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
6871 #define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
6872 
6873 #define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */
6874 #define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */
6875 #define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */
6876 #define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */
6877 #define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */
6878 #define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */
6879 #define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */
6880 #define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */
6881 #define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */
6882 #define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */
6883 #define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */
6884 #define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */
6885 #define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */
6886 #define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */
6887 
6888 /* UCSCTL6 Control Bits */
6889 #define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
6890 #define SMCLKOFF (0x0002) /* SMCLK Off */
6891 #define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */
6892 #define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */
6893 #define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
6894 #define XTS (0x0020) /* 1: Selects high-freq. oscillator */
6895 #define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */
6896 #define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */
6897 #define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */
6898 //#define RESERVED (0x0200) /* RESERVED */
6899 //#define RESERVED (0x0400) /* RESERVED */
6900 //#define RESERVED (0x0800) /* RESERVED */
6901 #define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
6902 //#define RESERVED (0x2000) /* RESERVED */
6903 #define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */
6904 #define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */
6905 
6906 /* UCSCTL6 Control Bits */
6907 #define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
6908 #define SMCLKOFF_L (0x0002) /* SMCLK Off */
6909 #define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */
6910 #define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */
6911 #define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
6912 #define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */
6913 #define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */
6914 #define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */
6915 //#define RESERVED (0x0200) /* RESERVED */
6916 //#define RESERVED (0x0400) /* RESERVED */
6917 //#define RESERVED (0x0800) /* RESERVED */
6918 //#define RESERVED (0x2000) /* RESERVED */
6919 
6920 /* UCSCTL6 Control Bits */
6921 #define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */
6922 //#define RESERVED (0x0200) /* RESERVED */
6923 //#define RESERVED (0x0400) /* RESERVED */
6924 //#define RESERVED (0x0800) /* RESERVED */
6925 #define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
6926 //#define RESERVED (0x2000) /* RESERVED */
6927 #define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */
6928 #define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */
6929 
6930 #define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */
6931 #define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */
6932 #define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */
6933 #define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */
6934 #define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */
6935 #define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */
6936 #define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */
6937 #define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */
6938 #define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */
6939 #define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */
6940 #define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */
6941 #define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */
6942 
6943 /* UCSCTL7 Control Bits */
6944 #define DCOFFG (0x0001) /* DCO Fault Flag */
6945 #define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
6946 #define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
6947 #define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */
6948 //#define RESERVED (0x0010) /* RESERVED */
6949 //#define RESERVED (0x0020) /* RESERVED */
6950 //#define RESERVED (0x0040) /* RESERVED */
6951 //#define RESERVED (0x0080) /* RESERVED */
6952 //#define RESERVED (0x0100) /* RESERVED */
6953 //#define RESERVED (0x0200) /* RESERVED */
6954 //#define RESERVED (0x0400) /* RESERVED */
6955 //#define RESERVED (0x0800) /* RESERVED */
6956 //#define RESERVED (0x1000) /* RESERVED */
6957 //#define RESERVED (0x2000) /* RESERVED */
6958 //#define RESERVED (0x4000) /* RESERVED */
6959 //#define RESERVED (0x8000) /* RESERVED */
6960 
6961 /* UCSCTL7 Control Bits */
6962 #define DCOFFG_L (0x0001) /* DCO Fault Flag */
6963 #define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
6964 #define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
6965 #define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */
6966 //#define RESERVED (0x0010) /* RESERVED */
6967 //#define RESERVED (0x0020) /* RESERVED */
6968 //#define RESERVED (0x0040) /* RESERVED */
6969 //#define RESERVED (0x0080) /* RESERVED */
6970 //#define RESERVED (0x0100) /* RESERVED */
6971 //#define RESERVED (0x0200) /* RESERVED */
6972 //#define RESERVED (0x0400) /* RESERVED */
6973 //#define RESERVED (0x0800) /* RESERVED */
6974 //#define RESERVED (0x1000) /* RESERVED */
6975 //#define RESERVED (0x2000) /* RESERVED */
6976 //#define RESERVED (0x4000) /* RESERVED */
6977 //#define RESERVED (0x8000) /* RESERVED */
6978 
6979 /* UCSCTL8 Control Bits */
6980 #define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
6981 #define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
6982 #define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
6983 #define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */
6984 //#define RESERVED (0x0010) /* RESERVED */
6985 //#define RESERVED (0x0020) /* RESERVED */
6986 //#define RESERVED (0x0040) /* RESERVED */
6987 //#define RESERVED (0x0080) /* RESERVED */
6988 //#define RESERVED (0x0100) /* RESERVED */
6989 //#define RESERVED (0x0200) /* RESERVED */
6990 //#define RESERVED (0x0400) /* RESERVED */
6991 //#define RESERVED (0x0800) /* RESERVED */
6992 //#define RESERVED (0x1000) /* RESERVED */
6993 //#define RESERVED (0x2000) /* RESERVED */
6994 //#define RESERVED (0x4000) /* RESERVED */
6995 //#define RESERVED (0x8000) /* RESERVED */
6996 
6997 /* UCSCTL8 Control Bits */
6998 #define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
6999 #define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
7000 #define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
7001 #define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */
7002 //#define RESERVED (0x0010) /* RESERVED */
7003 //#define RESERVED (0x0020) /* RESERVED */
7004 //#define RESERVED (0x0040) /* RESERVED */
7005 //#define RESERVED (0x0080) /* RESERVED */
7006 //#define RESERVED (0x0100) /* RESERVED */
7007 //#define RESERVED (0x0200) /* RESERVED */
7008 //#define RESERVED (0x0400) /* RESERVED */
7009 //#define RESERVED (0x0800) /* RESERVED */
7010 //#define RESERVED (0x1000) /* RESERVED */
7011 //#define RESERVED (0x2000) /* RESERVED */
7012 //#define RESERVED (0x4000) /* RESERVED */
7013 //#define RESERVED (0x8000) /* RESERVED */
7014 
7015 #endif
7016 /************************************************************
7017 * UNIFIED CLOCK SYSTEM FOR Radio Devices
7018 ************************************************************/
7019 #ifdef __MSP430_HAS_UCS_RF__ /* Definition to show that Module is available */
7020 
7021 #define OFS_UCSCTL0 (0x0000) /* UCS Control Register 0 */
7022 #define OFS_UCSCTL0_L OFS_UCSCTL0
7023 #define OFS_UCSCTL0_H OFS_UCSCTL0+1
7024 #define OFS_UCSCTL1 (0x0002) /* UCS Control Register 1 */
7025 #define OFS_UCSCTL1_L OFS_UCSCTL1
7026 #define OFS_UCSCTL1_H OFS_UCSCTL1+1
7027 #define OFS_UCSCTL2 (0x0004) /* UCS Control Register 2 */
7028 #define OFS_UCSCTL2_L OFS_UCSCTL2
7029 #define OFS_UCSCTL2_H OFS_UCSCTL2+1
7030 #define OFS_UCSCTL3 (0x0006) /* UCS Control Register 3 */
7031 #define OFS_UCSCTL3_L OFS_UCSCTL3
7032 #define OFS_UCSCTL3_H OFS_UCSCTL3+1
7033 #define OFS_UCSCTL4 (0x0008) /* UCS Control Register 4 */
7034 #define OFS_UCSCTL4_L OFS_UCSCTL4
7035 #define OFS_UCSCTL4_H OFS_UCSCTL4+1
7036 #define OFS_UCSCTL5 (0x000A) /* UCS Control Register 5 */
7037 #define OFS_UCSCTL5_L OFS_UCSCTL5
7038 #define OFS_UCSCTL5_H OFS_UCSCTL5+1
7039 #define OFS_UCSCTL6 (0x000C) /* UCS Control Register 6 */
7040 #define OFS_UCSCTL6_L OFS_UCSCTL6
7041 #define OFS_UCSCTL6_H OFS_UCSCTL6+1
7042 #define OFS_UCSCTL7 (0x000E) /* UCS Control Register 7 */
7043 #define OFS_UCSCTL7_L OFS_UCSCTL7
7044 #define OFS_UCSCTL7_H OFS_UCSCTL7+1
7045 #define OFS_UCSCTL8 (0x0010) /* UCS Control Register 8 */
7046 #define OFS_UCSCTL8_L OFS_UCSCTL8
7047 #define OFS_UCSCTL8_H OFS_UCSCTL8+1
7048 
7049 /* UCSCTL0 Control Bits */
7050 //#define RESERVED (0x0001) /* RESERVED */
7051 //#define RESERVED (0x0002) /* RESERVED */
7052 //#define RESERVED (0x0004) /* RESERVED */
7053 #define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */
7054 #define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */
7055 #define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */
7056 #define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */
7057 #define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */
7058 #define DCO0 (0x0100) /* DCO TAP Bit : 0 */
7059 #define DCO1 (0x0200) /* DCO TAP Bit : 1 */
7060 #define DCO2 (0x0400) /* DCO TAP Bit : 2 */
7061 #define DCO3 (0x0800) /* DCO TAP Bit : 3 */
7062 #define DCO4 (0x1000) /* DCO TAP Bit : 4 */
7063 //#define RESERVED (0x2000) /* RESERVED */
7064 //#define RESERVED (0x4000) /* RESERVED */
7065 //#define RESERVED (0x8000) /* RESERVED */
7066 
7067 /* UCSCTL0 Control Bits */
7068 //#define RESERVED (0x0001) /* RESERVED */
7069 //#define RESERVED (0x0002) /* RESERVED */
7070 //#define RESERVED (0x0004) /* RESERVED */
7071 #define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */
7072 #define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */
7073 #define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */
7074 #define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */
7075 #define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */
7076 //#define RESERVED (0x2000) /* RESERVED */
7077 //#define RESERVED (0x4000) /* RESERVED */
7078 //#define RESERVED (0x8000) /* RESERVED */
7079 
7080 /* UCSCTL0 Control Bits */
7081 //#define RESERVED (0x0001) /* RESERVED */
7082 //#define RESERVED (0x0002) /* RESERVED */
7083 //#define RESERVED (0x0004) /* RESERVED */
7084 #define DCO0_H (0x0001) /* DCO TAP Bit : 0 */
7085 #define DCO1_H (0x0002) /* DCO TAP Bit : 1 */
7086 #define DCO2_H (0x0004) /* DCO TAP Bit : 2 */
7087 #define DCO3_H (0x0008) /* DCO TAP Bit : 3 */
7088 #define DCO4_H (0x0010) /* DCO TAP Bit : 4 */
7089 //#define RESERVED (0x2000) /* RESERVED */
7090 //#define RESERVED (0x4000) /* RESERVED */
7091 //#define RESERVED (0x8000) /* RESERVED */
7092 
7093 /* UCSCTL1 Control Bits */
7094 #define DISMOD (0x0001) /* Disable Modulation */
7095 //#define RESERVED (0x0002) /* RESERVED */
7096 //#define RESERVED (0x0004) /* RESERVED */
7097 //#define RESERVED (0x0008) /* RESERVED */
7098 #define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */
7099 #define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */
7100 #define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */
7101 //#define RESERVED (0x0080) /* RESERVED */
7102 //#define RESERVED (0x0100) /* RESERVED */
7103 //#define RESERVED (0x0200) /* RESERVED */
7104 //#define RESERVED (0x0400) /* RESERVED */
7105 //#define RESERVED (0x0800) /* RESERVED */
7106 //#define RESERVED (0x1000) /* RESERVED */
7107 //#define RESERVED (0x2000) /* RESERVED */
7108 //#define RESERVED (0x4000) /* RESERVED */
7109 //#define RESERVED (0x8000) /* RESERVED */
7110 
7111 /* UCSCTL1 Control Bits */
7112 #define DISMOD_L (0x0001) /* Disable Modulation */
7113 //#define RESERVED (0x0002) /* RESERVED */
7114 //#define RESERVED (0x0004) /* RESERVED */
7115 //#define RESERVED (0x0008) /* RESERVED */
7116 #define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */
7117 #define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */
7118 #define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */
7119 //#define RESERVED (0x0080) /* RESERVED */
7120 //#define RESERVED (0x0100) /* RESERVED */
7121 //#define RESERVED (0x0200) /* RESERVED */
7122 //#define RESERVED (0x0400) /* RESERVED */
7123 //#define RESERVED (0x0800) /* RESERVED */
7124 //#define RESERVED (0x1000) /* RESERVED */
7125 //#define RESERVED (0x2000) /* RESERVED */
7126 //#define RESERVED (0x4000) /* RESERVED */
7127 //#define RESERVED (0x8000) /* RESERVED */
7128 
7129 #define DCORSEL_0 (0x0000) /* DCO RSEL 0 */
7130 #define DCORSEL_1 (0x0010) /* DCO RSEL 1 */
7131 #define DCORSEL_2 (0x0020) /* DCO RSEL 2 */
7132 #define DCORSEL_3 (0x0030) /* DCO RSEL 3 */
7133 #define DCORSEL_4 (0x0040) /* DCO RSEL 4 */
7134 #define DCORSEL_5 (0x0050) /* DCO RSEL 5 */
7135 #define DCORSEL_6 (0x0060) /* DCO RSEL 6 */
7136 #define DCORSEL_7 (0x0070) /* DCO RSEL 7 */
7137 
7138 /* UCSCTL2 Control Bits */
7139 #define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */
7140 #define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */
7141 #define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */
7142 #define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */
7143 #define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */
7144 #define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */
7145 #define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */
7146 #define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */
7147 #define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */
7148 #define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */
7149 //#define RESERVED (0x0400) /* RESERVED */
7150 //#define RESERVED (0x0800) /* RESERVED */
7151 #define FLLD0 (0x1000) /* Loop Divider Bit : 0 */
7152 #define FLLD1 (0x2000) /* Loop Divider Bit : 1 */
7153 #define FLLD2 (0x4000) /* Loop Divider Bit : 1 */
7154 //#define RESERVED (0x8000) /* RESERVED */
7155 
7156 /* UCSCTL2 Control Bits */
7157 #define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */
7158 #define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */
7159 #define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */
7160 #define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */
7161 #define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */
7162 #define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */
7163 #define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */
7164 #define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */
7165 //#define RESERVED (0x0400) /* RESERVED */
7166 //#define RESERVED (0x0800) /* RESERVED */
7167 //#define RESERVED (0x8000) /* RESERVED */
7168 
7169 /* UCSCTL2 Control Bits */
7170 #define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */
7171 #define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */
7172 //#define RESERVED (0x0400) /* RESERVED */
7173 //#define RESERVED (0x0800) /* RESERVED */
7174 #define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */
7175 #define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */
7176 #define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */
7177 //#define RESERVED (0x8000) /* RESERVED */
7178 
7179 #define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */
7180 #define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */
7181 #define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */
7182 #define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */
7183 #define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */
7184 #define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */
7185 #define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */
7186 #define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */
7187 #define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */
7188 #define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */
7189 #define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */
7190 #define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */
7191 #define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */
7192 #define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */
7193 
7194 /* UCSCTL3 Control Bits */
7195 #define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */
7196 #define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */
7197 #define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */
7198 //#define RESERVED (0x0008) /* RESERVED */
7199 #define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */
7200 #define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */
7201 #define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */
7202 //#define RESERVED (0x0080) /* RESERVED */
7203 //#define RESERVED (0x0100) /* RESERVED */
7204 //#define RESERVED (0x0200) /* RESERVED */
7205 //#define RESERVED (0x0400) /* RESERVED */
7206 //#define RESERVED (0x0800) /* RESERVED */
7207 //#define RESERVED (0x1000) /* RESERVED */
7208 //#define RESERVED (0x2000) /* RESERVED */
7209 //#define RESERVED (0x4000) /* RESERVED */
7210 //#define RESERVED (0x8000) /* RESERVED */
7211 
7212 /* UCSCTL3 Control Bits */
7213 #define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */
7214 #define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */
7215 #define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */
7216 //#define RESERVED (0x0008) /* RESERVED */
7217 #define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */
7218 #define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */
7219 #define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */
7220 //#define RESERVED (0x0080) /* RESERVED */
7221 //#define RESERVED (0x0100) /* RESERVED */
7222 //#define RESERVED (0x0200) /* RESERVED */
7223 //#define RESERVED (0x0400) /* RESERVED */
7224 //#define RESERVED (0x0800) /* RESERVED */
7225 //#define RESERVED (0x1000) /* RESERVED */
7226 //#define RESERVED (0x2000) /* RESERVED */
7227 //#define RESERVED (0x4000) /* RESERVED */
7228 //#define RESERVED (0x8000) /* RESERVED */
7229 
7230 #define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */
7231 #define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */
7232 #define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */
7233 #define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */
7234 #define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */
7235 #define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */
7236 #define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */
7237 #define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */
7238 #define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */
7239 #define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */
7240 #define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */
7241 #define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */
7242 #define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */
7243 #define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */
7244 #define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */
7245 #define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */
7246 #define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */
7247 #define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */
7248 #define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */
7249 #define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */
7250 #define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */
7251 #define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */
7252 #define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */
7253 #define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */
7254 #define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */
7255 
7256 /* UCSCTL4 Control Bits */
7257 #define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
7258 #define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
7259 #define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
7260 //#define RESERVED (0x0008) /* RESERVED */
7261 #define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
7262 #define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
7263 #define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
7264 //#define RESERVED (0x0080) /* RESERVED */
7265 #define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
7266 #define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
7267 #define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
7268 //#define RESERVED (0x0800) /* RESERVED */
7269 //#define RESERVED (0x1000) /* RESERVED */
7270 //#define RESERVED (0x2000) /* RESERVED */
7271 //#define RESERVED (0x4000) /* RESERVED */
7272 //#define RESERVED (0x8000) /* RESERVED */
7273 
7274 /* UCSCTL4 Control Bits */
7275 #define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
7276 #define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
7277 #define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
7278 //#define RESERVED (0x0008) /* RESERVED */
7279 #define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
7280 #define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
7281 #define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
7282 //#define RESERVED (0x0080) /* RESERVED */
7283 //#define RESERVED (0x0800) /* RESERVED */
7284 //#define RESERVED (0x1000) /* RESERVED */
7285 //#define RESERVED (0x2000) /* RESERVED */
7286 //#define RESERVED (0x4000) /* RESERVED */
7287 //#define RESERVED (0x8000) /* RESERVED */
7288 
7289 /* UCSCTL4 Control Bits */
7290 //#define RESERVED (0x0008) /* RESERVED */
7291 //#define RESERVED (0x0080) /* RESERVED */
7292 #define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
7293 #define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
7294 #define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
7295 //#define RESERVED (0x0800) /* RESERVED */
7296 //#define RESERVED (0x1000) /* RESERVED */
7297 //#define RESERVED (0x2000) /* RESERVED */
7298 //#define RESERVED (0x4000) /* RESERVED */
7299 //#define RESERVED (0x8000) /* RESERVED */
7300 
7301 #define SELM_0 (0x0000) /* MCLK Source Select 0 */
7302 #define SELM_1 (0x0001) /* MCLK Source Select 1 */
7303 #define SELM_2 (0x0002) /* MCLK Source Select 2 */
7304 #define SELM_3 (0x0003) /* MCLK Source Select 3 */
7305 #define SELM_4 (0x0004) /* MCLK Source Select 4 */
7306 #define SELM_5 (0x0005) /* MCLK Source Select 5 */
7307 #define SELM_6 (0x0006) /* MCLK Source Select 6 */
7308 #define SELM_7 (0x0007) /* MCLK Source Select 7 */
7309 #define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */
7310 #define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
7311 #define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */
7312 #define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
7313 #define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */
7314 #define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */
7315 
7316 #define SELS_0 (0x0000) /* SMCLK Source Select 0 */
7317 #define SELS_1 (0x0010) /* SMCLK Source Select 1 */
7318 #define SELS_2 (0x0020) /* SMCLK Source Select 2 */
7319 #define SELS_3 (0x0030) /* SMCLK Source Select 3 */
7320 #define SELS_4 (0x0040) /* SMCLK Source Select 4 */
7321 #define SELS_5 (0x0050) /* SMCLK Source Select 5 */
7322 #define SELS_6 (0x0060) /* SMCLK Source Select 6 */
7323 #define SELS_7 (0x0070) /* SMCLK Source Select 7 */
7324 #define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */
7325 #define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
7326 #define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */
7327 #define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
7328 #define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */
7329 #define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */
7330 
7331 #define SELA_0 (0x0000) /* ACLK Source Select 0 */
7332 #define SELA_1 (0x0100) /* ACLK Source Select 1 */
7333 #define SELA_2 (0x0200) /* ACLK Source Select 2 */
7334 #define SELA_3 (0x0300) /* ACLK Source Select 3 */
7335 #define SELA_4 (0x0400) /* ACLK Source Select 4 */
7336 #define SELA_5 (0x0500) /* ACLK Source Select 5 */
7337 #define SELA_6 (0x0600) /* ACLK Source Select 6 */
7338 #define SELA_7 (0x0700) /* ACLK Source Select 7 */
7339 #define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */
7340 #define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
7341 #define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */
7342 #define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */
7343 #define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */
7344 #define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */
7345 
7346 /* UCSCTL5 Control Bits */
7347 #define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
7348 #define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
7349 #define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
7350 //#define RESERVED (0x0008) /* RESERVED */
7351 #define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
7352 #define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
7353 #define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
7354 //#define RESERVED (0x0080) /* RESERVED */
7355 #define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
7356 #define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
7357 #define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
7358 //#define RESERVED (0x0800) /* RESERVED */
7359 #define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */
7360 #define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */
7361 #define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */
7362 //#define RESERVED (0x8000) /* RESERVED */
7363 
7364 /* UCSCTL5 Control Bits */
7365 #define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
7366 #define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
7367 #define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
7368 //#define RESERVED (0x0008) /* RESERVED */
7369 #define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
7370 #define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
7371 #define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
7372 //#define RESERVED (0x0080) /* RESERVED */
7373 //#define RESERVED (0x0800) /* RESERVED */
7374 //#define RESERVED (0x8000) /* RESERVED */
7375 
7376 /* UCSCTL5 Control Bits */
7377 //#define RESERVED (0x0008) /* RESERVED */
7378 //#define RESERVED (0x0080) /* RESERVED */
7379 #define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
7380 #define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
7381 #define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
7382 //#define RESERVED (0x0800) /* RESERVED */
7383 #define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */
7384 #define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */
7385 #define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */
7386 //#define RESERVED (0x8000) /* RESERVED */
7387 
7388 #define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
7389 #define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
7390 #define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
7391 #define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
7392 #define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
7393 #define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
7394 #define DIVM_6 (0x0006) /* MCLK Source Divider 6 */
7395 #define DIVM_7 (0x0007) /* MCLK Source Divider 7 */
7396 #define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
7397 #define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
7398 #define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
7399 #define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
7400 #define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
7401 #define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
7402 
7403 #define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
7404 #define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
7405 #define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
7406 #define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
7407 #define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
7408 #define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
7409 #define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */
7410 #define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */
7411 #define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
7412 #define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
7413 #define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
7414 #define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
7415 #define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
7416 #define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
7417 
7418 #define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
7419 #define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
7420 #define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
7421 #define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
7422 #define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
7423 #define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
7424 #define DIVA_6 (0x0600) /* ACLK Source Divider 6 */
7425 #define DIVA_7 (0x0700) /* ACLK Source Divider 7 */
7426 #define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
7427 #define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
7428 #define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
7429 #define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
7430 #define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
7431 #define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
7432 
7433 #define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */
7434 #define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */
7435 #define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */
7436 #define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */
7437 #define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */
7438 #define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */
7439 #define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */
7440 #define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */
7441 #define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */
7442 #define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */
7443 #define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */
7444 #define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */
7445 #define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */
7446 #define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */
7447 
7448 /* UCSCTL6 Control Bits */
7449 #define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
7450 #define SMCLKOFF (0x0002) /* SMCLK Off */
7451 #define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */
7452 #define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */
7453 #define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
7454 #define XTS (0x0020) /* 1: Selects high-freq. oscillator */
7455 #define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */
7456 #define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */
7457 #define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */
7458 //#define RESERVED (0x0200) /* RESERVED */
7459 //#define RESERVED (0x0400) /* RESERVED */
7460 //#define RESERVED (0x0800) /* RESERVED */
7461 //#define RESERVED (0x1000) /* RESERVED */
7462 //#define RESERVED (0x2000) /* RESERVED */
7463 //#define RESERVED (0x4000) /* RESERVED */
7464 //#define RESERVED (0x8000) /* RESERVED */
7465 
7466 /* UCSCTL6 Control Bits */
7467 #define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
7468 #define SMCLKOFF_L (0x0002) /* SMCLK Off */
7469 #define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */
7470 #define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */
7471 #define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
7472 #define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */
7473 #define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */
7474 #define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */
7475 //#define RESERVED (0x0200) /* RESERVED */
7476 //#define RESERVED (0x0400) /* RESERVED */
7477 //#define RESERVED (0x0800) /* RESERVED */
7478 //#define RESERVED (0x1000) /* RESERVED */
7479 //#define RESERVED (0x2000) /* RESERVED */
7480 //#define RESERVED (0x4000) /* RESERVED */
7481 //#define RESERVED (0x8000) /* RESERVED */
7482 
7483 /* UCSCTL6 Control Bits */
7484 #define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */
7485 //#define RESERVED (0x0200) /* RESERVED */
7486 //#define RESERVED (0x0400) /* RESERVED */
7487 //#define RESERVED (0x0800) /* RESERVED */
7488 //#define RESERVED (0x1000) /* RESERVED */
7489 //#define RESERVED (0x2000) /* RESERVED */
7490 //#define RESERVED (0x4000) /* RESERVED */
7491 //#define RESERVED (0x8000) /* RESERVED */
7492 
7493 #define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */
7494 #define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */
7495 #define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */
7496 #define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */
7497 #define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */
7498 #define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */
7499 #define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */
7500 #define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */
7501 
7502 /* UCSCTL7 Control Bits */
7503 #define DCOFFG (0x0001) /* DCO Fault Flag */
7504 #define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
7505 #define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
7506 #define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */
7507 //#define RESERVED (0x0010) /* RESERVED */
7508 //#define RESERVED (0x0020) /* RESERVED */
7509 //#define RESERVED (0x0040) /* RESERVED */
7510 //#define RESERVED (0x0080) /* RESERVED */
7511 //#define RESERVED (0x0100) /* RESERVED */
7512 //#define RESERVED (0x0200) /* RESERVED */
7513 //#define RESERVED (0x0400) /* RESERVED */
7514 //#define RESERVED (0x0800) /* RESERVED */
7515 //#define RESERVED (0x1000) /* RESERVED */
7516 //#define RESERVED (0x2000) /* RESERVED */
7517 //#define RESERVED (0x4000) /* RESERVED */
7518 //#define RESERVED (0x8000) /* RESERVED */
7519 
7520 /* UCSCTL7 Control Bits */
7521 #define DCOFFG_L (0x0001) /* DCO Fault Flag */
7522 #define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
7523 #define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
7524 #define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */
7525 //#define RESERVED (0x0010) /* RESERVED */
7526 //#define RESERVED (0x0020) /* RESERVED */
7527 //#define RESERVED (0x0040) /* RESERVED */
7528 //#define RESERVED (0x0080) /* RESERVED */
7529 //#define RESERVED (0x0100) /* RESERVED */
7530 //#define RESERVED (0x0200) /* RESERVED */
7531 //#define RESERVED (0x0400) /* RESERVED */
7532 //#define RESERVED (0x0800) /* RESERVED */
7533 //#define RESERVED (0x1000) /* RESERVED */
7534 //#define RESERVED (0x2000) /* RESERVED */
7535 //#define RESERVED (0x4000) /* RESERVED */
7536 //#define RESERVED (0x8000) /* RESERVED */
7537 
7538 /* UCSCTL8 Control Bits */
7539 #define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
7540 #define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
7541 #define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
7542 #define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */
7543 //#define RESERVED (0x0010) /* RESERVED */
7544 //#define RESERVED (0x0020) /* RESERVED */
7545 //#define RESERVED (0x0040) /* RESERVED */
7546 //#define RESERVED (0x0080) /* RESERVED */
7547 //#define RESERVED (0x0100) /* RESERVED */
7548 //#define RESERVED (0x0200) /* RESERVED */
7549 //#define RESERVED (0x0400) /* RESERVED */
7550 //#define RESERVED (0x0800) /* RESERVED */
7551 //#define RESERVED (0x1000) /* RESERVED */
7552 //#define RESERVED (0x2000) /* RESERVED */
7553 //#define RESERVED (0x4000) /* RESERVED */
7554 //#define RESERVED (0x8000) /* RESERVED */
7555 
7556 /* UCSCTL8 Control Bits */
7557 #define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
7558 #define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
7559 #define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
7560 #define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */
7561 //#define RESERVED (0x0010) /* RESERVED */
7562 //#define RESERVED (0x0020) /* RESERVED */
7563 //#define RESERVED (0x0040) /* RESERVED */
7564 //#define RESERVED (0x0080) /* RESERVED */
7565 //#define RESERVED (0x0100) /* RESERVED */
7566 //#define RESERVED (0x0200) /* RESERVED */
7567 //#define RESERVED (0x0400) /* RESERVED */
7568 //#define RESERVED (0x0800) /* RESERVED */
7569 //#define RESERVED (0x1000) /* RESERVED */
7570 //#define RESERVED (0x2000) /* RESERVED */
7571 //#define RESERVED (0x4000) /* RESERVED */
7572 //#define RESERVED (0x8000) /* RESERVED */
7573 
7574 #endif
7575 /************************************************************
7576 * USB
7577 ************************************************************/
7578 #ifdef __MSP430_HAS_USB__ /* Definition to show that Module is available */
7579 
7580 /* ========================================================================= */
7581 /* USB Configuration Registers */
7582 /* ========================================================================= */
7583 #define OFS_USBKEYID (0x0000) /* USB Controller key register */
7584 #define OFS_USBKEYID_L OFS_USBKEYID
7585 #define OFS_USBKEYID_H OFS_USBKEYID+1
7586 #define OFS_USBCNF (0x0002) /* USB Module configuration register */
7587 #define OFS_USBCNF_L OFS_USBCNF
7588 #define OFS_USBCNF_H OFS_USBCNF+1
7589 #define OFS_USBPHYCTL (0x0004) /* USB PHY control register */
7590 #define OFS_USBPHYCTL_L OFS_USBPHYCTL
7591 #define OFS_USBPHYCTL_H OFS_USBPHYCTL+1
7592 #define OFS_USBPWRCTL (0x0008) /* USB Power control register */
7593 #define OFS_USBPWRCTL_L OFS_USBPWRCTL
7594 #define OFS_USBPWRCTL_H OFS_USBPWRCTL+1
7595 #define OFS_USBPLLCTL (0x0010) /* USB PLL control register */
7596 #define OFS_USBPLLCTL_L OFS_USBPLLCTL
7597 #define OFS_USBPLLCTL_H OFS_USBPLLCTL+1
7598 #define OFS_USBPLLDIVB (0x0012) /* USB PLL Clock Divider Buffer control register */
7599 #define OFS_USBPLLDIVB_L OFS_USBPLLDIVB
7600 #define OFS_USBPLLDIVB_H OFS_USBPLLDIVB+1
7601 #define OFS_USBPLLIR (0x0014) /* USB PLL Interrupt control register */
7602 #define OFS_USBPLLIR_L OFS_USBPLLIR
7603 #define OFS_USBPLLIR_H OFS_USBPLLIR+1
7604 
7605 #define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */
7606 #define USBKEY (0x9628) /* USB Control Register key */
7607 
7608 /* USBCNF Control Bits */
7609 #define USB_EN (0x0001) /* USB - Module enable */
7610 #define PUR_EN (0x0002) /* USB - PUR pin enable */
7611 #define PUR_IN (0x0004) /* USB - PUR pin input value */
7612 #define BLKRDY (0x0008) /* USB - Block ready signal for DMA */
7613 #define FNTEN (0x0010) /* USB - Frame Number receive Trigger enable for DMA */
7614 //#define RESERVED (0x0020) /* USB - */
7615 //#define RESERVED (0x0040) /* USB - */
7616 //#define RESERVED (0x0080) /* USB - */
7617 //#define RESERVED (0x0100) /* USB - */
7618 //#define RESERVED (0x0200) /* USB - */
7619 //#define RESERVED (0x0400) /* USB - */
7620 //#define RESERVED (0x0800) /* USB - */
7621 //#define RESERVED (0x1000) /* USB - */
7622 //#define RESERVED (0x2000) /* USB - */
7623 //#define RESERVED (0x4000) /* USB - */
7624 //#define RESERVED (0x8000) /* USB - */
7625 
7626 /* USBCNF Control Bits */
7627 #define USB_EN_L (0x0001) /* USB - Module enable */
7628 #define PUR_EN_L (0x0002) /* USB - PUR pin enable */
7629 #define PUR_IN_L (0x0004) /* USB - PUR pin input value */
7630 #define BLKRDY_L (0x0008) /* USB - Block ready signal for DMA */
7631 #define FNTEN_L (0x0010) /* USB - Frame Number receive Trigger enable for DMA */
7632 //#define RESERVED (0x0020) /* USB - */
7633 //#define RESERVED (0x0040) /* USB - */
7634 //#define RESERVED (0x0080) /* USB - */
7635 //#define RESERVED (0x0100) /* USB - */
7636 //#define RESERVED (0x0200) /* USB - */
7637 //#define RESERVED (0x0400) /* USB - */
7638 //#define RESERVED (0x0800) /* USB - */
7639 //#define RESERVED (0x1000) /* USB - */
7640 //#define RESERVED (0x2000) /* USB - */
7641 //#define RESERVED (0x4000) /* USB - */
7642 //#define RESERVED (0x8000) /* USB - */
7643 
7644 /* USBPHYCTL Control Bits */
7645 #define PUOUT0 (0x0001) /* USB - USB Port Output Signal Bit 0 */
7646 #define PUOUT1 (0x0002) /* USB - USB Port Output Signal Bit 1 */
7647 #define PUIN0 (0x0004) /* USB - PU0/DP Input Data */
7648 #define PUIN1 (0x0008) /* USB - PU1/DM Input Data */
7649 //#define RESERVED (0x0010) /* USB - */
7650 #define PUOPE (0x0020) /* USB - USB Port Output Enable */
7651 //#define RESERVED (0x0040) /* USB - */
7652 #define PUSEL (0x0080) /* USB - USB Port Function Select */
7653 #define PUIPE (0x0100) /* USB - PHY Single Ended Input enable */
7654 //#define RESERVED (0x0200) /* USB - */
7655 //#define RESERVED (0x0100) /* USB - */
7656 //#define RESERVED (0x0200) /* USB - */
7657 //#define RESERVED (0x0400) /* USB - */
7658 //#define RESERVED (0x0800) /* USB - */
7659 //#define RESERVED (0x1000) /* USB - */
7660 //#define RESERVED (0x2000) /* USB - */
7661 //#define RESERVED (0x4000) /* USB - */
7662 //#define RESERVED (0x8000) /* USB - */
7663 
7664 /* USBPHYCTL Control Bits */
7665 #define PUOUT0_L (0x0001) /* USB - USB Port Output Signal Bit 0 */
7666 #define PUOUT1_L (0x0002) /* USB - USB Port Output Signal Bit 1 */
7667 #define PUIN0_L (0x0004) /* USB - PU0/DP Input Data */
7668 #define PUIN1_L (0x0008) /* USB - PU1/DM Input Data */
7669 //#define RESERVED (0x0010) /* USB - */
7670 #define PUOPE_L (0x0020) /* USB - USB Port Output Enable */
7671 //#define RESERVED (0x0040) /* USB - */
7672 #define PUSEL_L (0x0080) /* USB - USB Port Function Select */
7673 //#define RESERVED (0x0200) /* USB - */
7674 //#define RESERVED (0x0100) /* USB - */
7675 //#define RESERVED (0x0200) /* USB - */
7676 //#define RESERVED (0x0400) /* USB - */
7677 //#define RESERVED (0x0800) /* USB - */
7678 //#define RESERVED (0x1000) /* USB - */
7679 //#define RESERVED (0x2000) /* USB - */
7680 //#define RESERVED (0x4000) /* USB - */
7681 //#define RESERVED (0x8000) /* USB - */
7682 
7683 /* USBPHYCTL Control Bits */
7684 //#define RESERVED (0x0010) /* USB - */
7685 //#define RESERVED (0x0040) /* USB - */
7686 #define PUIPE_H (0x0001) /* USB - PHY Single Ended Input enable */
7687 //#define RESERVED (0x0200) /* USB - */
7688 //#define RESERVED (0x0100) /* USB - */
7689 //#define RESERVED (0x0200) /* USB - */
7690 //#define RESERVED (0x0400) /* USB - */
7691 //#define RESERVED (0x0800) /* USB - */
7692 //#define RESERVED (0x1000) /* USB - */
7693 //#define RESERVED (0x2000) /* USB - */
7694 //#define RESERVED (0x4000) /* USB - */
7695 //#define RESERVED (0x8000) /* USB - */
7696 
7697 #define PUDIR (0x0020) /* USB - Legacy Definition: USB Port Output Enable */
7698 #define PSEIEN (0x0100) /* USB - Legacy Definition: PHY Single Ended Input enable */
7699 
7700 /* USBPWRCTL Control Bits */
7701 #define VUOVLIFG (0x0001) /* USB - VUSB Overload Interrupt Flag */
7702 #define VBONIFG (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */
7703 #define VBOFFIFG (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */
7704 #define USBBGVBV (0x0008) /* USB - USB Bandgap and VBUS valid */
7705 #define USBDETEN (0x0010) /* USB - VBUS on/off events enable */
7706 #define OVLAOFF (0x0020) /* USB - LDO overload auto off enable */
7707 #define SLDOAON (0x0040) /* USB - Secondary LDO auto on enable */
7708 //#define RESERVED (0x0080) /* USB - */
7709 #define VUOVLIE (0x0100) /* USB - Overload indication Interrupt Enable */
7710 #define VBONIE (0x0200) /* USB - VBUS "Coming ON" Interrupt Enable */
7711 #define VBOFFIE (0x0400) /* USB - VBUS "Going OFF" Interrupt Enable */
7712 #define VUSBEN (0x0800) /* USB - LDO Enable (3.3V) */
7713 #define SLDOEN (0x1000) /* USB - Secondary LDO Enable (1.8V) */
7714 //#define RESERVED (0x2000) /* USB - */
7715 //#define RESERVED (0x4000) /* USB - */
7716 //#define RESERVED (0x8000) /* USB - */
7717 
7718 /* USBPWRCTL Control Bits */
7719 #define VUOVLIFG_L (0x0001) /* USB - VUSB Overload Interrupt Flag */
7720 #define VBONIFG_L (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */
7721 #define VBOFFIFG_L (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */
7722 #define USBBGVBV_L (0x0008) /* USB - USB Bandgap and VBUS valid */
7723 #define USBDETEN_L (0x0010) /* USB - VBUS on/off events enable */
7724 #define OVLAOFF_L (0x0020) /* USB - LDO overload auto off enable */
7725 #define SLDOAON_L (0x0040) /* USB - Secondary LDO auto on enable */
7726 //#define RESERVED (0x0080) /* USB - */
7727 //#define RESERVED (0x2000) /* USB - */
7728 //#define RESERVED (0x4000) /* USB - */
7729 //#define RESERVED (0x8000) /* USB - */
7730 
7731 /* USBPWRCTL Control Bits */
7732 //#define RESERVED (0x0080) /* USB - */
7733 #define VUOVLIE_H (0x0001) /* USB - Overload indication Interrupt Enable */
7734 #define VBONIE_H (0x0002) /* USB - VBUS "Coming ON" Interrupt Enable */
7735 #define VBOFFIE_H (0x0004) /* USB - VBUS "Going OFF" Interrupt Enable */
7736 #define VUSBEN_H (0x0008) /* USB - LDO Enable (3.3V) */
7737 #define SLDOEN_H (0x0010) /* USB - Secondary LDO Enable (1.8V) */
7738 //#define RESERVED (0x2000) /* USB - */
7739 //#define RESERVED (0x4000) /* USB - */
7740 //#define RESERVED (0x8000) /* USB - */
7741 
7742 /* USBPLLCTL Control Bits */
7743 //#define RESERVED (0x0001) /* USB - */
7744 //#define RESERVED (0x0002) /* USB - */
7745 //#define RESERVED (0x0004) /* USB - */
7746 //#define RESERVED (0x0008) /* USB - */
7747 //#define RESERVED (0x0010) /* USB - */
7748 //#define RESERVED (0x0020) /* USB - */
7749 #define UCLKSEL0 (0x0040) /* USB - Module Clock Select Bit 0 */
7750 #define UCLKSEL1 (0x0080) /* USB - Module Clock Select Bit 1 */
7751 #define UPLLEN (0x0100) /* USB - PLL enable */
7752 #define UPFDEN (0x0200) /* USB - Phase Freq. Discriminator enable */
7753 //#define RESERVED (0x0400) /* USB - */
7754 //#define RESERVED (0x0800) /* USB - */
7755 //#define RESERVED (0x1000) /* USB - */
7756 //#define RESERVED (0x2000) /* USB - */
7757 //#define RESERVED (0x4000) /* USB - */
7758 //#define RESERVED (0x8000) /* USB - */
7759 
7760 /* USBPLLCTL Control Bits */
7761 //#define RESERVED (0x0001) /* USB - */
7762 //#define RESERVED (0x0002) /* USB - */
7763 //#define RESERVED (0x0004) /* USB - */
7764 //#define RESERVED (0x0008) /* USB - */
7765 //#define RESERVED (0x0010) /* USB - */
7766 //#define RESERVED (0x0020) /* USB - */
7767 #define UCLKSEL0_L (0x0040) /* USB - Module Clock Select Bit 0 */
7768 #define UCLKSEL1_L (0x0080) /* USB - Module Clock Select Bit 1 */
7769 //#define RESERVED (0x0400) /* USB - */
7770 //#define RESERVED (0x0800) /* USB - */
7771 //#define RESERVED (0x1000) /* USB - */
7772 //#define RESERVED (0x2000) /* USB - */
7773 //#define RESERVED (0x4000) /* USB - */
7774 //#define RESERVED (0x8000) /* USB - */
7775 
7776 /* USBPLLCTL Control Bits */
7777 //#define RESERVED (0x0001) /* USB - */
7778 //#define RESERVED (0x0002) /* USB - */
7779 //#define RESERVED (0x0004) /* USB - */
7780 //#define RESERVED (0x0008) /* USB - */
7781 //#define RESERVED (0x0010) /* USB - */
7782 //#define RESERVED (0x0020) /* USB - */
7783 #define UPLLEN_H (0x0001) /* USB - PLL enable */
7784 #define UPFDEN_H (0x0002) /* USB - Phase Freq. Discriminator enable */
7785 //#define RESERVED (0x0400) /* USB - */
7786 //#define RESERVED (0x0800) /* USB - */
7787 //#define RESERVED (0x1000) /* USB - */
7788 //#define RESERVED (0x2000) /* USB - */
7789 //#define RESERVED (0x4000) /* USB - */
7790 //#define RESERVED (0x8000) /* USB - */
7791 
7792 #define UCLKSEL_0 (0x0000) /* USB - Module Clock Select: 0 */
7793 #define UCLKSEL_1 (0x0040) /* USB - Module Clock Select: 1 */
7794 #define UCLKSEL_2 (0x0080) /* USB - Module Clock Select: 2 */
7795 #define UCLKSEL_3 (0x00C0) /* USB - Module Clock Select: 3 (Reserved) */
7796 
7797 #define UCLKSEL__PLLCLK (0x0000) /* USB - Module Clock Select: PLLCLK */
7798 #define UCLKSEL__XT1CLK (0x0040) /* USB - Module Clock Select: XT1CLK */
7799 #define UCLKSEL__XT2CLK (0x0080) /* USB - Module Clock Select: XT2CLK */
7800 
7801 /* USBPLLDIVB Control Bits */
7802 #define UPMB0 (0x0001) /* USB - PLL feedback divider buffer Bit 0 */
7803 #define UPMB1 (0x0002) /* USB - PLL feedback divider buffer Bit 1 */
7804 #define UPMB2 (0x0004) /* USB - PLL feedback divider buffer Bit 2 */
7805 #define UPMB3 (0x0008) /* USB - PLL feedback divider buffer Bit 3 */
7806 #define UPMB4 (0x0010) /* USB - PLL feedback divider buffer Bit 4 */
7807 #define UPMB5 (0x0020) /* USB - PLL feedback divider buffer Bit 5 */
7808 //#define RESERVED (0x0040) /* USB - */
7809 //#define RESERVED (0x0080) /* USB - */
7810 #define UPQB0 (0x0100) /* USB - PLL prescale divider buffer Bit 0 */
7811 #define UPQB1 (0x0200) /* USB - PLL prescale divider buffer Bit 1 */
7812 #define UPQB2 (0x0400) /* USB - PLL prescale divider buffer Bit 2 */
7813 //#define RESERVED (0x0800) /* USB - */
7814 //#define RESERVED (0x1000) /* USB - */
7815 //#define RESERVED (0x2000) /* USB - */
7816 //#define RESERVED (0x4000) /* USB - */
7817 //#define RESERVED (0x8000) /* USB - */
7818 
7819 /* USBPLLDIVB Control Bits */
7820 #define UPMB0_L (0x0001) /* USB - PLL feedback divider buffer Bit 0 */
7821 #define UPMB1_L (0x0002) /* USB - PLL feedback divider buffer Bit 1 */
7822 #define UPMB2_L (0x0004) /* USB - PLL feedback divider buffer Bit 2 */
7823 #define UPMB3_L (0x0008) /* USB - PLL feedback divider buffer Bit 3 */
7824 #define UPMB4_L (0x0010) /* USB - PLL feedback divider buffer Bit 4 */
7825 #define UPMB5_L (0x0020) /* USB - PLL feedback divider buffer Bit 5 */
7826 //#define RESERVED (0x0040) /* USB - */
7827 //#define RESERVED (0x0080) /* USB - */
7828 //#define RESERVED (0x0800) /* USB - */
7829 //#define RESERVED (0x1000) /* USB - */
7830 //#define RESERVED (0x2000) /* USB - */
7831 //#define RESERVED (0x4000) /* USB - */
7832 //#define RESERVED (0x8000) /* USB - */
7833 
7834 /* USBPLLDIVB Control Bits */
7835 //#define RESERVED (0x0040) /* USB - */
7836 //#define RESERVED (0x0080) /* USB - */
7837 #define UPQB0_H (0x0001) /* USB - PLL prescale divider buffer Bit 0 */
7838 #define UPQB1_H (0x0002) /* USB - PLL prescale divider buffer Bit 1 */
7839 #define UPQB2_H (0x0004) /* USB - PLL prescale divider buffer Bit 2 */
7840 //#define RESERVED (0x0800) /* USB - */
7841 //#define RESERVED (0x1000) /* USB - */
7842 //#define RESERVED (0x2000) /* USB - */
7843 //#define RESERVED (0x4000) /* USB - */
7844 //#define RESERVED (0x8000) /* USB - */
7845 
7846 #define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */
7847 #define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */
7848 #define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */
7849 #define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */
7850 #define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */
7851 #define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */
7852 #define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */
7853 #define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */
7854 #define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */
7855 #define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */
7856 #define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */
7857 #define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */
7858 #define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */
7859 #define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */
7860 #define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */
7861 #define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */
7862 #define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */
7863 #define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */
7864 #define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */
7865 #define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */
7866 #define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */
7867 #define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */
7868 #define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */
7869 #define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */
7870 #define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */
7871 #define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */
7872 #define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */
7873 #define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */
7874 #define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */
7875 #define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */
7876 #define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */
7877 #define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */
7878 #define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */
7879 #define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */
7880 #define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */
7881 #define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */
7882 #define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */
7883 #define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */
7884 #define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */
7885 #define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */
7886 #define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */
7887 #define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */
7888 #define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */
7889 
7890 /* USBPLLIR Control Bits */
7891 #define USBOOLIFG (0x0001) /* USB - PLL out of lock Interrupt Flag */
7892 #define USBLOSIFG (0x0002) /* USB - PLL loss of signal Interrupt Flag */
7893 #define USBOORIFG (0x0004) /* USB - PLL out of range Interrupt Flag */
7894 //#define RESERVED (0x0008) /* USB - */
7895 //#define RESERVED (0x0010) /* USB - */
7896 //#define RESERVED (0x0020) /* USB - */
7897 //#define RESERVED (0x0040) /* USB - */
7898 //#define RESERVED (0x0080) /* USB - */
7899 #define USBOOLIE (0x0100) /* USB - PLL out of lock Interrupt enable */
7900 #define USBLOSIE (0x0200) /* USB - PLL loss of signal Interrupt enable */
7901 #define USBOORIE (0x0400) /* USB - PLL out of range Interrupt enable */
7902 //#define RESERVED (0x0800) /* USB - */
7903 //#define RESERVED (0x1000) /* USB - */
7904 //#define RESERVED (0x2000) /* USB - */
7905 //#define RESERVED (0x4000) /* USB - */
7906 //#define RESERVED (0x8000) /* USB - */
7907 
7908 /* USBPLLIR Control Bits */
7909 #define USBOOLIFG_L (0x0001) /* USB - PLL out of lock Interrupt Flag */
7910 #define USBLOSIFG_L (0x0002) /* USB - PLL loss of signal Interrupt Flag */
7911 #define USBOORIFG_L (0x0004) /* USB - PLL out of range Interrupt Flag */
7912 //#define RESERVED (0x0008) /* USB - */
7913 //#define RESERVED (0x0010) /* USB - */
7914 //#define RESERVED (0x0020) /* USB - */
7915 //#define RESERVED (0x0040) /* USB - */
7916 //#define RESERVED (0x0080) /* USB - */
7917 //#define RESERVED (0x0800) /* USB - */
7918 //#define RESERVED (0x1000) /* USB - */
7919 //#define RESERVED (0x2000) /* USB - */
7920 //#define RESERVED (0x4000) /* USB - */
7921 //#define RESERVED (0x8000) /* USB - */
7922 
7923 /* USBPLLIR Control Bits */
7924 //#define RESERVED (0x0008) /* USB - */
7925 //#define RESERVED (0x0010) /* USB - */
7926 //#define RESERVED (0x0020) /* USB - */
7927 //#define RESERVED (0x0040) /* USB - */
7928 //#define RESERVED (0x0080) /* USB - */
7929 #define USBOOLIE_H (0x0001) /* USB - PLL out of lock Interrupt enable */
7930 #define USBLOSIE_H (0x0002) /* USB - PLL loss of signal Interrupt enable */
7931 #define USBOORIE_H (0x0004) /* USB - PLL out of range Interrupt enable */
7932 //#define RESERVED (0x0800) /* USB - */
7933 //#define RESERVED (0x1000) /* USB - */
7934 //#define RESERVED (0x2000) /* USB - */
7935 //#define RESERVED (0x4000) /* USB - */
7936 //#define RESERVED (0x8000) /* USB - */
7937 
7938 /* ========================================================================= */
7939 /* USB Control Registers */
7940 /* ========================================================================= */
7941 #define OFS_USBIEPCNF_0 (0x0020) /* USB Input endpoint_0: Configuration */
7942 #define OFS_USBIEPCNT_0 (0x0021) /* USB Input endpoint_0: Byte Count */
7943 #define OFS_USBOEPCNF_0 (0x0022) /* USB Output endpoint_0: Configuration */
7944 #define OFS_USBOEPCNT_0 (0x0023) /* USB Output endpoint_0: byte count */
7945 #define OFS_USBIEPIE (0x002E) /* USB Input endpoint interrupt enable flags */
7946 #define OFS_USBOEPIE (0x002F) /* USB Output endpoint interrupt enable flags */
7947 #define OFS_USBIEPIFG (0x0030) /* USB Input endpoint interrupt flags */
7948 #define OFS_USBOEPIFG (0x0031) /* USB Output endpoint interrupt flags */
7949 #define OFS_USBVECINT (0x0032) /* USB Vector interrupt register */
7950 #define OFS_USBVECINT_L OFS_USBVECINT
7951 #define OFS_USBVECINT_H OFS_USBVECINT+1
7952 #define OFS_USBMAINT (0x0036) /* USB maintenance register */
7953 #define OFS_USBMAINT_L OFS_USBMAINT
7954 #define OFS_USBMAINT_H OFS_USBMAINT+1
7955 #define OFS_USBTSREG (0x0038) /* USB Time Stamp register */
7956 #define OFS_USBTSREG_L OFS_USBTSREG
7957 #define OFS_USBTSREG_H OFS_USBTSREG+1
7958 #define OFS_USBFN (0x003A) /* USB Frame number */
7959 #define OFS_USBFN_L OFS_USBFN
7960 #define OFS_USBFN_H OFS_USBFN+1
7961 #define OFS_USBCTL (0x003C) /* USB control register */
7962 #define OFS_USBIE (0x003D) /* USB interrupt enable register */
7963 #define OFS_USBIFG (0x003E) /* USB interrupt flag register */
7964 #define OFS_USBFUNADR (0x003F) /* USB Function address register */
7965 
7966 #define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */
7967 
7968 /* USBIEPCNF_0 Control Bits */
7969 /* USBOEPCNF_0 Control Bits */
7970 //#define RESERVED (0x0001) /* USB - */
7971 //#define RESERVED (0x0001) /* USB - */
7972 #define USBIIE (0x0004) /* USB - Transaction Interrupt indication enable */
7973 #define STALL (0x0008) /* USB - Stall Condition */
7974 //#define RESERVED (0x0010) /* USB - */
7975 #define TOGGLE (0x0020) /* USB - Toggle Bit */
7976 //#define RESERVED (0x0040) /* USB - */
7977 #define UBME (0x0080) /* USB - UBM In-Endpoint Enable */
7978 
7979 /* USBIEPBCNT_0 Control Bits */
7980 /* USBOEPBCNT_0 Control Bits */
7981 #define CNT0 (0x0001) /* USB - Byte Count Bit 0 */
7982 #define CNT1 (0x0001) /* USB - Byte Count Bit 1 */
7983 #define CNT2 (0x0004) /* USB - Byte Count Bit 2 */
7984 #define CNT3 (0x0008) /* USB - Byte Count Bit 3 */
7985 //#define RESERVED (0x0010) /* USB - */
7986 //#define RESERVED (0x0020) /* USB - */
7987 //#define RESERVED (0x0040) /* USB - */
7988 #define NAK (0x0080) /* USB - No Acknowledge Status Bit */
7989 
7990 /* USBMAINT Control Bits */
7991 #define UTIFG (0x0001) /* USB - Timer Interrupt Flag */
7992 #define UTIE (0x0002) /* USB - Timer Interrupt Enable */
7993 //#define RESERVED (0x0004) /* USB - */
7994 //#define RESERVED (0x0008) /* USB - */
7995 //#define RESERVED (0x0010) /* USB - */
7996 //#define RESERVED (0x0020) /* USB - */
7997 //#define RESERVED (0x0040) /* USB - */
7998 //#define RESERVED (0x0080) /* USB - */
7999 #define TSGEN (0x0100) /* USB - Time Stamp Generator Enable */
8000 #define TSESEL0 (0x0200) /* USB - Time Stamp Event Select Bit 0 */
8001 #define TSESEL1 (0x0400) /* USB - Time Stamp Event Select Bit 1 */
8002 #define TSE3 (0x0800) /* USB - Time Stamp Event #3 Bit */
8003 //#define RESERVED (0x1000) /* USB - */
8004 #define UTSEL0 (0x2000) /* USB - Timer Select Bit 0 */
8005 #define UTSEL1 (0x4000) /* USB - Timer Select Bit 1 */
8006 #define UTSEL2 (0x8000) /* USB - Timer Select Bit 2 */
8007 
8008 /* USBMAINT Control Bits */
8009 #define UTIFG_L (0x0001) /* USB - Timer Interrupt Flag */
8010 #define UTIE_L (0x0002) /* USB - Timer Interrupt Enable */
8011 //#define RESERVED (0x0004) /* USB - */
8012 //#define RESERVED (0x0008) /* USB - */
8013 //#define RESERVED (0x0010) /* USB - */
8014 //#define RESERVED (0x0020) /* USB - */
8015 //#define RESERVED (0x0040) /* USB - */
8016 //#define RESERVED (0x0080) /* USB - */
8017 //#define RESERVED (0x1000) /* USB - */
8018 
8019 /* USBMAINT Control Bits */
8020 //#define RESERVED (0x0004) /* USB - */
8021 //#define RESERVED (0x0008) /* USB - */
8022 //#define RESERVED (0x0010) /* USB - */
8023 //#define RESERVED (0x0020) /* USB - */
8024 //#define RESERVED (0x0040) /* USB - */
8025 //#define RESERVED (0x0080) /* USB - */
8026 #define TSGEN_H (0x0001) /* USB - Time Stamp Generator Enable */
8027 #define TSESEL0_H (0x0002) /* USB - Time Stamp Event Select Bit 0 */
8028 #define TSESEL1_H (0x0004) /* USB - Time Stamp Event Select Bit 1 */
8029 #define TSE3_H (0x0008) /* USB - Time Stamp Event #3 Bit */
8030 //#define RESERVED (0x1000) /* USB - */
8031 #define UTSEL0_H (0x0020) /* USB - Timer Select Bit 0 */
8032 #define UTSEL1_H (0x0040) /* USB - Timer Select Bit 1 */
8033 #define UTSEL2_H (0x0080) /* USB - Timer Select Bit 2 */
8034 
8035 #define TSESEL_0 (0x0000) /* USB - Time Stamp Event Select: 0 */
8036 #define TSESEL_1 (0x0200) /* USB - Time Stamp Event Select: 1 */
8037 #define TSESEL_2 (0x0400) /* USB - Time Stamp Event Select: 2 */
8038 #define TSESEL_3 (0x0600) /* USB - Time Stamp Event Select: 3 */
8039 
8040 #define UTSEL_0 (0x0000) /* USB - Timer Select: 0 */
8041 #define UTSEL_1 (0x2000) /* USB - Timer Select: 1 */
8042 #define UTSEL_2 (0x4000) /* USB - Timer Select: 2 */
8043 #define UTSEL_3 (0x6000) /* USB - Timer Select: 3 */
8044 #define UTSEL_4 (0x8000) /* USB - Timer Select: 4 */
8045 #define UTSEL_5 (0xA000) /* USB - Timer Select: 5 */
8046 #define UTSEL_6 (0xC000) /* USB - Timer Select: 6 */
8047 #define UTSEL_7 (0xE000) /* USB - Timer Select: 7 */
8048 
8049 /* USBCTL Control Bits */
8050 #define DIR (0x0001) /* USB - Data Response Bit */
8051 //#define RESERVED (0x0002) /* USB - */
8052 //#define RESERVED (0x0004) /* USB - */
8053 //#define RESERVED (0x0008) /* USB - */
8054 #define FRSTE (0x0010) /* USB - Function Reset Connection Enable */
8055 #define RWUP (0x0020) /* USB - Device Remote Wakeup Request */
8056 #define FEN (0x0040) /* USB - Function Enable Bit */
8057 //#define RESERVED (0x0080) /* USB - */
8058 
8059 /* USBIE Control Bits */
8060 #define STPOWIE (0x0001) /* USB - Setup Overwrite Interrupt Enable */
8061 //#define RESERVED (0x0002) /* USB - */
8062 #define SETUPIE (0x0004) /* USB - Setup Interrupt Enable */
8063 //#define RESERVED (0x0008) /* USB - */
8064 //#define RESERVED (0x0010) /* USB - */
8065 #define RESRIE (0x0020) /* USB - Function Resume Request Interrupt Enable */
8066 #define SUSRIE (0x0040) /* USB - Function Suspend Request Interrupt Enable */
8067 #define RSTRIE (0x0080) /* USB - Function Reset Request Interrupt Enable */
8068 
8069 /* USBIFG Control Bits */
8070 #define STPOWIFG (0x0001) /* USB - Setup Overwrite Interrupt Flag */
8071 //#define RESERVED (0x0002) /* USB - */
8072 #define SETUPIFG (0x0004) /* USB - Setup Interrupt Flag */
8073 //#define RESERVED (0x0008) /* USB - */
8074 //#define RESERVED (0x0010) /* USB - */
8075 #define RESRIFG (0x0020) /* USB - Function Resume Request Interrupt Flag */
8076 #define SUSRIFG (0x0040) /* USB - Function Suspend Request Interrupt Flag */
8077 #define RSTRIFG (0x0080) /* USB - Function Reset Request Interrupt Flag */
8078 
8079 //values of USBVECINT when USB-interrupt occured
8080 #define USBVECINT_NONE 0x00
8081 #define USBVECINT_PWR_DROP 0x02
8082 #define USBVECINT_PLL_LOCK 0x04
8083 #define USBVECINT_PLL_SIGNAL 0x06
8084 #define USBVECINT_PLL_RANGE 0x08
8085 #define USBVECINT_PWR_VBUSOn 0x0A
8086 #define USBVECINT_PWR_VBUSOff 0x0C
8087 #define USBVECINT_USB_TIMESTAMP 0x10
8088 #define USBVECINT_INPUT_ENDPOINT0 0x12
8089 #define USBVECINT_OUTPUT_ENDPOINT0 0x14
8090 #define USBVECINT_RSTR 0x16
8091 #define USBVECINT_SUSR 0x18
8092 #define USBVECINT_RESR 0x1A
8093 #define USBVECINT_SETUP_PACKET_RECEIVED 0x20
8094 #define USBVECINT_STPOW_PACKET_RECEIVED 0x22
8095 #define USBVECINT_INPUT_ENDPOINT1 0x24
8096 #define USBVECINT_INPUT_ENDPOINT2 0x26
8097 #define USBVECINT_INPUT_ENDPOINT3 0x28
8098 #define USBVECINT_INPUT_ENDPOINT4 0x2A
8099 #define USBVECINT_INPUT_ENDPOINT5 0x2C
8100 #define USBVECINT_INPUT_ENDPOINT6 0x2E
8101 #define USBVECINT_INPUT_ENDPOINT7 0x30
8102 #define USBVECINT_OUTPUT_ENDPOINT1 0x32
8103 #define USBVECINT_OUTPUT_ENDPOINT2 0x34
8104 #define USBVECINT_OUTPUT_ENDPOINT3 0x36
8105 #define USBVECINT_OUTPUT_ENDPOINT4 0x38
8106 #define USBVECINT_OUTPUT_ENDPOINT5 0x3A
8107 #define USBVECINT_OUTPUT_ENDPOINT6 0x3C
8108 #define USBVECINT_OUTPUT_ENDPOINT7 0x3E
8109 
8110 
8111 /* ========================================================================= */
8112 /* USB Operation Registers */
8113 /* ========================================================================= */
8114 
8115 #define OFS_USBIEPSIZXY_7 (0x23FF) /* Input Endpoint_7: X/Y-buffer size */
8116 #define OFS_USBIEPBCTY_7 (0x23FE) /* Input Endpoint_7: Y-byte count */
8117 #define OFS_USBIEPBBAY_7 (0x23FD) /* Input Endpoint_7: Y-buffer base addr. */
8118 //#define Spare_O (0x23FC) /* Not used */
8119 //#define Spare_O (0x23FB) /* Not used */
8120 #define OFS_USBIEPBCTX_7 (0x23FA) /* Input Endpoint_7: X-byte count */
8121 #define OFS_USBIEPBBAX_7 (0x23F9) /* Input Endpoint_7: X-buffer base addr. */
8122 #define OFS_USBIEPCNF_7 (0x23F8) /* Input Endpoint_7: Configuration */
8123 #define OFS_USBIEPSIZXY_6 (0x23F7) /* Input Endpoint_6: X/Y-buffer size */
8124 #define OFS_USBIEPBCTY_6 (0x23F6) /* Input Endpoint_6: Y-byte count */
8125 #define OFS_USBIEPBBAY_6 (0x23F5) /* Input Endpoint_6: Y-buffer base addr. */
8126 //#define Spare_O (0x23F4) /* Not used */
8127 //#define Spare_O (0x23F3) /* Not used */
8128 #define OFS_USBIEPBCTX_6 (0x23F2) /* Input Endpoint_6: X-byte count */
8129 #define OFS_USBIEPBBAX_6 (0x23F1) /* Input Endpoint_6: X-buffer base addr. */
8130 #define OFS_USBIEPCNF_6 (0x23F0) /* Input Endpoint_6: Configuration */
8131 #define OFS_USBIEPSIZXY_5 (0x23EF) /* Input Endpoint_5: X/Y-buffer size */
8132 #define OFS_USBIEPBCTY_5 (0x23EE) /* Input Endpoint_5: Y-byte count */
8133 #define OFS_USBIEPBBAY_5 (0x23ED) /* Input Endpoint_5: Y-buffer base addr. */
8134 //#define Spare_O (0x23EC) /* Not used */
8135 //#define Spare_O (0x23EB) /* Not used */
8136 #define OFS_USBIEPBCTX_5 (0x23EA) /* Input Endpoint_5: X-byte count */
8137 #define OFS_USBIEPBBAX_5 (0x23E9) /* Input Endpoint_5: X-buffer base addr. */
8138 #define OFS_USBIEPCNF_5 (0x23E8) /* Input Endpoint_5: Configuration */
8139 #define OFS_USBIEPSIZXY_4 (0x23E7) /* Input Endpoint_4: X/Y-buffer size */
8140 #define OFS_USBIEPBCTY_4 (0x23E6) /* Input Endpoint_4: Y-byte count */
8141 #define OFS_USBIEPBBAY_4 (0x23E5) /* Input Endpoint_4: Y-buffer base addr. */
8142 //#define Spare_O (0x23E4) /* Not used */
8143 //#define Spare_O (0x23E3) /* Not used */
8144 #define OFS_USBIEPBCTX_4 (0x23E2) /* Input Endpoint_4: X-byte count */
8145 #define OFS_USBIEPBBAX_4 (0x23E1) /* Input Endpoint_4: X-buffer base addr. */
8146 #define OFS_USBIEPCNF_4 (0x23E0) /* Input Endpoint_4: Configuration */
8147 #define OFS_USBIEPSIZXY_3 (0x23DF) /* Input Endpoint_3: X/Y-buffer size */
8148 #define OFS_USBIEPBCTY_3 (0x23DE) /* Input Endpoint_3: Y-byte count */
8149 #define OFS_USBIEPBBAY_3 (0x23DD) /* Input Endpoint_3: Y-buffer base addr. */
8150 //#define Spare_O (0x23DC) /* Not used */
8151 //#define Spare_O (0x23DB) /* Not used */
8152 #define OFS_USBIEPBCTX_3 (0x23DA) /* Input Endpoint_3: X-byte count */
8153 #define OFS_USBIEPBBAX_3 (0x23D9) /* Input Endpoint_3: X-buffer base addr. */
8154 #define OFS_USBIEPCNF_3 (0x23D8) /* Input Endpoint_3: Configuration */
8155 #define OFS_USBIEPSIZXY_2 (0x23D7) /* Input Endpoint_2: X/Y-buffer size */
8156 #define OFS_USBIEPBCTY_2 (0x23D6) /* Input Endpoint_2: Y-byte count */
8157 #define OFS_USBIEPBBAY_2 (0x23D5) /* Input Endpoint_2: Y-buffer base addr. */
8158 //#define Spare_O (0x23D4) /* Not used */
8159 //#define Spare_O (0x23D3) /* Not used */
8160 #define OFS_USBIEPBCTX_2 (0x23D2) /* Input Endpoint_2: X-byte count */
8161 #define OFS_USBIEPBBAX_2 (0x23D1) /* Input Endpoint_2: X-buffer base addr. */
8162 #define OFS_USBIEPCNF_2 (0x23D0) /* Input Endpoint_2: Configuration */
8163 #define OFS_USBIEPSIZXY_1 (0x23CF) /* Input Endpoint_1: X/Y-buffer size */
8164 #define OFS_USBIEPBCTY_1 (0x23CE) /* Input Endpoint_1: Y-byte count */
8165 #define OFS_USBIEPBBAY_1 (0x23CD) /* Input Endpoint_1: Y-buffer base addr. */
8166 //#define Spare_O (0x23CC) /* Not used */
8167 //#define Spare_O (0x23CB) /* Not used */
8168 #define OFS_USBIEPBCTX_1 (0x23CA) /* Input Endpoint_1: X-byte count */
8169 #define OFS_USBIEPBBAX_1 (0x23C9) /* Input Endpoint_1: X-buffer base addr. */
8170 #define OFS_USBIEPCNF_1 (0x23C8) /* Input Endpoint_1: Configuration */
8171 //#define (0x23C7)_O /* */
8172 //#define RESERVED_O (0x1C00) /* */
8173 //#define (0x23C0)_O /* */
8174 #define OFS_USBOEPSIZXY_7 (0x23BF) /* Output Endpoint_7: X/Y-buffer size */
8175 #define OFS_USBOEPBCTY_7 (0x23BE) /* Output Endpoint_7: Y-byte count */
8176 #define OFS_USBOEPBBAY_7 (0x23BD) /* Output Endpoint_7: Y-buffer base addr. */
8177 //#define Spare_O (0x23BC) /* Not used */
8178 //#define Spare_O (0x23BB) /* Not used */
8179 #define OFS_USBOEPBCTX_7 (0x23BA) /* Output Endpoint_7: X-byte count */
8180 #define OFS_USBOEPBBAX_7 (0x23B9) /* Output Endpoint_7: X-buffer base addr. */
8181 #define OFS_USBOEPCNF_7 (0x23B8) /* Output Endpoint_7: Configuration */
8182 #define OFS_USBOEPSIZXY_6 (0x23B7) /* Output Endpoint_6: X/Y-buffer size */
8183 #define OFS_USBOEPBCTY_6 (0x23B6) /* Output Endpoint_6: Y-byte count */
8184 #define OFS_USBOEPBBAY_6 (0x23B5) /* Output Endpoint_6: Y-buffer base addr. */
8185 //#define Spare_O (0x23B4) /* Not used */
8186 //#define Spare_O (0x23B3) /* Not used */
8187 #define OFS_USBOEPBCTX_6 (0x23B2) /* Output Endpoint_6: X-byte count */
8188 #define OFS_USBOEPBBAX_6 (0x23B1) /* Output Endpoint_6: X-buffer base addr. */
8189 #define OFS_USBOEPCNF_6 (0x23B0) /* Output Endpoint_6: Configuration */
8190 #define OFS_USBOEPSIZXY_5 (0x23AF) /* Output Endpoint_5: X/Y-buffer size */
8191 #define OFS_USBOEPBCTY_5 (0x23AE) /* Output Endpoint_5: Y-byte count */
8192 #define OFS_USBOEPBBAY_5 (0x23AD) /* Output Endpoint_5: Y-buffer base addr. */
8193 //#define Spare_O (0x23AC) /* Not used */
8194 //#define Spare_O (0x23AB) /* Not used */
8195 #define OFS_USBOEPBCTX_5 (0x23AA) /* Output Endpoint_5: X-byte count */
8196 #define OFS_USBOEPBBAX_5 (0x23A9) /* Output Endpoint_5: X-buffer base addr. */
8197 #define OFS_USBOEPCNF_5 (0x23A8) /* Output Endpoint_5: Configuration */
8198 #define OFS_USBOEPSIZXY_4 (0x23A7) /* Output Endpoint_4: X/Y-buffer size */
8199 #define OFS_USBOEPBCTY_4 (0x23A6) /* Output Endpoint_4: Y-byte count */
8200 #define OFS_USBOEPBBAY_4 (0x23A5) /* Output Endpoint_4: Y-buffer base addr. */
8201 //#define Spare_O (0x23A4) /* Not used */
8202 //#define Spare_O (0x23A3) /* Not used */
8203 #define OFS_USBOEPBCTX_4 (0x23A2) /* Output Endpoint_4: X-byte count */
8204 #define OFS_USBOEPBBAX_4 (0x23A1) /* Output Endpoint_4: X-buffer base addr. */
8205 #define OFS_USBOEPCNF_4 (0x23A0) /* Output Endpoint_4: Configuration */
8206 #define OFS_USBOEPSIZXY_3 (0x239F) /* Output Endpoint_3: X/Y-buffer size */
8207 #define OFS_USBOEPBCTY_3 (0x239E) /* Output Endpoint_3: Y-byte count */
8208 #define OFS_USBOEPBBAY_3 (0x239D) /* Output Endpoint_3: Y-buffer base addr. */
8209 //#define Spare_O (0x239C) /* Not used */
8210 //#define Spare_O (0x239B) /* Not used */
8211 #define OFS_USBOEPBCTX_3 (0x239A) /* Output Endpoint_3: X-byte count */
8212 #define OFS_USBOEPBBAX_3 (0x2399) /* Output Endpoint_3: X-buffer base addr. */
8213 #define OFS_USBOEPCNF_3 (0x2398) /* Output Endpoint_3: Configuration */
8214 #define OFS_USBOEPSIZXY_2 (0x2397) /* Output Endpoint_2: X/Y-buffer size */
8215 #define OFS_USBOEPBCTY_2 (0x2396) /* Output Endpoint_2: Y-byte count */
8216 #define OFS_USBOEPBBAY_2 (0x2395) /* Output Endpoint_2: Y-buffer base addr. */
8217 //#define Spare_O (0x2394) /* Not used */
8218 //#define Spare_O (0x2393) /* Not used */
8219 #define OFS_USBOEPBCTX_2 (0x2392) /* Output Endpoint_2: X-byte count */
8220 #define OFS_USBOEPBBAX_2 (0x2391) /* Output Endpoint_2: X-buffer base addr. */
8221 #define OFS_USBOEPCNF_2 (0x2390) /* Output Endpoint_2: Configuration */
8222 #define OFS_USBOEPSIZXY_1 (0x238F) /* Output Endpoint_1: X/Y-buffer size */
8223 #define OFS_USBOEPBCTY_1 (0x238E) /* Output Endpoint_1: Y-byte count */
8224 #define OFS_USBOEPBBAY_1 (0x238D) /* Output Endpoint_1: Y-buffer base addr. */
8225 //#define Spare_O (0x238C) /* Not used */
8226 //#define Spare_O (0x238B) /* Not used */
8227 #define OFS_USBOEPBCTX_1 (0x238A) /* Output Endpoint_1: X-byte count */
8228 #define OFS_USBOEPBBAX_1 (0x2389) /* Output Endpoint_1: X-buffer base addr. */
8229 #define OFS_USBOEPCNF_1 (0x2388) /* Output Endpoint_1: Configuration */
8230 #define OFS_USBSUBLK (0x2380) /* Setup Packet Block */
8231 #define OFS_USBIEP0BUF (0x2378) /* Input endpoint_0 buffer */
8232 #define OFS_USBOEP0BUF (0x2370) /* Output endpoint_0 buffer */
8233 #define OFS_USBTOPBUFF (0x236F) /* Top of buffer space */
8234 // (1904 Bytes) /* Buffer space */
8235 #define OFS_USBSTABUFF (0x1C00) /* Start of buffer space */
8236 
8237 /* USBIEPCNF_n Control Bits */
8238 /* USBOEPCNF_n Control Bits */
8239 //#define RESERVED (0x0001) /* USB - */
8240 //#define RESERVED (0x0001) /* USB - */
8241 #define DBUF (0x0010) /* USB - Double Buffer Enable */
8242 //#define RESERVED (0x0040) /* USB - */
8243 
8244 /* USBIEPBCNT_n Control Bits */
8245 /* USBOEPBCNT_n Control Bits */
8246 #define CNT4 (0x0010) /* USB - Byte Count Bit 3 */
8247 #define CNT5 (0x0020) /* USB - Byte Count Bit 3 */
8248 #define CNT6 (0x0040) /* USB - Byte Count Bit 3 */
8249 #endif
8250 /************************************************************
8251 * USCI Ax
8252 ************************************************************/
8253 #ifdef __MSP430_HAS_USCI_Ax__ /* Definition to show that Module is available */
8254 
8255 #define OFS_UCAxCTLW0 (0x0000) /* USCI Ax Control Word Register 0 */
8256 #define OFS_UCAxCTLW0_L OFS_UCAxCTLW0
8257 #define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1
8258 #define OFS_UCAxCTL0 (0x0001)
8259 #define OFS_UCAxCTL1 (0x0000)
8260 #define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */
8261 #define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */
8262 #define OFS_UCAxBRW (0x0006) /* USCI Ax Baud Word Rate 0 */
8263 #define OFS_UCAxBRW_L OFS_UCAxBRW
8264 #define OFS_UCAxBRW_H OFS_UCAxBRW+1
8265 #define OFS_UCAxBR0 (0x0006)
8266 #define OFS_UCAxBR1 (0x0007)
8267 #define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */
8268 #define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */
8269 #define OFS_UCAxMCTL (0x0008) /* USCI Ax Modulation Control */
8270 #define OFS_UCAxSTAT (0x000A) /* USCI Ax Status Register */
8271 #define OFS_UCAxRXBUF (0x000C) /* USCI Ax Receive Buffer */
8272 #define OFS_UCAxTXBUF (0x000E) /* USCI Ax Transmit Buffer */
8273 #define OFS_UCAxABCTL (0x0010) /* USCI Ax LIN Control */
8274 #define OFS_UCAxIRCTL (0x0012) /* USCI Ax IrDA Transmit Control */
8275 #define OFS_UCAxIRCTL_L OFS_UCAxIRCTL
8276 #define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1
8277 #define OFS_UCAxIRTCTL (0x0012)
8278 #define OFS_UCAxIRRCTL (0x0013)
8279 #define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */
8280 #define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */
8281 #define OFS_UCAxICTL (0x001C) /* USCI Ax Interrupt Enable Register */
8282 #define OFS_UCAxICTL_L OFS_UCAxICTL
8283 #define OFS_UCAxICTL_H OFS_UCAxICTL+1
8284 #define OFS_UCAxIE (0x001C)
8285 #define OFS_UCAxIFG (0x001D)
8286 #define UCAxIE UCAxICTL_L /* USCI Ax Interrupt Enable Register */
8287 #define UCAxIFG UCAxICTL_H /* USCI Ax Interrupt Flags Register */
8288 #define OFS_UCAxIV (0x001E) /* USCI Ax Interrupt Vector Register */
8289 
8290 #define OFS_UCAxCTLW0__SPI (0x0000)
8291 #define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI
8292 #define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1
8293 #define OFS_UCAxCTL0__SPI (0x0001)
8294 #define OFS_UCAxCTL1__SPI (0x0000)
8295 #define OFS_UCAxBRW__SPI (0x0006)
8296 #define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI
8297 #define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1
8298 #define OFS_UCAxBR0__SPI (0x0006)
8299 #define OFS_UCAxBR1__SPI (0x0007)
8300 #define OFS_UCAxMCTL__SPI (0x0008)
8301 #define OFS_UCAxSTAT__SPI (0x000A)
8302 #define OFS_UCAxRXBUF__SPI (0x000C)
8303 #define OFS_UCAxTXBUF__SPI (0x000E)
8304 #define OFS_UCAxICTL__SPI (0x001C)
8305 #define OFS_UCAxICTL__SPI_L OFS_UCAxICTL__SPI
8306 #define OFS_UCAxICTL__SPI_H OFS_UCAxICTL__SPI+1
8307 #define OFS_UCAxIE__SPI (0x001C)
8308 #define OFS_UCAxIFG__SPI (0x001D)
8309 #define OFS_UCAxIV__SPI (0x001E)
8310 
8311 #endif
8312 /************************************************************
8313 * USCI Bx
8314 ************************************************************/
8315 #ifdef __MSP430_HAS_USCI_Bx__ /* Definition to show that Module is available */
8316 
8317 #define OFS_UCBxCTLW0__SPI (0x0000)
8318 #define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI
8319 #define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1
8320 #define OFS_UCBxCTL0__SPI (0x0001)
8321 #define OFS_UCBxCTL1__SPI (0x0000)
8322 #define OFS_UCBxBRW__SPI (0x0006)
8323 #define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI
8324 #define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1
8325 #define OFS_UCBxBR0__SPI (0x0006)
8326 #define OFS_UCBxBR1__SPI (0x0007)
8327 #define OFS_UCBxSTAT__SPI (0x000A)
8328 #define OFS_UCBxRXBUF__SPI (0x000C)
8329 #define OFS_UCBxTXBUF__SPI (0x000E)
8330 #define OFS_UCBxICTL__SPI (0x001C)
8331 #define OFS_UCBxICTL__SPI_L OFS_UCBxICTL__SPI
8332 #define OFS_UCBxICTL__SPI_H OFS_UCBxICTL__SPI+1
8333 #define OFS_UCBxIE__SPI (0x001C)
8334 #define OFS_UCBxIFG__SPI (0x001D)
8335 #define OFS_UCBxIV__SPI (0x001E)
8336 
8337 #define OFS_UCBxCTLW0 (0x0000) /* USCI Bx Control Word Register 0 */
8338 #define OFS_UCBxCTLW0_L OFS_UCBxCTLW0
8339 #define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1
8340 #define OFS_UCBxCTL0 (0x0001)
8341 #define OFS_UCBxCTL1 (0x0000)
8342 #define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */
8343 #define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */
8344 #define OFS_UCBxBRW (0x0006) /* USCI Bx Baud Word Rate 0 */
8345 #define OFS_UCBxBRW_L OFS_UCBxBRW
8346 #define OFS_UCBxBRW_H OFS_UCBxBRW+1
8347 #define OFS_UCBxBR0 (0x0006)
8348 #define OFS_UCBxBR1 (0x0007)
8349 #define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */
8350 #define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */
8351 #define OFS_UCBxSTAT (0x000A) /* USCI Bx Status Register */
8352 #define OFS_UCBxRXBUF (0x000C) /* USCI Bx Receive Buffer */
8353 #define OFS_UCBxTXBUF (0x000E) /* USCI Bx Transmit Buffer */
8354 #define OFS_UCBxI2COA (0x0010) /* USCI Bx I2C Own Address */
8355 #define OFS_UCBxI2COA_L OFS_UCBxI2COA
8356 #define OFS_UCBxI2COA_H OFS_UCBxI2COA+1
8357 #define OFS_UCBxI2CSA (0x0012) /* USCI Bx I2C Slave Address */
8358 #define OFS_UCBxI2CSA_L OFS_UCBxI2CSA
8359 #define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1
8360 #define OFS_UCBxICTL (0x001C) /* USCI Bx Interrupt Enable Register */
8361 #define OFS_UCBxICTL_L OFS_UCBxICTL
8362 #define OFS_UCBxICTL_H OFS_UCBxICTL+1
8363 #define OFS_UCBxIE (0x001C)
8364 #define OFS_UCBxIFG (0x001D)
8365 #define UCBxIE UCBxICTL_L /* USCI Bx Interrupt Enable Register */
8366 #define UCBxIFG UCBxICTL_H /* USCI Bx Interrupt Flags Register */
8367 #define OFS_UCBxIV (0x001E) /* USCI Bx Interrupt Vector Register */
8368 
8369 #endif
8370 #if (defined(__MSP430_HAS_USCI_Ax__) || defined(__MSP430_HAS_USCI_Bx__))
8371 
8372 // UCAxCTL0 UART-Mode Control Bits
8373 #define UCPEN (0x80) /* Async. Mode: Parity enable */
8374 #define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
8375 #define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
8376 #define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
8377 #define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
8378 #define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
8379 #define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
8380 #define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
8381 
8382 // UCxxCTL0 SPI-Mode Control Bits
8383 #define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
8384 #define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
8385 #define UCMST (0x08) /* Sync. Mode: Master Select */
8386 
8387 // UCBxCTL0 I2C-Mode Control Bits
8388 #define UCA10 (0x80) /* 10-bit Address Mode */
8389 #define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
8390 #define UCMM (0x20) /* Multi-Master Environment */
8391 //#define res (0x10) /* reserved */
8392 #define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
8393 #define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
8394 #define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
8395 #define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
8396 
8397 // UCAxCTL1 UART-Mode Control Bits
8398 #define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
8399 #define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
8400 #define UCRXEIE (0x20) /* RX Error interrupt enable */
8401 #define UCBRKIE (0x10) /* Break interrupt enable */
8402 #define UCDORM (0x08) /* Dormant (Sleep) Mode */
8403 #define UCTXADDR (0x04) /* Send next Data as Address */
8404 #define UCTXBRK (0x02) /* Send next Data as Break */
8405 #define UCSWRST (0x01) /* USCI Software Reset */
8406 
8407 // UCxxCTL1 SPI-Mode Control Bits
8408 //#define res (0x20) /* reserved */
8409 //#define res (0x10) /* reserved */
8410 //#define res (0x08) /* reserved */
8411 //#define res (0x04) /* reserved */
8412 //#define res (0x02) /* reserved */
8413 
8414 // UCBxCTL1 I2C-Mode Control Bits
8415 //#define res (0x20) /* reserved */
8416 #define UCTR (0x10) /* Transmit/Receive Select/Flag */
8417 #define UCTXNACK (0x08) /* Transmit NACK */
8418 #define UCTXSTP (0x04) /* Transmit STOP */
8419 #define UCTXSTT (0x02) /* Transmit START */
8420 #define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
8421 #define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
8422 #define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
8423 #define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
8424 #define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */
8425 #define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */
8426 #define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */
8427 
8428 /* UCAxMCTL Control Bits */
8429 #define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
8430 #define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
8431 #define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
8432 #define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
8433 #define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
8434 #define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
8435 #define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
8436 #define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
8437 
8438 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
8439 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
8440 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
8441 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
8442 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
8443 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
8444 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
8445 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
8446 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
8447 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
8448 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
8449 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
8450 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
8451 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
8452 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
8453 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
8454 
8455 #define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
8456 #define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
8457 #define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
8458 #define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
8459 #define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
8460 #define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
8461 #define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
8462 #define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
8463 
8464 /* UCAxSTAT Control Bits */
8465 #define UCLISTEN (0x80) /* USCI Listen mode */
8466 #define UCFE (0x40) /* USCI Frame Error Flag */
8467 #define UCOE (0x20) /* USCI Overrun Error Flag */
8468 #define UCPE (0x10) /* USCI Parity Error Flag */
8469 #define UCBRK (0x08) /* USCI Break received */
8470 #define UCRXERR (0x04) /* USCI RX Error Flag */
8471 #define UCADDR (0x02) /* USCI Address received Flag */
8472 #define UCBUSY (0x01) /* USCI Busy Flag */
8473 #define UCIDLE (0x02) /* USCI Idle line detected Flag */
8474 
8475 /* UCBxSTAT Control Bits */
8476 #define UCSCLLOW (0x40) /* SCL low */
8477 #define UCGC (0x20) /* General Call address received Flag */
8478 #define UCBBUSY (0x10) /* Bus Busy Flag */
8479 
8480 /* UCAxIRTCTL Control Bits */
8481 #define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
8482 #define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
8483 #define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
8484 #define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
8485 #define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
8486 #define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
8487 #define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
8488 #define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
8489 
8490 /* UCAxIRRCTL Control Bits */
8491 #define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
8492 #define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
8493 #define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
8494 #define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
8495 #define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
8496 #define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
8497 #define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
8498 #define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
8499 
8500 /* UCAxABCTL Control Bits */
8501 //#define res (0x80) /* reserved */
8502 //#define res (0x40) /* reserved */
8503 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
8504 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
8505 #define UCSTOE (0x08) /* Sync-Field Timeout error */
8506 #define UCBTOE (0x04) /* Break Timeout error */
8507 //#define res (0x02) /* reserved */
8508 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */
8509 
8510 /* UCBxI2COA Control Bits */
8511 #define UCGCEN (0x8000) /* I2C General Call enable */
8512 #define UCOA9 (0x0200) /* I2C Own Address 9 */
8513 #define UCOA8 (0x0100) /* I2C Own Address 8 */
8514 #define UCOA7 (0x0080) /* I2C Own Address 7 */
8515 #define UCOA6 (0x0040) /* I2C Own Address 6 */
8516 #define UCOA5 (0x0020) /* I2C Own Address 5 */
8517 #define UCOA4 (0x0010) /* I2C Own Address 4 */
8518 #define UCOA3 (0x0008) /* I2C Own Address 3 */
8519 #define UCOA2 (0x0004) /* I2C Own Address 2 */
8520 #define UCOA1 (0x0002) /* I2C Own Address 1 */
8521 #define UCOA0 (0x0001) /* I2C Own Address 0 */
8522 
8523 /* UCBxI2COA Control Bits */
8524 #define UCOA7_L (0x0080) /* I2C Own Address 7 */
8525 #define UCOA6_L (0x0040) /* I2C Own Address 6 */
8526 #define UCOA5_L (0x0020) /* I2C Own Address 5 */
8527 #define UCOA4_L (0x0010) /* I2C Own Address 4 */
8528 #define UCOA3_L (0x0008) /* I2C Own Address 3 */
8529 #define UCOA2_L (0x0004) /* I2C Own Address 2 */
8530 #define UCOA1_L (0x0002) /* I2C Own Address 1 */
8531 #define UCOA0_L (0x0001) /* I2C Own Address 0 */
8532 
8533 /* UCBxI2COA Control Bits */
8534 #define UCGCEN_H (0x0080) /* I2C General Call enable */
8535 #define UCOA9_H (0x0002) /* I2C Own Address 9 */
8536 #define UCOA8_H (0x0001) /* I2C Own Address 8 */
8537 
8538 /* UCBxI2CSA Control Bits */
8539 #define UCSA9 (0x0200) /* I2C Slave Address 9 */
8540 #define UCSA8 (0x0100) /* I2C Slave Address 8 */
8541 #define UCSA7 (0x0080) /* I2C Slave Address 7 */
8542 #define UCSA6 (0x0040) /* I2C Slave Address 6 */
8543 #define UCSA5 (0x0020) /* I2C Slave Address 5 */
8544 #define UCSA4 (0x0010) /* I2C Slave Address 4 */
8545 #define UCSA3 (0x0008) /* I2C Slave Address 3 */
8546 #define UCSA2 (0x0004) /* I2C Slave Address 2 */
8547 #define UCSA1 (0x0002) /* I2C Slave Address 1 */
8548 #define UCSA0 (0x0001) /* I2C Slave Address 0 */
8549 
8550 /* UCBxI2CSA Control Bits */
8551 #define UCSA7_L (0x0080) /* I2C Slave Address 7 */
8552 #define UCSA6_L (0x0040) /* I2C Slave Address 6 */
8553 #define UCSA5_L (0x0020) /* I2C Slave Address 5 */
8554 #define UCSA4_L (0x0010) /* I2C Slave Address 4 */
8555 #define UCSA3_L (0x0008) /* I2C Slave Address 3 */
8556 #define UCSA2_L (0x0004) /* I2C Slave Address 2 */
8557 #define UCSA1_L (0x0002) /* I2C Slave Address 1 */
8558 #define UCSA0_L (0x0001) /* I2C Slave Address 0 */
8559 
8560 /* UCBxI2CSA Control Bits */
8561 #define UCSA9_H (0x0002) /* I2C Slave Address 9 */
8562 #define UCSA8_H (0x0001) /* I2C Slave Address 8 */
8563 
8564 /* UCAxIE Control Bits */
8565 #define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */
8566 #define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */
8567 
8568 /* UCAxIE Control Bits */
8569 #define UCTXIE_L (0x0002) /* USCI Transmit Interrupt Enable */
8570 #define UCRXIE_L (0x0001) /* USCI Receive Interrupt Enable */
8571 
8572 /* UCBxIE Control Bits */
8573 #define UCNACKIE (0x0020) /* NACK Condition interrupt enable */
8574 #define UCALIE (0x0010) /* Arbitration Lost interrupt enable */
8575 #define UCSTPIE (0x0008) /* STOP Condition interrupt enable */
8576 #define UCSTTIE (0x0004) /* START Condition interrupt enable */
8577 #define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */
8578 #define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */
8579 
8580 /* UCBxIE Control Bits */
8581 #define UCNACKIE_L (0x0020) /* NACK Condition interrupt enable */
8582 #define UCALIE_L (0x0010) /* Arbitration Lost interrupt enable */
8583 #define UCSTPIE_L (0x0008) /* STOP Condition interrupt enable */
8584 #define UCSTTIE_L (0x0004) /* START Condition interrupt enable */
8585 #define UCTXIE_L (0x0002) /* USCI Transmit Interrupt Enable */
8586 #define UCRXIE_L (0x0001) /* USCI Receive Interrupt Enable */
8587 
8588 /* UCAxIFG Control Bits */
8589 #define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */
8590 #define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */
8591 
8592 /* UCAxIFG Control Bits */
8593 #define UCTXIFG_L (0x0002) /* USCI Transmit Interrupt Flag */
8594 #define UCRXIFG_L (0x0001) /* USCI Receive Interrupt Flag */
8595 
8596 /* UCBxIFG Control Bits */
8597 #define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */
8598 #define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */
8599 #define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */
8600 #define UCSTTIFG (0x0004) /* START Condition interrupt Flag */
8601 #define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */
8602 #define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */
8603 
8604 /* UCBxIFG Control Bits */
8605 #define UCNACKIFG_L (0x0020) /* NAK Condition interrupt Flag */
8606 #define UCALIFG_L (0x0010) /* Arbitration Lost interrupt Flag */
8607 #define UCSTPIFG_L (0x0008) /* STOP Condition interrupt Flag */
8608 #define UCSTTIFG_L (0x0004) /* START Condition interrupt Flag */
8609 #define UCTXIFG_L (0x0002) /* USCI Transmit Interrupt Flag */
8610 #define UCRXIFG_L (0x0001) /* USCI Receive Interrupt Flag */
8611 
8612 /* USCI Definitions */
8613 #define USCI_NONE (0x0000) /* No Interrupt pending */
8614 #define USCI_UCRXIFG (0x0002) /* USCI UCRXIFG */
8615 #define USCI_UCTXIFG (0x0004) /* USCI UCTXIFG */
8616 #define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */
8617 #define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */
8618 #define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/
8619 #define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/
8620 #define USCI_I2C_UCRXIFG (0x000A) /* USCI I2C Mode: UCRXIFG */
8621 #define USCI_I2C_UCTXIFG (0x000C) /* USCI I2C Mode: UCTXIFG */
8622 
8623 #endif
8624 /************************************************************
8625 * USCI Ax
8626 ************************************************************/
8627 #ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */
8628 
8629 #define OFS_UCAxCTLW0 (0x0000) /* USCI Ax Control Word Register 0 */
8630 #define OFS_UCAxCTLW0_L OFS_UCAxCTLW0
8631 #define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1
8632 #define OFS_UCAxCTL0 (0x0001)
8633 #define OFS_UCAxCTL1 (0x0000)
8634 #define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */
8635 #define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */
8636 #define OFS_UCAxCTLW1 (0x0002) /* USCI Ax Control Word Register 1 */
8637 #define OFS_UCAxCTLW1_L OFS_UCAxCTLW1
8638 #define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1
8639 #define OFS_UCAxBRW (0x0006) /* USCI Ax Baud Word Rate 0 */
8640 #define OFS_UCAxBRW_L OFS_UCAxBRW
8641 #define OFS_UCAxBRW_H OFS_UCAxBRW+1
8642 #define OFS_UCAxBR0 (0x0006)
8643 #define OFS_UCAxBR1 (0x0007)
8644 #define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */
8645 #define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */
8646 #define OFS_UCAxMCTLW (0x0008) /* USCI Ax Modulation Control */
8647 #define OFS_UCAxMCTLW_L OFS_UCAxMCTLW
8648 #define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1
8649 #define OFS_UCAxSTATW (0x000A) /* USCI Ax Status Register */
8650 #define OFS_UCAxRXBUF (0x000C) /* USCI Ax Receive Buffer */
8651 #define OFS_UCAxRXBUF_L OFS_UCAxRXBUF
8652 #define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1
8653 #define OFS_UCAxTXBUF (0x000E) /* USCI Ax Transmit Buffer */
8654 #define OFS_UCAxTXBUF_L OFS_UCAxTXBUF
8655 #define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1
8656 #define OFS_UCAxABCTL (0x0010) /* USCI Ax LIN Control */
8657 #define OFS_UCAxIRCTL (0x0012) /* USCI Ax IrDA Transmit Control */
8658 #define OFS_UCAxIRCTL_L OFS_UCAxIRCTL
8659 #define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1
8660 #define OFS_UCAxIRTCTL (0x0012)
8661 #define OFS_UCAxIRRCTL (0x0013)
8662 #define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */
8663 #define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */
8664 #define OFS_UCAxIE (0x001A) /* USCI Ax Interrupt Enable Register */
8665 #define OFS_UCAxIE_L OFS_UCAxIE
8666 #define OFS_UCAxIE_H OFS_UCAxIE+1
8667 #define OFS_UCAxIFG (0x001C) /* USCI Ax Interrupt Flags Register */
8668 #define OFS_UCAxIFG_L OFS_UCAxIFG
8669 #define OFS_UCAxIFG_H OFS_UCAxIFG+1
8670 #define OFS_UCAxIE__UART (0x001A)
8671 #define OFS_UCAxIE__UART_L OFS_UCAxIE__UART
8672 #define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1
8673 #define OFS_UCAxIFG__UART (0x001C)
8674 #define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART
8675 #define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1
8676 #define OFS_UCAxIV (0x001E) /* USCI Ax Interrupt Vector Register */
8677 
8678 #define OFS_UCAxCTLW0__SPI (0x0000)
8679 #define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI
8680 #define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1
8681 #define OFS_UCAxCTL0__SPI (0x0001)
8682 #define OFS_UCAxCTL1__SPI (0x0000)
8683 #define OFS_UCAxBRW__SPI (0x0006)
8684 #define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI
8685 #define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1
8686 #define OFS_UCAxBR0__SPI (0x0006)
8687 #define OFS_UCAxBR1__SPI (0x0007)
8688 #define OFS_UCAxSTATW__SPI (0x000A)
8689 #define OFS_UCAxRXBUF__SPI (0x000C)
8690 #define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI
8691 #define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1
8692 #define OFS_UCAxTXBUF__SPI (0x000E)
8693 #define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI
8694 #define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1
8695 #define OFS_UCAxIE__SPI (0x001A)
8696 #define OFS_UCAxIFG__SPI (0x001C)
8697 #define OFS_UCAxIV__SPI (0x001E)
8698 
8699 #endif
8700 /************************************************************
8701 * USCI Bx
8702 ************************************************************/
8703 #ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */
8704 
8705 #define OFS_UCBxCTLW0__SPI (0x0000)
8706 #define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI
8707 #define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1
8708 #define OFS_UCBxCTL0__SPI (0x0001)
8709 #define OFS_UCBxCTL1__SPI (0x0000)
8710 #define OFS_UCBxBRW__SPI (0x0006)
8711 #define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI
8712 #define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1
8713 #define OFS_UCBxBR0__SPI (0x0006)
8714 #define OFS_UCBxBR1__SPI (0x0007)
8715 #define OFS_UCBxSTATW__SPI (0x0008)
8716 #define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI
8717 #define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1
8718 #define OFS_UCBxRXBUF__SPI (0x000C)
8719 #define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI
8720 #define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1
8721 #define OFS_UCBxTXBUF__SPI (0x000E)
8722 #define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI
8723 #define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1
8724 #define OFS_UCBxIE__SPI (0x002A)
8725 #define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI
8726 #define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1
8727 #define OFS_UCBxIFG__SPI (0x002C)
8728 #define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI
8729 #define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1
8730 #define OFS_UCBxIV__SPI (0x002E)
8731 
8732 #define OFS_UCBxCTLW0 (0x0000) /* USCI Bx Control Word Register 0 */
8733 #define OFS_UCBxCTLW0_L OFS_UCBxCTLW0
8734 #define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1
8735 #define OFS_UCBxCTL0 (0x0001)
8736 #define OFS_UCBxCTL1 (0x0000)
8737 #define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */
8738 #define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */
8739 #define OFS_UCBxCTLW1 (0x0002) /* USCI Bx Control Word Register 1 */
8740 #define OFS_UCBxCTLW1_L OFS_UCBxCTLW1
8741 #define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1
8742 #define OFS_UCBxBRW (0x0006) /* USCI Bx Baud Word Rate 0 */
8743 #define OFS_UCBxBRW_L OFS_UCBxBRW
8744 #define OFS_UCBxBRW_H OFS_UCBxBRW+1
8745 #define OFS_UCBxBR0 (0x0006)
8746 #define OFS_UCBxBR1 (0x0007)
8747 #define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */
8748 #define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */
8749 #define OFS_UCBxSTATW (0x0008) /* USCI Bx Status Word Register */
8750 #define OFS_UCBxSTATW_L OFS_UCBxSTATW
8751 #define OFS_UCBxSTATW_H OFS_UCBxSTATW+1
8752 #define OFS_UCBxSTATW__I2C (0x0008)
8753 #define OFS_UCBxSTAT__I2C (0x0008)
8754 #define OFS_UCBxBCNT__I2C (0x0009)
8755 #define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */
8756 #define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */
8757 #define OFS_UCBxTBCNT (0x000A) /* USCI Bx Byte Counter Threshold Register */
8758 #define OFS_UCBxTBCNT_L OFS_UCBxTBCNT
8759 #define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1
8760 #define OFS_UCBxRXBUF (0x000C) /* USCI Bx Receive Buffer */
8761 #define OFS_UCBxRXBUF_L OFS_UCBxRXBUF
8762 #define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1
8763 #define OFS_UCBxTXBUF (0x000E) /* USCI Bx Transmit Buffer */
8764 #define OFS_UCBxTXBUF_L OFS_UCBxTXBUF
8765 #define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1
8766 #define OFS_UCBxI2COA0 (0x0014) /* USCI Bx I2C Own Address 0 */
8767 #define OFS_UCBxI2COA0_L OFS_UCBxI2COA0
8768 #define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1
8769 #define OFS_UCBxI2COA1 (0x0016) /* USCI Bx I2C Own Address 1 */
8770 #define OFS_UCBxI2COA1_L OFS_UCBxI2COA1
8771 #define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1
8772 #define OFS_UCBxI2COA2 (0x0018) /* USCI Bx I2C Own Address 2 */
8773 #define OFS_UCBxI2COA2_L OFS_UCBxI2COA2
8774 #define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1
8775 #define OFS_UCBxI2COA3 (0x001A) /* USCI Bx I2C Own Address 3 */
8776 #define OFS_UCBxI2COA3_L OFS_UCBxI2COA3
8777 #define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1
8778 #define OFS_UCBxADDRX (0x001C) /* USCI Bx Received Address Register */
8779 #define OFS_UCBxADDRX_L OFS_UCBxADDRX
8780 #define OFS_UCBxADDRX_H OFS_UCBxADDRX+1
8781 #define OFS_UCBxADDMASK (0x001E) /* USCI Bx Address Mask Register */
8782 #define OFS_UCBxADDMASK_L OFS_UCBxADDMASK
8783 #define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1
8784 #define OFS_UCBxI2CSA (0x0020) /* USCI Bx I2C Slave Address */
8785 #define OFS_UCBxI2CSA_L OFS_UCBxI2CSA
8786 #define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1
8787 #define OFS_UCBxIE (0x002A) /* USCI Bx Interrupt Enable Register */
8788 #define OFS_UCBxIE_L OFS_UCBxIE
8789 #define OFS_UCBxIE_H OFS_UCBxIE+1
8790 #define OFS_UCBxIFG (0x002C) /* USCI Bx Interrupt Flags Register */
8791 #define OFS_UCBxIFG_L OFS_UCBxIFG
8792 #define OFS_UCBxIFG_H OFS_UCBxIFG+1
8793 #define OFS_UCBxIE__I2C (0x002A)
8794 #define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C
8795 #define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1
8796 #define OFS_UCBxIFG__I2C (0x002C)
8797 #define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C
8798 #define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1
8799 #define OFS_UCBxIV (0x002E) /* USCI Bx Interrupt Vector Register */
8800 
8801 #endif
8802 #if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__))
8803 
8804 // UCAxCTLW0 UART-Mode Control Bits
8805 #define UCPEN (0x8000) /* Async. Mode: Parity enable */
8806 #define UCPAR (0x4000) /* Async. Mode: Parity 0:odd / 1:even */
8807 #define UCMSB (0x2000) /* Async. Mode: MSB first 0:LSB / 1:MSB */
8808 #define UC7BIT (0x1000) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
8809 #define UCSPB (0x0800) /* Async. Mode: Stop Bits 0:one / 1: two */
8810 #define UCMODE1 (0x0400) /* Async. Mode: USCI Mode 1 */
8811 #define UCMODE0 (0x0200) /* Async. Mode: USCI Mode 0 */
8812 #define UCSYNC (0x0100) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
8813 #define UCSSEL1 (0x0080) /* USCI 0 Clock Source Select 1 */
8814 #define UCSSEL0 (0x0040) /* USCI 0 Clock Source Select 0 */
8815 #define UCRXEIE (0x0020) /* RX Error interrupt enable */
8816 #define UCBRKIE (0x0010) /* Break interrupt enable */
8817 #define UCDORM (0x0008) /* Dormant (Sleep) Mode */
8818 #define UCTXADDR (0x0004) /* Send next Data as Address */
8819 #define UCTXBRK (0x0002) /* Send next Data as Break */
8820 #define UCSWRST (0x0001) /* USCI Software Reset */
8821 
8822 // UCAxCTLW0 UART-Mode Control Bits
8823 #define UCSSEL1_L (0x0080) /* USCI 0 Clock Source Select 1 */
8824 #define UCSSEL0_L (0x0040) /* USCI 0 Clock Source Select 0 */
8825 #define UCRXEIE_L (0x0020) /* RX Error interrupt enable */
8826 #define UCBRKIE_L (0x0010) /* Break interrupt enable */
8827 #define UCDORM_L (0x0008) /* Dormant (Sleep) Mode */
8828 #define UCTXADDR_L (0x0004) /* Send next Data as Address */
8829 #define UCTXBRK_L (0x0002) /* Send next Data as Break */
8830 #define UCSWRST_L (0x0001) /* USCI Software Reset */
8831 
8832 // UCAxCTLW0 UART-Mode Control Bits
8833 #define UCPEN_H (0x0080) /* Async. Mode: Parity enable */
8834 #define UCPAR_H (0x0040) /* Async. Mode: Parity 0:odd / 1:even */
8835 #define UCMSB_H (0x0020) /* Async. Mode: MSB first 0:LSB / 1:MSB */
8836 #define UC7BIT_H (0x0010) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
8837 #define UCSPB_H (0x0008) /* Async. Mode: Stop Bits 0:one / 1: two */
8838 #define UCMODE1_H (0x0004) /* Async. Mode: USCI Mode 1 */
8839 #define UCMODE0_H (0x0002) /* Async. Mode: USCI Mode 0 */
8840 #define UCSYNC_H (0x0001) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
8841 
8842 // UCxxCTLW0 SPI-Mode Control Bits
8843 #define UCCKPH (0x8000) /* Sync. Mode: Clock Phase */
8844 #define UCCKPL (0x4000) /* Sync. Mode: Clock Polarity */
8845 #define UCMST (0x0800) /* Sync. Mode: Master Select */
8846 //#define res (0x0020) /* reserved */
8847 //#define res (0x0010) /* reserved */
8848 //#define res (0x0008) /* reserved */
8849 //#define res (0x0004) /* reserved */
8850 #define UCSTEM (0x0002) /* USCI STE Mode */
8851 
8852 // UCBxCTLW0 I2C-Mode Control Bits
8853 #define UCA10 (0x8000) /* 10-bit Address Mode */
8854 #define UCSLA10 (0x4000) /* 10-bit Slave Address Mode */
8855 #define UCMM (0x2000) /* Multi-Master Environment */
8856 //#define res (0x1000) /* reserved */
8857 //#define res (0x0100) /* reserved */
8858 #define UCTXACK (0x0020) /* Transmit ACK */
8859 #define UCTR (0x0010) /* Transmit/Receive Select/Flag */
8860 #define UCTXNACK (0x0008) /* Transmit NACK */
8861 #define UCTXSTP (0x0004) /* Transmit STOP */
8862 #define UCTXSTT (0x0002) /* Transmit START */
8863 
8864 // UCBxCTLW0 I2C-Mode Control Bits
8865 //#define res (0x1000) /* reserved */
8866 //#define res (0x0100) /* reserved */
8867 #define UCTXACK_L (0x0020) /* Transmit ACK */
8868 #define UCTR_L (0x0010) /* Transmit/Receive Select/Flag */
8869 #define UCTXNACK_L (0x0008) /* Transmit NACK */
8870 #define UCTXSTP_L (0x0004) /* Transmit STOP */
8871 #define UCTXSTT_L (0x0002) /* Transmit START */
8872 
8873 // UCBxCTLW0 I2C-Mode Control Bits
8874 #define UCA10_H (0x0080) /* 10-bit Address Mode */
8875 #define UCSLA10_H (0x0040) /* 10-bit Slave Address Mode */
8876 #define UCMM_H (0x0020) /* Multi-Master Environment */
8877 //#define res (0x1000) /* reserved */
8878 //#define res (0x0100) /* reserved */
8879 
8880 #define UCMODE_0 (0x0000) /* Sync. Mode: USCI Mode: 0 */
8881 #define UCMODE_1 (0x0200) /* Sync. Mode: USCI Mode: 1 */
8882 #define UCMODE_2 (0x0400) /* Sync. Mode: USCI Mode: 2 */
8883 #define UCMODE_3 (0x0600) /* Sync. Mode: USCI Mode: 3 */
8884 
8885 #define UCSSEL_0 (0x0000) /* USCI 0 Clock Source: 0 */
8886 #define UCSSEL_1 (0x0040) /* USCI 0 Clock Source: 1 */
8887 #define UCSSEL_2 (0x0080) /* USCI 0 Clock Source: 2 */
8888 #define UCSSEL_3 (0x00C0) /* USCI 0 Clock Source: 3 */
8889 #define UCSSEL__UCLK (0x0000) /* USCI 0 Clock Source: UCLK */
8890 #define UCSSEL__ACLK (0x0040) /* USCI 0 Clock Source: ACLK */
8891 #define UCSSEL__SMCLK (0x0080) /* USCI 0 Clock Source: SMCLK */
8892 
8893 // UCAxCTLW1 UART-Mode Control Bits
8894 #define UCGLIT1 (0x0002) /* USCI Deglitch Time Bit 1 */
8895 #define UCGLIT0 (0x0001) /* USCI Deglitch Time Bit 0 */
8896 
8897 // UCAxCTLW1 UART-Mode Control Bits
8898 #define UCGLIT1_L (0x0002) /* USCI Deglitch Time Bit 1 */
8899 #define UCGLIT0_L (0x0001) /* USCI Deglitch Time Bit 0 */
8900 
8901 // UCBxCTLW1 I2C-Mode Control Bits
8902 #define UCETXINT (0x0100) /* USCI Early UCTXIFG0 */
8903 #define UCCLTO1 (0x0080) /* USCI Clock low timeout Bit: 1 */
8904 #define UCCLTO0 (0x0040) /* USCI Clock low timeout Bit: 0 */
8905 #define UCSTPNACK (0x0020) /* USCI Acknowledge Stop last byte */
8906 #define UCSWACK (0x0010) /* USCI Software controlled ACK */
8907 #define UCASTP1 (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
8908 #define UCASTP0 (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
8909 #define UCGLIT1 (0x0002) /* USCI Deglitch time Bit: 1 */
8910 #define UCGLIT0 (0x0001) /* USCI Deglitch time Bit: 0 */
8911 
8912 // UCBxCTLW1 I2C-Mode Control Bits
8913 #define UCCLTO1_L (0x0080) /* USCI Clock low timeout Bit: 1 */
8914 #define UCCLTO0_L (0x0040) /* USCI Clock low timeout Bit: 0 */
8915 #define UCSTPNACK_L (0x0020) /* USCI Acknowledge Stop last byte */
8916 #define UCSWACK_L (0x0010) /* USCI Software controlled ACK */
8917 #define UCASTP1_L (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
8918 #define UCASTP0_L (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
8919 #define UCGLIT1_L (0x0002) /* USCI Deglitch time Bit: 1 */
8920 #define UCGLIT0_L (0x0001) /* USCI Deglitch time Bit: 0 */
8921 
8922 // UCBxCTLW1 I2C-Mode Control Bits
8923 #define UCETXINT_H (0x0001) /* USCI Early UCTXIFG0 */
8924 
8925 #define UCGLIT_0 (0x0000) /* USCI Deglitch time: 0 */
8926 #define UCGLIT_1 (0x0001) /* USCI Deglitch time: 1 */
8927 #define UCGLIT_2 (0x0002) /* USCI Deglitch time: 2 */
8928 #define UCGLIT_3 (0x0003) /* USCI Deglitch time: 3 */
8929 
8930 #define UCASTP_0 (0x0000) /* USCI Automatic Stop condition generation: 0 */
8931 #define UCASTP_1 (0x0004) /* USCI Automatic Stop condition generation: 1 */
8932 #define UCASTP_2 (0x0008) /* USCI Automatic Stop condition generation: 2 */
8933 #define UCASTP_3 (0x000C) /* USCI Automatic Stop condition generation: 3 */
8934 
8935 #define UCCLTO_0 (0x0000) /* USCI Clock low timeout: 0 */
8936 #define UCCLTO_1 (0x0040) /* USCI Clock low timeout: 1 */
8937 #define UCCLTO_2 (0x0080) /* USCI Clock low timeout: 2 */
8938 #define UCCLTO_3 (0x00C0) /* USCI Clock low timeout: 3 */
8939 
8940 /* UCAxMCTLW Control Bits */
8941 #define UCBRS7 (0x8000) /* USCI Second Stage Modulation Select 7 */
8942 #define UCBRS6 (0x4000) /* USCI Second Stage Modulation Select 6 */
8943 #define UCBRS5 (0x2000) /* USCI Second Stage Modulation Select 5 */
8944 #define UCBRS4 (0x1000) /* USCI Second Stage Modulation Select 4 */
8945 #define UCBRS3 (0x0800) /* USCI Second Stage Modulation Select 3 */
8946 #define UCBRS2 (0x0400) /* USCI Second Stage Modulation Select 2 */
8947 #define UCBRS1 (0x0200) /* USCI Second Stage Modulation Select 1 */
8948 #define UCBRS0 (0x0100) /* USCI Second Stage Modulation Select 0 */
8949 #define UCBRF3 (0x0080) /* USCI First Stage Modulation Select 3 */
8950 #define UCBRF2 (0x0040) /* USCI First Stage Modulation Select 2 */
8951 #define UCBRF1 (0x0020) /* USCI First Stage Modulation Select 1 */
8952 #define UCBRF0 (0x0010) /* USCI First Stage Modulation Select 0 */
8953 #define UCOS16 (0x0001) /* USCI 16-times Oversampling enable */
8954 
8955 /* UCAxMCTLW Control Bits */
8956 #define UCBRF3_L (0x0080) /* USCI First Stage Modulation Select 3 */
8957 #define UCBRF2_L (0x0040) /* USCI First Stage Modulation Select 2 */
8958 #define UCBRF1_L (0x0020) /* USCI First Stage Modulation Select 1 */
8959 #define UCBRF0_L (0x0010) /* USCI First Stage Modulation Select 0 */
8960 #define UCOS16_L (0x0001) /* USCI 16-times Oversampling enable */
8961 
8962 /* UCAxMCTLW Control Bits */
8963 #define UCBRS7_H (0x0080) /* USCI Second Stage Modulation Select 7 */
8964 #define UCBRS6_H (0x0040) /* USCI Second Stage Modulation Select 6 */
8965 #define UCBRS5_H (0x0020) /* USCI Second Stage Modulation Select 5 */
8966 #define UCBRS4_H (0x0010) /* USCI Second Stage Modulation Select 4 */
8967 #define UCBRS3_H (0x0008) /* USCI Second Stage Modulation Select 3 */
8968 #define UCBRS2_H (0x0004) /* USCI Second Stage Modulation Select 2 */
8969 #define UCBRS1_H (0x0002) /* USCI Second Stage Modulation Select 1 */
8970 #define UCBRS0_H (0x0001) /* USCI Second Stage Modulation Select 0 */
8971 
8972 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
8973 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
8974 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
8975 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
8976 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
8977 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
8978 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
8979 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
8980 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
8981 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
8982 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
8983 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
8984 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
8985 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
8986 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
8987 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
8988 
8989 /* UCAxSTATW Control Bits */
8990 #define UCLISTEN (0x0080) /* USCI Listen mode */
8991 #define UCFE (0x0040) /* USCI Frame Error Flag */
8992 #define UCOE (0x0020) /* USCI Overrun Error Flag */
8993 #define UCPE (0x0010) /* USCI Parity Error Flag */
8994 #define UCBRK (0x0008) /* USCI Break received */
8995 #define UCRXERR (0x0004) /* USCI RX Error Flag */
8996 #define UCADDR (0x0002) /* USCI Address received Flag */
8997 #define UCBUSY (0x0001) /* USCI Busy Flag */
8998 #define UCIDLE (0x0002) /* USCI Idle line detected Flag */
8999 
9000 /* UCBxSTATW I2C Control Bits */
9001 #define UCBCNT7 (0x8000) /* USCI Byte Counter Bit 7 */
9002 #define UCBCNT6 (0x4000) /* USCI Byte Counter Bit 6 */
9003 #define UCBCNT5 (0x2000) /* USCI Byte Counter Bit 5 */
9004 #define UCBCNT4 (0x1000) /* USCI Byte Counter Bit 4 */
9005 #define UCBCNT3 (0x0800) /* USCI Byte Counter Bit 3 */
9006 #define UCBCNT2 (0x0400) /* USCI Byte Counter Bit 2 */
9007 #define UCBCNT1 (0x0200) /* USCI Byte Counter Bit 1 */
9008 #define UCBCNT0 (0x0100) /* USCI Byte Counter Bit 0 */
9009 #define UCSCLLOW (0x0040) /* SCL low */
9010 #define UCGC (0x0020) /* General Call address received Flag */
9011 #define UCBBUSY (0x0010) /* Bus Busy Flag */
9012 
9013 /* UCBxTBCNT I2C Control Bits */
9014 #define UCTBCNT7 (0x0080) /* USCI Byte Counter Bit 7 */
9015 #define UCTBCNT6 (0x0040) /* USCI Byte Counter Bit 6 */
9016 #define UCTBCNT5 (0x0020) /* USCI Byte Counter Bit 5 */
9017 #define UCTBCNT4 (0x0010) /* USCI Byte Counter Bit 4 */
9018 #define UCTBCNT3 (0x0008) /* USCI Byte Counter Bit 3 */
9019 #define UCTBCNT2 (0x0004) /* USCI Byte Counter Bit 2 */
9020 #define UCTBCNT1 (0x0002) /* USCI Byte Counter Bit 1 */
9021 #define UCTBCNT0 (0x0001) /* USCI Byte Counter Bit 0 */
9022 
9023 /* UCAxIRCTL Control Bits */
9024 #define UCIRRXFL5 (0x8000) /* IRDA Receive Filter Length 5 */
9025 #define UCIRRXFL4 (0x4000) /* IRDA Receive Filter Length 4 */
9026 #define UCIRRXFL3 (0x2000) /* IRDA Receive Filter Length 3 */
9027 #define UCIRRXFL2 (0x1000) /* IRDA Receive Filter Length 2 */
9028 #define UCIRRXFL1 (0x0800) /* IRDA Receive Filter Length 1 */
9029 #define UCIRRXFL0 (0x0400) /* IRDA Receive Filter Length 0 */
9030 #define UCIRRXPL (0x0200) /* IRDA Receive Input Polarity */
9031 #define UCIRRXFE (0x0100) /* IRDA Receive Filter enable */
9032 #define UCIRTXPL5 (0x0080) /* IRDA Transmit Pulse Length 5 */
9033 #define UCIRTXPL4 (0x0040) /* IRDA Transmit Pulse Length 4 */
9034 #define UCIRTXPL3 (0x0020) /* IRDA Transmit Pulse Length 3 */
9035 #define UCIRTXPL2 (0x0010) /* IRDA Transmit Pulse Length 2 */
9036 #define UCIRTXPL1 (0x0008) /* IRDA Transmit Pulse Length 1 */
9037 #define UCIRTXPL0 (0x0004) /* IRDA Transmit Pulse Length 0 */
9038 #define UCIRTXCLK (0x0002) /* IRDA Transmit Pulse Clock Select */
9039 #define UCIREN (0x0001) /* IRDA Encoder/Decoder enable */
9040 
9041 /* UCAxIRCTL Control Bits */
9042 #define UCIRTXPL5_L (0x0080) /* IRDA Transmit Pulse Length 5 */
9043 #define UCIRTXPL4_L (0x0040) /* IRDA Transmit Pulse Length 4 */
9044 #define UCIRTXPL3_L (0x0020) /* IRDA Transmit Pulse Length 3 */
9045 #define UCIRTXPL2_L (0x0010) /* IRDA Transmit Pulse Length 2 */
9046 #define UCIRTXPL1_L (0x0008) /* IRDA Transmit Pulse Length 1 */
9047 #define UCIRTXPL0_L (0x0004) /* IRDA Transmit Pulse Length 0 */
9048 #define UCIRTXCLK_L (0x0002) /* IRDA Transmit Pulse Clock Select */
9049 #define UCIREN_L (0x0001) /* IRDA Encoder/Decoder enable */
9050 
9051 /* UCAxIRCTL Control Bits */
9052 #define UCIRRXFL5_H (0x0080) /* IRDA Receive Filter Length 5 */
9053 #define UCIRRXFL4_H (0x0040) /* IRDA Receive Filter Length 4 */
9054 #define UCIRRXFL3_H (0x0020) /* IRDA Receive Filter Length 3 */
9055 #define UCIRRXFL2_H (0x0010) /* IRDA Receive Filter Length 2 */
9056 #define UCIRRXFL1_H (0x0008) /* IRDA Receive Filter Length 1 */
9057 #define UCIRRXFL0_H (0x0004) /* IRDA Receive Filter Length 0 */
9058 #define UCIRRXPL_H (0x0002) /* IRDA Receive Input Polarity */
9059 #define UCIRRXFE_H (0x0001) /* IRDA Receive Filter enable */
9060 
9061 /* UCAxABCTL Control Bits */
9062 //#define res (0x80) /* reserved */
9063 //#define res (0x40) /* reserved */
9064 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
9065 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
9066 #define UCSTOE (0x08) /* Sync-Field Timeout error */
9067 #define UCBTOE (0x04) /* Break Timeout error */
9068 //#define res (0x02) /* reserved */
9069 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */
9070 
9071 /* UCBxI2COA0 Control Bits */
9072 #define UCGCEN (0x8000) /* I2C General Call enable */
9073 #define UCOAEN (0x0400) /* I2C Own Address enable */
9074 #define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
9075 #define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
9076 #define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
9077 #define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
9078 #define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
9079 #define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
9080 #define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
9081 #define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
9082 #define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
9083 #define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
9084 
9085 /* UCBxI2COA0 Control Bits */
9086 #define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
9087 #define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
9088 #define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
9089 #define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
9090 #define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
9091 #define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
9092 #define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
9093 #define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
9094 
9095 /* UCBxI2COA0 Control Bits */
9096 #define UCGCEN_H (0x0080) /* I2C General Call enable */
9097 #define UCOAEN_H (0x0004) /* I2C Own Address enable */
9098 #define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
9099 #define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
9100 
9101 /* UCBxI2COAx Control Bits */
9102 #define UCOAEN (0x0400) /* I2C Own Address enable */
9103 #define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
9104 #define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
9105 #define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
9106 #define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
9107 #define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
9108 #define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
9109 #define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
9110 #define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
9111 #define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
9112 #define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
9113 
9114 /* UCBxI2COAx Control Bits */
9115 #define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
9116 #define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
9117 #define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
9118 #define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
9119 #define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
9120 #define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
9121 #define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
9122 #define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
9123 
9124 /* UCBxI2COAx Control Bits */
9125 #define UCOAEN_H (0x0004) /* I2C Own Address enable */
9126 #define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
9127 #define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
9128 
9129 /* UCBxADDRX Control Bits */
9130 #define UCADDRX9 (0x0200) /* I2C Receive Address Bit 9 */
9131 #define UCADDRX8 (0x0100) /* I2C Receive Address Bit 8 */
9132 #define UCADDRX7 (0x0080) /* I2C Receive Address Bit 7 */
9133 #define UCADDRX6 (0x0040) /* I2C Receive Address Bit 6 */
9134 #define UCADDRX5 (0x0020) /* I2C Receive Address Bit 5 */
9135 #define UCADDRX4 (0x0010) /* I2C Receive Address Bit 4 */
9136 #define UCADDRX3 (0x0008) /* I2C Receive Address Bit 3 */
9137 #define UCADDRX2 (0x0004) /* I2C Receive Address Bit 2 */
9138 #define UCADDRX1 (0x0002) /* I2C Receive Address Bit 1 */
9139 #define UCADDRX0 (0x0001) /* I2C Receive Address Bit 0 */
9140 
9141 /* UCBxADDRX Control Bits */
9142 #define UCADDRX7_L (0x0080) /* I2C Receive Address Bit 7 */
9143 #define UCADDRX6_L (0x0040) /* I2C Receive Address Bit 6 */
9144 #define UCADDRX5_L (0x0020) /* I2C Receive Address Bit 5 */
9145 #define UCADDRX4_L (0x0010) /* I2C Receive Address Bit 4 */
9146 #define UCADDRX3_L (0x0008) /* I2C Receive Address Bit 3 */
9147 #define UCADDRX2_L (0x0004) /* I2C Receive Address Bit 2 */
9148 #define UCADDRX1_L (0x0002) /* I2C Receive Address Bit 1 */
9149 #define UCADDRX0_L (0x0001) /* I2C Receive Address Bit 0 */
9150 
9151 /* UCBxADDRX Control Bits */
9152 #define UCADDRX9_H (0x0002) /* I2C Receive Address Bit 9 */
9153 #define UCADDRX8_H (0x0001) /* I2C Receive Address Bit 8 */
9154 
9155 /* UCBxADDMASK Control Bits */
9156 #define UCADDMASK9 (0x0200) /* I2C Address Mask Bit 9 */
9157 #define UCADDMASK8 (0x0100) /* I2C Address Mask Bit 8 */
9158 #define UCADDMASK7 (0x0080) /* I2C Address Mask Bit 7 */
9159 #define UCADDMASK6 (0x0040) /* I2C Address Mask Bit 6 */
9160 #define UCADDMASK5 (0x0020) /* I2C Address Mask Bit 5 */
9161 #define UCADDMASK4 (0x0010) /* I2C Address Mask Bit 4 */
9162 #define UCADDMASK3 (0x0008) /* I2C Address Mask Bit 3 */
9163 #define UCADDMASK2 (0x0004) /* I2C Address Mask Bit 2 */
9164 #define UCADDMASK1 (0x0002) /* I2C Address Mask Bit 1 */
9165 #define UCADDMASK0 (0x0001) /* I2C Address Mask Bit 0 */
9166 
9167 /* UCBxADDMASK Control Bits */
9168 #define UCADDMASK7_L (0x0080) /* I2C Address Mask Bit 7 */
9169 #define UCADDMASK6_L (0x0040) /* I2C Address Mask Bit 6 */
9170 #define UCADDMASK5_L (0x0020) /* I2C Address Mask Bit 5 */
9171 #define UCADDMASK4_L (0x0010) /* I2C Address Mask Bit 4 */
9172 #define UCADDMASK3_L (0x0008) /* I2C Address Mask Bit 3 */
9173 #define UCADDMASK2_L (0x0004) /* I2C Address Mask Bit 2 */
9174 #define UCADDMASK1_L (0x0002) /* I2C Address Mask Bit 1 */
9175 #define UCADDMASK0_L (0x0001) /* I2C Address Mask Bit 0 */
9176 
9177 /* UCBxADDMASK Control Bits */
9178 #define UCADDMASK9_H (0x0002) /* I2C Address Mask Bit 9 */
9179 #define UCADDMASK8_H (0x0001) /* I2C Address Mask Bit 8 */
9180 
9181 /* UCBxI2CSA Control Bits */
9182 #define UCSA9 (0x0200) /* I2C Slave Address Bit 9 */
9183 #define UCSA8 (0x0100) /* I2C Slave Address Bit 8 */
9184 #define UCSA7 (0x0080) /* I2C Slave Address Bit 7 */
9185 #define UCSA6 (0x0040) /* I2C Slave Address Bit 6 */
9186 #define UCSA5 (0x0020) /* I2C Slave Address Bit 5 */
9187 #define UCSA4 (0x0010) /* I2C Slave Address Bit 4 */
9188 #define UCSA3 (0x0008) /* I2C Slave Address Bit 3 */
9189 #define UCSA2 (0x0004) /* I2C Slave Address Bit 2 */
9190 #define UCSA1 (0x0002) /* I2C Slave Address Bit 1 */
9191 #define UCSA0 (0x0001) /* I2C Slave Address Bit 0 */
9192 
9193 /* UCBxI2CSA Control Bits */
9194 #define UCSA7_L (0x0080) /* I2C Slave Address Bit 7 */
9195 #define UCSA6_L (0x0040) /* I2C Slave Address Bit 6 */
9196 #define UCSA5_L (0x0020) /* I2C Slave Address Bit 5 */
9197 #define UCSA4_L (0x0010) /* I2C Slave Address Bit 4 */
9198 #define UCSA3_L (0x0008) /* I2C Slave Address Bit 3 */
9199 #define UCSA2_L (0x0004) /* I2C Slave Address Bit 2 */
9200 #define UCSA1_L (0x0002) /* I2C Slave Address Bit 1 */
9201 #define UCSA0_L (0x0001) /* I2C Slave Address Bit 0 */
9202 
9203 /* UCBxI2CSA Control Bits */
9204 #define UCSA9_H (0x0002) /* I2C Slave Address Bit 9 */
9205 #define UCSA8_H (0x0001) /* I2C Slave Address Bit 8 */
9206 
9207 /* UCAxIE UART Control Bits */
9208 #define UCTXCPTIE (0x0008) /* UART Transmit Complete Interrupt Enable */
9209 #define UCSTTIE (0x0004) /* UART Start Bit Interrupt Enalble */
9210 #define UCTXIE (0x0002) /* UART Transmit Interrupt Enable */
9211 #define UCRXIE (0x0001) /* UART Receive Interrupt Enable */
9212 
9213 /* UCAxIE/UCBxIE SPI Control Bits */
9214 
9215 /* UCBxIE I2C Control Bits */
9216 #define UCBIT9IE (0x4000) /* I2C Bit 9 Position Interrupt Enable 3 */
9217 #define UCTXIE3 (0x2000) /* I2C Transmit Interrupt Enable 3 */
9218 #define UCRXIE3 (0x1000) /* I2C Receive Interrupt Enable 3 */
9219 #define UCTXIE2 (0x0800) /* I2C Transmit Interrupt Enable 2 */
9220 #define UCRXIE2 (0x0400) /* I2C Receive Interrupt Enable 2 */
9221 #define UCTXIE1 (0x0200) /* I2C Transmit Interrupt Enable 1 */
9222 #define UCRXIE1 (0x0100) /* I2C Receive Interrupt Enable 1 */
9223 #define UCCLTOIE (0x0080) /* I2C Clock Low Timeout interrupt enable */
9224 #define UCBCNTIE (0x0040) /* I2C Automatic stop assertion interrupt enable */
9225 #define UCNACKIE (0x0020) /* I2C NACK Condition interrupt enable */
9226 #define UCALIE (0x0010) /* I2C Arbitration Lost interrupt enable */
9227 #define UCSTPIE (0x0008) /* I2C STOP Condition interrupt enable */
9228 #define UCSTTIE (0x0004) /* I2C START Condition interrupt enable */
9229 #define UCTXIE0 (0x0002) /* I2C Transmit Interrupt Enable 0 */
9230 #define UCRXIE0 (0x0001) /* I2C Receive Interrupt Enable 0 */
9231 
9232 /* UCAxIFG UART Control Bits */
9233 #define UCTXCPTIFG (0x0008) /* UART Transmit Complete Interrupt Flag */
9234 #define UCSTTIFG (0x0004) /* UART Start Bit Interrupt Flag */
9235 #define UCTXIFG (0x0002) /* UART Transmit Interrupt Flag */
9236 #define UCRXIFG (0x0001) /* UART Receive Interrupt Flag */
9237 
9238 /* UCAxIFG/UCBxIFG SPI Control Bits */
9239 #define UCTXIFG (0x0002) /* SPI Transmit Interrupt Flag */
9240 #define UCRXIFG (0x0001) /* SPI Receive Interrupt Flag */
9241 
9242 /* UCBxIFG Control Bits */
9243 #define UCBIT9IFG (0x4000) /* I2C Bit 9 Possition Interrupt Flag 3 */
9244 #define UCTXIFG3 (0x2000) /* I2C Transmit Interrupt Flag 3 */
9245 #define UCRXIFG3 (0x1000) /* I2C Receive Interrupt Flag 3 */
9246 #define UCTXIFG2 (0x0800) /* I2C Transmit Interrupt Flag 2 */
9247 #define UCRXIFG2 (0x0400) /* I2C Receive Interrupt Flag 2 */
9248 #define UCTXIFG1 (0x0200) /* I2C Transmit Interrupt Flag 1 */
9249 #define UCRXIFG1 (0x0100) /* I2C Receive Interrupt Flag 1 */
9250 #define UCCLTOIFG (0x0080) /* I2C Clock low Timeout interrupt Flag */
9251 #define UCBCNTIFG (0x0040) /* I2C Byte counter interrupt flag */
9252 #define UCNACKIFG (0x0020) /* I2C NACK Condition interrupt Flag */
9253 #define UCALIFG (0x0010) /* I2C Arbitration Lost interrupt Flag */
9254 #define UCSTPIFG (0x0008) /* I2C STOP Condition interrupt Flag */
9255 #define UCSTTIFG (0x0004) /* I2C START Condition interrupt Flag */
9256 #define UCTXIFG0 (0x0002) /* I2C Transmit Interrupt Flag 0 */
9257 #define UCRXIFG0 (0x0001) /* I2C Receive Interrupt Flag 0 */
9258 
9259 /* USCI UART Definitions */
9260 #define USCI_NONE (0x0000) /* No Interrupt pending */
9261 #define USCI_UART_UCRXIFG (0x0002) /* USCI UCRXIFG */
9262 #define USCI_UART_UCTXIFG (0x0004) /* USCI UCTXIFG */
9263 #define USCI_UART_UCSTTIFG (0x0006) /* USCI UCSTTIFG */
9264 #define USCI_UART_UCTXCPTIFG (0x0008) /* USCI UCTXCPTIFG */
9265 
9266 /* USCI SPI Definitions */
9267 #define USCI_SPI_UCRXIFG (0x0002) /* USCI UCRXIFG */
9268 #define USCI_SPI_UCTXIFG (0x0004) /* USCI UCTXIFG */
9269 
9270 /* USCI I2C Definitions */
9271 #define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */
9272 #define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */
9273 #define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/
9274 #define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/
9275 #define USCI_I2C_UCRXIFG3 (0x000A) /* USCI I2C Mode: UCRXIFG3 */
9276 #define USCI_I2C_UCTXIFG3 (0x000C) /* USCI I2C Mode: UCTXIFG3 */
9277 #define USCI_I2C_UCRXIFG2 (0x000E) /* USCI I2C Mode: UCRXIFG2 */
9278 #define USCI_I2C_UCTXIFG2 (0x0010) /* USCI I2C Mode: UCTXIFG2 */
9279 #define USCI_I2C_UCRXIFG1 (0x0012) /* USCI I2C Mode: UCRXIFG1 */
9280 #define USCI_I2C_UCTXIFG1 (0x0014) /* USCI I2C Mode: UCTXIFG1 */
9281 #define USCI_I2C_UCRXIFG0 (0x0016) /* USCI I2C Mode: UCRXIFG0 */
9282 #define USCI_I2C_UCTXIFG0 (0x0018) /* USCI I2C Mode: UCTXIFG0 */
9283 #define USCI_I2C_UCBCNTIFG (0x001A) /* USCI I2C Mode: UCBCNTIFG */
9284 #define USCI_I2C_UCCLTOIFG (0x001C) /* USCI I2C Mode: UCCLTOIFG */
9285 #define USCI_I2C_UCBIT9IFG (0x001E) /* USCI I2C Mode: UCBIT9IFG */
9286 
9287 #endif
9288 /************************************************************
9289 * WATCHDOG TIMER A
9290 ************************************************************/
9291 #ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */
9292 
9293 #define OFS_WDTCTL (0x000C) /* Watchdog Timer Control */
9294 #define OFS_WDTCTL_L OFS_WDTCTL
9295 #define OFS_WDTCTL_H OFS_WDTCTL+1
9296 /* The bit names have been prefixed with "WDT" */
9297 /* WDTCTL Control Bits */
9298 #define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */
9299 #define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */
9300 #define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */
9301 #define WDTCNTCL (0x0008) /* WDT - Timer Clear */
9302 #define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */
9303 #define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */
9304 #define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */
9305 #define WDTHOLD (0x0080) /* WDT - Timer hold */
9306 
9307 /* WDTCTL Control Bits */
9308 #define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */
9309 #define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */
9310 #define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */
9311 #define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */
9312 #define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */
9313 #define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */
9314 #define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */
9315 #define WDTHOLD_L (0x0080) /* WDT - Timer hold */
9316 
9317 #define WDTPW (0x5A00)
9318 
9319 #define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */
9320 #define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */
9321 #define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
9322 #define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */
9323 #define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */
9324 #define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
9325 #define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
9326 #define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
9327 #define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */
9328 #define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */
9329 #define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
9330 #define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */
9331 #define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */
9332 #define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
9333 #define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
9334 #define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
9335 
9336 #define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
9337 #define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
9338 #define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
9339 #define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */
9340 #define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
9341 #define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
9342 #define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
9343 
9344 /* WDT-interval times [1ms] coded with Bits 0-2 */
9345 /* WDT is clocked by fSMCLK (assumed 1MHz) */
9346 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
9347 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
9348 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
9349 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
9350 /* WDT is clocked by fACLK (assumed 32KHz) */
9351 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
9352 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
9353 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
9354 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
9355 /* Watchdog mode -> reset after expired time */
9356 /* WDT is clocked by fSMCLK (assumed 1MHz) */
9357 #define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
9358 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
9359 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
9360 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
9361 /* WDT is clocked by fACLK (assumed 32KHz) */
9362 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
9363 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
9364 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
9365 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */
9366 
9367 #endif
9368 
9369 /************************************************************
9370 * TLV Descriptors
9371 ************************************************************/
9372 #define __MSP430_HAS_TLV__ /* Definition to show that Module is available */
9373 #define TLV_BASE __MSP430_BASEADDRESS_TLV__
9374 
9375 #define TLV_START (0x1A08) /* Start Address of the TLV structure */
9376 #define TLV_END (0x1AFF) /* End Address of the TLV structure */
9377 
9378 #define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */
9379 #define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
9380 #define TLV_Reserved3 (0x03) /* Future usage */
9381 #define TLV_Reserved4 (0x04) /* Future usage */
9382 #define TLV_BLANK (0x05) /* Blank descriptor */
9383 #define TLV_Reserved6 (0x06) /* Future usage */
9384 #define TLV_Reserved7 (0x07) /* Serial Number */
9385 #define TLV_DIERECORD (0x08) /* Die Record */
9386 #define TLV_ADCCAL (0x11) /* ADC12 calibration */
9387 #define TLV_ADC12CAL (0x11) /* ADC12 calibration */
9388 #define TLV_REFCAL (0x12) /* REF calibration */
9389 #define TLV_ADC10CAL (0x13) /* ADC10 calibration */
9390 #define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */
9391 #define TLV_TAGEXT (0xFE) /* Tag extender */
9392 #define TLV_TAGEND (0xFF) /* Tag End of Table */
9393 
9394 /************************************************************
9395 * Interrupt Vectors (offset from 0xFF80)
9396 ************************************************************/
9397 
9398 #pragma diag_suppress 1107
9399 #define VECTOR_NAME(name) name##_ptr
9400 #define EMIT_PRAGMA(x) _Pragma(#x)
9401 #define CREATE_VECTOR(name) void * const VECTOR_NAME(name) = (void *)(long)&name
9402 #define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
9403 #define PLACE_INTERRUPT(func) EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
9404 #define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
9405  PLACE_VECTOR(VECTOR_NAME(func), offset) \
9406  PLACE_INTERRUPT(func)
9407 
9408 
9409 /************************************************************
9410 * End of Modules
9411 ************************************************************/
9412 
9413 #ifdef __cplusplus
9414 }
9415 #endif /* extern "C" */
9416 
9417 #endif /* #ifndef __msp430F5XX_F6XXGENERIC */
9418 
__SFR_FARPTR
void(* __SFR_FARPTR)()
Definition: CCS/msp430f5xx_6xxgeneric.h:67
Copyright 2013, Texas Instruments Incorporated