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MSPM0C110X Driver Library
2.05.00.05
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Direct Memory Access (DMA) Driver Library.
#include <stdbool.h>#include <stdint.h>#include <ti/devices/msp/msp.h>#include <ti/driverlib/dl_common.h>
Go to the source code of this file.
Data Structures | |
| struct | DL_DMA_Config |
| Configuration struct for DL_DMA_initChannel. More... | |
Macros | |
| #define | DL_DMA_INTERRUPT_CHANNEL0 (DMA_CPU_INT_IMASK_DMACH0_SET) |
| DMA channel 0 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL1 (DMA_CPU_INT_IMASK_DMACH1_SET) |
| DMA channel 1 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL2 (DMA_CPU_INT_IMASK_DMACH2_SET) |
| DMA channel 2 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL3 (DMA_CPU_INT_IMASK_DMACH3_SET) |
| DMA channel 3 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL4 (DMA_CPU_INT_IMASK_DMACH4_SET) |
| DMA channel 4 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL5 (DMA_CPU_INT_IMASK_DMACH5_SET) |
| DMA channel 5 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL6 (DMA_CPU_INT_IMASK_DMACH6_SET) |
| DMA channel 6 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL7 (DMA_CPU_INT_IMASK_DMACH7_SET) |
| DMA channel 7 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL8 (DMA_CPU_INT_IMASK_DMACH8_SET) |
| DMA channel 8 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL9 (DMA_CPU_INT_IMASK_DMACH9_SET) |
| DMA channel 9 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL10 (DMA_CPU_INT_IMASK_DMACH10_SET) |
| DMA channel 10 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL12 (DMA_CPU_INT_IMASK_DMACH12_SET) |
| DMA channel 12 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL13 (DMA_CPU_INT_IMASK_DMACH13_SET) |
| DMA channel 13 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL14 (DMA_CPU_INT_IMASK_DMACH14_SET) |
| DMA channel 14 interrupt. | |
| #define | DL_DMA_INTERRUPT_CHANNEL15 (DMA_CPU_INT_IMASK_DMACH15_SET) |
| DMA channel 15 interrupt. | |
| #define | DL_DMA_INTERRUPT_ADDR_ERROR (DMA_CPU_INT_IMASK_ADDRERR_SET) |
| DMA address error, source address not reachable. | |
| #define | DL_DMA_INTERRUPT_DATA_ERROR (DMA_CPU_INT_IMASK_DATAERR_SET) |
| DMA data error, source data might be corrupted (PAR or ECC error) | |
| #define | DL_DMA_EVENT_CHANNEL0 (DMA_GEN_EVENT_IMASK_DMACH0_SET) |
| DMA channel 0 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL1 (DMA_GEN_EVENT_IMASK_DMACH1_SET) |
| DMA channel 1 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL2 (DMA_GEN_EVENT_IMASK_DMACH2_SET) |
| DMA channel 2 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL3 (DMA_GEN_EVENT_IMASK_DMACH3_SET) |
| DMA channel 3 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL4 (DMA_GEN_EVENT_IMASK_DMACH4_SET) |
| DMA channel 4 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL5 (DMA_GEN_EVENT_IMASK_DMACH5_SET) |
| DMA channel 5 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL6 (DMA_GEN_EVENT_IMASK_DMACH6_SET) |
| DMA channel 6 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL7 (DMA_GEN_EVENT_IMASK_DMACH7_SET) |
| DMA channel 7 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL8 (DMA_GEN_EVENT_IMASK_DMACH8_SET) |
| DMA channel 8 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL9 (DMA_GEN_EVENT_IMASK_DMACH9_SET) |
| DMA channel 9 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL10 (DMA_GEN_EVENT_IMASK_DMACH10_SET) |
| DMA channel 10 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL12 (DMA_GEN_EVENT_IMASK_DMACH12_SET) |
| DMA channel 12 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL13 (DMA_GEN_EVENT_IMASK_DMACH13_SET) |
| DMA channel 13 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL14 (DMA_GEN_EVENT_IMASK_DMACH14_SET) |
| DMA channel 14 interrupt. | |
| #define | DL_DMA_EVENT_CHANNEL15 (DMA_GEN_EVENT_IMASK_DMACH15_SET) |
| DMA channel 15 interrupt. | |
| #define | DL_DMA_EVENT_ADDR_ERROR (DMA_GEN_EVENT_IMASK_ADDRERR_SET) |
| DMA address error, source address not reachable. | |
| #define | DL_DMA_EVENT_DATA_ERROR (DMA_GEN_EVENT_IMASK_DATAERR_SET) |
| DMA data error, source data might be corrupted (PAR or ECC error) | |
Enumerations | |
| enum | DL_DMA_TRANSFER_MODE { DL_DMA_SINGLE_TRANSFER_MODE = DMA_DMACTL_DMATM_SINGLE, DL_DMA_SINGLE_BLOCK_TRANSFER_MODE = DMA_DMACTL_DMATM_BLOCK } |
| enum | DL_DMA_EXTENDED_MODE { DL_DMA_NORMAL_MODE = DMA_DMACTL_DMAEM_NORMAL } |
| enum | DL_DMA_INCREMENT { DL_DMA_ADDR_UNCHANGED = DMA_DMACTL_DMASRCINCR_UNCHANGED, DL_DMA_ADDR_DECREMENT = DMA_DMACTL_DMASRCINCR_DECREMENT, DL_DMA_ADDR_INCREMENT = DMA_DMACTL_DMASRCINCR_INCREMENT, DL_DMA_ADDR_STRIDE_2 = DMA_DMACTL_DMASRCINCR_STRIDE_2, DL_DMA_ADDR_STRIDE_3 = DMA_DMACTL_DMASRCINCR_STRIDE_3, DL_DMA_ADDR_STRIDE_4 = DMA_DMACTL_DMASRCINCR_STRIDE_4, DL_DMA_ADDR_STRIDE_5 = DMA_DMACTL_DMASRCINCR_STRIDE_5, DL_DMA_ADDR_STRIDE_6 = DMA_DMACTL_DMASRCINCR_STRIDE_6, DL_DMA_ADDR_STRIDE_7 = DMA_DMACTL_DMASRCINCR_STRIDE_7, DL_DMA_ADDR_STRIDE_8 = DMA_DMACTL_DMASRCINCR_STRIDE_8, DL_DMA_ADDR_STRIDE_9 = DMA_DMACTL_DMASRCINCR_STRIDE_9 } |
| enum | DL_DMA_EARLY_INTERRUPT_THRESHOLD { DL_DMA_EARLY_INTERRUPT_THRESHOLD_DISABLED = DMA_DMACTL_DMAPREIRQ_PREIRQ_DISABLE, DL_DMA_EARLY_INTERRUPT_THRESHOLD_1 = DMA_DMACTL_DMAPREIRQ_PREIRQ_1, DL_DMA_EARLY_INTERRUPT_THRESHOLD_2 = DMA_DMACTL_DMAPREIRQ_PREIRQ_2, DL_DMA_EARLY_INTERRUPT_THRESHOLD_4 = DMA_DMACTL_DMAPREIRQ_PREIRQ_4, DL_DMA_EARLY_INTERRUPT_THRESHOLD_8 = DMA_DMACTL_DMAPREIRQ_PREIRQ_8, DL_DMA_EARLY_INTERRUPT_THRESHOLD_32 = DMA_DMACTL_DMAPREIRQ_PREIRQ_32, DL_DMA_EARLY_INTERRUPT_THRESHOLD_64 = DMA_DMACTL_DMAPREIRQ_PREIRQ_64, DL_DMA_EARLY_INTERRUPT_THRESHOLD_HALF = DMA_DMACTL_DMAPREIRQ_PREIRQ_HALF } |
| enum | DL_DMA_BURST_SIZE { DL_DMA_BURST_SIZE_INFINITY = DMA_DMAPRIO_BURSTSZ_INFINITI, DL_DMA_BURST_SIZE_8 = DMA_DMAPRIO_BURSTSZ_BURST_8, DL_DMA_BURST_SIZE_16 = DMA_DMAPRIO_BURSTSZ_BUSRT_16, DL_DMA_BURST_SIZE_32 = DMA_DMAPRIO_BURSTSZ_BURST_32 } |
| enum | DL_DMA_TRIGGER_TYPE { DL_DMA_TRIGGER_TYPE_INTERNAL = DMA_DMATCTL_DMATINT_INTERNAL, DL_DMA_TRIGGER_TYPE_EXTERNAL = DMA_DMATCTL_DMATINT_EXTERNAL } |
| enum | DL_DMA_WIDTH { DL_DMA_WIDTH_BYTE = DMA_DMACTL_DMASRCWDTH_BYTE, DL_DMA_WIDTH_HALF_WORD = DMA_DMACTL_DMASRCWDTH_HALF, DL_DMA_WIDTH_WORD = DMA_DMACTL_DMASRCWDTH_WORD, DL_DMA_WIDTH_LONG = DMA_DMACTL_DMASRCWDTH_LONG } |
| enum | DL_DMA_EVENT_IIDX { DL_DMA_EVENT_IIDX_NO_INTR = DMA_GEN_EVENT_IIDX_STAT_NO_INTR, DL_DMA_EVENT_IIDX_DMACH0 = DMA_GEN_EVENT_IIDX_STAT_DMACH0, DL_DMA_EVENT_IIDX_DMACH1 = DMA_GEN_EVENT_IIDX_STAT_DMACH1, DL_DMA_EVENT_IIDX_DMACH2 = DMA_GEN_EVENT_IIDX_STAT_DMACH2, DL_DMA_EVENT_IIDX_DMACH3 = DMA_GEN_EVENT_IIDX_STAT_DMACH3, DL_DMA_EVENT_IIDX_DMACH4 = DMA_GEN_EVENT_IIDX_STAT_DMACH4, DL_DMA_EVENT_IIDX_DMACH5 = DMA_GEN_EVENT_IIDX_STAT_DMACH5, DL_DMA_EVENT_IIDX_DMACH6 = DMA_GEN_EVENT_IIDX_STAT_DMACH6, DL_DMA_EVENT_IIDX_DMACH7 = DMA_GEN_EVENT_IIDX_STAT_DMACH7, DL_DMA_EVENT_IIDX_DMACH8 = DMA_GEN_EVENT_IIDX_STAT_DMACH8, DL_DMA_EVENT_IIDX_DMACH9 = DMA_GEN_EVENT_IIDX_STAT_DMACH9, DL_DMA_EVENT_IIDX_DMACH10 = DMA_GEN_EVENT_IIDX_STAT_DMACH10, DL_DMA_EVENT_IIDX_DMACH11 = DMA_GEN_EVENT_IIDX_STAT_DMACH11, DL_DMA_EVENT_IIDX_DMACH12 = DMA_GEN_EVENT_IIDX_STAT_DMACH12, DL_DMA_EVENT_IIDX_DMACH13 = DMA_GEN_EVENT_IIDX_STAT_DMACH13, DL_DMA_EVENT_IIDX_DMACH14 = DMA_GEN_EVENT_IIDX_STAT_DMACH14, DL_DMA_EVENT_IIDX_DMACH15 = DMA_GEN_EVENT_IIDX_STAT_DMACH15, DL_DMA_EVENT_IIDX_ADDR_ERROR = DMA_GEN_EVENT_IIDX_STAT_ADDRERR, DL_DMA_EVENT_IIDX_DATA_ERROR = DMA_GEN_EVENT_IIDX_STAT_DATAERR } |
| enum | DL_DMA_PUBLISHER_INDEX { DL_DMA_PUBLISHER_INDEX_0 = 0 } |
| enum | DL_DMA_SUBSCRIBER_INDEX { DL_DMA_SUBSCRIBER_INDEX_0 = 0, DL_DMA_SUBSCRIBER_INDEX_1 = 1 } |
| enum | DL_DMA_AUTOEN { DL_DMA_AUTOEN_DISABLE = DMA_DMACTL_DMAAUTOEN_DISABLE } |
Functions | |
| void | DL_DMA_initChannel (DMA_Regs *dma, uint8_t channelNum, const DL_DMA_Config *config) |
| Initialize a DMA channel. More... | |
| __STATIC_INLINE void | DL_DMA_configTransfer (DMA_Regs *dma, uint8_t channelNum, DL_DMA_TRANSFER_MODE transferMode, DL_DMA_EXTENDED_MODE extendedMode, DL_DMA_WIDTH srcWidth, DL_DMA_WIDTH destWidth, DL_DMA_INCREMENT srcIncrement, DL_DMA_INCREMENT destIncrement) |
| Configure a DMA channel for a transfer. More... | |
| __STATIC_INLINE void | DL_DMA_enableRoundRobinPriority (DMA_Regs *dma) |
| Configure the DMA for round-robin priority. More... | |
| __STATIC_INLINE void | DL_DMA_disableRoundRobinPriority (DMA_Regs *dma) |
| Disable round-robin priority for the DMA. More... | |
| __STATIC_INLINE bool | DL_DMA_isRoundRobinPriorityEnabled (const DMA_Regs *dma) |
| Check if round-robin priority is enabled for the DMA. More... | |
| __STATIC_INLINE void | DL_DMA_setBurstSize (DMA_Regs *dma, DL_DMA_BURST_SIZE burstSize) |
| Set the burst size for block transfers. More... | |
| __STATIC_INLINE DL_DMA_BURST_SIZE | DL_DMA_getBurstSize (const DMA_Regs *dma) |
| Get the burst size for block transfers. More... | |
| __STATIC_INLINE void | DL_DMA_enableChannel (DMA_Regs *dma, uint8_t channelNum) |
| Enable a DMA channel for transfers. More... | |
| __STATIC_INLINE void | DL_DMA_disableChannel (DMA_Regs *dma, uint8_t channelNum) |
| Disable a DMA channel for transfers. More... | |
| __STATIC_INLINE bool | DL_DMA_isChannelEnabled (const DMA_Regs *dma, uint8_t channelNum) |
| Check if a DMA channel is enabled for transfers. More... | |
| __STATIC_INLINE void | DL_DMA_configMode (DMA_Regs *dma, uint8_t channelNum, DL_DMA_TRANSFER_MODE transferMode, DL_DMA_EXTENDED_MODE extendedMode) |
| Configure the mode for a DMA channel. More... | |
| __STATIC_INLINE void | DL_DMA_setTransferMode (DMA_Regs *dma, uint8_t channelNum, DL_DMA_TRANSFER_MODE transferMode) |
| Set a DMA channel's transfer mode. More... | |
| __STATIC_INLINE DL_DMA_TRANSFER_MODE | DL_DMA_getTransferMode (const DMA_Regs *dma, uint8_t channelNum) |
| Get a DMA channel's transfer mode. More... | |
| __STATIC_INLINE void | DL_DMA_setExtendedMode (DMA_Regs *dma, uint8_t channelNum, DL_DMA_EXTENDED_MODE extendedMode) |
| Set a DMA channel's extended mode. More... | |
| __STATIC_INLINE DL_DMA_EXTENDED_MODE | DL_DMA_getExtendedMode (const DMA_Regs *dma, uint8_t channelNum) |
| Get a DMA channel's extended mode. More... | |
| __STATIC_INLINE void | DL_DMA_startTransfer (DMA_Regs *dma, uint8_t channelNum) |
| Start a DMA transfer using software. More... | |
| __STATIC_INLINE void | DL_DMA_setTrigger (DMA_Regs *dma, uint8_t channelNum, uint8_t trigger, DL_DMA_TRIGGER_TYPE triggerType) |
| Set a channel's trigger for a DMA transfer. More... | |
| __STATIC_INLINE uint32_t | DL_DMA_getTrigger (const DMA_Regs *dma, uint8_t channelNum) |
| Get the current trigger for a DMA channel. More... | |
| __STATIC_INLINE DL_DMA_TRIGGER_TYPE | DL_DMA_getTriggerType (const DMA_Regs *dma, uint8_t channelNum) |
| Get the current trigger type for a DMA channel. More... | |
| __STATIC_INLINE void | DL_DMA_setSrcAddr (DMA_Regs *dma, uint8_t channelNum, uint32_t srcAddr) |
| Set a DMA channel's source address. More... | |
| __STATIC_INLINE uint32_t | DL_DMA_getSrcAddr (const DMA_Regs *dma, uint8_t channelNum) |
| Get a DMA channel's source address. More... | |
| __STATIC_INLINE void | DL_DMA_setDestAddr (DMA_Regs *dma, uint8_t channelNum, uint32_t destAddr) |
| Set a DMA channel's destination address. More... | |
| __STATIC_INLINE uint32_t | DL_DMA_getDestAddr (const DMA_Regs *dma, uint8_t channelNum) |
| Get a DMA channel's destination address. More... | |
| __STATIC_INLINE void | DL_DMA_setTransferSize (DMA_Regs *dma, uint8_t channelNum, uint16_t size) |
| Set the size of a block for a DMA transfer. More... | |
| __STATIC_INLINE uint16_t | DL_DMA_getTransferSize (const DMA_Regs *dma, uint8_t channelNum) |
| Get a channel's size of block of data for a DMA transfer. More... | |
| __STATIC_INLINE void | DL_DMA_setSrcIncrement (DMA_Regs *dma, uint8_t channelNum, DL_DMA_INCREMENT srcIncrement) |
| Set a channel's source address increment amount. More... | |
| __STATIC_INLINE DL_DMA_INCREMENT | DL_DMA_getSrcIncrement (const DMA_Regs *dma, uint8_t channelNum) |
| Return a channel's source address increment amount. More... | |
| __STATIC_INLINE void | DL_DMA_setDestIncrement (DMA_Regs *dma, uint8_t channelNum, DL_DMA_INCREMENT destIncrement) |
| Set a channel's destination address increment amount. More... | |
| __STATIC_INLINE DL_DMA_INCREMENT | DL_DMA_getDestIncrement (const DMA_Regs *dma, uint8_t channelNum) |
| Return a channel's destination address increment amount. More... | |
| __STATIC_INLINE void | DL_DMA_setSrcWidth (DMA_Regs *dma, uint8_t channelNum, DL_DMA_WIDTH srcWidth) |
| Set the width of the DMA source address for a channel. More... | |
| __STATIC_INLINE DL_DMA_WIDTH | DL_DMA_getSrcWidth (const DMA_Regs *dma, uint8_t channelNum) |
| Get the width of the DMA source address for a channel. More... | |
| __STATIC_INLINE void | DL_DMA_setDestWidth (DMA_Regs *dma, uint8_t channelNum, DL_DMA_WIDTH destWidth) |
| Set the width of the DMA destination address for a channel. More... | |
| __STATIC_INLINE DL_DMA_WIDTH | DL_DMA_getDestWidth (const DMA_Regs *dma, uint8_t channelNum) |
| Get the width of the DMA destination address for a channel. More... | |
| __STATIC_INLINE void | DL_DMA_enableInterrupt (DMA_Regs *dma, uint32_t interruptMask) |
| Enable DMA interrupts. More... | |
| __STATIC_INLINE void | DL_DMA_disableInterrupt (DMA_Regs *dma, uint32_t interruptMask) |
| Disable DMA interrupts. More... | |
| __STATIC_INLINE uint32_t | DL_DMA_getEnabledInterrupts (const DMA_Regs *dma, uint32_t interruptMask) |
| Check which DMA interrupts are enabled. More... | |
| __STATIC_INLINE uint32_t | DL_DMA_getEnabledInterruptStatus (const DMA_Regs *dma, uint32_t interruptMask) |
| Check interrupt flag of enabled DMA interrupts. More... | |
| __STATIC_INLINE uint32_t | DL_DMA_getRawInterruptStatus (const DMA_Regs *dma, uint32_t interruptMask) |
| Check interrupt flag of any DMA interrupt. More... | |
| __STATIC_INLINE DL_DMA_EVENT_IIDX | DL_DMA_getPendingInterrupt (const DMA_Regs *dma) |
| Get highest priority pending DMA interrupt. More... | |
| __STATIC_INLINE void | DL_DMA_clearInterruptStatus (DMA_Regs *dma, uint32_t interruptMask) |
| Clear pending DMA interrupts. More... | |
| __STATIC_INLINE void | DL_DMA_setPublisherChanID (DMA_Regs *dma, DL_DMA_PUBLISHER_INDEX index, uint8_t chanID) |
| Sets the event publisher channel id. More... | |
| __STATIC_INLINE uint8_t | DL_DMA_getPublisherChanID (DMA_Regs *dma, DL_DMA_PUBLISHER_INDEX index) |
| Gets the event publisher channel id. More... | |
| __STATIC_INLINE void | DL_DMA_setSubscriberChanID (DMA_Regs *dma, DL_DMA_SUBSCRIBER_INDEX index, uint8_t chanID) |
| Sets the event subscriber channel id. More... | |
| __STATIC_INLINE uint8_t | DL_DMA_getSubscriberChanID (DMA_Regs *dma, DL_DMA_SUBSCRIBER_INDEX index) |
| Gets the event subscriber channel id. More... | |
| __STATIC_INLINE void | DL_DMA_enableEvent (DMA_Regs *dma, uint32_t eventMask) |
| Enable DMA event. More... | |
| __STATIC_INLINE void | DL_DMA_disableEvent (DMA_Regs *dma, uint32_t eventMask) |
| Disable DMA event. More... | |
| __STATIC_INLINE uint32_t | DL_DMA_getEnabledEvents (const DMA_Regs *dma, uint32_t eventMask) |
| Check which dma events triggers are enabled. More... | |
| __STATIC_INLINE uint32_t | DL_DMA_getEnabledEventStatus (const DMA_Regs *dma, uint32_t eventMask) |
| Check event flag of enabled dma event. More... | |
| __STATIC_INLINE uint32_t | DL_DMA_getRawEventsStatus (const DMA_Regs *dma, uint32_t eventMask) |
| Check event flag of any dma event. More... | |
| __STATIC_INLINE void | DL_DMA_clearEventsStatus (DMA_Regs *dma, uint32_t eventMask) |
| Clear pending dma events. More... | |