MSPM0G3507SensorlessFOCMotorControlLibrary  1.0
drv8316.h
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75 /*!****************************************************************************
76  * @file drv8316.h
77  * @brief DRV8316 gate driver Module
78  *
79  *
80  * @anchor drv8316_h
81  * # Overview
82  *
83  * defines APIs for drv8316 gate driver
84  *
85  * <hr>
86  ******************************************************************************/
87 
88 #ifndef DRV8316_H
89 #define DRV8316_H
90 
91 #include "stdint.h"
92 #include "main.h"
93 #include "appInputCtrlInterface.h"
94 
95 #ifdef __cplusplus
96 extern "C" {
97 #endif
98 
99 #if defined DRV8316 || defined DRV8316_DRIVER
100 
102 #define DRV8316_ADDR_MASK (0x7E00)
103 
105 #define DRV8316_DATA_MASK (0xFF)
106 
108 #define DRV8316_FAULT_FLG 0x01
109 
110 
112 #define DRV8316_ICSTAT0_FAULT_MASK 0x56
113 /* IC_STAT: RESERVED | BK_FLT | RESERVED | OCP | NPOR(UVLO) | OVP | OT | FAULT */
114 
116 #define DRV8316_ICSTAT1_FAULT_MASK 0xFF
117 /* STAT 1 : OTW | OTS | OCP_HC | OCP_LC | OCP_HB | OCP_LB | OCP_HA | OCP_LA */
118 
120 #define DRV8316_ICSTAT2_FAULT_MASK 0x78
121 /* STAT 2 : OTW MCE | OTP_ERR | BUCK_OCP | BUCK_UV | VCP_UV | SPI_PARITY| SPI_SCLK | SPI_ADDR */
122 
124 #define DRV8316_IC_STAT 0x00
125 
126 #define DRV8316_STAT1 0x01
127 
128 #define DRV8316_STAT2 0x02
129 
130 #define DRV8316_CTRL1 0x03
131 
132 #define DRV8316_CTRL2 0x04
133 
134 #define DRV8316_CTRL3 0x05
135 
136 #define DRV8316_CTRL4 0x06
137 
138 #define DRV8316_CTRL5 0x07
139 
140 #define DRV8316_CTRL6 0x08
141 
142 #define DRV8316_CTRL7 0x09
143 
144 #define DRV8316_CTRL8 0x0A
145 
146 #define DRV8316_CTRL9 0x0B
147 
148 #define DRV8316_CTRL10 0x0C
149 
150 #define DRV8316_TESTMODE 0x3F
151 
152 #define DRV8316_TESTCONFIG0 0x10
153 
154 #define DRV8316_TESTCONFIG1 0x11
155 
156 #define DRV8316_TESTCONFIG2 0x12
157 
158 #define DRV8316_TESTCONFIG3 0x13
159 
160 #define DRV8316_TESTCONFIG4 0x14
161 
162 #define DRV8316_TESTCONFIG5 0x15
163 
164 #define DRV8316_TESTCONFIG6 0x16
165 
166 #define DRV8316_TESTCONFIG7 0x17
167 
168 #define DRV8316_TESTCONFIG8 0x18
169 
170 #define DRV8316_TESTCONFIG9 0x19
171 
172 #define DRV8316_TESTCONFIG10 0x1A
173 
174 #define DRV8316_TESTCONFIG11 0x1B
175 
176 #define DRV8316_TESTCONFIG12 0x1C
177 
178 #define DRV8316_TESTCONFIG13 0x1D
179 
180 #define DRV8316_OTPCONFIG1 0x21
181 
182 #define DRV8316_OTPCONFIG2 0x22
183 
184 #define DRV8316_OTPCONFIG3 0x23
185 
186 #define DRV8316_OTPCONFIG4 0x24
187 
188 #define DRV8316_OTPCONFIG5 0x25
189 
190 #define DRV8316_OTPCONFIG6 0x26
191 
192 #define DRV8316_OTPCONFIG13 0x2D
193 
194 #define DRV8316_OTPTEST 0x3A
195 
196 #define DRV8316_CSA_MASK 0x00000003
197 
199 #define DRV8316_CSA_GAIN_POS 0
200 
202 #define DRV8316_OTPTEST_WRITE_PROTECT_MASK 0xDF
203 
204 #define DRV8316_OTPTEST_OTP_RELOAD_POS 5
205 
206 /******************************************************************************/
208 #define GD1_REG2_MASK 0x0C000000
209 
211 #define GD1_REG2_GD_POS 23
212 
214 #define GD1_REG2_DRV_POS 0
215 
217 #define GD1_REG2_WRITE_PROTECT_MASK 0xE7
218 
220 #define DRV8316_REG2_DEFAULT 0x38
221 
222 /******************************************************************************/
224 #define GD1_REG3_MASK 0x000C0000
225 
227 #define GD1_REG3_GD_POS 16
228 
230 #define GD1_REG3_DRV_POS 0
231 
233 #define GD1_REG3_WRITE_PROTECT_MASK 0xF2
234 
236 #define DRV8316_REG3_DEFAULT 0x42
237 
238 /******************************************************************************/
240 #define GD1_REG4_MASK 0x00003F00
241 
243 #define GD1_REG4_GD_POS 8
244 
246 #define GD1_REG4_DRV_POS 0
247 
249 #define GD1_REG4_WRITE_PROTECT_MASK 0xC8
250 
252 #define DRV8316_REG4_DEFAULT 0x08
253 
254 /******************************************************************************/
256 #define GD1_REG5_MASK 0x00000000
257 
259 #define GD1_REG5_GD_POS 0
260 
262 #define GD1_REG5_DRV_POS 0
263 
265 #define GD1_REG5_WRITE_PROTECT_MASK 0xFC
266 
268 #define DRV8316_REG5_DEFAULT 0x00
269 
270 /******************************************************************************/
272 #define GD2_REG6_MASK 0x03F00000
273 
275 #define GD2_REG6_GD_POS 20
276 
278 #define GD2_REG6_DRV_POS 0
279 
281 #define GD2_REG6_WRITE_PROTECT_MASK 0x00
282 
284 #define DRV8316_REG6_DEFAULT 0x00
285 
286 /******************************************************************************/
288 #define GD2_REG10_MASK 0x7C000000
289 
291 #define GD2_REG10_GD_POS 26
292 
294 #define GD2_REG10_DRV_POS 0
295 
297 #define GD2_REG10_WRITE_PROTECT_MASK 0xE0
298 
300 #define DRV8316_REG10_DEFAULT 0x00
301 
302 /******************************************************************************/
304 typedef union
305 {
306  struct drv8316Cfg1
307  {
308  uint32_t
310  csaGain: 2,
312  enASR: 1,
314  enAAR: 1,
316  reserved1: 1,
318  reserved2: 1,
320  IlimRecir: 1,
322  bemfThr: 1,
324  ocpMode: 2,
326  ocpLvl: 1,
328  ocpRetry: 1,
330  cbcDeg: 2,
332  ocpCBC: 1,
334  drvOff: 1,
336  otwRep: 1,
338  reserved3: 1,
340  ovpEn: 1,
342  ovpSel: 1,
344  pwm100DutySel: 1,
346  disRR: 1,
348  halfRR: 1,
350  clrFLT: 1,
352  pwmMode: 2,
354  slewRate: 2,
356  reserved: 4;
357  }b;
358  uint32_t w;
359 }GATE_DRIVE_DRV8316_CFG1_T;
360 
362 typedef union
363 {
364  struct drv8316Cfg2
365  {
366  uint32_t
368  reserved: 17,
370  minOnTime: 3,
372  buckDis: 1,
374  buckSel: 2,
376  buckCl: 1,
378  buckPsDis: 1,
380  buckSr: 1,
382  targetDelay: 4,
384  delayCompEn: 1,
386  reserved1: 1;
387  }b;
388  uint32_t w;
389 }GATE_DRIVE_DRV8316_CFG2_T;
390 
391 /*
392 typedef struct hvDie8316Interface
393 {
395  GATE_DRIVE_DRV8316_CFG1_T gateDrvCfg1;
397  GATE_DRIVE_DRV8316_CFG2_T gateDrvCfg2;
398 } HV_DIE_EEPROM_INTERFACE_T;
399 
400 extern HV_DIE_EEPROM_INTERFACE_T *pGateDriverConfig;
401 
402 void drv8316ParamsInit(void);
403 
408 uint32_t drv8316FaultStatusRead(void);
409 
414 uint32_t drv8316FaultBitRead(void);
415 
419 void drv8316TestModeEntry(void);
420 
421 #endif
422 
423 #ifdef __cplusplus
424 }
425 #endif
426 #endif /* DRV8316_H */
appInputCtrlInterface.h
Application Defines Module.
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