MSPM0C1106HallSensoredTrapMotorControlLibrary  1.0
Data Structures | Macros | Enumerations | Functions
drv8316.h File Reference

Detailed Description

DRV8316_MODULE Module.

Overview

API's releated to DRV8316

#include "hal.h"
Include dependency graph for drv8316.h:

Go to the source code of this file.

Data Structures

struct  DRV8316_Instance
 Defines DRV8316 instance. More...
 

Macros

#define DRV8316_ADDR_MASK   (0x7E00)
 Defines the address mask.
 
#define DRV8316_DATA_MASK   (0x00FF)
 Defines the data mask.
 
#define DRV8316_DATA_TRANSMIT_TO_READ   (0x00)
 Defines the data transmitted while reading a register.
 
#define DRV8316_INITIAL_PARITY   (0x00)
 Defines the initial parity of command word.
 
#define DRV8316_PARITY_CHECK   (0x01)
 Defines the parity checking bit.
 
#define DRV8316_RIGHT_SHIFT_REGISTER   (1)
 Defines the number of bits right shifted.
 
#define DRV8316_PARITY_BIT_POSITION   (8)
 Defines the position of the parity in command word.
 
#define DRV8316_ADDR_BIT_POSITION   (9)
 Defines the position of the parity in command word.
 
#define DRV8316_SPICMD_BIT_POSITION   (15)
 Defines the position of the parity in command word.
 
#define DRV8316_CLEAR_BIT_MASK   (0x01)
 Defines the claer bit mask.
 
#define DRV8316_MAXIMUM_RESET_TIME   (40)
 Defines the time to clear the nSLEEP pin to reset faults.
 
#define DRV8316_MAXIMUM_WAKEUP_TIME   (2000)
 Defines the time to wakeup the drv after reset.
 
#define DRV8316_VOLTAGE_CONV_CONST   _IQ20(13.417)
 Defines voltage conversion constant.
 
#define DRV8316_CSA_REF_VOLTAGE   (3000)
 Defines CSA reference voltage.
 
#define DRV8316_CSAGAIN_0P15VA_IQ   _IQ20(0.15)
 Defines CSA gains 0.15 in IQ20.
 
#define DRV8316_CSAGAIN_0P3VA_IQ   _IQ20(0.3)
 Defines CSA gains 0.3 in IQ20.
 
#define DRV8316_CSAGAIN_0P6VA_IQ   _IQ20(0.6)
 Defines CSA gains 0.6 in IQ20.
 
#define DRV8316_CSAGAIN_1P2VA_IQ   _IQ20(1.2)
 Defines CSA gains 1.2 in IQ20.
 

Enumerations

enum  DRV8316_CTRL01_MASK { DRV8316_CTRL01_MASK_REG_LOCK = 0x07 << 0 }
 
enum  DRV8316_CTRL02_MASK {
  DRV8316_CTRL02_MASK_CLR_FLT = 0x01 << 0,
  DRV8316_CTRL02_MASK_PWM_MODE = 0x03 << 1,
  DRV8316_CTRL02_MASK_SLEW = 0x03 << 3,
  DRV8316_CTRL02_MASK_SDO_MODE = 0x01 << 5
}
 
enum  DRV8316_CTRL03_MASK {
  DRV8316_CTRL03_MASK_OTW_REP = 0x01 << 0,
  DRV8316_CTRL03_MASK_OVP_EN = 0x01 << 2,
  DRV8316_CTRL03_MASK_OVP_SEL = 0x01 << 3,
  DRV8316_CTRL03_MASK_PWM_100_DUTY_SEL = 0x01 << 4
}
 
enum  DRV8316_CTRL04_MASK {
  DRV8316_CTRL04_MASK_OCP_MODE = 0x03 << 0,
  DRV8316_CTRL04_MASK_OCP_LVL = 0x01 << 2,
  DRV8316_CTRL04_MASK_OCP_RETRY = 0x01 << 3,
  DRV8316_CTRL04_MASK_OCP_DEG = 0x03 << 4,
  DRV8316_CTRL04_MASK_OCP_CBC = 0x01 << 6,
  DRV8316_CTRL04_MASK_DRV_OFF = 0x01 << 7
}
 
enum  DRV8316_CTRL05_MASK {
  DRV8316_CTRL05_MASK_CSA_GAIN = 0x03 << 0,
  DRV8316_CTRL05_MASK_EN_ASR = 0x01 << 2,
  DRV8316_CTRL05_MASK_EN_AAR = 0x01 << 3,
  DRV8316_CTRL05_MASK_ILIM_RECIR = 0x01 << 6
}
 
enum  DRV8316_CTRL06_MASK {
  DRV8316_CTRL06_MASK_BUCK_DIS = 0x01 << 0,
  DRV8316_CTRL06_MASK_BUCK_SEL = 0x03 << 1,
  DRV8316_CTRL06_MASK_BUCK_CL = 0x01 << 3,
  DRV8316_CTRL06_MASK_BUCK_PS_DIS = 0x01 << 4
}
 
enum  DRV8316_CTRL10_MASK {
  DRV8316_CTRL10_MASK_DLY_TARGET = 0x0F << 0,
  DRV8316_CTRL10_MASK_DLYCMP_EN = 0x01 << 4
}
 
enum  DRV8316_CTRL01 {
  DRV8316_CTRL01_REG_UNLOCK = 0x03 << 0,
  DRV8316_CTRL01_REG_LOCK = 0x06 << 0
}
 
enum  DRV8316_CTRL02 {
  DRV8316_CTRL02_CLR_FLT = 0x01 << 0,
  DRV8316_CTRL02_PWMMODE_6x = 0x00 << 1,
  DRV8316_CTRL02_PWMMODE_6x_CL = 0x01 << 1,
  DRV8316_CTRL02_PWMMODE_3x = 0x02 << 1,
  DRV8316_CTRL02_PWMMODE_3x_CL = 0x03 << 1,
  DRV8316_CTRL02_SLEWRATE_25 = 0x00 << 3,
  DRV8316_CTRL02_SLEWRATE_50 = 0x01 << 3,
  DRV8316_CTRL02_SLEWRATE_125 = 0x02 << 3,
  DRV8316_CTRL02_SLEWRATE_200 = 0x03 << 3,
  DRV8316_CTRL02_SDO_OPEN_DRAIN_MODE = 0x00 << 5,
  DRV8316_CTRL02_SDO_PUSH_PULL_MODE = 0x01 << 5
}
 
enum  DRV8316_CTRL03 {
  DRV8316_CTRL03_OTW_REP_DISABLE = 0x00 << 0,
  DRV8316_CTRL03_OTW_REP_ENABLE = 0x01 << 0,
  DRV8316_CTRL03_OVP_DISABLE = 0x00 << 2,
  DRV8316_CTRL03_OVP_ENABLE = 0x01 << 2,
  DRV8316_CTRL03_OVP_SEL_34V = 0x00 << 3,
  DRV8316_CTRL03_OVP_SEL_22V = 0x01 << 3,
  DRV8316_CTRL03_PWM_20KHZ = 0x00 << 4,
  DRV8316_CTRL03_PWM_40KHZ = 0x01 << 4
}
 
enum  DRV8316_CTRL04 {
  DRV8316_CTRL04_OCP_LATCHED = 0x00 << 0,
  DRV8316_CTRL04_OCP_AUTO_RETRY = 0x01 << 0,
  DRV8316_CTRL04_OCP_REPORT = 0x02 << 0,
  DRV8316_CTRL04_OCP_DISABLE = 0x03 << 0,
  DRV8316_CTRL04_OCP_LVL_16A = 0x00 << 2,
  DRV8316_CTRL04_OCP_LVL_24A = 0x01 << 2,
  DRV8316_CTRL04_OCP_RETRY_5MS = 0x00 << 3,
  DRV8316_CTRL04_OCP_RETRY_500MS = 0x01 << 3,
  DRV8316_CTRL04_OCP_DEG_0P2US = 0x00 << 4,
  DRV8316_CTRL04_OCP_DEG_0P6US = 0x01 << 4,
  DRV8316_CTRL04_OCP_DEG_1P25US = 0x02 << 4,
  DRV8316_CTRL04_OCP_DEG_1P6US = 0x03 << 4,
  DRV8316_CTRL04_OCP_CBC_DISABLE = 0x00 << 6,
  DRV8316_CTRL04_OCP_CBC_ENABLE = 0x01 << 6,
  DRV8316_CTRL04_DRV_OFF_NO_ACTION = 0x00 << 7,
  DRV8316_CTRL04_DRV_OFF_LOW_POWER_MODE = 0x01 << 7
}
 
enum  DRV8316_CTRL05 {
  DRV8316_CTRL05_CSA_GAIN_0P15VA = 0x00 << 0,
  DRV8316_CTRL05_CSA_GAIN_0P3VA = 0x01 << 0,
  DRV8316_CTRL05_CSA_GAIN_0P6VA = 0x02 << 0,
  DRV8316_CTRL05_CSA_GAIN_1P2VA = 0x03 << 0,
  DRV8316_CTRL05_EN_ASR_DISABLE = 0x00 << 2,
  DRV8316_CTRL05_EN_ASR_ENABLE = 0x01 << 2,
  DRV8316_CTRL05_EN_AAR_DISABLE = 0x00 << 3,
  DRV8316_CTRL05_EN_AAR_ENABLE = 0x01 << 3,
  DRV8316_CTRL05_ILIM_RECIR_BRAKE_MODE = 0x00 << 6,
  DRV8316_CTRL05_ILIM_RECIR_COAST_MODE = 0x01 << 6
}
 
enum  DRV8316_CTRL06 {
  DRV8316_CTRL06_BUCK_DIS_ENABLE = 0x00 << 0,
  DRV8316_CTRL06_BUCK_DIS_DISABLE = 0x01 << 0,
  DRV8316_CTRL06_BUCK_SEL_3P3V = 0x00 << 1,
  DRV8316_CTRL06_BUCK_SEL_5P0V = 0x01 << 1,
  DRV8316_CTRL06_BUCK_SEL_4P0V = 0x02 << 1,
  DRV8316_CTRL06_BUCK_SEL_5P7V = 0x03 << 1,
  DRV8316_CTRL06_BUCK_CL_600MA = 0x00 << 3,
  DRV8316_CTRL06_BUCK_CL_150MA = 0x01 << 3,
  DRV8316_CTRL06_BUCK_PS_DIS_ENABLE = 0x00 << 4,
  DRV8316_CTRL06_BUCK_PS_DIS_DISABLE = 0x01 << 4
}
 
enum  DRV8316_CTRL10 {
  DRV8316_CTRL10_DLY_TARGET_0P0US = 0x00 << 0,
  DRV8316_CTRL10_DLY_TARGET_0P4US = 0x01 << 0,
  DRV8316_CTRL10_DLY_TARGET_0P6US = 0x02 << 0,
  DRV8316_CTRL10_DLY_TARGET_0P8US = 0x03 << 0,
  DRV8316_CTRL10_DLY_TARGET_1P0US = 0x04 << 0,
  DRV8316_CTRL10_DLY_TARGET_1P2US = 0x05 << 0,
  DRV8316_CTRL10_DLY_TARGET_1P4US = 0x06 << 0,
  DRV8316_CTRL10_DLY_TARGET_1P6US = 0x07 << 0,
  DRV8316_CTRL10_DLY_TARGET_1P8US = 0x08 << 0,
  DRV8316_CTRL10_DLY_TARGET_2P0US = 0x09 << 0,
  DRV8316_CTRL10_DLY_TARGET_2P2US = 0x0A << 0,
  DRV8316_CTRL10_DLY_TARGET_2P4US = 0x0B << 0,
  DRV8316_CTRL10_DLY_TARGET_2P6US = 0x0C << 0,
  DRV8316_CTRL10_DLY_TARGET_2P8US = 0x0D << 0,
  DRV8316_CTRL10_DLY_TARGET_3P0US = 0x0E << 0,
  DRV8316_CTRL10_DLY_TARGET_3P2US = 0x0F << 0,
  DRV8316_CTRL10_DLYCMP_EN_DISABLE = 0x00 << 4,
  DRV8316_CTRL10_DLYCMP_EN_ENABLE = 0x01 << 4
}
 
enum  DRV8316_SPI {
  DRV8316_SPI_READ = 1 << 15,
  DRV8316_SPI_WRITE = 0 << 15
}
 
enum  DRV8316_ADDR {
  DRV8316_ADDR_STAT_IC = 0x0,
  DRV8316_ADDR_STAT_1 = 0x1,
  DRV8316_ADDR_STAT_2 = 0x2,
  DRV8316_ADDR_CTRL_1 = 0x3,
  DRV8316_ADDR_CTRL_2 = 0x4,
  DRV8316_ADDR_CTRL_3 = 0x5,
  DRV8316_ADDR_CTRL_4 = 0x6,
  DRV8316_ADDR_CTRL_5 = 0x7,
  DRV8316_ADDR_CTRL_6 = 0x8,
  DRV8316_ADDR_CTRL_10 = 0xC
}
 
enum  DRV8316_CSAGAIN {
  DRV8316_CSAGAIN_0P15VA = 0x00 << 0,
  DRV8316_CSAGAIN_0P3VA = 0x01 << 0,
  DRV8316_CSAGAIN_0P6VA = 0x02 << 0,
  DRV8316_CSAGAIN_1P2VA = 0x03 << 0
}
 
enum  DRV8316_DRVOFF_PIN_STAT {
  DRV8316_DRVOFF_PIN_LOW = HAL_GPIO_PIN_LOW,
  DRV8316_DRVOFF_PIN_HIGH = HAL_GPIO_PIN_HIGH
}
 
enum  DRV8316_DRV_NSLEEP_STAT {
  DRV8316_DRV_NSLEEP_SLEEP = HAL_GPIO_PIN_LOW,
  DRV8316_DRV_NSLEEP_AWAKE = HAL_GPIO_PIN_HIGH
}
 

Functions

__STATIC_INLINE void DRV8316_setDrvoff (DRV8316_Instance *drvHandle, DRV8316_DRVOFF_PIN_STAT value)
 set drvoff More...
 
__STATIC_INLINE void DRV8316_setnSleep (DRV8316_Instance *drvHandle, DRV8316_DRV_NSLEEP_STAT value)
 set nSleep More...
 
void DRV8316_init (DRV8316_Instance *drvHandle)
 initialize the drv8316 module More...
 
uint16_t DRV8316_SPIWrite (DRV8316_Instance *drvHandle, DRV8316_ADDR addr, uint8_t data)
 write data to spi More...
 
uint16_t DRV8316_SPIRead (DRV8316_Instance *drvHandle, DRV8316_ADDR addr)
 write data to spi More...
 
void DRV8316_enable (DRV8316_Instance *drvHandle)
 Enable DRV. More...
 
void DRV8316_updateCTRLRegs (DRV8316_Instance *drvHandle, DRV8316_ADDR regAddr, uint16_t value, uint16_t mask)
 update the drv registers More...
 
void DRV8316_updateCSAScaleFactor (DRV8316_Instance *drvHandle, DRV8316_CSAGAIN csa)
 updates the current gain scale factor More...
 
_iq20 DRV8316_getVoltage (HAL_ADC_CHAN chan)
 Get voltage from adc channel. More...
 
_iq20 DRV8316_getCurrent (HAL_ADC_CHAN chan, DRV8316_Instance *drvHandle, _iq20 vRef)
 Get current from adc channel. More...
 
void DRV8316_ADCVRefSel (HAL_ADC_VREF adcRef, HAL_ADC_CHAN chan, HAL_ADC_INT_VREF internalVRef, uint16_t externalVRef)
 updates the adc voltage reference More...
 
__STATIC_INLINE void DRV8316_updateSPICsagain (DRV8316_Instance *drvHandle, DRV8316_CSAGAIN csaGain)
 Update the SPI CSA gain register. More...
 
__STATIC_INLINE void DRV8316_unlockRegs (DRV8316_Instance *drvHandle)
 unlock all registers More...
 
__STATIC_INLINE void DRV8316_clearfaultBit (DRV8316_Instance *drvHandle)
 clear the status registers More...
 
__STATIC_INLINE _iq20 DRV8316_getcsaVref (uint16_t vRef)
 get Current reference in IQ20 More...
 
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