dl_lfss.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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 */
/*!****************************************************************************
 *  @file       dl_lfss.h
 *  @brief      LFSS(Low Frequency Sub-System) Peripheral Interface
 *  @defgroup   LFSS Low Frequeuncy Sub-System (LFSS)
 *
 *  @anchor ti_devices_msp_dl_lfss_Overview
 *  # Overview
 *  The Low Frequency Sub-System (LFSS) Driver Library allows full configuration
 *  of the MSPM0 LFSS module.
 *  The LFSS IP enables a separate, dedicated battery supply used for
 *  maintaining continuous operation of real time clock (RTC), tamper detection
 *  input / output (TIO) module, an independent asynchronous watchdog timer
 *  (IWDT) and a small scratchpad memory storage (SPM).
 *
 *  <hr>
 ******************************************************************************
 */
#ifndef ti_dl_dl_lfss__include
#define ti_dl_dl_lfss__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#if defined(__MSPM0_HAS_LFSS__) || defined(DOXYGEN__INCLUDE)

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */


#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_0                   (LFSS_CPU_INT_IMASK_TIO0_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_1                   (LFSS_CPU_INT_IMASK_TIO1_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_2                   (LFSS_CPU_INT_IMASK_TIO2_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_3                   (LFSS_CPU_INT_IMASK_TIO3_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_4                   (LFSS_CPU_INT_IMASK_TIO4_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_5                   (LFSS_CPU_INT_IMASK_TIO6_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_6                   (LFSS_CPU_INT_IMASK_TIO6_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_7                   (LFSS_CPU_INT_IMASK_TIO7_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_8                   (LFSS_CPU_INT_IMASK_TIO8_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_9                   (LFSS_CPU_INT_IMASK_TIO9_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_10                   (LFSS_CPU_INT_IMASK_TIO10_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_11                   (LFSS_CPU_INT_IMASK_TIO11_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_12                   (LFSS_CPU_INT_IMASK_TIO12_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_13                   (LFSS_CPU_INT_IMASK_TIO13_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_14                   (LFSS_CPU_INT_IMASK_TIO14_SET)

#define DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_15                   (LFSS_CPU_INT_IMASK_TIO15_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_0                   (LFSS_GEN_EVENT_IMASK_TIO0_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_1                   (LFSS_GEN_EVENT_IMASK_TIO1_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_2                   (LFSS_GEN_EVENT_IMASK_TIO2_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_3                   (LFSS_GEN_EVENT_IMASK_TIO3_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_4                   (LFSS_GEN_EVENT_IMASK_TIO4_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_5                   (LFSS_GEN_EVENT_IMASK_TIO5_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_6                   (LFSS_GEN_EVENT_IMASK_TIO6_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_7                   (LFSS_GEN_EVENT_IMASK_TIO7_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_8                   (LFSS_GEN_EVENT_IMASK_TIO8_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_9                   (LFSS_GEN_EVENT_IMASK_TIO9_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_10                   (LFSS_GEN_EVENT_IMASK_TIO10_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_11                   (LFSS_GEN_EVENT_IMASK_TIO11_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_12                   (LFSS_GEN_EVENT_IMASK_TIO12_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_13                   (LFSS_GEN_EVENT_IMASK_TIO13_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_14                   (LFSS_GEN_EVENT_IMASK_TIO14_SET)

#define DL_LFSS_TAMPERIO_EVENT_TAMPERIO_15                   (LFSS_GEN_EVENT_IMASK_TIO15_SET)

#define LFSS_TAMPER_IO_PIN_ENABLE 0x1

#define LFSS_TAMPER_IO_PIN_MASK 0x1

typedef enum {
    DL_LFSS_TAMPERIO_0 = 0x0000,
    DL_LFSS_TAMPERIO_1 = 0x0001,
    DL_LFSS_TAMPERIO_2 = 0x0002,
    DL_LFSS_TAMPERIO_3 = 0x0003,
    DL_LFSS_TAMPERIO_4 = 0x0004,
    DL_LFSS_TAMPERIO_5 = 0x0005,
    DL_LFSS_TAMPERIO_6 = 0x0006,
    DL_LFSS_TAMPERIO_7 = 0x0007,
    DL_LFSS_TAMPERIO_8 = 0x0008,
    DL_LFSS_TAMPERIO_9 = 0x0009,
    DL_LFSS_TAMPERIO_10 = 0x000A,
    DL_LFSS_TAMPERIO_11 = 0x000B,
    DL_LFSS_TAMPERIO_12 = 0x000C,
    DL_LFSS_TAMPERIO_13 = 0x000D,
    DL_LFSS_TAMPERIO_14 = 0x000E,
    DL_LFSS_TAMPERIO_15 = 0x000F,
} DL_LFSS_TAMPERIO;

typedef enum {
    DL_LFSS_TAMPERIO_VALUE_0 = 0x00000,
    DL_LFSS_TAMPERIO_VALUE_1 = 0x0001,
} DL_LFSS_TAMPERIO_VALUE;

typedef enum {
    DL_LFSS_TAMPERIO_OUTPUT_SOURCE_TOUT = LFSS_TIOCTL_TOUTSEL_TOUT,
    DL_LFSS_TAMPERIO_OUTPUT_SOURCE_LFCLK = LFSS_TIOCTL_TOUTSEL_LFCLKEXT,
    DL_LFSS_TAMPERIO_OUTPUT_SOURCE_HEARTBEAT = LFSS_TIOCTL_TOUTSEL_HEARTBEAT,
    DL_LFSS_TAMPERIO_OUTPUT_SOURCE_TIME_STAMP_EVENT = LFSS_TIOCTL_TOUTSEL_TSEVTSTAT,
} DL_LFSS_TAMPERIO_OUTPUT_SOURCE;

typedef enum {
    DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_NONE = LFSS_TIOCTL_FILTEREN_NO_FLT,
    DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_30_USEC = LFSS_TIOCTL_FILTEREN_FLT_1,
    DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_100_USEC = LFSS_TIOCTL_FILTEREN_FLT_2,
    DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_200_USEC = LFSS_TIOCTL_FILTEREN_FLT_3,
} DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH;

typedef enum {
    DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_DISABLE = LFSS_TIOCTL_POLARITY_DISABLE,
    DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_RISE = LFSS_TIOCTL_POLARITY_RISE,
    DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_FALL = LFSS_TIOCTL_POLARITY_FALL,
    DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_BOTH = LFSS_TIOCTL_POLARITY_BOTH,

} DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY;

typedef enum {
    DL_LFSS_TAMPERIO_MODE_TAMPER = LFSS_TIOCTL_IOMUX_TAMPER,
    DL_LFSS_TAMPERIO_MODE_IOMUX = LFSS_TIOCTL_IOMUX_IOMUX
} DL_LFSS_TAMPERIO_MODE;

typedef enum {
    DL_LFSS_HEARTBEAT_INTERVAL_0_125_SEC = LFSS_HEARTBEAT_HBINTERVAL_HBINT0P125,
    DL_LFSS_HEARTBEAT_INTERVAL_0_25_SEC = LFSS_HEARTBEAT_HBINTERVAL_HBINT0P25,
    DL_LFSS_HEARTBEAT_INTERVAL_05_SEC = LFSS_HEARTBEAT_HBINTERVAL_HBINT0P5,
    DL_LFSS_HEARTBEAT_INTERVAL_1_SEC = LFSS_HEARTBEAT_HBINTERVAL_HBINT1,
    DL_LFSS_HEARTBEAT_INTERVAL_2_SEC = LFSS_HEARTBEAT_HBINTERVAL_HBINT2,
    DL_LFSS_HEARTBEAT_INTERVAL_4_SEC = LFSS_HEARTBEAT_HBINTERVAL_HBINT4,
    DL_LFSS_HEARTBEAT_INTERVAL_8_SEC = LFSS_HEARTBEAT_HBINTERVAL_HBINT8,
    DL_LFSS_HEARTBEAT_INTERVAL_16_SEC = LFSS_HEARTBEAT_HBINTERVAL_HBINT16,
} DL_LFSS_HEARTBEAT_INTERVAL;

typedef enum {
    DL_LFSS_HEARTBEAT_PULSE_WIDTH_1_MSEC = LFSS_HEARTBEAT_HBWIDTH_HBPWDTH1,
    DL_LFSS_HEARTBEAT_PULSE_WIDTH_2_MSEC = LFSS_HEARTBEAT_HBWIDTH_HBPWDTH2,
    DL_LFSS_HEARTBEAT_PULSE_WIDTH_4_MSEC = LFSS_HEARTBEAT_HBWIDTH_HBPWDTH4,
    DL_LFSS_HEARTBEAT_PULSE_WIDTH_8_MSEC = LFSS_HEARTBEAT_HBWIDTH_HBPWDTH8,
    DL_LFSS_HEARTBEAT_PULSE_WIDTH_16_MSEC = LFSS_HEARTBEAT_HBWIDTH_HBPWDTH16,
    DL_LFSS_HEARTBEAT_PULSE_WIDTH_32_MSEC = LFSS_HEARTBEAT_HBWIDTH_HBPWDTH32,
    DL_LFSS_HEARTBEAT_PULSE_WIDTH_64_MSEC = LFSS_HEARTBEAT_HBWIDTH_HBPWDTH64,
    DL_LFSS_HEARTBEAT_PULSE_WIDTH_128_MSEC = LFSS_HEARTBEAT_HBWIDTH_HBPWDTH128,
} DL_LFSS_HEARTBEAT_PULSE_WIDTH;

typedef enum {
    DL_LFSS_HEARTBEAT_MODE_DISABLED = LFSS_HEARTBEAT_HBMODE_HB_DIS,
    DL_LFSS_HEARTBEAT_MODE_ALWAYS_ON = LFSS_HEARTBEAT_HBMODE_HB_ALLWAYS,
    DL_LFSS_HEARTBEAT_MODE_TIME_STAMP = LFSS_HEARTBEAT_HBMODE_HB_TS,
    DL_LFSS_HEARTBEAT_MODE_POWER_FAIL = LFSS_HEARTBEAT_HBMODE_HB_VDDFAIL,
} DL_LFSS_HEARTBEAT_MODE;

typedef enum {
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_0 = LFSS_CPU_INT_IIDX_STAT_TIO0,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_1 = LFSS_CPU_INT_IIDX_STAT_TIO1,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_2 = LFSS_CPU_INT_IIDX_STAT_TIO2,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_3 = LFSS_CPU_INT_IIDX_STAT_TIO3,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_4 = LFSS_CPU_INT_IIDX_STAT_TIO4,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_5 = LFSS_CPU_INT_IIDX_STAT_TIO5,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_6 = LFSS_CPU_INT_IIDX_STAT_TIO6,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_7 = LFSS_CPU_INT_IIDX_STAT_TIO7,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_8 = LFSS_CPU_INT_IIDX_STAT_TIO8,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_9 = LFSS_CPU_INT_IIDX_STAT_TIO9,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_10 = LFSS_CPU_INT_IIDX_STAT_TIO10,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_11 = LFSS_CPU_INT_IIDX_STAT_TIO11,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_12 = LFSS_CPU_INT_IIDX_STAT_TIO12,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_13 = LFSS_CPU_INT_IIDX_STAT_TIO13,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_14 = LFSS_CPU_INT_IIDX_STAT_TIO14,
    DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_15 = LFSS_CPU_INT_IIDX_STAT_TIO15,
} DL_LFSS_TAMPERIO_IIDX;

typedef enum {
    DL_LFSS_SCRATCHPAD_MEM_WORD_0 = 0x0000,
    DL_LFSS_SCRATCHPAD_MEM_WORD_1 = 0x0001,
    DL_LFSS_SCRATCHPAD_MEM_WORD_2 = 0x0002,
    DL_LFSS_SCRATCHPAD_MEM_WORD_3 = 0x0003,
    DL_LFSS_SCRATCHPAD_MEM_WORD_4 = 0x0004,
    DL_LFSS_SCRATCHPAD_MEM_WORD_5 = 0x0005,
    DL_LFSS_SCRATCHPAD_MEM_WORD_6 = 0x0006,
    DL_LFSS_SCRATCHPAD_MEM_WORD_7 = 0x0007,
} DL_LFSS_SCRATCHPAD_MEM_WORD;

typedef enum {
    DL_LFSS_SCRATCHPAD_MEM_BYTE_0 = 0x0000,
    DL_LFSS_SCRATCHPAD_MEM_BYTE_1 = 0x0001,
    DL_LFSS_SCRATCHPAD_MEM_BYTE_2 = 0x0002,
    DL_LFSS_SCRATCHPAD_MEM_BYTE_3 = 0x0003,
} DL_LFSS_SCRATCHPAD_MEM_BYTE;

typedef enum {
    DL_LFSS_IWDT_CLOCK_DIVIDE_1 = 0x00000000,
    DL_LFSS_IWDT_CLOCK_DIVIDE_2 = 0x00000001,
    DL_LFSS_IWDT_CLOCK_DIVIDE_3 = 0x00000002,
    DL_LFSS_IWDT_CLOCK_DIVIDE_4 = 0x00000003,
    DL_LFSS_IWDT_CLOCK_DIVIDE_5 = 0x00000004,
    DL_LFSS_IWDT_CLOCK_DIVIDE_6 = 0x00000005,
    DL_LFSS_IWDT_CLOCK_DIVIDE_7 = 0x00000006,
    DL_LFSS_IWDT_CLOCK_DIVIDE_8 = 0x00000007
} DL_LFSS_IWDT_CLOCK_DIVIDE;

typedef enum {
    DL_LFSS_IWDT_TIMER_PERIOD_6_BITS = LFSS_WDTCTL_PER_PER_EN_6,
    DL_LFSS_IWDT_TIMER_PERIOD_8_BITS = LFSS_WDTCTL_PER_PER_EN_8,
    DL_LFSS_IWDT_TIMER_PERIOD_10_BITS = LFSS_WDTCTL_PER_PER_EN_10,
    DL_LFSS_IWDT_TIMER_PERIOD_12_BITS = LFSS_WDTCTL_PER_PER_EN_12,
    DL_LFSS_IWDT_TIMER_PERIOD_15_BITS = LFSS_WDTCTL_PER_PER_EN_15,
    DL_LFSS_IWDT_TIMER_PERIOD_18_BITS = LFSS_WDTCTL_PER_PER_EN_18,
    DL_LFSS_IWDT_TIMER_PERIOD_21_BITS = LFSS_WDTCTL_PER_PER_EN_21,
    DL_LFSS_IWDT_TIMER_PERIOD_25_BITS = LFSS_WDTCTL_PER_PER_EN_25
} DL_LFSS_IWDT_TIMER_PERIOD;

/* clang-format on */

__STATIC_INLINE void DL_LFSS_TamperIO_enableOutputInversion(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] |=
        LFSS_TIOCTL_OUTINV_ENABLE;
}

__STATIC_INLINE bool DL_LFSS_TamperIO_isOutputInversionEnabled(
    const LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    return ((lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &
                LFSS_TIOCTL_OUTINV_MASK) == LFSS_TIOCTL_OUTINV_ENABLE);
}

__STATIC_INLINE void DL_LFSS_TamperIO_disableOutputInversion(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &=
        ~(LFSS_TIOCTL_OUTINV_MASK);
}

__STATIC_INLINE void DL_LFSS_TamperIO_setOutputSource(LFSS_Regs *lfss,
    DL_LFSS_TAMPERIO tamperIO, DL_LFSS_TAMPERIO_OUTPUT_SOURCE source)
{
    DL_Common_updateReg(&lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO],
        (uint32_t) source, LFSS_TIOCTL_TOUTSEL_MASK);
}

__STATIC_INLINE DL_LFSS_TAMPERIO_OUTPUT_SOURCE
DL_LFSS_TamperIO_getOutputSource(
    const LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    return ((DL_LFSS_TAMPERIO_OUTPUT_SOURCE)(
        lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &
        LFSS_TIOCTL_TOUTSEL_MASK));
}

__STATIC_INLINE void DL_LFSS_TamperIO_setGlitchFilterWidth(LFSS_Regs *lfss,
    DL_LFSS_TAMPERIO tamperIO, DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH width)
{
    DL_Common_updateReg(&lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO],
        (uint32_t) width, LFSS_TIOCTL_FILTEREN_MASK);
}

__STATIC_INLINE DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH
DL_LFSS_TamperIO_getGlitchFilterWidth(
    const LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    return ((DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH)(
        lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &
        LFSS_TIOCTL_FILTEREN_MASK));
}

__STATIC_INLINE void DL_LFSS_TamperIO_setEdgeDetectionPolarity(LFSS_Regs *lfss,
    DL_LFSS_TAMPERIO tamperIO,
    DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY polarity)
{
    DL_Common_updateReg(&lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO],
        (uint32_t) polarity, LFSS_TIOCTL_POLARITY_MASK);
}

__STATIC_INLINE DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY
DL_LFSS_TamperIO_getEdgeDetectionPolarity(
    const LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    return ((DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY)(
        lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &
        LFSS_TIOCTL_POLARITY_MASK));
}

__STATIC_INLINE void DL_LFSS_TamperIO_enableInternalPullUp(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] |=
        LFSS_TIOCTL_PIPU_ENABLE;
}

__STATIC_INLINE bool DL_LFSS_TamperIO_isInternalPullUpEnabled(
    const LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    return ((lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &
                LFSS_TIOCTL_PIPU_MASK) == LFSS_TIOCTL_PIPU_ENABLE);
}

__STATIC_INLINE void DL_LFSS_TamperIO_disableInternalPullUp(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &=
        ~(LFSS_TIOCTL_PIPU_MASK);
}

__STATIC_INLINE void DL_LFSS_TamperIO_enableInternalPullDown(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] |=
        LFSS_TIOCTL_PIPD_ENABLE;
}

__STATIC_INLINE bool DL_LFSS_TamperIO_isInternalPullDownEnabled(
    const LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    return ((lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &
                LFSS_TIOCTL_PIPD_MASK) == LFSS_TIOCTL_PIPD_ENABLE);
}

__STATIC_INLINE void DL_LFSS_TamperIO_disableInternalPullDown(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &=
        ~(LFSS_TIOCTL_PIPD_MASK);
}

__STATIC_INLINE void DL_LFSS_TamperIO_enableInput(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] |=
        LFSS_TIOCTL_INENA_ENABLE;
}

__STATIC_INLINE bool DL_LFSS_TamperIO_isInputEnabled(
    const LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    return ((lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &
                LFSS_TIOCTL_INENA_MASK) == LFSS_TIOCTL_INENA_ENABLE);
}

__STATIC_INLINE void DL_LFSS_TamperIO_disableInput(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &=
        ~(LFSS_TIOCTL_INENA_MASK);
}

__STATIC_INLINE void DL_LFSS_TamperIO_setMode(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO, DL_LFSS_TAMPERIO_MODE mode)
{
    DL_Common_updateReg(&lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO],
        (uint32_t) mode, LFSS_TIOCTL_IOMUX_MASK);
}

__STATIC_INLINE DL_LFSS_TAMPERIO_MODE DL_LFSS_TamperIO_getMode(
    const LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    return ((DL_LFSS_TAMPERIO_MODE)(
        lfss->IPSPECIFIC_TIO.TIOCTL[(uint32_t) tamperIO] &
        LFSS_TIOCTL_IOMUX_MASK));
}

__STATIC_INLINE void DL_LFSS_TamperIO_enableOutput(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_TIO.TOE3_0;

    /* Point to correct base register */
    pReg = (uint32_t *) ((uint8_t *) pReg + (uint8_t)(4 * (tamperIO / 4)));

    /* Set just the one bit for the specified tamper IO */
    *pReg |= LFSS_TAMPER_IO_PIN_ENABLE << (8 * (tamperIO % 4));
}

__STATIC_INLINE void DL_LFSS_TamperIO_disableOutput(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_TIO.TOE3_0;

    /* Point to correct base register */
    pReg = (uint32_t *) ((uint8_t *) pReg + (uint8_t)(4 * (tamperIO / 4)));

    /* Clear just the one bit for the specified tamper IO */
    *pReg &= ~(LFSS_TAMPER_IO_PIN_ENABLE << (8 * (tamperIO % 4)));
}

__STATIC_INLINE uint32_t DL_LFSS_TamperIO_isOutputEnabled(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_TIO.TOE3_0;

    /* Point to correct base register */
    pReg = (uint32_t *) ((uint8_t *) pReg + (uint8_t)(4 * (tamperIO / 4)));

    volatile uint32_t pinMask = LFSS_TAMPER_IO_PIN_MASK
                                << (8 * (tamperIO % 4));
    volatile uint32_t enableMask = LFSS_TAMPER_IO_PIN_ENABLE
                                   << (8 * (tamperIO % 4));

    /* Get just the one bit for the specified tamper IO */
    return ((*pReg & pinMask) == enableMask);
}

__STATIC_INLINE void DL_LFSS_TamperIO_setOutputValue(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO, DL_LFSS_TAMPERIO_VALUE outVal)
{
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_TIO.TOUT3_0;

    /* Point to correct base register */
    pReg = (uint32_t *) ((uint8_t *) pReg + (uint8_t)(4 * (tamperIO / 4)));

    volatile uint32_t valueMask = outVal << (8 * (tamperIO % 4));
    volatile uint32_t pinMask   = LFSS_TAMPER_IO_PIN_MASK
                                << (8 * (tamperIO % 4));

    DL_Common_updateReg(pReg, valueMask, pinMask);
}

__STATIC_INLINE DL_LFSS_TAMPERIO_VALUE DL_LFSS_TamperIO_getOutputValue(
    LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_TIO.TOUT3_0;

    /* Point to correct base register */
    pReg = (uint32_t *) ((uint8_t *) pReg + (uint8_t)(4 * (tamperIO / 4)));

    volatile uint32_t pinMask = LFSS_TAMPER_IO_PIN_MASK
                                << (8 * (tamperIO % 4));

    uint32_t outVal = (*pReg & pinMask) >> (8 * (tamperIO % 4));

    return (DL_LFSS_TAMPERIO_VALUE)(outVal);
}

__STATIC_INLINE DL_LFSS_TAMPERIO_VALUE DL_LFSS_TamperIO_getInputValue(
    const LFSS_Regs *lfss, DL_LFSS_TAMPERIO tamperIO)
{
    const volatile uint32_t *pReg = &lfss->IPSPECIFIC_TIO.TIN3_0;

    /* Point to correct base register */
    pReg = (uint32_t *) ((uint8_t *) pReg + (uint8_t)(4 * (tamperIO / 4)));

    volatile uint32_t pinMask = LFSS_TAMPER_IO_PIN_MASK
                                << (8 * (tamperIO % 4));

    uint32_t inputVal = (*pReg & pinMask) >> (8 * (tamperIO % 4));

    return (DL_LFSS_TAMPERIO_VALUE)(inputVal);
}

__STATIC_INLINE void DL_LFSS_TamperIO_setHeartBeatInterval(
    LFSS_Regs *lfss, DL_LFSS_HEARTBEAT_INTERVAL interval)
{
    DL_Common_updateReg(&lfss->IPSPECIFIC_TIO.HEARTBEAT, (uint32_t) interval,
        LFSS_HEARTBEAT_HBINTERVAL_MASK);
}

__STATIC_INLINE DL_LFSS_HEARTBEAT_INTERVAL
DL_LFSS_TamperIO_getHeartBeatInterval(const LFSS_Regs *lfss)
{
    uint32_t interval =
        lfss->IPSPECIFIC_TIO.HEARTBEAT & LFSS_HEARTBEAT_HBINTERVAL_MASK;

    return (DL_LFSS_HEARTBEAT_INTERVAL)(interval);
}

__STATIC_INLINE void DL_LFSS_TamperIO_setHeartBeatPulseWidth(
    LFSS_Regs *lfss, DL_LFSS_HEARTBEAT_PULSE_WIDTH width)
{
    DL_Common_updateReg(&lfss->IPSPECIFIC_TIO.HEARTBEAT, (uint32_t) width,
        LFSS_HEARTBEAT_HBWIDTH_MASK);
}

__STATIC_INLINE DL_LFSS_HEARTBEAT_PULSE_WIDTH
DL_LFSS_TamperIO_getHeartBeatPulseWidth(const LFSS_Regs *lfss)
{
    uint32_t width =
        (lfss->IPSPECIFIC_TIO.HEARTBEAT & LFSS_HEARTBEAT_HBWIDTH_MASK);

    return (DL_LFSS_HEARTBEAT_PULSE_WIDTH)(width);
}

__STATIC_INLINE void DL_LFSS_TamperIO_setHeartBeatMode(
    LFSS_Regs *lfss, DL_LFSS_HEARTBEAT_MODE mode)
{
    DL_Common_updateReg(&lfss->IPSPECIFIC_TIO.HEARTBEAT, (uint32_t) mode,
        LFSS_HEARTBEAT_HBMODE_MASK);
}

__STATIC_INLINE DL_LFSS_HEARTBEAT_MODE DL_LFSS_TamperIO_getHeartBeatMode(
    const LFSS_Regs *lfss)
{
    uint32_t mode =
        (lfss->IPSPECIFIC_TIO.HEARTBEAT & LFSS_HEARTBEAT_HBMODE_MASK);

    return (DL_LFSS_HEARTBEAT_MODE)(mode);
}

__STATIC_INLINE void DL_LFSS_TamperIO_enableWriteProtectLock(LFSS_Regs *lfss)
{
    lfss->IPSPECIFIC_TIO.TIOLOCK =
        (LFSS_TIOLOCK_PROTECT_SET | LFSS_TIOLOCK_KEY_UNLOCK_W);
}

__STATIC_INLINE bool DL_LFSS_TamperIO_isWriteProtectLockEnabled(
    const LFSS_Regs *lfss)
{
    return ((lfss->IPSPECIFIC_TIO.TIOLOCK & LFSS_TIOLOCK_PROTECT_MASK) ==
            LFSS_TIOLOCK_PROTECT_SET);
}

__STATIC_INLINE void DL_LFSS_TamperIO_disableWriteProtectLock(LFSS_Regs *lfss)
{
    lfss->IPSPECIFIC_TIO.TIOLOCK =
        (LFSS_TIOLOCK_PROTECT_CLR | LFSS_TIOLOCK_KEY_UNLOCK_W);
}

__STATIC_INLINE void DL_LFSS_IWDT_enableModule(LFSS_Regs *lfss)
{
    lfss->IPSPECIFIC_WDT.WDTEN =
        (LFSS_WDTEN_KEY_UNLOCK_W | LFSS_WDTEN_ENABLE_SET);
}

__STATIC_INLINE void DL_LFSS_IWDT_disableModule(LFSS_Regs *lfss)
{
    lfss->IPSPECIFIC_WDT.WDTEN =
        (LFSS_WDTEN_KEY_UNLOCK_W | LFSS_WDTEN_ENABLE_CLR);
}

__STATIC_INLINE bool DL_LFSS_IWDT_isModuleEnabled(const LFSS_Regs *lfss)
{
    return ((lfss->IPSPECIFIC_WDT.WDTEN & LFSS_WDTEN_ENABLE_MASK) ==
            LFSS_WDTEN_ENABLE_SET);
}

__STATIC_INLINE void DL_LFSS_IWDT_enableFreeRun(LFSS_Regs *lfss)
{
    lfss->IPSPECIFIC_WDT.WDTDBGCTL = LFSS_WDTDBGCTL_FREE_RUN;
}

__STATIC_INLINE void DL_LFSS_IWDT_disableFreeRun(LFSS_Regs *lfss)
{
    lfss->IPSPECIFIC_WDT.WDTDBGCTL = LFSS_WDTDBGCTL_FREE_STOP;
}

__STATIC_INLINE bool DL_LFSS_IWDT_isFreeRunEnabled(const LFSS_Regs *lfss)
{
    return ((lfss->IPSPECIFIC_WDT.WDTDBGCTL & LFSS_WDTDBGCTL_FREE_MASK) ==
            LFSS_WDTDBGCTL_FREE_RUN);
}

__STATIC_INLINE void DL_LFSS_IWDT_setClockDivider(
    LFSS_Regs *lfss, DL_LFSS_IWDT_CLOCK_DIVIDE divider)
{
    DL_Common_updateReg(&lfss->IPSPECIFIC_WDT.WDTCTL,
        ((uint32_t) divider | LFSS_WDTCTL_KEY_UNLOCK_W),
        LFSS_WDTCTL_CLKDIV_MASK | LFSS_WDTCTL_KEY_MASK);
}

__STATIC_INLINE DL_LFSS_IWDT_CLOCK_DIVIDE DL_LFSS_IWDT_getClockDivider(
    const LFSS_Regs *lfss)
{
    uint32_t divider = (lfss->IPSPECIFIC_WDT.WDTCTL & LFSS_WDTCTL_CLKDIV_MASK);

    return (DL_LFSS_IWDT_CLOCK_DIVIDE)(divider);
}

__STATIC_INLINE void DL_LFSS_IWDT_setTimerPeriod(
    LFSS_Regs *lfss, DL_LFSS_IWDT_TIMER_PERIOD period)
{
    DL_Common_updateReg(&lfss->IPSPECIFIC_WDT.WDTCTL,
        ((uint32_t) period | LFSS_WDTCTL_KEY_UNLOCK_W),
        LFSS_WDTCTL_PER_MASK | LFSS_WDTCTL_KEY_MASK);
}

__STATIC_INLINE DL_LFSS_IWDT_TIMER_PERIOD DL_LFSS_IWDT_getTimerPeriod(
    const LFSS_Regs *lfss)
{
    uint32_t period = (lfss->IPSPECIFIC_WDT.WDTCTL & LFSS_WDTCTL_PER_MASK);

    return (DL_LFSS_IWDT_TIMER_PERIOD)(period);
}

__STATIC_INLINE void DL_LFSS_IWDT_restart(LFSS_Regs *lfss)
{
    lfss->IPSPECIFIC_WDT.WDTCNTRST = LFSS_WDTCNTRST_RESTART_VALUE;
}

__STATIC_INLINE bool DL_LFSS_IWDT_isWatchdogRunning(const LFSS_Regs *lfss)
{
    return ((lfss->IPSPECIFIC_WDT.WDTSTAT & LFSS_WDTSTAT_RUN_MASK) ==
            LFSS_WDTSTAT_RUN_RUN);
}

__STATIC_INLINE void DL_LFSS_IWDT_enableWriteProtect(LFSS_Regs *lfss)
{
    lfss->IPSPECIFIC_WDT.WDTLOCK =
        (LFSS_WDTLOCK_PROTECT_SET | LFSS_WDTLOCK_KEY_UNLOCK_W);
}

__STATIC_INLINE bool DL_LFSS_IWDT_isWriteProtectEnabled(const LFSS_Regs *lfss)
{
    return ((lfss->IPSPECIFIC_WDT.WDTLOCK & LFSS_WDTLOCK_PROTECT_MASK) ==
            LFSS_WDTLOCK_PROTECT_SET);
}

__STATIC_INLINE void DL_LFSS_IWDT_disableWriteProtect(LFSS_Regs *lfss)
{
    lfss->IPSPECIFIC_WDT.WDTLOCK =
        (LFSS_WDTLOCK_PROTECT_CLR | LFSS_WDTLOCK_KEY_UNLOCK_W);
}

__STATIC_INLINE void DL_LFSS_writeScratchPadData32(
    LFSS_Regs *lfss, DL_LFSS_SCRATCHPAD_MEM_WORD memIndex, uint32_t data)
{
    lfss->IPSPECIFIC_MEM.SPMEM[(uint32_t) memIndex] = data;
}

__STATIC_INLINE void DL_LFSS_writeScratchPadData8(LFSS_Regs *lfss,
    DL_LFSS_SCRATCHPAD_MEM_WORD memIndex,
    DL_LFSS_SCRATCHPAD_MEM_BYTE byteIndex, uint32_t data)
{
    /* Point to correct SPMEM word */
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_MEM.SPMEM[(uint32_t) memIndex];

    /* Get the correct bit based on the byteIndex */
    uint32_t offset = ((uint32_t) byteIndex * (uint32_t) 8);
    data            = data << offset;
    uint32_t mask   = ((uint32_t) 0x000000FFU) << offset;

    DL_Common_updateReg(pReg, data, mask);
}

__STATIC_INLINE uint32_t DL_LFSS_readScratchPadDataWord(
    const LFSS_Regs *lfss, DL_LFSS_SCRATCHPAD_MEM_WORD memIndex)
{
    return (lfss->IPSPECIFIC_MEM.SPMEM[(uint32_t) memIndex]);
}

__STATIC_INLINE uint8_t DL_LFSS_readScratchPadDataByte(LFSS_Regs *lfss,
    DL_LFSS_SCRATCHPAD_MEM_WORD memIndex,
    DL_LFSS_SCRATCHPAD_MEM_BYTE byteIndex)
{
    /* Point to correct SPMEM word */
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_MEM.SPMEM[(uint32_t) memIndex];

    /* Get the correct bit based on the byteIndex */
    uint32_t offset = ((uint32_t) byteIndex * (uint32_t) 8);
    uint32_t mask   = ((uint32_t) 0x000000FFU) << offset;

    return (((*pReg & mask)) >> offset);
}

__STATIC_INLINE void DL_LFSS_enableScratchPadWriteProtectByte(LFSS_Regs *lfss,
    DL_LFSS_SCRATCHPAD_MEM_WORD memIndex,
    DL_LFSS_SCRATCHPAD_MEM_BYTE byteIndex)
{
    /* Point to correct SPMWPROT register */
    uint32_t regIndex       = (uint32_t) memIndex >> (uint32_t) 2;
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_MEM.SPMWPROT0 + regIndex;

    /* Get the correct bit based on the byteIndex */
    uint32_t mask = (uint32_t) 1 << ((((uint32_t) memIndex % (uint32_t) 4)
                                         << (uint32_t) 2) +
                                     (uint32_t) byteIndex);

    *pReg |= (LFSS_SPMWPROT0_KEY_UNLOCK_W | mask);
}

__STATIC_INLINE bool DL_LFSS_isScratchPadWriteProtectByteEnabled(
    LFSS_Regs *lfss, DL_LFSS_SCRATCHPAD_MEM_WORD memIndex,
    DL_LFSS_SCRATCHPAD_MEM_BYTE byteIndex)
{
    /* Point to correct SPMWPROT index */
    uint32_t regIndex       = (uint32_t) memIndex >> (uint32_t) 2;
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_MEM.SPMWPROT0 + regIndex;

    /* Get the correct bit based on the byteIndex */
    uint32_t mask = (uint32_t) 1 << ((((uint32_t) memIndex % (uint32_t) 4)
                                         << (uint32_t) 2) +
                                     (uint32_t) byteIndex);

    return ((*pReg & mask) == mask);
}

__STATIC_INLINE void DL_LFSS_disableScratchPadWriteProtectByte(LFSS_Regs *lfss,
    DL_LFSS_SCRATCHPAD_MEM_WORD memIndex,
    DL_LFSS_SCRATCHPAD_MEM_BYTE byteIndex)
{
    /* Point to correct SPMWPROT index */
    uint32_t regIndex       = (uint32_t) memIndex >> (uint32_t) 2;
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_MEM.SPMWPROT0 + regIndex;

    /* Get the correct bit based on the byteIndex */
    uint32_t mask = (uint32_t) 1 << ((((uint32_t) memIndex % (uint32_t) 4)
                                         << (uint32_t) 2) +
                                     (uint32_t) byteIndex);

    *pReg = ((*pReg & (~mask)) | LFSS_SPMWPROT1_KEY_UNLOCK_W);
}

__STATIC_INLINE void DL_LFSS_enableScratchPadTamperEraseByte(LFSS_Regs *lfss,
    DL_LFSS_SCRATCHPAD_MEM_WORD memIndex,
    DL_LFSS_SCRATCHPAD_MEM_BYTE byteIndex)
{
    /* Point to correct SPMTERASE index */
    uint32_t regIndex       = (uint32_t) memIndex >> (uint32_t) 2;
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_MEM.SPMTERASE0 + regIndex;

    /* Get the correct bit based on the byteIndex */
    uint32_t mask = (uint32_t) 1 << ((((uint32_t) memIndex % (uint32_t) 4)
                                         << (uint32_t) 2) +
                                     (uint32_t) byteIndex);

    *pReg |= (LFSS_SPMTERASE0_KEY_UNLOCK_W | mask);
}

__STATIC_INLINE bool DL_LFSS_isScratchPadTamperEraseByteEnabled(
    LFSS_Regs *lfss, DL_LFSS_SCRATCHPAD_MEM_WORD memIndex,
    DL_LFSS_SCRATCHPAD_MEM_BYTE byteIndex)
{
    /* Point to correct SPMTERASE index */
    uint32_t regIndex       = (uint32_t) memIndex >> (uint32_t) 2;
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_MEM.SPMTERASE0 + regIndex;

    /* Get the correct bit based on the byteIndex */
    uint32_t mask = (uint32_t) 1 << ((((uint32_t) memIndex % (uint32_t) 4)
                                         << (uint32_t) 2) +
                                     (uint32_t) byteIndex);

    return ((*pReg & mask) == mask);
}

__STATIC_INLINE void DL_LFSS_disableScratchPadTamperEraseByte(LFSS_Regs *lfss,
    DL_LFSS_SCRATCHPAD_MEM_WORD memIndex,
    DL_LFSS_SCRATCHPAD_MEM_BYTE byteIndex)
{
    /* Point to correct SPMTERASE index */
    uint32_t regIndex       = (uint32_t) memIndex >> (uint32_t) 2;
    volatile uint32_t *pReg = &lfss->IPSPECIFIC_MEM.SPMTERASE0 + regIndex;

    /* Get the correct bit based on the byteIndex */
    uint32_t mask = (uint32_t) 1 << ((((uint32_t) memIndex % (uint32_t) 4)
                                         << (uint32_t) 2) +
                                     (uint32_t) byteIndex);

    *pReg = ((*pReg & (~mask)) | LFSS_SPMWPROT2_KEY_UNLOCK_W);
}

__STATIC_INLINE void DL_LFSS_TamperIO_enableInterrupt(
    LFSS_Regs *lfss, uint32_t interruptMask)
{
    lfss->CPU_INT.IMASK |= interruptMask;
}

__STATIC_INLINE void DL_LFSS_TamperIO_disableInterrupt(
    LFSS_Regs *lfss, uint32_t interruptMask)
{
    lfss->CPU_INT.IMASK &= ~(interruptMask);
}

__STATIC_INLINE uint32_t DL_LFSS_TamperIO_getEnabledInterrupts(
    const LFSS_Regs *lfss, uint32_t interruptMask)
{
    return (lfss->CPU_INT.IMASK & interruptMask);
}

__STATIC_INLINE uint32_t DL_LFSS_TamperIO_getEnabledInterruptStatus(
    const LFSS_Regs *lfss, uint32_t interruptMask)
{
    return (lfss->CPU_INT.MIS & interruptMask);
}

__STATIC_INLINE uint32_t DL_LFSS_TamperIO_getRawInterruptStatus(
    const LFSS_Regs *lfss, uint32_t interruptMask)
{
    return (lfss->CPU_INT.RIS & interruptMask);
}

__STATIC_INLINE DL_LFSS_TAMPERIO_IIDX DL_LFSS_TamperIO_getPendingInterrupt(
    const LFSS_Regs *lfss)
{
    return (DL_LFSS_TAMPERIO_IIDX)(lfss->CPU_INT.IIDX);
}

__STATIC_INLINE void DL_LFSS_TamperIO_clearInterruptStatus(
    LFSS_Regs *lfss, uint32_t interruptMask)
{
    lfss->CPU_INT.ICLR = interruptMask;
}

__STATIC_INLINE void DL_LFSS_TamperIO_enableEvent(
    LFSS_Regs *lfss, uint32_t eventMask)
{
    lfss->GEN_EVENT.IMASK |= (eventMask);
}

__STATIC_INLINE void DL_LFSS_TamperIO_disableEvent(
    LFSS_Regs *lfss, uint32_t eventMask)
{
    lfss->GEN_EVENT.IMASK &= ~(eventMask);
}

__STATIC_INLINE uint32_t DL_LFSS_TamperIO_getEnabledEvents(
    const LFSS_Regs *lfss, uint32_t eventMask)
{
    return ((lfss->GEN_EVENT.IMASK) & (eventMask));
}

__STATIC_INLINE uint32_t DL_LFSS_TamperIO_getEnabledEventStatus(
    const LFSS_Regs *lfss, uint32_t eventMask)
{
    return ((lfss->GEN_EVENT.MIS) & eventMask);
}

__STATIC_INLINE uint32_t DL_LFSS_TamperIO_getRawEventsStatus(
    const LFSS_Regs *lfss, uint32_t eventMask)
{
    return ((lfss->GEN_EVENT.RIS) & eventMask);
}

__STATIC_INLINE void DL_LFSS_TamperIO_clearEventsStatus(
    LFSS_Regs *lfss, uint32_t eventMask)
{
    lfss->GEN_EVENT.ICLR |= (eventMask);
}

__STATIC_INLINE void DL_LFSS_TamperIO_setPublisherChanID(
    LFSS_Regs *lfss, uint8_t chanID)
{
    lfss->FPUB_0 = (chanID & LFSS_FPUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_LFSS_TamperIO_getPublisherChanID(
    const LFSS_Regs *lfss)
{
    return (uint8_t)(lfss->FPUB_0 & LFSS_FPUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE void DL_LFSS_reset(LFSS_Regs *lfss)
{
    lfss->IPSPECIFIC_RTC.LFSSRST =
        (LFSS_LFSSRST_KEY_UNLOCK_W | LFSS_LFSSRST_VBATPOR_SET);
}

#ifdef __cplusplus
}
#endif
#endif /* __MSPM0_HAS_LFSS__ */
#endif /* ti_dl_dl_lfss__include */