dl_opa.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
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/*!****************************************************************************
 *  @file       dl_opa.h
 *  @brief      Op-Amp (OPA) Driver Library
 *  @defgroup   OPA Op-Amp (OPA)
 *
 *  @anchor ti_dl_dl_opa_Overview
 *  # Overview
 *
 *  The OP-Amp Driver Library allows full configuration of the MSPM0 OPA module.
 *  The OPA is a zero-drift chopper stabilized operational amplifier with a
 *  programmable gain stage.
 *
 *  <hr>

 ******************************************************************************
 */
#ifndef ti_dl_dl_opa__include
#define ti_dl_dl_opa__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#ifdef __MSPM0_HAS_OA__

#ifdef __cplusplus
extern "C" {
#endif

typedef enum {
    DL_OPA_CHOPPING_MODE_DISABLE = OA_CFG_CHOP_OFF,
    DL_OPA_CHOPPING_MODE_STANDARD = OA_CFG_CHOP_ON,
    DL_OPA_CHOPPING_MODE_ADC_AVERAGING = OA_CFG_CHOP_AVGON,
} DL_OPA_CHOPPING_MODE;

typedef enum {

    DL_OPA_OUTPUT_PIN_ENABLED = OA_CFG_OUTPIN_ENABLED,
    DL_OPA_OUTPUT_PIN_DISABLED = OA_CFG_OUTPIN_DISABLED,

} DL_OPA_OUTPUT_PIN_STATE;

typedef enum {
    DL_OPA_PSEL_OPEN = OA_CFG_PSEL_NC,
    DL_OPA_PSEL_IN0_POS = OA_CFG_PSEL_EXTPIN0,
    DL_OPA_PSEL_IN1_POS = OA_CFG_PSEL_EXTPIN1,
    DL_OPA_PSEL_DAC_OUT = OA_CFG_PSEL_DAC12OUT,
    DL_OPA_PSEL_DAC8_OUT = OA_CFG_PSEL_DAC8OUT,
    DL_OPA_PSEL_VREF = OA_CFG_PSEL_VREF,
    DL_OPA_PSEL_RTOP = OA_CFG_PSEL_OANM1RTOP,

    DL_OPA_PSEL_GPAMP_OUT = OA_CFG_PSEL_GPAMP_OUT_INT,
    DL_OPA_PSEL_GND = OA_CFG_PSEL_VSS,

} DL_OPA_PSEL;

typedef enum {
    DL_OPA_NSEL_OPEN = OA_CFG_NSEL_NC,
    DL_OPA_NSEL_IN0_NEG = OA_CFG_NSEL_EXTPIN0,
    DL_OPA_NSEL_IN1_NEG = OA_CFG_NSEL_EXTPIN1,
    DL_OPA_NSEL_RBOT = OA_CFG_NSEL_OANP1RBOT,
    DL_OPA_NSEL_RTAP = OA_CFG_NSEL_OANRTAP,
    DL_OPA_NSEL_RTOP = OA_CFG_NSEL_OANRTOP,
    DL_OPA_NSEL_SPARE = OA_CFG_NSEL_SPARE,
} DL_OPA_NSEL;

typedef enum {
    DL_OPA_MSEL_OPEN = OA_CFG_MSEL_NC,
    DL_OPA_MSEL_IN1_NEG = OA_CFG_MSEL_EXTNPIN1,
    DL_OPA_MSEL_GND = OA_CFG_MSEL_VSS,
    DL_OPA_MSEL_DAC_OUT = OA_CFG_MSEL_DAC12OUT,
    DL_OPA_MSEL_RTOP = OA_CFG_MSEL_OANM1RTOP,
} DL_OPA_MSEL;

typedef enum {
    DL_OPA_GBW_HIGH = OA_CFGBASE_GBW_HIGHGAIN,
    DL_OPA_GBW_LOW = OA_CFGBASE_GBW_LOWGAIN,
} DL_OPA_GBW;

typedef enum {
    DL_OPA_GAIN_N0_P1 = (((uint32_t) 0x0) << OA_CFG_GAIN_OFS),
    DL_OPA_GAIN_N1_P2 = (((uint32_t) 0x1) << OA_CFG_GAIN_OFS),
    DL_OPA_GAIN_N3_P4 = (((uint32_t) 0x2) << OA_CFG_GAIN_OFS),
    DL_OPA_GAIN_N7_P8 = (((uint32_t) 0x3) << OA_CFG_GAIN_OFS),
    DL_OPA_GAIN_N15_P16 = (((uint32_t) 0x4) << OA_CFG_GAIN_OFS),
    DL_OPA_GAIN_N31_P32 = (((uint32_t) 0x5) << OA_CFG_GAIN_OFS),
} DL_OPA_GAIN;

typedef struct {
    DL_OPA_CHOPPING_MODE choppingMode;
    DL_OPA_OUTPUT_PIN_STATE outputPinState;
    DL_OPA_PSEL pselChannel;
    DL_OPA_NSEL nselChannel;
    DL_OPA_MSEL mselChannel;
    DL_OPA_GAIN gain;
} DL_OPA_Config;

__STATIC_INLINE void DL_OPA_enablePower(OA_Regs *opa)
{
    opa->GPRCM.PWREN = (OA_PWREN_KEY_UNLOCK_W | OA_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_OPA_disablePower(OA_Regs *opa)
{
    opa->GPRCM.PWREN = (OA_PWREN_KEY_UNLOCK_W | OA_PWREN_ENABLE_DISABLE);
}

__STATIC_INLINE bool DL_OPA_isPowerEnabled(const OA_Regs *opa)
{
    return (
        (opa->GPRCM.PWREN & OA_PWREN_ENABLE_MASK) == OA_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_OPA_reset(OA_Regs *opa)
{
    opa->GPRCM.RSTCTL = (OA_RSTCTL_KEY_UNLOCK_W | OA_RSTCTL_RESETSTKYCLR_CLR |
                         OA_RSTCTL_RESETASSERT_ASSERT);
}

__STATIC_INLINE bool DL_OPA_isReset(const OA_Regs *opa)
{
    return ((opa->GPRCM.STAT & OA_GPRCM_STAT_RESETSTKY_MASK) ==
            OA_GPRCM_STAT_RESETSTKY_RESET);
}

__STATIC_INLINE void DL_OPA_enable(OA_Regs *opa)
{
    opa->CTL |= OA_CTL_ENABLE_ON;
}

__STATIC_INLINE bool DL_OPA_isEnabled(const OA_Regs *opa)
{
    return ((opa->CTL & OA_CTL_ENABLE_MASK) == OA_CTL_ENABLE_ON);
}

__STATIC_INLINE void DL_OPA_disable(OA_Regs *opa)
{
    opa->CTL &= ~(OA_CTL_ENABLE_MASK);
}

__STATIC_INLINE void DL_OPA_init(OA_Regs *opa, const DL_OPA_Config *config)
{
    DL_Common_updateReg(&opa->CFG,
        (uint32_t) config->choppingMode | (uint32_t) config->outputPinState |
            (uint32_t) config->pselChannel | (uint32_t) config->nselChannel |
            (uint32_t) config->mselChannel | (uint32_t) config->gain,
        OA_CFG_CHOP_MASK | OA_CFG_OUTPIN_MASK | OA_CFG_PSEL_MASK |
            OA_CFG_NSEL_MASK | OA_CFG_MSEL_MASK | OA_CFG_GAIN_MASK);
}

__STATIC_INLINE void DL_OPA_setGainBandwidth(
    OA_Regs *opa, DL_OPA_GBW bandwidth)
{
    DL_Common_updateReg(
        &opa->CFGBASE, (uint32_t) bandwidth, OA_CFGBASE_GBW_MASK);
}

__STATIC_INLINE DL_OPA_GBW DL_OPA_getGainBandwidth(const OA_Regs *opa)
{
    uint32_t bandwidth = (opa->CFGBASE & OA_CFGBASE_GBW_MASK);

    return (DL_OPA_GBW)(bandwidth);
}

__STATIC_INLINE void DL_OPA_enableRailToRailInput(OA_Regs *opa)
{
    opa->CFGBASE |= OA_CFGBASE_RRI_ON;
}

__STATIC_INLINE bool DL_OPA_isRailToRailInputEnabled(OA_Regs *opa)
{
    return ((opa->CFGBASE &= OA_CFGBASE_RRI_MASK) == OA_CFGBASE_RRI_ON);
}

__STATIC_INLINE void DL_OPA_disableRailToRailInput(OA_Regs *opa)
{
    opa->CFGBASE &= ~(OA_CFGBASE_RRI_MASK);
}

__STATIC_INLINE void DL_OPA_setChoppingMode(
    OA_Regs *opa, DL_OPA_CHOPPING_MODE mode)
{
    DL_Common_updateReg(&opa->CFG, (uint32_t) mode, OA_CFG_CHOP_MASK);
}

__STATIC_INLINE DL_OPA_CHOPPING_MODE DL_OPA_getChoppingMode(const OA_Regs *opa)
{
    uint32_t mode = (opa->CFG & OA_CFG_CHOP_MASK);

    return (DL_OPA_CHOPPING_MODE)(mode);
}

__STATIC_INLINE void DL_OPA_setOutputPinState(
    OA_Regs *opa, DL_OPA_OUTPUT_PIN_STATE state)
{
    DL_Common_updateReg(&opa->CFG, (uint32_t) state, OA_CFG_OUTPIN_MASK);
}

__STATIC_INLINE DL_OPA_OUTPUT_PIN_STATE DL_OPA_getOutputPinState(
    const OA_Regs *opa)
{
    uint32_t state = (opa->CFG & OA_CFG_OUTPIN_MASK);

    return (DL_OPA_OUTPUT_PIN_STATE)(state);
}

__STATIC_INLINE void DL_OPA_disableOutputPin(OA_Regs *opa)
{
    opa->CFG &= ~(OA_CFG_OUTPIN_MASK);
}

__STATIC_INLINE void DL_OPA_setNonInvertingInputChannel(
    OA_Regs *opa, DL_OPA_PSEL inputChannel)
{
    DL_Common_updateReg(&opa->CFG, (uint32_t) inputChannel, OA_CFG_PSEL_MASK);
}

__STATIC_INLINE DL_OPA_PSEL DL_OPA_getNonInvertingInputChannel(
    const OA_Regs *opa)
{
    uint32_t inputChannel = (opa->CFG & OA_CFG_PSEL_MASK);

    return (DL_OPA_PSEL)(inputChannel);
}

__STATIC_INLINE void DL_OPA_setInvertingInputChannel(
    OA_Regs *opa, DL_OPA_NSEL inputChannel)
{
    DL_Common_updateReg(&opa->CFG, (uint32_t) inputChannel, OA_CFG_NSEL_MASK);
}

__STATIC_INLINE DL_OPA_NSEL DL_OPA_getInvertingInputChannel(const OA_Regs *opa)
{
    uint32_t inputChannel = (opa->CFG & OA_CFG_NSEL_MASK);

    return (DL_OPA_NSEL)(inputChannel);
}

__STATIC_INLINE void DL_OPA_setMMUXInputChannel(
    OA_Regs *opa, DL_OPA_MSEL inputChannel)
{
    DL_Common_updateReg(&opa->CFG, (uint32_t) inputChannel, OA_CFG_MSEL_MASK);
}

__STATIC_INLINE DL_OPA_MSEL DL_OPA_getMMUXInputChannel(const OA_Regs *opa)
{
    uint32_t inputChannel = (opa->CFG & OA_CFG_MSEL_MASK);

    return (DL_OPA_MSEL)(inputChannel);
}

__STATIC_INLINE void DL_OPA_setGain(OA_Regs *opa, DL_OPA_GAIN gain)
{
    DL_Common_updateReg(&opa->CFG, (uint32_t) gain, OA_CFG_GAIN_MASK);
}

__STATIC_INLINE DL_OPA_GAIN DL_OPA_getGain(const OA_Regs *opa)
{
    uint32_t gain = (opa->CFG & OA_CFG_GAIN_MASK);

    return (DL_OPA_GAIN)(gain);
}

DL_OPA_GAIN DL_OPA_increaseGain(OA_Regs *opa);

DL_OPA_GAIN DL_OPA_decreaseGain(OA_Regs *opa);

__STATIC_INLINE bool DL_OPA_isReady(const OA_Regs *opa)
{
    return ((opa->STAT & OA_STAT_RDY_MASK) == OA_STAT_RDY_TRUE);
}

#ifdef __cplusplus
}
#endif
#endif /* __MSPM0_HAS_OA__ */

#endif /* ti_dl_dl_opa__include */