dl_core.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
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 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
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 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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/*!****************************************************************************
 *  @file       dl_core.h
 *  @brief      CPU Core Driver Library
 *  @defgroup   CORE M0P Core
 *
 *  @anchor ti_dl_m0p_dl_core_Overview
 *  # Overview
 *
 *  The Core module enables software to read from core registers of the CPU to
 *  get more information about the device at runtime.
 *
 *  <hr>
 ******************************************************************************
 */
#ifndef ti_dl_m0p_dl_core__include
#define ti_dl_m0p_dl_core__include

#include <stdint.h>

#include <ti/devices/msp/msp.h>

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

#define DL_CORE_CACHE_ENABLED                          (CPUSS_CTL_ICACHE_ENABLE)

#define DL_CORE_CACHE_DISABLED                        (CPUSS_CTL_ICACHE_DISABLE)

#define DL_CORE_PREFETCH_ENABLED                     (CPUSS_CTL_PREFETCH_ENABLE)

#define DL_CORE_PREFETCH_DISABLED                   (CPUSS_CTL_PREFETCH_DISABLE)

#define DL_CORE_LITERAL_CACHE_ENABLED                   (CPUSS_CTL_LITEN_ENABLE)

#define DL_CORE_LITERAL_CACHE_DISABLED                 (CPUSS_CTL_LITEN_DISABLE)

#define delay_cycles(cycles) DL_Common_delayCycles(cycles)

/* clang-format on  */


__STATIC_INLINE uint32_t DL_CORE_getImplementer(void)
{
    return (
        (SCB->CPUID & SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}

__STATIC_INLINE uint32_t DL_CORE_getVariant(void)
{
    return ((SCB->CPUID & SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}

__STATIC_INLINE uint32_t DL_CORE_getArchitecture(void)
{
    return ((SCB->CPUID & SCB_CPUID_ARCHITECTURE_Msk) >>
            SCB_CPUID_ARCHITECTURE_Pos);
}

__STATIC_INLINE uint32_t DL_CORE_getPartNumber(void)
{
    return ((SCB->CPUID & SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}

__STATIC_INLINE uint32_t DL_CORE_getRevision(void)
{
    return ((SCB->CPUID & (uint32_t)SCB_CPUID_REVISION_Msk) >> (uint32_t)SCB_CPUID_REVISION_Pos);
}

__STATIC_INLINE void DL_CORE_configInstruction(uint32_t icache, uint32_t prefetch, uint32_t litCache)
{
    CPUSS->CTL = (icache | prefetch | litCache);
}

__STATIC_INLINE uint32_t DL_CORE_getInstructionConfig(void)
{
    return(CPUSS->CTL & (CPUSS_CTL_ICACHE_MASK | CPUSS_CTL_PREFETCH_MASK | CPUSS_CTL_LITEN_MASK));
}

#ifdef __cplusplus
}

#endif

#endif /* ti_dl_m0p_dl_core__include */