dl_vref.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
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 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
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 *    from this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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/*!****************************************************************************
 *  @file       dl_vref.h
 *  @brief      Voltage Reference (VREF) Driver Library
 *  @defgroup   VREF Voltage Reference (VREF)
 *
 *  @anchor ti_dl_dl_vref_Overview
 *  # Overview
 *
 *  The Voltage Reference Driver Library allows full configuration of
 *  the MSPM0 VREF module.
 *  The VREF module contains a configurable voltage reference buffer which
 *  allows users to supply a stable internal reference to on-board analog
 *  peripherals. It also supports bringing in an external reference for
 *  applications where higher accuracy is required.
 *
 *  <hr>
 ******************************************************************************
 */
#ifndef ti_dl_dl_m0p_vref__include
#define ti_dl_dl_m0p_vref__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#ifdef __MSPM0_HAS_VREF__

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

#define DL_VREF_CTL1_READY_NOTRDY    (VREF_CTL1_READY_NOTRDY)

#define DL_VREF_CTL1_READY_RDY    (VREF_CTL1_READY_RDY)


#define DL_VREF_SH_MIN             (VREF_CTL2_SHCYCLE_MINIMUM)

#define DL_VREF_SH_MAX             (VREF_CTL2_SHCYCLE_MAXIMUM)

#define DL_VREF_HOLD_MIN             (VREF_CTL2_HCYCLE_MINIMUM)

#define DL_VREF_HOLD_MAX             (VREF_CTL2_HCYCLE_MAXIMUM)

/* clang-format on */

typedef enum {
    DL_VREF_CLOCK_LFCLK = VREF_CLKSEL_LFCLK_SEL_MASK,
    DL_VREF_CLOCK_MFCLK = VREF_CLKSEL_MFCLK_SEL_MASK,
    DL_VREF_CLOCK_BUSCLK = VREF_CLKSEL_BUSCLK_SEL_MASK,
} DL_VREF_CLOCK;

typedef enum {
    DL_VREF_CLOCK_DIVIDE_1 = 0,
    DL_VREF_CLOCK_DIVIDE_2 = 1,
    DL_VREF_CLOCK_DIVIDE_4 = 3,
    DL_VREF_CLOCK_DIVIDE_6 = 5,
    DL_VREF_CLOCK_DIVIDE_8 = 7,
} DL_VREF_CLOCK_DIVIDE;

typedef enum {
    DL_VREF_ENABLE_DISABLE = VREF_CTL0_ENABLE_DISABLE,
    DL_VREF_ENABLE_ENABLE = VREF_CTL0_ENABLE_ENABLE,
} DL_VREF_ENABLE;

typedef enum {
    DL_VREF_BUFCONFIG_OUTPUT_2_5V = VREF_CTL0_BUFCONFIG_OUTPUT2P5V,
    DL_VREF_BUFCONFIG_OUTPUT_1_4V = VREF_CTL0_BUFCONFIG_OUTPUT1P4V,
} DL_VREF_BUFCONFIG;

typedef enum {
    DL_VREF_SHMODE_DISABLE = VREF_CTL0_SHMODE_DISABLE,
    DL_VREF_SHMODE_ENABLE = VREF_CTL0_SHMODE_ENABLE,
} DL_VREF_SHMODE;

typedef struct {
    DL_VREF_CLOCK clockSel;
    DL_VREF_CLOCK_DIVIDE divideRatio;
} DL_VREF_ClockConfig;

typedef struct {
    DL_VREF_ENABLE vrefEnable;
    DL_VREF_BUFCONFIG bufConfig;
    DL_VREF_SHMODE shModeEnable;
    uint32_t shCycleCount;
    uint32_t holdCycleCount;
} DL_VREF_Config;

__STATIC_INLINE void DL_VREF_enablePower(VREF_Regs *vref)
{
    vref->GPRCM.PWREN = VREF_PWREN_KEY_UNLOCK_W | VREF_PWREN_ENABLE_ENABLE;
}

__STATIC_INLINE void DL_VREF_disablePower(VREF_Regs *vref)
{
    vref->GPRCM.PWREN = VREF_PWREN_KEY_UNLOCK_W | VREF_PWREN_ENABLE_DISABLE;
}
__STATIC_INLINE bool DL_VREF_isPowerEnabled(VREF_Regs *vref)
{
    return ((VREF->GPRCM.PWREN & VREF_PWREN_ENABLE_MASK) ==
            VREF_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_VREF_enableInternalRef(VREF_Regs *vref)
{
    vref->CTL0 |= VREF_CTL0_ENABLE_ENABLE;
}

__STATIC_INLINE void DL_VREF_disableInternalRef(VREF_Regs *vref)
{
    vref->CTL0 &= ~VREF_CTL0_ENABLE_MASK;
}

__STATIC_INLINE bool DL_VREF_isEnabled(const VREF_Regs *vref)
{
    return ((vref->CTL0 & VREF_CTL0_ENABLE_MASK) == VREF_CTL0_ENABLE_ENABLE);
}

#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L122X_L222X)

__STATIC_INLINE void DL_VREF_enableInternalRefCOMP(VREF_Regs *vref)
{
    vref->CTL0 |= VREF_CTL0_COMP_VREF_ENABLE_ENABLE;
}

__STATIC_INLINE bool DL_VREF_isInternalRefCOMPEnabled(const VREF_Regs *vref)
{
    return ((vref->CTL0 & VREF_CTL0_COMP_VREF_ENABLE_MASK) ==
            VREF_CTL0_COMP_VREF_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_VREF_disableInternalRefCOMP(VREF_Regs *vref)
{
    vref->CTL0 &= ~(VREF_CTL0_COMP_VREF_ENABLE_MASK);
}
#endif

void DL_VREF_setClockConfig(
    VREF_Regs *vref, const DL_VREF_ClockConfig *config);

void DL_VREF_getClockConfig(
    const VREF_Regs *vref, DL_VREF_ClockConfig *config);

__STATIC_INLINE void DL_VREF_reset(VREF_Regs *vref)
{
    vref->GPRCM.RSTCTL =
        VREF_RSTCTL_RESETASSERT_MASK | VREF_RSTCTL_KEY_UNLOCK_W;
}

__STATIC_INLINE bool DL_VREF_isReset(const VREF_Regs *vref)
{
    return (vref->GPRCM.STAT & VREF_STAT_RESETSTKY_MASK) ==
           VREF_STAT_RESETSTKY_RESET;
}

__STATIC_INLINE uint32_t DL_VREF_getStatus(const VREF_Regs *vref)
{
    return vref->CTL1 & VREF_CTL1_READY_MASK;
}

void DL_VREF_configReference(VREF_Regs *vref, const DL_VREF_Config *config);

#ifdef __cplusplus
}
#endif

#endif /* __MSPM0_HAS_VREF__ */

#endif /* ti_dl_dl_m0p_vref__include */