dl_mcan.h

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/*
 * Copyright (c) 2021, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/*!****************************************************************************
 *  @file       dl_mcan.h
 *  @brief      Modular Controller Area Network (MCAN) Driver Library
 *  @defgroup   MCAN Modular Controller Area Network (MCAN)
 *
 *  @anchor ti_dl_dl_mcan_Overview
 *  # Overview
 *
 *  The MCAN Driver Library allows full configuration of the MSPM0 MCAN (CAN-FD)
 *  module.
 *  The Modular Controller Area Network (MCAN) peripheral supports both
 *  communication through classic CAN and CAN-FD protocols.
 *
 *  <hr>
 ******************************************************************************
 */
#ifndef ti_dl_dl_mcan__include
#define ti_dl_dl_mcan__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#ifdef __MSPM0_HAS_MCAN__

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

#define DL_MCAN_INTR_MASK_ALL (MCAN_IR_RF0N_MASK |                          \
                               MCAN_IR_RF0W_MASK |                          \
                               MCAN_IR_RF0F_MASK |                          \
                               MCAN_IR_RF0L_MASK |                          \
                               MCAN_IR_RF1N_MASK |                          \
                               MCAN_IR_RF1W_MASK |                          \
                               MCAN_IR_RF1F_MASK |                          \
                               MCAN_IR_RF1L_MASK |                          \
                               MCAN_IR_HPM_MASK  |                          \
                               MCAN_IR_TC_MASK   |                          \
                               MCAN_IR_TCF_MASK  |                          \
                               MCAN_IR_TFE_MASK  |                          \
                               MCAN_IR_TEFN_MASK |                          \
                               MCAN_IR_TEFW_MASK |                          \
                               MCAN_IR_TEFF_MASK |                          \
                               MCAN_IR_TEFL_MASK |                          \
                               MCAN_IR_TSW_MASK  |                          \
                               MCAN_IR_MRAF_MASK |                          \
                               MCAN_IR_TOO_MASK  |                          \
                               MCAN_IR_DRX_MASK  |                          \
                               MCAN_IR_BEU_MASK  |                          \
                               MCAN_IR_ELO_MASK  |                          \
                               MCAN_IR_EP_MASK   |                          \
                               MCAN_IR_EW_MASK   |                          \
                               MCAN_IR_BO_MASK   |                          \
                               MCAN_IR_WDI_MASK  |                          \
                               MCAN_IR_PEA_MASK  |                          \
                               MCAN_IR_PED_MASK  |                          \
                               MCAN_IR_ARA_MASK)

#define DL_MCAN_MAX_PAYLOAD_BYTES                                          (64U)


#define DL_MCAN_INTERRUPT_ARA                                 (MCAN_IR_ARA_MASK)

#define DL_MCAN_INTERRUPT_PED                                 (MCAN_IR_PED_MASK)

#define DL_MCAN_INTERRUPT_PEA                                 (MCAN_IR_PEA_MASK)

#define DL_MCAN_INTERRUPT_WDI                                 (MCAN_IR_WDI_MASK)

#define DL_MCAN_INTERRUPT_BO                                   (MCAN_IR_BO_MASK)

#define DL_MCAN_INTERRUPT_EW                                 (MCAN_IR_EW_MASK)

#define DL_MCAN_INTERRUPT_EP                                 (MCAN_IR_EP_MASK)

#define DL_MCAN_INTERRUPT_ELO                                 (MCAN_IR_ELO_MASK)

#define DL_MCAN_INTERRUPT_BEU                                 (MCAN_IR_BEU_MASK)

#define DL_MCAN_INTERRUPT_DRX                                 (MCAN_IR_DRX_MASK)

#define DL_MCAN_INTERRUPT_TOO                                 (MCAN_IR_TOO_MASK)

#define DL_MCAN_INTERRUPT_MRAF                               (MCAN_IR_MRAF_MASK)

#define DL_MCAN_INTERRUPT_TSW                                 (MCAN_IR_TSW_MASK)

#define DL_MCAN_INTERRUPT_TEFL                               (MCAN_IR_TEFL_MASK)

#define DL_MCAN_INTERRUPT_TEFF                               (MCAN_IR_TEFF_MASK)

#define DL_MCAN_INTERRUPT_TEFW                               (MCAN_IR_TEFW_MASK)

#define DL_MCAN_INTERRUPT_TEFN                               (MCAN_IR_TEFN_MASK)

#define DL_MCAN_INTERRUPT_TFE                                 (MCAN_IR_TFE_MASK)

#define DL_MCAN_INTERRUPT_TCF                                 (MCAN_IR_TCF_MASK)

#define DL_MCAN_INTERRUPT_TC                                   (MCAN_IR_TC_MASK)

#define DL_MCAN_INTERRUPT_HPM                                 (MCAN_IR_HPM_MASK)

#define DL_MCAN_INTERRUPT_RF1L                               (MCAN_IR_RF1L_MASK)

#define DL_MCAN_INTERRUPT_RF1F                               (MCAN_IR_RF1F_MASK)

#define DL_MCAN_INTERRUPT_RF1W                               (MCAN_IR_RF1W_MASK)

#define DL_MCAN_INTERRUPT_RF1N                               (MCAN_IR_RF1N_MASK)

#define DL_MCAN_INTERRUPT_RF0L                               (MCAN_IR_RF0L_MASK)

#define DL_MCAN_INTERRUPT_RF0F                               (MCAN_IR_RF0F_MASK)

#define DL_MCAN_INTERRUPT_RF0W                               (MCAN_IR_RF0W_MASK)

#define DL_MCAN_INTERRUPT_RF0N                               (MCAN_IR_RF0N_MASK)

#define DL_MCAN_MSP_INTERRUPT_WAKEUP                     (MCAN_IMASK_WAKEUP_SET)

#define DL_MCAN_MSP_INTERRUPT_TIMESTAMP_OVERFLOW (MCAN_IMASK_EXT_TS_CNTR_OVFL_SET)

#define DL_MCAN_MSP_INTERRUPT_DOUBLE_ERROR_DETECTION        (MCAN_IMASK_DED_SET)

#define DL_MCAN_MSP_INTERRUPT_SINGLE_ERROR_CORRECTION       (MCAN_IMASK_SEC_SET)

#define DL_MCAN_MSP_INTERRUPT_LINE1                       (MCAN_IMASK_INTL1_SET)

#define DL_MCAN_MSP_INTERRUPT_LINE0                       (MCAN_IMASK_INTL0_SET)

#define DL_MCAN_INTR_SRC_RX_FIFO0_NEW_MSG                    (MCAN_IR_RF0N_MASK)

#define DL_MCAN_INTR_SRC_RX_FIFO0_WATERMARK                  (MCAN_IR_RF0W_MASK)

#define DL_MCAN_INTR_SRC_RX_FIFO0_FULL                       (MCAN_IR_RF0F_MASK)

#define DL_MCAN_INTR_SRC_RX_FIFO0_MSG_LOST                   (MCAN_IR_RF0L_MASK)

#define DL_MCAN_INTR_SRC_RX_FIFO1_NEW_MSG                    (MCAN_IR_RF1N_MASK)

#define DL_MCAN_INTR_SRC_RX_FIFO1_WATERMARK                  (MCAN_IR_RF1W_MASK)

#define DL_MCAN_INTR_SRC_RX_FIFO1_FULL                       (MCAN_IR_RF1F_MASK)

#define DL_MCAN_INTR_SRC_RX_FIFO1_MSG_LOST                   (MCAN_IR_RF1L_MASK)

#define DL_MCAN_INTR_SRC_HIGH_PRIO_MSG                        (MCAN_IR_HPM_MASK)

#define DL_MCAN_INTR_SRC_TRANS_COMPLETE                        (MCAN_IR_TC_MASK)

#define DL_MCAN_INTR_SRC_TRANS_CANCEL_FINISH                  (MCAN_IR_TCF_MASK)

#define DL_MCAN_INTR_SRC_TX_FIFO_EMPTY                        (MCAN_IR_TFE_MASK)

#define DL_MCAN_INTR_SRC_TX_EVT_FIFO_NEW_ENTRY               (MCAN_IR_TEFN_MASK)

#define DL_MCAN_INTR_SRC_TX_EVT_FIFO_WATERMARK               (MCAN_IR_TEFW_MASK)

#define DL_MCAN_INTR_SRC_TX_EVT_FIFO_FULL                    (MCAN_IR_TEFF_MASK)

#define DL_MCAN_INTR_SRC_TX_EVT_FIFO_ELEM_LOST               (MCAN_IR_TEFL_MASK)

#define DL_MCAN_INTR_SRC_TIMESTAMP_WRAPAROUND                 (MCAN_IR_TSW_MASK)

#define DL_MCAN_INTR_SRC_MSG_RAM_ACCESS_FAILURE              (MCAN_IR_MRAF_MASK)

#define DL_MCAN_INTR_SRC_TIMEOUT                              (MCAN_IR_TOO_MASK)

#define DL_MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG                (MCAN_IR_DRX_MASK)

#define DL_MCAN_INTR_SRC_BIT_ERR_UNCORRECTED                  (MCAN_IR_BEU_MASK)

#define DL_MCAN_INTR_SRC_ERR_LOG_OVRFLW                       (MCAN_IR_ELO_MASK)

#define DL_MCAN_INTR_SRC_ERR_PASSIVE                           (MCAN_IR_EP_MASK)

#define DL_MCAN_INTR_SRC_WARNING_STATUS                        (MCAN_IR_EW_MASK)

#define DL_MCAN_INTR_SRC_BUS_OFF_STATUS                        (MCAN_IR_BO_MASK)

#define DL_MCAN_INTR_SRC_WATCHDOG                             (MCAN_IR_WDI_MASK)

#define DL_MCAN_INTR_SRC_PROTOCOL_ERR_ARB                     (MCAN_IR_PEA_MASK)

#define DL_MCAN_INTR_SRC_PROTOCOL_ERR_DATA                    (MCAN_IR_PED_MASK)

#define DL_MCAN_INTR_SRC_RES_ADDR_ACCESS                      (MCAN_IR_ARA_MASK)

/* User defined ranges */
#define DL_MCAN_DBTP_DSJW_MAX                                             (0xFU)

#define DL_MCAN_DBTP_DTSEG2_MAX                                           (0xFU)

#define DL_MCAN_DBTP_DTSEG1_MAX                                          (0x1FU)

#define DL_MCAN_DBTP_DBRP_MAX                                            (0x1FU)

#define DL_MCAN_NBTP_NSJW_MAX                                            (0x7FU)

#define DL_MCAN_NBTP_NTSEG2_MAX                                          (0x7FU)

#define DL_MCAN_NBTP_NTSEG1_MAX                                          (0xFFU)

#define DL_MCAN_NBTP_NBRP_MAX                                           (0x1FFU)

#define DL_MCAN_RWD_WDC_MAX                                              (0xFFU)

#define DL_MCAN_TDCR_TDCF_MAX                                            (0x7FU)

#define DL_MCAN_TDCR_TDCO_MAX                                            (0x7FU)

#define DL_MCAN_XIDAM_EIDM_MAX                                     (0x1FFFFFFFU)

#define DL_MCAN_TSCC_TCP_MAX                                              (0xFU)

#define DL_MCAN_TOCC_TOP_MAX                                           (0xFFFFU)

/* clang-format on */

typedef enum {
    DL_MCAN_INSTANCE_0 = SYSCTL_SYSSTATUS_MCAN0READY_MASK,
} DL_MCAN_INSTANCE;

typedef enum {
    DL_MCAN_FCLK_SYSPLLCLK1 = SYSCTL_GENCLKCFG_CANCLKSRC_SYSPLLOUT1,
    DL_MCAN_FCLK_HFCLK = SYSCTL_GENCLKCFG_CANCLKSRC_HFCLK,
} DL_MCAN_FCLK;

typedef enum {
    DL_MCAN_FCLK_DIV_1 = MCAN_CLKDIV_RATIO_DIV_BY_1_,
    DL_MCAN_FCLK_DIV_2 = MCAN_CLKDIV_RATIO_DIV_BY_2_,
    DL_MCAN_FCLK_DIV_4 = MCAN_CLKDIV_RATIO_DIV_BY_4_,
} DL_MCAN_FCLK_DIV;

typedef enum {
    DL_MCAN_INTR_LINE_NUM_0 = 0U,
    DL_MCAN_INTR_LINE_NUM_1 = 1U

} DL_MCAN_INTR_LINE_NUM;

typedef enum {

    DL_MCAN_ID_TYPE_11_BIT = 0U,
    DL_MCAN_ID_TYPE_29_BIT = 1U

} DL_MCAN_ID_TYPE;

typedef enum {
    DL_MCAN_OPERATION_MODE_NORMAL = 0U,
    DL_MCAN_OPERATION_MODE_SW_INIT = 1U

} DL_MCAN_OPERATION_MODE;

typedef enum {
    DL_MCAN_MEM_TYPE_BUF = 0U,
    DL_MCAN_MEM_TYPE_FIFO = 1U

} DL_MCAN_MEM_TYPE;

typedef enum {
    DL_MCAN_RX_FIFO_NUM_0 = 0U,
    DL_MCAN_RX_FIFO_NUM_1 = 1U
} DL_MCAN_RX_FIFO_NUM;

typedef enum {
    DL_MCAN_PIN_TYPE_RX = 0U,
    DL_MCAN_PIN_TYPE_TX = 1U
} DL_MCAN_PIN_TYPE;

typedef enum {
    DL_MCAN_ELEM_SIZE_8BYTES = 0U,
    DL_MCAN_ELEM_SIZE_12BYTES = 1U,
    DL_MCAN_ELEM_SIZE_16BYTES = 2U,
    DL_MCAN_ELEM_SIZE_20BYTES = 3U,
    DL_MCAN_ELEM_SIZE_24BYTES = 4U,
    DL_MCAN_ELEM_SIZE_32BYTES = 5U,
    DL_MCAN_ELEM_SIZE_48BYTES = 6U,
    DL_MCAN_ELEM_SIZE_64BYTES = 7U
} DL_MCAN_ELEM_SIZE;

typedef enum {
    DL_MCAN_TIMEOUT_SELECT_CONT = 0U,
    DL_MCAN_TIMEOUT_SELECT_TX_EVENT_FIFO = 1U,
    DL_MCAN_TIMEOUT_SELECT_RX_FIFO0 = 2U,
    DL_MCAN_TIMEOUT_SELECT_RX_FIFO1 = 3U

} DL_MCAN_TIMEOUT_SELECT;

typedef enum {
    DL_MCAN_INTR_SRC_MCAN_EXT_TS = 0x0,
    DL_MCAN_INTR_SRC_MCAN_LINE_0 = 0x1,
    DL_MCAN_INTR_SRC_MCAN_LINE_1 = 0x2,
} DL_MCAN_INTR_SRC_MCAN;

typedef enum {
    DL_MCAN_ECC_ERR_TYPE_SEC = 0U,
    DL_MCAN_ECC_ERR_TYPE_DED = 1U

} DL_MCAN_ECC_ERR_TYPE;

typedef enum {
    DL_MCAN_LPBK_MODE_INTERNAL = 0U,
    DL_MCAN_LPBK_MODE_EXTERNAL = 1U

} DL_MCAN_LPBK_MODE;

typedef enum {
    DL_MCAN_COM_STATE_SYNCHRONIZING = 0U,
    DL_MCAN_COM_STATE_IDLE = 1U,
    DL_MCAN_COM_STATE_RECEIVER = 2U,
    DL_MCAN_COM_STATE_TRANSMITTER = 3U
} DL_MCAN_COM_STATE;

typedef enum {
    DL_MCAN_ERR_CODE_NO_ERROR = 0U,
    DL_MCAN_ERR_CODE_STUFF_ERROR = 1U,
    DL_MCAN_ERR_CODE_FORM_ERROR = 2U,
    DL_MCAN_ERR_CODE_ACK_ERROR = 3U,
    DL_MCAN_ERR_CODE_BIT1_ERROR = 4U,
    DL_MCAN_ERR_CODE_BIT0_ERROR = 5U,
    DL_MCAN_ERR_CODE_CRC_ERROR = 6U,
    DL_MCAN_ERR_CODE_NO_CHANGE = 7U

} DL_MCAN_ERR_CODE;

typedef struct {
    DL_MCAN_FCLK clockSel;
    DL_MCAN_FCLK_DIV divider;
} DL_MCAN_ClockConfig;

typedef struct {
    uint32_t nomRatePrescalar;
    uint32_t nomTimeSeg1;
    uint32_t nomTimeSeg2;
    uint32_t nomSynchJumpWidth;
    uint32_t dataRatePrescalar;
    uint32_t dataTimeSeg1;
    uint32_t dataTimeSeg2;
    uint32_t dataSynchJumpWidth;
} DL_MCAN_BitTimingParams;

typedef struct {
    uint32_t tdcf;
    uint32_t tdco;
} DL_MCAN_TDCConfig;

typedef struct {
    uint32_t rrfe;
    uint32_t rrfs;
    uint32_t anfe;
    uint32_t anfs;
} DL_MCAN_GlobalFiltConfig;

typedef struct {
    uint32_t fdMode;
    uint32_t brsEnable;
    uint32_t txpEnable;
    uint32_t efbi;
    uint32_t pxhddisable;
    uint32_t darEnable;
    uint32_t wkupReqEnable;
    uint32_t autoWkupEnable;
    uint32_t emulationEnable;
    uint32_t wdcPreload;
    DL_MCAN_TDCConfig tdcConfig;
    uint32_t tdcEnable;
} DL_MCAN_InitParams;

typedef struct {
    uint32_t monEnable;
    uint32_t asmEnable;
    uint32_t tsPrescalar;
    uint32_t tsSelect;
    uint32_t timeoutSelect;
    uint32_t timeoutPreload;
    uint32_t timeoutCntEnable;
    DL_MCAN_GlobalFiltConfig filterConfig;
} DL_MCAN_ConfigParams;

typedef struct {
    uint32_t transErrLogCnt;
    uint32_t recErrCnt;
    uint32_t rpStatus;
    uint32_t canErrLogCnt;
} DL_MCAN_ErrCntStatus;

typedef struct {
    uint32_t lastErrCode;
    uint32_t act;
    uint32_t errPassive;
    uint32_t warningStatus;
    uint32_t busOffStatus;
    uint32_t dlec;
    uint32_t resi;
    uint32_t rbrs;
    uint32_t rfdf;
    uint32_t pxe;
    uint32_t tdcv;
} DL_MCAN_ProtocolStatus;

typedef struct {
    uint32_t flssa;
    uint32_t lss;
    uint32_t flesa;
    uint32_t lse;
    uint32_t txStartAddr;
    uint32_t txBufNum;
    uint32_t txFIFOSize;
    uint32_t txBufMode;
    uint32_t txBufElemSize;
    uint32_t txEventFIFOStartAddr;
    uint32_t txEventFIFOSize;
    uint32_t txEventFIFOWaterMark;
    uint32_t rxFIFO0startAddr;
    uint32_t rxFIFO0size;
    uint32_t rxFIFO0waterMark;
    uint32_t rxFIFO0OpMode;
    uint32_t rxFIFO1startAddr;
    uint32_t rxFIFO1size;
    uint32_t rxFIFO1waterMark;
    uint32_t rxFIFO1OpMode;
    uint32_t rxBufStartAddr;
    uint32_t rxBufElemSize;
    uint32_t rxFIFO0ElemSize;
    uint32_t rxFIFO1ElemSize;
} DL_MCAN_MsgRAMConfigParams;

typedef struct {
    uint32_t bufIdx;
    uint32_t msi;
    uint32_t filterIdx;
    uint32_t filterList;
} DL_MCAN_HighPriorityMsgInfo;

typedef struct {
    uint32_t statusLow;
    uint32_t statusHigh;
} DL_MCAN_RxNewDataStatus;

typedef struct {
    uint32_t num;
    uint32_t fillLvl;
    uint32_t getIdx;
    uint32_t putIdx;
    uint32_t fifoFull;
    uint32_t msgLost;
} DL_MCAN_RxFIFOStatus;

typedef struct {
    uint32_t freeLvl;
    uint32_t getIdx;
    uint32_t putIdx;
    uint32_t fifoFull;
} DL_MCAN_TxFIFOStatus;

typedef struct {
    uint32_t fillLvl;
    uint32_t getIdx;
    uint32_t putIdx;
    uint32_t fifoFull;
    uint32_t eleLost;
} DL_MCAN_TxEventFIFOStatus;

typedef struct {
    uint32_t errType;
    uint32_t rowNum;
    uint32_t bit1;
    uint32_t bit2;
    uint32_t errOnce;
    uint32_t errForce;
} DL_MCAN_ECCErrForceParams;

typedef struct {
    uint32_t secErr;
    uint32_t dedErr;
    uint32_t row;
    uint32_t bit1;

} DL_MCAN_ECCErrStatus;

typedef struct {
    uint32_t scheme;
    uint32_t modId;
    uint32_t major;
    uint32_t minor;
    uint32_t day;
    uint32_t mon;
    uint32_t year;
    uint32_t subStep;
    uint32_t step;
    uint32_t rel;
} DL_MCAN_RevisionId;

typedef struct {
    uint32_t scheme;
    uint32_t modId;
    uint32_t major;
    uint32_t minor;
} DL_MCAN_ECCAggrRevisionId;

typedef struct {
    uint32_t enable;
    uint32_t enableChk;
    uint32_t enableRdModWr;
} DL_MCAN_ECCConfigParams;

typedef struct {
    uint32_t scheme;
    uint32_t modId;
    uint32_t major;
    uint32_t minor;
} DL_MCAN_ECCWrapRevisionId;

typedef struct {
    uint32_t id;
    uint32_t rtr;
    uint32_t xtd;
    uint32_t esi;
    uint32_t dlc;
    uint32_t brs;
    uint32_t fdf;
    uint32_t efc;
    uint32_t mm;
    uint8_t data[DL_MCAN_MAX_PAYLOAD_BYTES];
} DL_MCAN_TxBufElement;

typedef struct {
    uint32_t id;
    uint32_t rtr;
    uint32_t xtd;
    uint32_t esi;
    uint32_t rxts;
    uint32_t dlc;
    uint32_t brs;
    uint32_t fdf;
    uint32_t fidx;
    uint32_t anmf;
    uint8_t data[DL_MCAN_MAX_PAYLOAD_BYTES];
} DL_MCAN_RxBufElement;

typedef struct {
    uint32_t id;
    uint32_t rtr;
    uint32_t xtd;
    uint32_t esi;
    uint32_t txts;
    uint32_t dlc;
    uint32_t brs;
    uint32_t fdf;
    uint32_t et;
    uint32_t mm;
} DL_MCAN_TxEventFIFOElement;

typedef struct {
    uint32_t sfid2;
    uint32_t sfid1;
    uint32_t sfec;
    uint32_t sft;
} DL_MCAN_StdMsgIDFilterElement;

typedef struct {
    uint32_t efid1;
    uint32_t efec;
    uint32_t efid2;
    uint32_t eft;
} DL_MCAN_ExtMsgIDFilterElement;

typedef struct {
    uint32_t clkDivConf;

    uint32_t clkConf;

    uint32_t clkEnConf;

    uint32_t ctrlConf;

    uint32_t nomBitTimeConf;

    uint32_t dataBitTimeConf;

    uint32_t timeCntConf;

    uint32_t timeCntVal;

    uint32_t timeOutConf;

    uint32_t timeOutCntVal;

    uint32_t txDelCompConf;

    uint32_t intEnConf;

    uint32_t intLnSelConf;

    uint32_t intLnEnableConf;

    uint32_t globFiltIDConf;

    uint32_t stdFiltIDConf;

    uint32_t exFiltIDConf;

    uint32_t exFiltIDMsk;

    uint32_t rxFIFO0Conf;

    uint32_t rxBuffConf;

    uint32_t rxFIFO1Conf;

    uint32_t rxDataSize;

    uint32_t txBuffConf;

    uint32_t txDataSize;

    uint32_t txBuffTxIntConf;

    uint32_t txBuffCancIntConf;

    uint32_t txEvntFIFOConf;

    uint32_t ssCtrlConf;

    uint32_t ssIntEnConf;

    uint32_t preSclConf;

    uint32_t edcVecConf;

    uint32_t edcConf2;

    uint32_t edcConf1;

    uint32_t edcConf0;

    uint32_t intEvnt0Conf;

    uint32_t ramWDConf;

    uint32_t testConf;

    bool backupRdy;
} DL_MCAN_backupConfig;

typedef enum {
    DL_MCAN_CLOCK_DIVIDE_1 = MCAN_CLKDIV_RATIO_DIV_BY_1_,
    DL_MCAN_CLOCK_DIVIDE_2 = MCAN_CLKDIV_RATIO_DIV_BY_2_,
    DL_MCAN_CLOCK_DIVIDE_4 = MCAN_CLKDIV_RATIO_DIV_BY_4_
} DL_MCAN_CLOCK_DIVIDE;

typedef enum {
    DL_MCAN_IIDX_WAKEUP = MCAN_IIDX_STAT_WAKEUP,
    DL_MCAN_IIDX_TIMESTAMP_OVERFLOW = MCAN_IIDX_STAT_EXT_TS_CNTR_OVFL,
    DL_MCAN_IIDX_DOUBLE_ERROR_DETECTION = MCAN_IIDX_STAT_DED,
    DL_MCAN_IIDX_SINGLE_ERROR_CORRECTION = MCAN_IIDX_STAT_SEC,
    DL_MCAN_IIDX_LINE1 = MCAN_IIDX_STAT_INTL1,
    DL_MCAN_IIDX_LINE0 = MCAN_IIDX_STAT_INTL0
} DL_MCAN_IIDX;

bool DL_MCAN_isReady(DL_MCAN_INSTANCE instance);

void DL_MCAN_setClockConfig(
    MCAN_Regs *mcan, const DL_MCAN_ClockConfig *config);

void DL_MCAN_getClockConfig(MCAN_Regs *mcan, DL_MCAN_ClockConfig *config);
bool DL_MCAN_isInReset(const MCAN_Regs *mcan);

bool DL_MCAN_isFDOpEnable(const MCAN_Regs *mcan);

bool DL_MCAN_isMemInitDone(const MCAN_Regs *mcan);

void DL_MCAN_setOpMode(MCAN_Regs *mcan, uint32_t mode);

uint32_t DL_MCAN_getOpMode(const MCAN_Regs *mcan);

int32_t DL_MCAN_init(MCAN_Regs *mcan, const DL_MCAN_InitParams *initParams);

int32_t DL_MCAN_config(
    MCAN_Regs *mcan, const DL_MCAN_ConfigParams *configParams);

void DL_MCAN_eccConfig(
    MCAN_Regs *mcan, const DL_MCAN_ECCConfigParams *configParams);

int32_t DL_MCAN_setBitTime(
    MCAN_Regs *mcan, const DL_MCAN_BitTimingParams *configParams);

int32_t DL_MCAN_msgRAMConfig(
    MCAN_Regs *mcan, const DL_MCAN_MsgRAMConfigParams *msgRAMConfigParams);

int32_t DL_MCAN_setExtIDAndMask(MCAN_Regs *mcan, uint32_t idMask);

void DL_MCAN_writeMsgRam(MCAN_Regs *mcan, uint32_t memType, uint32_t bufNum,
    const DL_MCAN_TxBufElement *elem);

int32_t DL_MCAN_TXBufAddReq(MCAN_Regs *mcan, uint32_t bufNum);

void DL_MCAN_getNewDataStatus(
    const MCAN_Regs *mcan, DL_MCAN_RxNewDataStatus *newDataStatus);

void DL_MCAN_clearNewDataStatus(
    MCAN_Regs *mcan, const DL_MCAN_RxNewDataStatus *newDataStatus);

void DL_MCAN_readMsgRam(const MCAN_Regs *mcan, uint32_t memType,
    uint32_t bufNum, uint32_t fifoNum, DL_MCAN_RxBufElement *elem);

void DL_MCAN_readTxEventFIFO(
    const MCAN_Regs *mcan, DL_MCAN_TxEventFIFOElement *txEventElem);

void DL_MCAN_addStdMsgIDFilter(MCAN_Regs *mcan, uint32_t filtNum,
    const DL_MCAN_StdMsgIDFilterElement *elem);

void DL_MCAN_addExtMsgIDFilter(MCAN_Regs *mcan, uint32_t filtNum,
    const DL_MCAN_ExtMsgIDFilterElement *elem);

void DL_MCAN_lpbkModeEnable(MCAN_Regs *mcan, uint32_t lpbkMode, bool enable);

void DL_MCAN_getErrCounters(
    const MCAN_Regs *mcan, DL_MCAN_ErrCntStatus *errCounter);

void DL_MCAN_getProtocolStatus(
    const MCAN_Regs *mcan, DL_MCAN_ProtocolStatus *protStatus);

void DL_MCAN_enableIntr(MCAN_Regs *mcan, uint32_t intrMask, bool enable);

void DL_MCAN_selectIntrLine(
    MCAN_Regs *mcan, uint32_t intrMask, uint32_t lineNum);

uint32_t DL_MCAN_getIntrLineSelectStatus(const MCAN_Regs *mcan);

void DL_MCAN_enableIntrLine(MCAN_Regs *mcan, uint32_t lineNum, bool enable);

uint32_t DL_MCAN_getIntrStatus(const MCAN_Regs *mcan);

void DL_MCAN_clearIntrStatus(
    MCAN_Regs *mcan, uint32_t intrMask, DL_MCAN_INTR_SRC_MCAN eoi);

void DL_MCAN_getHighPriorityMsgStatus(
    const MCAN_Regs *mcan, DL_MCAN_HighPriorityMsgInfo *hpm);

void DL_MCAN_getRxFIFOStatus(
    const MCAN_Regs *mcan, DL_MCAN_RxFIFOStatus *fifoStatus);

int32_t DL_MCAN_writeRxFIFOAck(
    MCAN_Regs *mcan, uint32_t fifoNum, uint32_t idx);

void DL_MCAN_getTxFIFOQueStatus(
    const MCAN_Regs *mcan, DL_MCAN_TxFIFOStatus *fifoStatus);

uint32_t DL_MCAN_getTxBufReqPend(const MCAN_Regs *mcan);

int32_t DL_MCAN_txBufCancellationReq(MCAN_Regs *mcan, uint32_t buffNum);

uint32_t DL_MCAN_getTxBufTransmissionStatus(const MCAN_Regs *mcan);

uint32_t DL_MCAN_txBufCancellationStatus(const MCAN_Regs *mcan);

int32_t DL_MCAN_TXBufTransIntrEnable(
    MCAN_Regs *mcan, uint32_t bufNum, bool enable);

int32_t DL_MCAN_getTxBufCancellationIntrEnable(
    const MCAN_Regs *mcan, uint32_t bufNum, bool enable);

void DL_MCAN_addClockStopRequest(MCAN_Regs *mcan, bool enable);

void DL_MCAN_getTxEventFIFOStatus(
    const MCAN_Regs *mcan, DL_MCAN_TxEventFIFOStatus *fifoStatus);

int32_t DL_MCAN_writeTxEventFIFOAck(MCAN_Regs *mcan, uint32_t idx);

void DL_MCAN_eccForceError(
    MCAN_Regs *mcan, const DL_MCAN_ECCErrForceParams *eccErr);

void DL_MCAN_eccGetErrorStatus(MCAN_Regs *mcan, DL_MCAN_ECCErrStatus *eccErr);

void DL_MCAN_eccClearErrorStatus(MCAN_Regs *mcan, uint32_t errType);

void DL_MCAN_eccWriteEOI(MCAN_Regs *mcan, uint32_t errType);

void DL_MCAN_eccEnableIntr(MCAN_Regs *mcan, uint32_t errType, bool enable);

uint32_t DL_MCAN_eccGetIntrStatus(const MCAN_Regs *mcan, uint32_t errType);

void DL_MCAN_eccClearIntrStatus(MCAN_Regs *mcan, uint32_t errType);

void DL_MCAN_extTSCounterConfig(MCAN_Regs *mcan, uint32_t prescalar);

void DL_MCAN_extTSCounterEnable(MCAN_Regs *mcan, bool enable);

void DL_MCAN_extTSEnableIntr(MCAN_Regs *mcan, bool enable);

void DL_MCAN_extTSWriteEOI(MCAN_Regs *mcan);

uint32_t DL_MCAN_extTSGetUnservicedIntrCount(const MCAN_Regs *mcan);

/* ========================================================================== */
/*                          Advance Functions                                 */
/* ========================================================================== */

void DL_MCAN_getRevisionId(const MCAN_Regs *mcan, DL_MCAN_RevisionId *revId);

uint32_t DL_MCAN_getClockStopAck(const MCAN_Regs *mcan);

void DL_MCAN_extTSSetRawStatus(MCAN_Regs *mcan);

void DL_MCAN_extTSClearRawStatus(MCAN_Regs *mcan);

uint32_t DL_MCAN_getRxPinState(const MCAN_Regs *mcan);

void DL_MCAN_setTxPinState(MCAN_Regs *mcan, uint32_t state);

uint32_t DL_MCAN_getTxPinState(const MCAN_Regs *mcan);

uint32_t DL_MCAN_getTSCounterVal(const MCAN_Regs *mcan);

uint32_t DL_MCAN_getClkStopAck(const MCAN_Regs *mcan);

void DL_MCAN_getBitTime(
    const MCAN_Regs *mcan, DL_MCAN_BitTimingParams *configParams);

void DL_MCAN_resetTSCounter(MCAN_Regs *mcan);

uint32_t DL_MCAN_getTOCounterVal(const MCAN_Regs *mcan);

void DL_MCAN_eccAggrGetRevisionId(
    const MCAN_Regs *mcan, DL_MCAN_ECCAggrRevisionId *revId);

void DL_MCAN_eccWrapGetRevisionId(
    MCAN_Regs *mcan, DL_MCAN_ECCWrapRevisionId *revId);

bool DL_MCAN_extTSIsIntrEnable(const MCAN_Regs *mcan);

uint32_t DL_MCAN_getEndianVal(const MCAN_Regs *mcan);

uint32_t DL_MCAN_getExtIDANDMask(const MCAN_Regs *mcan);

__STATIC_INLINE void DL_MCAN_enablePower(MCAN_Regs *mcan)
{
    mcan->MCANSS.PWREN = (MCAN_PWREN_KEY_UNLOCK_W | MCAN_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_MCAN_disablePower(MCAN_Regs *mcan)
{
    mcan->MCANSS.PWREN = (MCAN_PWREN_KEY_UNLOCK_W | MCAN_PWREN_ENABLE_DISABLE);
}

__STATIC_INLINE bool DL_MCAN_isPowerEnabled(const MCAN_Regs *mcan)
{
    return ((mcan->MCANSS.PWREN & MCAN_PWREN_ENABLE_MASK) ==
            MCAN_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_MCAN_reset(MCAN_Regs *mcan)
{
    mcan->MCANSS.RSTCTL =
        (MCAN_RSTCTL_KEY_UNLOCK_W | MCAN_RSTCTL_RESETSTKYCLR_CLR |
            MCAN_RSTCTL_RESETASSERT_ASSERT);
}

__STATIC_INLINE bool DL_MCAN_isReset(const MCAN_Regs *mcan)
{
    return ((mcan->MCANSS.STAT & MCAN_STAT_RESETSTKY_MASK) ==
            MCAN_STAT_RESETSTKY_RESET);
}

__STATIC_INLINE void DL_MCAN_enableInterrupt(
    MCAN_Regs *mcan, uint32_t interruptMask)
{
    mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.IMASK |= interruptMask;
}

__STATIC_INLINE void DL_MCAN_disableInterrupt(
    MCAN_Regs *mcan, uint32_t interruptMask)
{
    mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.IMASK &= ~(interruptMask);
}

__STATIC_INLINE uint32_t DL_MCAN_getEnabledInterrupts(
    const MCAN_Regs *mcan, uint32_t interruptMask)
{
    return (mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.IMASK & interruptMask);
}

__STATIC_INLINE uint32_t DL_MCAN_getEnabledInterruptStatus(
    const MCAN_Regs *mcan, uint32_t interruptMask)
{
    return (mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.MIS & interruptMask);
}

__STATIC_INLINE uint32_t DL_MCAN_getRawInterruptStatus(
    const MCAN_Regs *mcan, uint32_t interruptMask)
{
    return (mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.RIS & interruptMask);
}

__STATIC_INLINE DL_MCAN_IIDX DL_MCAN_getPendingInterrupt(const MCAN_Regs *mcan)
{
    // TODO: Need to figure out return values for this.
    return ((DL_MCAN_IIDX) mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.IIDX);
}

__STATIC_INLINE void DL_MCAN_clearInterruptStatus(
    MCAN_Regs *mcan, uint32_t interruptMask)
{
    mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.ICLR = interruptMask;
}

__STATIC_INLINE bool DL_MCAN_isModuleClockEnabled(const MCAN_Regs *mcan)
{
    return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKEN &
                MCAN_CLKEN_CLK_REQEN_MASK) == MCAN_CLKEN_CLK_REQEN_SET);
}

__STATIC_INLINE void DL_MCAN_enableModuleClock(MCAN_Regs *mcan)
{
    mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKEN = MCAN_CLKEN_CLK_REQEN_SET;
}

__STATIC_INLINE void DL_MCAN_disableModuleClock(MCAN_Regs *mcan)
{
    mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKEN = MCAN_CLKEN_CLK_REQEN_CLR;
}

__STATIC_INLINE uint32_t DL_MCAN_getModuleClockDivider(const MCAN_Regs *mcan)
{
    return (
        mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKDIV & MCAN_CLKDIV_RATIO_MASK);
}

__STATIC_INLINE void DL_MCAN_setModuleClockDivider(
    MCAN_Regs *mcan, uint32_t clkdiv)
{
    DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKDIV, clkdiv,
        MCAN_CLKDIV_RATIO_MASK);
}

__STATIC_INLINE bool DL_MCAN_isClockStopGateRequestEnabled(
    const MCAN_Regs *mcan)
{
    return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL &
                MCAN_CLKCTL_STOPREQ_MASK) == MCAN_CLKCTL_STOPREQ_ENABLE);
}

__STATIC_INLINE void DL_MCAN_enableClockStopGateRequest(MCAN_Regs *mcan)
{
    DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
        MCAN_CLKCTL_STOPREQ_ENABLE, MCAN_CLKCTL_STOPREQ_MASK);
}

__STATIC_INLINE void DL_MCAN_disableClockStopGateRequest(MCAN_Regs *mcan)
{
    DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
        MCAN_CLKCTL_STOPREQ_DISABLE, MCAN_CLKCTL_STOPREQ_MASK);
}

__STATIC_INLINE bool DL_MCAN_isClockStopWakeupInterruptEnabled(
    const MCAN_Regs *mcan)
{
    return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL &
                MCAN_CLKCTL_WAKEUP_INT_EN_MASK) ==
            MCAN_CLKCTL_WAKEUP_INT_EN_ENABLE);
}

__STATIC_INLINE void DL_MCAN_enableClockStopWakeupInterrupt(MCAN_Regs *mcan)
{
    DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
        MCAN_CLKCTL_WAKEUP_INT_EN_ENABLE, MCAN_CLKCTL_WAKEUP_INT_EN_MASK);
}

__STATIC_INLINE void DL_MCAN_disableClockStopWakeupInterrupt(MCAN_Regs *mcan)
{
    DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
        MCAN_CLKCTL_WAKEUP_INT_EN_DISABLE, MCAN_CLKCTL_WAKEUP_INT_EN_MASK);
}

__STATIC_INLINE bool DL_MCAN_isGlitchFilterWakeupEnabled(const MCAN_Regs *mcan)
{
    return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL &
                MCAN_CLKCTL_WKUP_GLTFLT_EN_MASK) ==
            MCAN_CLKCTL_WKUP_GLTFLT_EN_ENABLE);
}

__STATIC_INLINE void DL_MCAN_enableGlitchFilterWakeup(MCAN_Regs *mcan)
{
    DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
        MCAN_CLKCTL_WKUP_GLTFLT_EN_ENABLE, MCAN_CLKCTL_WKUP_GLTFLT_EN_MASK);
}

__STATIC_INLINE void DL_MCAN_disableGlitchFilterWakeup(MCAN_Regs *mcan)
{
    DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
        MCAN_CLKCTL_WKUP_GLTFLT_EN_DISABLE, MCAN_CLKCTL_WKUP_GLTFLT_EN_MASK);
}

__STATIC_INLINE bool DL_MCAN_getClockStopAcknowledgeStatus(
    const MCAN_Regs *mcan)
{
    return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKSTS &
                MCAN_CLKSTS_CLKSTOP_ACKSTS_MASK) ==
            MCAN_CLKSTS_CLKSTOP_ACKSTS_SET);
}

__STATIC_INLINE bool DL_MCAN_getClockStopHardwareOverrideStatus(
    const MCAN_Regs *mcan)
{
    return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKSTS &
                MCAN_CLKSTS_STOPREQ_HW_OVR_MASK) ==
            MCAN_CLKSTS_STOPREQ_HW_OVR_SET);
}

__STATIC_INLINE bool DL_MCAN_getControllerClockRequestStatus(
    const MCAN_Regs *mcan)
{
    return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKSTS &
                MCAN_CLKSTS_CCLKDONE_MASK) == MCAN_CLKSTS_CCLKDONE_SET);
}

bool DL_MCAN_saveConfiguration(
    const MCAN_Regs *mcan, DL_MCAN_backupConfig *ptr);

bool DL_MCAN_restoreConfiguration(MCAN_Regs *mcan, DL_MCAN_backupConfig *ptr);

#ifdef __cplusplus
}
#endif

#endif /* __MSPM0_HAS_MCAN__ */

#endif /* ti_dl_dl_mcan__include */