dl_adc12.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/*!****************************************************************************
 *  @file       dl_adc12.h
 *  @brief      Analog to Digital Converter (ADC)
 *  @defgroup   ADC12 Analog to Digital Converter (ADC12)
 *
 *  @anchor ti_dl_dl_adc12_Overview
 *  # Overview
 *
 *  The Analog to Digital Converter Driver Library allows full configuration of
 *  the MSPM0 ADC module.
 *  The ADC is a high-performance successive-approximation-register (SAR)
 *  analog-to-digital converter.
 *
 *  <hr>
 ******************************************************************************/
#ifndef ti_dl_dl_adc12__include
#define ti_dl_dl_adc12__include

#include <math.h>
#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>
#include <ti/driverlib/m0p/dl_factoryregion.h>

#ifdef __MSPM0_HAS_ADC12__

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

#if (ADC_SYS_NUM_ANALOG_CHAN > 16)
/*
 * @brief Device has more than 16 ADC input channels
 */
#define DEVICE_HAS_GREATER_THAN_16_INPUT_CHAN
#endif

#define DL_ADC12_SEQ_END_ADDR_00                     (ADC12_CTL2_ENDADD_ADDR_00)

#define DL_ADC12_SEQ_END_ADDR_01                     (ADC12_CTL2_ENDADD_ADDR_01)

#define DL_ADC12_SEQ_END_ADDR_02                     (ADC12_CTL2_ENDADD_ADDR_02)

#define DL_ADC12_SEQ_END_ADDR_03                     (ADC12_CTL2_ENDADD_ADDR_03)

#define DL_ADC12_SEQ_END_ADDR_04                     (ADC12_CTL2_ENDADD_ADDR_04)

#define DL_ADC12_SEQ_END_ADDR_05                     (ADC12_CTL2_ENDADD_ADDR_05)

#define DL_ADC12_SEQ_END_ADDR_06                     (ADC12_CTL2_ENDADD_ADDR_06)

#define DL_ADC12_SEQ_END_ADDR_07                     (ADC12_CTL2_ENDADD_ADDR_07)

#define DL_ADC12_SEQ_END_ADDR_08                     (ADC12_CTL2_ENDADD_ADDR_08)

#define DL_ADC12_SEQ_END_ADDR_09                     (ADC12_CTL2_ENDADD_ADDR_09)

#define DL_ADC12_SEQ_END_ADDR_10                     (ADC12_CTL2_ENDADD_ADDR_10)

#define DL_ADC12_SEQ_END_ADDR_11                     (ADC12_CTL2_ENDADD_ADDR_11)

#define DL_ADC12_SEQ_START_ADDR_00                 (ADC12_CTL2_STARTADD_ADDR_00)

#define DL_ADC12_SEQ_START_ADDR_01                 (ADC12_CTL2_STARTADD_ADDR_01)

#define DL_ADC12_SEQ_START_ADDR_02                 (ADC12_CTL2_STARTADD_ADDR_02)

#define DL_ADC12_SEQ_START_ADDR_03                 (ADC12_CTL2_STARTADD_ADDR_03)

#define DL_ADC12_SEQ_START_ADDR_04                 (ADC12_CTL2_STARTADD_ADDR_04)

#define DL_ADC12_SEQ_START_ADDR_05                 (ADC12_CTL2_STARTADD_ADDR_05)

#define DL_ADC12_SEQ_START_ADDR_06                 (ADC12_CTL2_STARTADD_ADDR_06)

#define DL_ADC12_SEQ_START_ADDR_07                 (ADC12_CTL2_STARTADD_ADDR_07)

#define DL_ADC12_SEQ_START_ADDR_08                 (ADC12_CTL2_STARTADD_ADDR_08)

#define DL_ADC12_SEQ_START_ADDR_09                 (ADC12_CTL2_STARTADD_ADDR_09)

#define DL_ADC12_SEQ_START_ADDR_10                 (ADC12_CTL2_STARTADD_ADDR_10)

#define DL_ADC12_SEQ_START_ADDR_11                 (ADC12_CTL2_STARTADD_ADDR_11)

#define DL_ADC12_SAMP_MODE_SINGLE                     (ADC12_CTL1_CONSEQ_SINGLE)

#define DL_ADC12_SAMP_MODE_SINGLE_REPEAT        (ADC12_CTL1_CONSEQ_REPEATSINGLE)

#define DL_ADC12_SAMP_MODE_SEQUENCE                 (ADC12_CTL1_CONSEQ_SEQUENCE)

#define DL_ADC12_SAMP_MODE_SEQUENCE_REPEAT    (ADC12_CTL1_CONSEQ_REPEATSEQUENCE)

#define DL_ADC12_HW_AVG_NUM_ACC_DISABLED               (ADC12_CTL1_AVGN_DISABLE)

#define DL_ADC12_HW_AVG_NUM_ACC_2                        (ADC12_CTL1_AVGN_AVG_2)

#define DL_ADC12_HW_AVG_NUM_ACC_4                        (ADC12_CTL1_AVGN_AVG_4)

#define DL_ADC12_HW_AVG_NUM_ACC_8                        (ADC12_CTL1_AVGN_AVG_8)

#define DL_ADC12_HW_AVG_NUM_ACC_16                      (ADC12_CTL1_AVGN_AVG_16)

#define DL_ADC12_HW_AVG_NUM_ACC_32                      (ADC12_CTL1_AVGN_AVG_32)

#define DL_ADC12_HW_AVG_NUM_ACC_64                      (ADC12_CTL1_AVGN_AVG_64)

#define DL_ADC12_HW_AVG_NUM_ACC_128                    (ADC12_CTL1_AVGN_AVG_128)

#define DL_ADC12_HW_AVG_DEN_DIV_BY_1                    (ADC12_CTL1_AVGD_SHIFT0)

#define DL_ADC12_HW_AVG_DEN_DIV_BY_2                    (ADC12_CTL1_AVGD_SHIFT1)

#define DL_ADC12_HW_AVG_DEN_DIV_BY_4                    (ADC12_CTL1_AVGD_SHIFT2)

#define DL_ADC12_HW_AVG_DEN_DIV_BY_8                    (ADC12_CTL1_AVGD_SHIFT3)

#define DL_ADC12_HW_AVG_DEN_DIV_BY_16                   (ADC12_CTL1_AVGD_SHIFT4)

#define DL_ADC12_HW_AVG_DEN_DIV_BY_32                   (ADC12_CTL1_AVGD_SHIFT5)

#define DL_ADC12_HW_AVG_DEN_DIV_BY_64                   (ADC12_CTL1_AVGD_SHIFT6)

#define DL_ADC12_HW_AVG_DEN_DIV_BY_128                  (ADC12_CTL1_AVGD_SHIFT7)

#define DL_ADC12_POWER_DOWN_MODE_AUTO                    (ADC12_CTL0_PWRDN_AUTO)

#define DL_ADC12_POWER_DOWN_MODE_MANUAL                (ADC12_CTL0_PWRDN_MANUAL)

#define DL_ADC12_INPUT_CHAN_0                      (ADC12_MEMCTL_CHANSEL_CHAN_0)

#define DL_ADC12_INPUT_CHAN_1                      (ADC12_MEMCTL_CHANSEL_CHAN_1)

#define DL_ADC12_INPUT_CHAN_2                      (ADC12_MEMCTL_CHANSEL_CHAN_2)

#define DL_ADC12_INPUT_CHAN_3                      (ADC12_MEMCTL_CHANSEL_CHAN_3)

#define DL_ADC12_INPUT_CHAN_4                      (ADC12_MEMCTL_CHANSEL_CHAN_4)

#define DL_ADC12_INPUT_CHAN_5                      (ADC12_MEMCTL_CHANSEL_CHAN_5)

#define DL_ADC12_INPUT_CHAN_6                      (ADC12_MEMCTL_CHANSEL_CHAN_6)

#define DL_ADC12_INPUT_CHAN_7                      (ADC12_MEMCTL_CHANSEL_CHAN_7)

#define DL_ADC12_INPUT_CHAN_8                      (ADC12_MEMCTL_CHANSEL_CHAN_8)

#define DL_ADC12_INPUT_CHAN_9                      (ADC12_MEMCTL_CHANSEL_CHAN_9)

#define DL_ADC12_INPUT_CHAN_10                    (ADC12_MEMCTL_CHANSEL_CHAN_10)

#define DL_ADC12_INPUT_CHAN_11                    (ADC12_MEMCTL_CHANSEL_CHAN_11)

#define DL_ADC12_INPUT_CHAN_12                    (ADC12_MEMCTL_CHANSEL_CHAN_12)

#define DL_ADC12_INPUT_CHAN_13                    (ADC12_MEMCTL_CHANSEL_CHAN_13)

#define DL_ADC12_INPUT_CHAN_14                    (ADC12_MEMCTL_CHANSEL_CHAN_14)

#define DL_ADC12_INPUT_CHAN_15                    (ADC12_MEMCTL_CHANSEL_CHAN_15)

#ifdef DEVICE_HAS_GREATER_THAN_16_INPUT_CHAN

#define DL_ADC12_INPUT_CHAN_16                    (ADC12_MEMCTL_CHANSEL_CHAN_16)

#define DL_ADC12_INPUT_CHAN_17                    (ADC12_MEMCTL_CHANSEL_CHAN_17)

#define DL_ADC12_INPUT_CHAN_18                    (ADC12_MEMCTL_CHANSEL_CHAN_18)

#define DL_ADC12_INPUT_CHAN_19                    (ADC12_MEMCTL_CHANSEL_CHAN_19)

#define DL_ADC12_INPUT_CHAN_20                    (ADC12_MEMCTL_CHANSEL_CHAN_20)

#define DL_ADC12_INPUT_CHAN_21                    (ADC12_MEMCTL_CHANSEL_CHAN_21)

#define DL_ADC12_INPUT_CHAN_22                    (ADC12_MEMCTL_CHANSEL_CHAN_22)

#define DL_ADC12_INPUT_CHAN_23                    (ADC12_MEMCTL_CHANSEL_CHAN_23)

#define DL_ADC12_INPUT_CHAN_24                    (ADC12_MEMCTL_CHANSEL_CHAN_24)

#define DL_ADC12_INPUT_CHAN_25                    (ADC12_MEMCTL_CHANSEL_CHAN_25)

#define DL_ADC12_INPUT_CHAN_26                    (ADC12_MEMCTL_CHANSEL_CHAN_26)

#define DL_ADC12_INPUT_CHAN_27                    (ADC12_MEMCTL_CHANSEL_CHAN_27)

#define DL_ADC12_INPUT_CHAN_28                    (ADC12_MEMCTL_CHANSEL_CHAN_28)

#define DL_ADC12_INPUT_CHAN_29                    (ADC12_MEMCTL_CHANSEL_CHAN_29)

#define DL_ADC12_INPUT_CHAN_30                    (ADC12_MEMCTL_CHANSEL_CHAN_30)

#define DL_ADC12_INPUT_CHAN_31                    (ADC12_MEMCTL_CHANSEL_CHAN_31)

#endif /* DEVICE_HAS_GREATER_THAN_16_INPUT_CHAN */

#define DL_ADC12_REFERENCE_VOLTAGE_VDDA                (ADC12_MEMCTL_VRSEL_VDDA_VSSA)

#define DL_ADC12_REFERENCE_VOLTAGE_EXTREF            (ADC12_MEMCTL_VRSEL_EXTREF_VREFM)

#define DL_ADC12_REFERENCE_VOLTAGE_INTREF            (ADC12_MEMCTL_VRSEL_INTREF_VSSA)

#ifndef __MSPM0_HAS_LEGACY_ADC_REFERENCE__

#define DL_ADC12_REFERENCE_VOLTAGE_VDDA_VSSA               (ADC12_MEMCTL_VRSEL_VDDA_VSSA)

#define DL_ADC12_REFERENCE_VOLTAGE_EXTREF_VREFM            (ADC12_MEMCTL_VRSEL_EXTREF_VREFM)

#define DL_ADC12_REFERENCE_VOLTAGE_INTREF_VSSA            (ADC12_MEMCTL_VRSEL_INTREF_VSSA)

#define DL_ADC12_REFERENCE_VOLTAGE_VDDA_VREFM            (ADC12_MEMCTL_VRSEL_VDDA_VREFM)

#define DL_ADC12_REFERENCE_VOLTAGE_INTREF_VREFM            (ADC12_MEMCTL_VRSEL_INTREF_VREFM)

#endif

#define DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0      (ADC12_MEMCTL_STIME_SEL_SCOMP0)

#define DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP1      (ADC12_MEMCTL_STIME_SEL_SCOMP1)

#define DL_ADC12_AVERAGING_MODE_ENABLED              (ADC12_MEMCTL_AVGEN_ENABLE)

#define DL_ADC12_AVERAGING_MODE_DISABLED            (ADC12_MEMCTL_AVGEN_DISABLE)

#define DL_ADC12_BURN_OUT_SOURCE_ENABLED             (ADC12_MEMCTL_BCSEN_ENABLE)

#define DL_ADC12_BURN_OUT_SOURCE_DISABLED           (ADC12_MEMCTL_BCSEN_DISABLE)

#define DL_ADC12_TRIGGER_MODE_AUTO_NEXT           (ADC12_MEMCTL_TRIG_AUTO_NEXT)

#define DL_ADC12_TRIGGER_MODE_TRIGGER_NEXT      (ADC12_MEMCTL_TRIG_TRIGGER_NEXT)

#define DL_ADC12_WINDOWS_COMP_MODE_ENABLED         (ADC12_MEMCTL_WINCOMP_ENABLE)

#define DL_ADC12_WINDOWS_COMP_MODE_DISABLED       (ADC12_MEMCTL_WINCOMP_DISABLE)

#define DL_ADC12_STATUS_CONVERSION_ACTIVE             (ADC12_STATUS_BUSY_ACTIVE)

#define DL_ADC12_STATUS_CONVERSION_IDLE                 (ADC12_STATUS_BUSY_IDLE)

#define DL_ADC12_STATUS_REFERENCE_READY           (ADC12_STATUS_REFBUFRDY_READY)

#define DL_ADC12_STATUS_REFERENCE_NOTREADY     (ADC12_STATUS_REFBUFRDY_NOTREADY)

#define DL_ADC12_INTERRUPT_OVERFLOW           (ADC12_CPU_INT_IMASK_OVIFG_SET)

#define DL_ADC12_INTERRUPT_TRIG_OVF      (ADC12_CPU_INT_IMASK_TOVIFG_SET)

#define DL_ADC12_INTERRUPT_WINDOW_COMP_HIGH (ADC12_CPU_INT_IMASK_HIGHIFG_SET)

#define DL_ADC12_INTERRUPT_WINDOW_COMP_LOW   (ADC12_CPU_INT_IMASK_LOWIFG_SET)

#define DL_ADC12_INTERRUPT_INIFG              (ADC12_CPU_INT_IMASK_INIFG_SET)

#define DL_ADC12_INTERRUPT_DMA_DONE         (ADC12_CPU_INT_IMASK_DMADONE_SET)

#define DL_ADC12_INTERRUPT_UNDERFLOW          (ADC12_CPU_INT_IMASK_UVIFG_SET)

#define DL_ADC12_INTERRUPT_MEM0_RESULT_LOADED \
                                         (ADC12_CPU_INT_IMASK_MEMRESIFG0_SET)

#define DL_ADC12_INTERRUPT_MEM1_RESULT_LOADED \
                                         (ADC12_CPU_INT_IMASK_MEMRESIFG1_SET)

#define DL_ADC12_INTERRUPT_MEM2_RESULT_LOADED \
                                         (ADC12_CPU_INT_IMASK_MEMRESIFG2_SET)

#define DL_ADC12_INTERRUPT_MEM3_RESULT_LOADED \
                                         (ADC12_CPU_INT_IMASK_MEMRESIFG3_SET)

#define DL_ADC12_INTERRUPT_MEM4_RESULT_LOADED \
                                         (ADC12_CPU_INT_IMASK_MEMRESIFG4_SET)

#define DL_ADC12_INTERRUPT_MEM5_RESULT_LOADED \
                                         (ADC12_CPU_INT_IMASK_MEMRESIFG5_SET)

#define DL_ADC12_INTERRUPT_MEM6_RESULT_LOADED \
                                         (ADC12_CPU_INT_IMASK_MEMRESIFG6_SET)

#define DL_ADC12_INTERRUPT_MEM7_RESULT_LOADED \
                                         (ADC12_CPU_INT_IMASK_MEMRESIFG7_SET)

#define DL_ADC12_INTERRUPT_MEM8_RESULT_LOADED \
                                         (ADC12_CPU_INT_IMASK_MEMRESIFG8_SET)

#define DL_ADC12_INTERRUPT_MEM9_RESULT_LOADED \
                                         (ADC12_CPU_INT_IMASK_MEMRESIFG9_SET)

#define DL_ADC12_INTERRUPT_MEM10_RESULT_LOADED \
                                        (ADC12_CPU_INT_IMASK_MEMRESIFG10_SET)

#define DL_ADC12_INTERRUPT_MEM11_RESULT_LOADED \
                                        (ADC12_CPU_INT_IMASK_MEMRESIFG11_SET)

#define DL_ADC12_EVENT_WINDOW_COMP_HIGH     (ADC12_GEN_EVENT_IMASK_HIGHIFG_SET)

#define DL_ADC12_EVENT_WINDOW_COMP_LOW       (ADC12_GEN_EVENT_IMASK_LOWIFG_SET)

#define DL_ADC12_EVENT_INIFG                  (ADC12_GEN_EVENT_IMASK_INIFG_SET)

#define DL_ADC12_EVENT_MEM0_RESULT_LOADED \
                                         (ADC12_GEN_EVENT_IMASK_MEMRESIFG0_SET)

#define DL_ADC12_DMA_MEM0_RESULT_LOADED  (ADC12_DMA_TRIG_IMASK_MEMRESIFG0_SET)

#define DL_ADC12_DMA_MEM1_RESULT_LOADED  (ADC12_DMA_TRIG_IMASK_MEMRESIFG1_SET)

#define DL_ADC12_DMA_MEM2_RESULT_LOADED  (ADC12_DMA_TRIG_IMASK_MEMRESIFG2_SET)

#define DL_ADC12_DMA_MEM3_RESULT_LOADED  (ADC12_DMA_TRIG_IMASK_MEMRESIFG3_SET)

#define DL_ADC12_DMA_MEM4_RESULT_LOADED  (ADC12_DMA_TRIG_IMASK_MEMRESIFG4_SET)

#define DL_ADC12_DMA_MEM5_RESULT_LOADED  (ADC12_DMA_TRIG_IMASK_MEMRESIFG5_SET)

#define DL_ADC12_DMA_MEM6_RESULT_LOADED  (ADC12_DMA_TRIG_IMASK_MEMRESIFG6_SET)

#define DL_ADC12_DMA_MEM7_RESULT_LOADED  (ADC12_DMA_TRIG_IMASK_MEMRESIFG7_SET)

#define DL_ADC12_DMA_MEM8_RESULT_LOADED  (ADC12_DMA_TRIG_IMASK_MEMRESIFG8_SET)

#define DL_ADC12_DMA_MEM9_RESULT_LOADED  (ADC12_DMA_TRIG_IMASK_MEMRESIFG9_SET)

#define DL_ADC12_DMA_MEM10_RESULT_LOADED \
                                        (ADC12_DMA_TRIG_IMASK_MEMRESIFG10_SET)

#define DL_ADC12_DMA_MEM11_RESULT_LOADED \
                                        (ADC12_DMA_TRIG_IMASK_MEMRESIFG11_SET)

#define DL_ADC12_SVT_OFFSET                  ((uint32_t)0x555000 >> (uint32_t)2)

/* clang-format on */

typedef enum {

    DL_ADC12_MEM_IDX_0 = 0,

    DL_ADC12_MEM_IDX_1 = 1,

    DL_ADC12_MEM_IDX_2 = 2,

    DL_ADC12_MEM_IDX_3 = 3,

    DL_ADC12_MEM_IDX_4 = 4,

    DL_ADC12_MEM_IDX_5 = 5,

    DL_ADC12_MEM_IDX_6 = 6,

    DL_ADC12_MEM_IDX_7 = 7,

    DL_ADC12_MEM_IDX_8 = 8,

    DL_ADC12_MEM_IDX_9 = 9,

    DL_ADC12_MEM_IDX_10 = 10,

    DL_ADC12_MEM_IDX_11 = 11,

} DL_ADC12_MEM_IDX;

typedef enum {

    DL_ADC12_REPEAT_MODE_ENABLED = ADC12_CTL1_CONSEQ_REPEATSINGLE,

    DL_ADC12_REPEAT_MODE_DISABLED = ADC12_CTL1_CONSEQ_SINGLE

} DL_ADC12_REPEAT_MODE;

typedef enum {
    DL_ADC12_SAMPLING_SOURCE_AUTO = ADC12_CTL1_SAMPMODE_AUTO,

    DL_ADC12_SAMPLING_SOURCE_MANUAL = ADC12_CTL1_SAMPMODE_MANUAL
} DL_ADC12_SAMPLING_SOURCE;

typedef enum {
    DL_ADC12_TRIG_SRC_SOFTWARE = ADC12_CTL1_TRIGSRC_SOFTWARE,

    DL_ADC12_TRIG_SRC_EVENT = ADC12_CTL1_TRIGSRC_EVENT

} DL_ADC12_TRIG_SRC;

typedef enum {
    DL_ADC12_SAMP_CONV_RES_12_BIT = ADC12_CTL2_RES_BIT_12,
    DL_ADC12_SAMP_CONV_RES_10_BIT = ADC12_CTL2_RES_BIT_10,
    DL_ADC12_SAMP_CONV_RES_8_BIT = ADC12_CTL2_RES_BIT_8
} DL_ADC12_SAMP_CONV_RES;

typedef enum {
    DL_ADC12_SAMP_CONV_DATA_FORMAT_UNSIGNED = ADC12_CTL2_DF_UNSIGNED,

    DL_ADC12_SAMP_CONV_DATA_FORMAT_SIGNED = ADC12_CTL2_DF_SIGNED

} DL_ADC12_SAMP_CONV_DATA_FORMAT;

typedef enum {
    DL_ADC12_IIDX_OVERFLOW = ADC12_CPU_INT_IIDX_STAT_OVIFG,

    DL_ADC12_IIDX_TRIG_OVERFLOW = ADC12_CPU_INT_IIDX_STAT_TOVIFG,

    DL_ADC12_IIDX_WINDOW_COMP_HIGH = ADC12_CPU_INT_IIDX_STAT_HIGHIFG,

    DL_ADC12_IIDX_WINDOW_COMP_LOW = ADC12_CPU_INT_IIDX_STAT_LOWIFG,

    DL_ADC12_IIDX_INIFG = ADC12_CPU_INT_IIDX_STAT_INIFG,

    DL_ADC12_IIDX_DMA_DONE = ADC12_CPU_INT_IIDX_STAT_DMADONE,

    DL_ADC12_IIDX_UNDERFLOW = ADC12_CPU_INT_IIDX_STAT_UVIFG,

    DL_ADC12_IIDX_MEM0_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG0,

    DL_ADC12_IIDX_MEM1_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG1,

    DL_ADC12_IIDX_MEM2_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG2,

    DL_ADC12_IIDX_MEM3_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG3,

    DL_ADC12_IIDX_MEM4_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG4,

    DL_ADC12_IIDX_MEM5_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG5,

    DL_ADC12_IIDX_MEM6_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG6,

    DL_ADC12_IIDX_MEM7_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG7,

    DL_ADC12_IIDX_MEM8_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG8,

    DL_ADC12_IIDX_MEM9_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG9,

    DL_ADC12_IIDX_MEM10_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG10,

    DL_ADC12_IIDX_MEM11_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG11,
} DL_ADC12_IIDX;

/* clang-format on */
typedef enum {
    DL_ADC12_CLOCK_SYSOSC = ADC12_CLKCFG_SAMPCLK_SYSOSC,
    DL_ADC12_CLOCK_ULPCLK = ADC12_CLKCFG_SAMPCLK_ULPCLK,
    DL_ADC12_CLOCK_HFCLK = ADC12_CLKCFG_SAMPCLK_HFCLK,
} DL_ADC12_CLOCK;

typedef enum {

    DL_ADC12_CLOCK_DIVIDE_1 = ADC12_CTL0_SCLKDIV_DIV_BY_1,

    DL_ADC12_CLOCK_DIVIDE_2 = ADC12_CTL0_SCLKDIV_DIV_BY_2,

    DL_ADC12_CLOCK_DIVIDE_4 = ADC12_CTL0_SCLKDIV_DIV_BY_4,

    DL_ADC12_CLOCK_DIVIDE_8 = ADC12_CTL0_SCLKDIV_DIV_BY_8,

    DL_ADC12_CLOCK_DIVIDE_16 = ADC12_CTL0_SCLKDIV_DIV_BY_16,

    DL_ADC12_CLOCK_DIVIDE_24 = ADC12_CTL0_SCLKDIV_DIV_BY_24,

    DL_ADC12_CLOCK_DIVIDE_32 = ADC12_CTL0_SCLKDIV_DIV_BY_32,

    DL_ADC12_CLOCK_DIVIDE_48 = ADC12_CTL0_SCLKDIV_DIV_BY_48,

} DL_ADC12_CLOCK_DIVIDE;

typedef enum {
    DL_ADC12_CLOCK_FREQ_RANGE_1_TO_4 = ADC12_CLKFREQ_FRANGE_RANGE1TO4,

    DL_ADC12_CLOCK_FREQ_RANGE_4_TO_8 = ADC12_CLKFREQ_FRANGE_RANGE4TO8,

    DL_ADC12_CLOCK_FREQ_RANGE_8_TO_16 = ADC12_CLKFREQ_FRANGE_RANGE8TO16,

    DL_ADC12_CLOCK_FREQ_RANGE_16_TO_20 = ADC12_CLKFREQ_FRANGE_RANGE16TO20,

    DL_ADC12_CLOCK_FREQ_RANGE_20_TO_24 = ADC12_CLKFREQ_FRANGE_RANGE20TO24,

    DL_ADC12_CLOCK_FREQ_RANGE_24_TO_32 = ADC12_CLKFREQ_FRANGE_RANGE24TO32,

    DL_ADC12_CLOCK_FREQ_RANGE_32_TO_40 = ADC12_CLKFREQ_FRANGE_RANGE32TO40,

    DL_ADC12_CLOCK_FREQ_RANGE_40_TO_48 = ADC12_CLKFREQ_FRANGE_RANGE40TO48,

} DL_ADC12_CLOCK_FREQ_RANGE;

typedef struct {
    DL_ADC12_CLOCK clockSel;
    DL_ADC12_CLOCK_FREQ_RANGE freqRange;
    DL_ADC12_CLOCK_DIVIDE divideRatio;
} DL_ADC12_ClockConfig;

__STATIC_INLINE void DL_ADC12_enablePower(ADC12_Regs *adc12)
{
    adc12->ULLMEM.GPRCM.PWREN =
        (ADC12_PWREN_KEY_UNLOCK_W | ADC12_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_ADC12_disablePower(ADC12_Regs *adc12)
{
    adc12->ULLMEM.GPRCM.PWREN =
        (ADC12_PWREN_KEY_UNLOCK_W | ADC12_PWREN_ENABLE_DISABLE);
}

__STATIC_INLINE bool DL_ADC12_isPowerEnabled(const ADC12_Regs *adc12)
{
    return ((adc12->ULLMEM.GPRCM.PWREN & ADC12_PWREN_ENABLE_MASK) ==
            ADC12_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_ADC12_reset(ADC12_Regs *adc12)
{
    adc12->ULLMEM.GPRCM.RSTCTL =
        (ADC12_RSTCTL_KEY_UNLOCK_W | ADC12_RSTCTL_RESETSTKYCLR_CLR |
            ADC12_RSTCTL_RESETASSERT_ASSERT);
}

__STATIC_INLINE bool DL_ADC12_isReset(const ADC12_Regs *adc12)
{
    return ((adc12->ULLMEM.GPRCM.STAT & ADC12_STAT_RESETSTKY_MASK) ==
            ADC12_STAT_RESETSTKY_RESET);
}

__STATIC_INLINE void DL_ADC12_initSingleSample(ADC12_Regs *adc12,
    uint32_t repeatMode, uint32_t sampleMode, uint32_t trigSrc,
    uint32_t resolution, uint32_t dataFormat)
{
    DL_Common_updateReg(&adc12->ULLMEM.CTL1,
        (repeatMode | sampleMode | trigSrc),
        (ADC12_CTL1_SAMPMODE_MASK | ADC12_CTL1_CONSEQ_MASK |
            ADC12_CTL1_TRIGSRC_MASK));

    DL_Common_updateReg(&adc12->ULLMEM.CTL2,
        (ADC12_CTL2_STARTADD_ADDR_00 | ADC12_CTL2_ENDADD_ADDR_00 | resolution |
            dataFormat),
        (ADC12_CTL2_STARTADD_MASK | ADC12_CTL2_ENDADD_MASK |
            ADC12_CTL2_RES_MASK | ADC12_CTL2_DF_MASK));
}

__STATIC_INLINE void DL_ADC12_setStartAddress(
    ADC12_Regs *adc12, uint32_t startAdd)
{
    DL_Common_updateReg(
        &adc12->ULLMEM.CTL2, startAdd, ADC12_CTL2_STARTADD_MASK);
}

__STATIC_INLINE uint32_t DL_ADC12_getStartAddress(const ADC12_Regs *adc12)
{
    return (adc12->ULLMEM.CTL2 & ADC12_CTL2_STARTADD_MASK);
}

__STATIC_INLINE void DL_ADC12_setEndAddress(ADC12_Regs *adc12, uint32_t endAdd)
{
    DL_Common_updateReg(&adc12->ULLMEM.CTL2, endAdd, ADC12_CTL2_ENDADD_MASK);
}

__STATIC_INLINE uint32_t DL_ADC12_getEndAddress(const ADC12_Regs *adc12)
{
    return (adc12->ULLMEM.CTL2 & ADC12_CTL2_ENDADD_MASK);
}

__STATIC_INLINE void DL_ADC12_initSeqSample(ADC12_Regs *adc12,
    uint32_t repeatMode, uint32_t sampleMode, uint32_t trigSrc,
    uint32_t startAdd, uint32_t endAdd, uint32_t resolution,
    uint32_t dataFormat)
{
    DL_Common_updateReg(&adc12->ULLMEM.CTL1,
        (ADC12_CTL1_CONSEQ_SEQUENCE | repeatMode | sampleMode | trigSrc),
        (ADC12_CTL1_SAMPMODE_MASK | ADC12_CTL1_CONSEQ_MASK |
            ADC12_CTL1_TRIGSRC_MASK));

    DL_Common_updateReg(&adc12->ULLMEM.CTL2,
        (startAdd | endAdd | resolution | dataFormat),
        (ADC12_CTL2_ENDADD_MASK | ADC12_CTL2_STARTADD_MASK |
            ADC12_CTL2_RES_MASK | ADC12_CTL2_DF_MASK));
}

__STATIC_INLINE uint32_t DL_ADC12_getResolution(const ADC12_Regs *adc12)
{
    return (adc12->ULLMEM.CTL2 & ADC12_CTL2_RES_MASK);
}

__STATIC_INLINE uint32_t DL_ADC12_getDataFormat(const ADC12_Regs *adc12)
{
    return (adc12->ULLMEM.CTL2 & ADC12_CTL2_DF_MASK);
}

__STATIC_INLINE uint32_t DL_ADC12_getSamplingSource(const ADC12_Regs *adc12)
{
    return (adc12->ULLMEM.CTL1 & ADC12_CTL1_SAMPMODE_MASK);
}

__STATIC_INLINE uint32_t DL_ADC12_getSampleMode(const ADC12_Regs *adc12)
{
    return (adc12->ULLMEM.CTL1 & ADC12_CTL1_CONSEQ_MASK);
}

__STATIC_INLINE DL_ADC12_TRIG_SRC DL_ADC12_getTriggerSource(
    const ADC12_Regs *adc12)
{
    uint32_t trigSrc = adc12->ULLMEM.CTL1 & ADC12_CTL1_TRIGSRC_MASK;

    return (DL_ADC12_TRIG_SRC)(trigSrc);
}

__STATIC_INLINE void DL_ADC12_startConversion(ADC12_Regs *adc12)
{
    adc12->ULLMEM.CTL1 |= (ADC12_CTL1_SC_START);
}

__STATIC_INLINE void DL_ADC12_stopConversion(ADC12_Regs *adc12)
{
    adc12->ULLMEM.CTL1 &= ~(ADC12_CTL1_SC_START);
}

__STATIC_INLINE bool DL_ADC12_isConversionStarted(const ADC12_Regs *adc12)
{
    return ((adc12->ULLMEM.CTL1 & ADC12_CTL1_SC_MASK) == ADC12_CTL1_SC_START);
}

__STATIC_INLINE void DL_ADC12_enableDMA(ADC12_Regs *adc12)
{
    adc12->ULLMEM.CTL2 |= (ADC12_CTL2_DMAEN_ENABLE);
}

__STATIC_INLINE void DL_ADC12_disableDMA(ADC12_Regs *adc12)
{
    adc12->ULLMEM.CTL2 &= ~(ADC12_CTL2_DMAEN_ENABLE);
}

__STATIC_INLINE bool DL_ADC12_isDMAEnabled(const ADC12_Regs *adc12)
{
    return ((adc12->ULLMEM.CTL2 & ADC12_CTL2_DMAEN_ENABLE) ==
            ADC12_CTL2_DMAEN_ENABLE);
}

__STATIC_INLINE void DL_ADC12_setDMASamplesCnt(
    ADC12_Regs *adc12, uint8_t sampCnt)
{
    DL_Common_updateReg(&adc12->ULLMEM.CTL2, (((uint32_t) sampCnt) << 11),
        ADC12_CTL2_SAMPCNT_MASK);
}

__STATIC_INLINE uint8_t DL_ADC12_getDMASampleCnt(const ADC12_Regs *adc12)
{
    return (uint8_t)((adc12->ULLMEM.CTL2 & ADC12_CTL2_SAMPCNT_MASK) >> 11);
}

__STATIC_INLINE void DL_ADC12_enableFIFO(ADC12_Regs *adc12)
{
    adc12->ULLMEM.CTL2 |= (ADC12_CTL2_FIFOEN_ENABLE);
}

__STATIC_INLINE void DL_ADC12_disableFIFO(ADC12_Regs *adc12)
{
    adc12->ULLMEM.CTL2 &= ~(ADC12_CTL2_FIFOEN_ENABLE);
}

__STATIC_INLINE bool DL_ADC12_isFIFOEnabled(const ADC12_Regs *adc12)
{
    return ((adc12->ULLMEM.CTL2 & ADC12_CTL2_FIFOEN_MASK) ==
            ADC12_CTL2_FIFOEN_ENABLE);
}

void DL_ADC12_setClockConfig(
    ADC12_Regs *adc12, const DL_ADC12_ClockConfig *config);

void DL_ADC12_getClockConfig(
    const ADC12_Regs *adc12, DL_ADC12_ClockConfig *config);

__STATIC_INLINE void DL_ADC12_setPowerDownMode(
    ADC12_Regs *adc12, uint32_t powerDownMode)
{
    DL_Common_updateReg(
        &adc12->ULLMEM.CTL0, powerDownMode, ADC12_CTL0_PWRDN_MASK);
}

__STATIC_INLINE uint32_t DL_ADC12_getPowerDownMode(const ADC12_Regs *adc12)
{
    return (adc12->ULLMEM.CTL0 & ADC12_CTL0_PWRDN_MASK);
}

__STATIC_INLINE void DL_ADC12_enableConversions(ADC12_Regs *adc12)
{
    adc12->ULLMEM.CTL0 |= (ADC12_CTL0_ENC_ON);
}

__STATIC_INLINE void DL_ADC12_disableConversions(ADC12_Regs *adc12)
{
    adc12->ULLMEM.CTL0 &= ~(ADC12_CTL0_ENC_ON);
}

__STATIC_INLINE bool DL_ADC12_isConversionsEnabled(const ADC12_Regs *adc12)
{
    return ((adc12->ULLMEM.CTL0 & ADC12_CTL0_ENC_MASK) == ADC12_CTL0_ENC_ON);
}

__STATIC_INLINE void DL_ADC12_configHwAverage(
    ADC12_Regs *adc12, uint32_t numerator, uint32_t denominator)
{
    DL_Common_updateReg(&adc12->ULLMEM.CTL1, (numerator | denominator),
        (ADC12_CTL1_AVGN_MASK | ADC12_CTL1_AVGD_MASK));
}

__STATIC_INLINE uint32_t DL_ADC12_getHwAverageConfig(const ADC12_Regs *adc12)
{
    return (
        adc12->ULLMEM.CTL1 & (ADC12_CTL1_AVGN_MASK | ADC12_CTL1_AVGD_MASK));
}

__STATIC_INLINE void DL_ADC12_setSampleTime0(
    ADC12_Regs *adc12, uint16_t adcclks)
{
    adc12->ULLMEM.SCOMP0 = (adcclks);
}

__STATIC_INLINE uint16_t DL_ADC12_getSampleTime0(const ADC12_Regs *adc12)
{
    return (uint16_t)(adc12->ULLMEM.SCOMP0 + (uint32_t) 1);
}

__STATIC_INLINE void DL_ADC12_setSampleTime1(
    ADC12_Regs *adc12, uint16_t adcclks)
{
    adc12->ULLMEM.SCOMP1 = (adcclks);
}

__STATIC_INLINE uint16_t DL_ADC12_getSampleTime1(const ADC12_Regs *adc12)
{
    return (uint16_t)(adc12->ULLMEM.SCOMP1 + (uint32_t) 1);
}

__STATIC_INLINE void DL_ADC12_configWinCompLowThld(
    ADC12_Regs *adc12, uint16_t threshold)
{
    adc12->ULLMEM.WCLOW = (threshold);
}

__STATIC_INLINE void DL_ADC12_configWinCompHighThld(
    ADC12_Regs *adc12, uint16_t threshold)
{
    adc12->ULLMEM.WCHIGH = (threshold);
}

__STATIC_INLINE uint32_t DL_ADC12_getFIFOData(const ADC12_Regs *adc12)
{
    volatile const uint32_t *pReg = &adc12->ULLMEM.FIFODATA;

    return (uint32_t)(*(pReg + DL_ADC12_SVT_OFFSET));
}

__STATIC_INLINE uint32_t DL_ADC12_getFIFOAddress(const ADC12_Regs *adc12)
{
    return ((uint32_t)(&adc12->ULLMEM.FIFODATA + DL_ADC12_SVT_OFFSET));
}

__STATIC_INLINE void DL_ADC12_configConversionMem(ADC12_Regs *adc12,
    DL_ADC12_MEM_IDX idx, uint32_t chansel, uint32_t vref, uint32_t stime,
    uint32_t avgen, uint32_t bcsen, uint32_t trig, uint32_t wincomp)
{
    adc12->ULLMEM.MEMCTL[idx] =
        (chansel | vref | stime | avgen | bcsen | trig | wincomp);
}

__STATIC_INLINE uint32_t DL_ADC12_getConversionMemConfig(
    const ADC12_Regs *adc12, DL_ADC12_MEM_IDX idx)
{
    return (adc12->ULLMEM.MEMCTL[idx]);
}

__STATIC_INLINE uint16_t DL_ADC12_getMemResult(
    const ADC12_Regs *adc12, DL_ADC12_MEM_IDX idx)
{
    volatile const uint32_t *pReg = &adc12->ULLMEM.MEMRES[idx];

    return (uint16_t)(*(pReg + DL_ADC12_SVT_OFFSET));
}

__STATIC_INLINE uint32_t DL_ADC12_getMemResultAddress(
    const ADC12_Regs *adc12, DL_ADC12_MEM_IDX idx)
{
    return ((uint32_t)(&adc12->ULLMEM.MEMRES[idx] + DL_ADC12_SVT_OFFSET));
}

__STATIC_INLINE uint32_t DL_ADC12_getStatus(const ADC12_Regs *adc12)
{
    return (adc12->ULLMEM.STATUS);
}

__STATIC_INLINE void DL_ADC12_disableForcingSYSOSCOnInRunMode(
    ADC12_Regs *adc12)
{
    DL_Common_updateReg(&adc12->ULLMEM.GPRCM.CLKCFG,
        (ADC12_CLKCFG_CCONRUN_DISABLE | ADC12_CLKCFG_KEY_UNLOCK_W),
        (ADC12_CLKCFG_CCONRUN_MASK | ADC12_CLKCFG_KEY_MASK));
}

__STATIC_INLINE void DL_ADC12_forceSYSOSCOnInRunMode(ADC12_Regs *adc12)
{
    adc12->ULLMEM.GPRCM.CLKCFG |=
        (ADC12_CLKCFG_KEY_UNLOCK_W | ADC12_CLKCFG_CCONRUN_ENABLE);
}

__STATIC_INLINE void DL_ADC12_disableForcingSYSOSCOnInStopMode(
    ADC12_Regs *adc12)
{
    DL_Common_updateReg(&adc12->ULLMEM.GPRCM.CLKCFG,
        (ADC12_CLKCFG_CCONSTOP_DISABLE | ADC12_CLKCFG_KEY_UNLOCK_W),
        (ADC12_CLKCFG_CCONSTOP_MASK | ADC12_CLKCFG_KEY_MASK));
}

__STATIC_INLINE void DL_ADC12_forceSYSOSCOnInStopMode(ADC12_Regs *adc12)
{
    adc12->ULLMEM.GPRCM.CLKCFG |=
        (ADC12_CLKCFG_KEY_UNLOCK_W | ADC12_CLKCFG_CCONSTOP_ENABLE);
}

__STATIC_INLINE void DL_ADC12_enableInterrupt(
    ADC12_Regs *adc12, uint32_t interruptMask)
{
    adc12->ULLMEM.CPU_INT.IMASK |= (interruptMask);
}

__STATIC_INLINE void DL_ADC12_disableInterrupt(
    ADC12_Regs *adc12, uint32_t interruptMask)
{
    adc12->ULLMEM.CPU_INT.IMASK &= ~(interruptMask);
}

__STATIC_INLINE uint32_t DL_ADC12_getEnabledInterrupts(
    const ADC12_Regs *adc12, uint32_t interruptMask)
{
    return (adc12->ULLMEM.CPU_INT.IMASK & interruptMask);
}

__STATIC_INLINE uint32_t DL_ADC12_getEnabledInterruptStatus(
    const ADC12_Regs *adc12, uint32_t interruptMask)
{
    return (adc12->ULLMEM.CPU_INT.MIS & interruptMask);
}

__STATIC_INLINE uint32_t DL_ADC12_getRawInterruptStatus(
    const ADC12_Regs *adc12, uint32_t interruptMask)
{
    return (adc12->ULLMEM.CPU_INT.RIS & interruptMask);
}

__STATIC_INLINE DL_ADC12_IIDX DL_ADC12_getPendingInterrupt(
    const ADC12_Regs *adc12)
{
    return ((DL_ADC12_IIDX) adc12->ULLMEM.CPU_INT.IIDX);
}

__STATIC_INLINE void DL_ADC12_clearInterruptStatus(
    ADC12_Regs *adc12, uint32_t interruptMask)
{
    adc12->ULLMEM.CPU_INT.ICLR |= (interruptMask);
}

__STATIC_INLINE void DL_ADC12_setPublisherChanID(
    ADC12_Regs *adc12, uint8_t chanID)
{
    adc12->ULLMEM.FPUB_1 = (chanID & ADC12_FPUB_1_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_ADC12_getPublisherChanID(const ADC12_Regs *adc12)
{
    return (uint8_t)(adc12->ULLMEM.FPUB_1 & ADC12_FPUB_1_CHANID_MAXIMUM);
}

__STATIC_INLINE void DL_ADC12_setSubscriberChanID(
    ADC12_Regs *adc12, uint8_t chanID)
{
    adc12->ULLMEM.FSUB_0 = (chanID & ADC12_FSUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_ADC12_getSubscriberChanID(const ADC12_Regs *adc12)
{
    return (uint8_t)(adc12->ULLMEM.FSUB_0 & ADC12_FSUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE void DL_ADC12_enableEvent(
    ADC12_Regs *adc12, uint32_t eventMask)
{
    adc12->ULLMEM.GEN_EVENT.IMASK |= (eventMask);
}

__STATIC_INLINE void DL_ADC12_disableEvent(
    ADC12_Regs *adc12, uint32_t eventMask)
{
    adc12->ULLMEM.GEN_EVENT.IMASK &= ~(eventMask);
}

__STATIC_INLINE uint32_t DL_ADC12_getEnabledEvents(
    const ADC12_Regs *adc12, uint32_t eventMask)
{
    return (adc12->ULLMEM.GEN_EVENT.IMASK & eventMask);
}

__STATIC_INLINE uint32_t DL_ADC12_getEnabledEventStatus(
    const ADC12_Regs *adc12, uint32_t eventMask)
{
    return (adc12->ULLMEM.GEN_EVENT.MIS & ~(eventMask));
}

__STATIC_INLINE uint32_t DL_ADC12_getRawEventsStatus(
    const ADC12_Regs *adc12, uint32_t eventMask)
{
    return (adc12->ULLMEM.GEN_EVENT.RIS & ~(eventMask));
}

__STATIC_INLINE void DL_ADC12_clearEventsStatus(
    ADC12_Regs *adc12, uint32_t eventMask)
{
    adc12->ULLMEM.GEN_EVENT.ICLR |= (eventMask);
}

__STATIC_INLINE void DL_ADC12_enableDMATrigger(
    ADC12_Regs *adc12, uint32_t dmaMask)
{
    adc12->ULLMEM.DMA_TRIG.IMASK |= (dmaMask);
}

__STATIC_INLINE void DL_ADC12_disableDMATrigger(
    ADC12_Regs *adc12, uint32_t dmaMask)
{
    adc12->ULLMEM.DMA_TRIG.IMASK &= ~(dmaMask);
}

__STATIC_INLINE uint32_t DL_ADC12_getEnabledDMATrigger(
    const ADC12_Regs *adc12, uint32_t dmaMask)
{
    return (adc12->ULLMEM.DMA_TRIG.IMASK & dmaMask);
}

__STATIC_INLINE uint32_t DL_ADC12_getEnabledDMATriggerStatus(
    const ADC12_Regs *adc12, uint32_t dmaMask)
{
    return (adc12->ULLMEM.DMA_TRIG.MIS & ~(dmaMask));
}

__STATIC_INLINE uint32_t DL_ADC12_getRawDMATriggerStatus(
    const ADC12_Regs *adc12, uint32_t dmaMask)
{
    return (adc12->ULLMEM.DMA_TRIG.RIS & ~(dmaMask));
}

__STATIC_INLINE void DL_ADC12_clearDMATriggerStatus(
    ADC12_Regs *adc12, uint32_t dmaMask)
{
    adc12->ULLMEM.DMA_TRIG.ICLR |= (dmaMask);
}

#ifdef __MSPM0_HAS_ADC12_SH_CAP_DISCH__

__STATIC_INLINE void DL_ADC12_enableSAMPCAP(ADC12_Regs *adc12)
{
    adc12->ULLMEM.CTL2 |= (ADC12_CTL2_RSTSAMPCAPEN_ENABLE);
}

__STATIC_INLINE void DL_ADC12_disableSAMPCAP(ADC12_Regs *adc12)
{
    adc12->ULLMEM.CTL2 &= ~(ADC12_CTL2_RSTSAMPCAPEN_ENABLE);
}

__STATIC_INLINE bool DL_ADC12_isSAMPCAPEnabled(const ADC12_Regs *adc12)
{
    return ((adc12->ULLMEM.CTL2 & ADC12_CTL2_RSTSAMPCAPEN_MASK) ==
            ADC12_CTL2_RSTSAMPCAPEN_ENABLE);
}
#endif /* ADC HAS SAMPLE AND HOLD CAPACITOR DISCHARGE*/

#ifdef __MSPM0C110X_ADC_ERR_06__

__STATIC_INLINE int16_t DL_ADC12_getADCOffsetCalibration(float userRef)
{
    float adcBuff = DL_FactoryRegion_getADCOffset() * (3.3 / userRef);
    return (int16_t)(round(adcBuff));
}
#endif

#ifdef __cplusplus
}
#endif

#endif /* __MSPM0_HAS_ADC12__ */

#endif /* ti_dl_dl_adc12__include */