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MSPM0C1105_C1106 Driver Library
2.05.01.00
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SPI Driver Library.
#include <stdbool.h>#include <stdint.h>#include <ti/devices/msp/msp.h>#include <ti/driverlib/dl_common.h>
Go to the source code of this file.
Data Structures | |
| struct | DL_SPI_Config |
| Configuration struct for DL_SPI_init. More... | |
| struct | DL_SPI_ClockConfig |
| Configuration struct for DL_SPI_setClockConfig. More... | |
| struct | DL_SPI_backupConfig |
| Configuration structure to backup SPI peripheral state before going to STOP/STANDBY mode. Used by DL_SPI_saveConfiguration and DL_SPI_restoreConfiguration. More... | |
Macros | |
| #define | DL_SPI_CD_MODE_DATA (SPI_CTL1_CDMODE_DATA >> SPI_CTL1_CDMODE_OFS) |
| Data mode. | |
| #define | DL_SPI_CD_MODE_COMMAND (SPI_CTL1_CDMODE_COMMAND >> SPI_CTL1_CDMODE_OFS) |
| Command mode. | |
| #define | DL_SPI_INTERRUPT_DMA_DONE_TX (SPI_CPU_INT_IMASK_DMA_DONE_TX_SET) |
| DMA done 1 event for transmit interrupt. | |
| #define | DL_SPI_INTERRUPT_DMA_DONE_RX (SPI_CPU_INT_IMASK_DMA_DONE_RX_SET) |
| DMA done 1 event for receive interrupt. | |
| #define | DL_SPI_INTERRUPT_IDLE (SPI_CPU_INT_IMASK_IDLE_SET) |
| SPI has finished transfers and changed into idle mode interrupt. | |
| #define | DL_SPI_INTERRUPT_TX_EMPTY (SPI_CPU_INT_IMASK_TXEMPTY_SET) |
| Transmit FIFO empty interrupt. | |
| #define | DL_SPI_INTERRUPT_TX (SPI_CPU_INT_IMASK_TX_SET) |
| Transmit FIFO interrupt. | |
| #define | DL_SPI_INTERRUPT_RX (SPI_CPU_INT_IMASK_RX_SET) |
| Receive FIFO interrupt. | |
| #define | DL_SPI_INTERRUPT_RX_TIMEOUT (SPI_CPU_INT_IMASK_RTOUT_SET) |
| Receive timeout interrupt. | |
| #define | DL_SPI_INTERRUPT_RX_FULL (SPI_CPU_INT_IMASK_RXFULL_SET) |
| Receive FIFO full interrupt. | |
| #define | DL_SPI_INTERRUPT_TX_UNDERFLOW (SPI_CPU_INT_IMASK_TXFIFO_UNF_SET) |
| Transmit FIFO underflow interrupt. | |
| #define | DL_SPI_INTERRUPT_PARITY_ERROR (SPI_CPU_INT_IMASK_PER_SET) |
| Parity error. | |
| #define | DL_SPI_INTERRUPT_RX_OVERFLOW (SPI_CPU_INT_IMASK_RXFIFO_OVF_SET) |
| Receive FIFO overflow interrupt. | |
| #define | DL_SPI_DMA_INTERRUPT_RX (SPI_DMA_TRIG_RX_IMASK_RX_SET) |
| SPI interrupt for enabling SPI receive as DMA trigger. | |
| #define | DL_SPI_DMA_INTERRUPT_RX_TIMEOUT (SPI_DMA_TRIG_RX_IMASK_RTOUT_SET) |
| SPI interrupt for enabling SPI receive timeout as DMA trigger. | |
| #define | DL_SPI_DMA_INTERRUPT_TX (SPI_DMA_TRIG_TX_IMASK_TX_SET) |
| SPI interrupt for enabling SPI transmit as DMA trigger. | |
Enumerations | |
| enum | DL_SPI_DMA_IIDX_RX { DL_SPI_DMA_IIDX_RX_TRIGGER = SPI_DMA_TRIG_RX_IIDX_STAT_RX_EVT, DL_SPI_DMA_IIDX_RX_TIMEOUT_TRIGGER = SPI_DMA_TRIG_RX_IIDX_STAT_RTOUT_EVT } |
| enum | DL_SPI_DMA_IIDX_TX { DL_SPI_DMA_IIDX_TX_TRIGGER = SPI_DMA_TRIG_TX_IIDX_STAT_TX_EVT } |
| enum | DL_SPI_PARITY { DL_SPI_PARITY_EVEN, DL_SPI_PARITY_ODD, DL_SPI_PARITY_NONE = (SPI_CTL1_PREN_DISABLE | SPI_CTL1_PTEN_DISABLE) } |
| enum | DL_SPI_FRAME_FORMAT { DL_SPI_FRAME_FORMAT_MOTO3_POL0_PHA0, DL_SPI_FRAME_FORMAT_MOTO3_POL0_PHA1, DL_SPI_FRAME_FORMAT_MOTO3_POL1_PHA0, DL_SPI_FRAME_FORMAT_MOTO3_POL1_PHA1, DL_SPI_FRAME_FORMAT_MOTO4_POL0_PHA0, DL_SPI_FRAME_FORMAT_MOTO4_POL0_PHA1, DL_SPI_FRAME_FORMAT_MOTO4_POL1_PHA0, DL_SPI_FRAME_FORMAT_MOTO4_POL1_PHA1, DL_SPI_FRAME_FORMAT_TI_SYNC = (SPI_CTL0_FRF_TI_SYNC) } |
| enum | DL_SPI_MODE { DL_SPI_MODE_CONTROLLER = (SPI_CTL1_CP_ENABLE), DL_SPI_MODE_PERIPHERAL = (SPI_CTL1_CP_DISABLE) } |
| enum | DL_SPI_BIT_ORDER { DL_SPI_BIT_ORDER_MSB_FIRST = (SPI_CTL1_MSB_ENABLE), DL_SPI_BIT_ORDER_LSB_FIRST = (SPI_CTL1_MSB_DISABLE) } |
| enum | DL_SPI_DATA_SIZE { DL_SPI_DATA_SIZE_4 = (SPI_CTL0_DSS_DSS_4), DL_SPI_DATA_SIZE_5 = (SPI_CTL0_DSS_DSS_5), DL_SPI_DATA_SIZE_6 = (SPI_CTL0_DSS_DSS_6), DL_SPI_DATA_SIZE_7 = (SPI_CTL0_DSS_DSS_7), DL_SPI_DATA_SIZE_8 = (SPI_CTL0_DSS_DSS_8), DL_SPI_DATA_SIZE_9 = (SPI_CTL0_DSS_DSS_9), DL_SPI_DATA_SIZE_10 = (SPI_CTL0_DSS_DSS_10), DL_SPI_DATA_SIZE_11 = (SPI_CTL0_DSS_DSS_11), DL_SPI_DATA_SIZE_12 = (SPI_CTL0_DSS_DSS_12), DL_SPI_DATA_SIZE_13 = (SPI_CTL0_DSS_DSS_13), DL_SPI_DATA_SIZE_14 = (SPI_CTL0_DSS_DSS_14), DL_SPI_DATA_SIZE_15 = (SPI_CTL0_DSS_DSS_15), DL_SPI_DATA_SIZE_16 = (SPI_CTL0_DSS_DSS_16) } |
| enum | DL_SPI_CHIP_SELECT { DL_SPI_CHIP_SELECT_0 = (SPI_CTL0_CSSEL_CSSEL_0), DL_SPI_CHIP_SELECT_1 = (SPI_CTL0_CSSEL_CSSEL_1), DL_SPI_CHIP_SELECT_2 = (SPI_CTL0_CSSEL_CSSEL_2), DL_SPI_CHIP_SELECT_3 = (SPI_CTL0_CSSEL_CSSEL_3), DL_SPI_CHIP_SELECT_NONE = (0) } |
| enum | DL_SPI_TX_FIFO_LEVEL { DL_SPI_TX_FIFO_LEVEL_3_4_EMPTY = SPI_IFLS_TXIFLSEL_LVL_3_4, DL_SPI_TX_FIFO_LEVEL_1_2_EMPTY = SPI_IFLS_TXIFLSEL_LVL_1_2, DL_SPI_TX_FIFO_LEVEL_1_4_EMPTY = SPI_IFLS_TXIFLSEL_LVL_1_4, DL_SPI_TX_FIFO_LEVEL_EMPTY = SPI_IFLS_TXIFLSEL_LVL_EMPTY, DL_SPI_TX_FIFO_LEVEL_ONE_FRAME = SPI_IFLS_TXIFLSEL_LEVEL_1 } |
| enum | DL_SPI_RX_FIFO_LEVEL { DL_SPI_RX_FIFO_LEVEL_ONE_FRAME = SPI_IFLS_RXIFLSEL_LEVEL_1, DL_SPI_RX_FIFO_LEVEL_FULL = SPI_IFLS_RXIFLSEL_LVL_FULL, DL_SPI_RX_FIFO_LEVEL_3_4_FULL = SPI_IFLS_RXIFLSEL_LVL_3_4, DL_SPI_RX_FIFO_LEVEL_1_2_FULL = SPI_IFLS_RXIFLSEL_LVL_1_2, DL_SPI_RX_FIFO_LEVEL_1_4_FULL = SPI_IFLS_RXIFLSEL_LVL_1_4 } |
| enum | DL_SPI_IIDX { DL_SPI_IIDX_DMA_DONE_TX = SPI_CPU_INT_IIDX_STAT_DMA_DONE_TX_EVT, DL_SPI_IIDX_DMA_DONE_RX = SPI_CPU_INT_IIDX_STAT_DMA_DONE_RX_EVT, DL_SPI_IIDX_IDLE = SPI_CPU_INT_IIDX_STAT_IDLE_EVT, DL_SPI_IIDX_TX_EMPTY = SPI_CPU_INT_IIDX_STAT_TX_EMPTY, DL_SPI_IIDX_TX = SPI_CPU_INT_IIDX_STAT_TX_EVT, DL_SPI_IIDX_RX = SPI_CPU_INT_IIDX_STAT_RX_EVT, DL_SPI_IIDX_RX_TIMEOUT = SPI_CPU_INT_IIDX_STAT_RTOUT_EVT, DL_SPI_IIDX_RX_FULL = SPI_CPU_INT_IIDX_STAT_RXFULL_EVT, DL_SPI_IIDX_TX_UNDERFLOW = SPI_CPU_INT_IIDX_STAT_TXFIFO_UNF_EVT, DL_SPI_IIDX_PARITY_ERROR = SPI_CPU_INT_IIDX_STAT_PER_EVT, DL_SPI_IIDX_RX_OVERFLOW = SPI_CPU_INT_IIDX_STAT_RXFIFO_OFV_EVT } |
| enum | DL_SPI_CLOCK_DIVIDE_RATIO { DL_SPI_CLOCK_DIVIDE_RATIO_1 = SPI_CLKDIV_RATIO_DIV_BY_1, DL_SPI_CLOCK_DIVIDE_RATIO_2 = SPI_CLKDIV_RATIO_DIV_BY_2, DL_SPI_CLOCK_DIVIDE_RATIO_3 = SPI_CLKDIV_RATIO_DIV_BY_3, DL_SPI_CLOCK_DIVIDE_RATIO_4 = SPI_CLKDIV_RATIO_DIV_BY_4, DL_SPI_CLOCK_DIVIDE_RATIO_5 = SPI_CLKDIV_RATIO_DIV_BY_5, DL_SPI_CLOCK_DIVIDE_RATIO_6 = SPI_CLKDIV_RATIO_DIV_BY_6, DL_SPI_CLOCK_DIVIDE_RATIO_7 = SPI_CLKDIV_RATIO_DIV_BY_7, DL_SPI_CLOCK_DIVIDE_RATIO_8 = SPI_CLKDIV_RATIO_DIV_BY_8 } |
| enum | DL_SPI_CLOCK { DL_SPI_CLOCK_BUSCLK = SPI_CLKSEL_SYSCLK_SEL_ENABLE, DL_SPI_CLOCK_MFCLK = SPI_CLKSEL_MFCLK_SEL_ENABLE, DL_SPI_CLOCK_LFCLK = SPI_CLKSEL_LFCLK_SEL_ENABLE } |
Functions | |
| void | DL_SPI_init (SPI_Regs *spi, const DL_SPI_Config *config) |
| Initialize the SPI peripheral. More... | |
| __STATIC_INLINE void | DL_SPI_enablePower (SPI_Regs *spi) |
| Enables the Peripheral Write Enable (PWREN) register for the SPI. More... | |
| __STATIC_INLINE void | DL_SPI_disablePower (SPI_Regs *spi) |
| Disables the Peripheral Write Enable (PWREN) register for the SPI. More... | |
| __STATIC_INLINE bool | DL_SPI_isPowerEnabled (const SPI_Regs *spi) |
| Returns if the Peripheral Write Enable (PWREN) register for the SPI is enabled. More... | |
| __STATIC_INLINE void | DL_SPI_reset (SPI_Regs *spi) |
| Resets spi peripheral. More... | |
| __STATIC_INLINE bool | DL_SPI_isReset (const SPI_Regs *spi) |
| Returns if spi peripheral was reset. More... | |
| __STATIC_INLINE void | DL_SPI_enable (SPI_Regs *spi) |
| Enable the SPI peripheral. More... | |
| __STATIC_INLINE bool | DL_SPI_isEnabled (const SPI_Regs *spi) |
| Checks if the SPI peripheral is enabled. More... | |
| __STATIC_INLINE void | DL_SPI_disable (SPI_Regs *spi) |
| Disable the SPI peripheral. More... | |
| void | DL_SPI_setClockConfig (SPI_Regs *spi, const DL_SPI_ClockConfig *config) |
| Configure SPI source clock. More... | |
| void | DL_SPI_getClockConfig (const SPI_Regs *spi, DL_SPI_ClockConfig *config) |
| Get SPI source clock configuration. More... | |
| __STATIC_INLINE bool | DL_SPI_isBusy (const SPI_Regs *spi) |
| Checks if the SPI is busy transmitting. More... | |
| __STATIC_INLINE bool | DL_SPI_isTXFIFOEmpty (const SPI_Regs *spi) |
| Checks if the TX FIFO is empty. More... | |
| __STATIC_INLINE bool | DL_SPI_isTXFIFOFull (const SPI_Regs *spi) |
| Checks if the TX FIFO is full. More... | |
| __STATIC_INLINE bool | DL_SPI_isRXFIFOEmpty (const SPI_Regs *spi) |
| Checks if the RX FIFO is empty. More... | |
| __STATIC_INLINE bool | DL_SPI_isRXFIFOFull (const SPI_Regs *spi) |
| Checks if the RX FIFO is full. More... | |
| __STATIC_INLINE void | DL_SPI_setParity (SPI_Regs *spi, DL_SPI_PARITY parity) |
| Sets the parity configuration used for transactions. More... | |
| __STATIC_INLINE DL_SPI_PARITY | DL_SPI_getParity (const SPI_Regs *spi) |
| Get the current receive and transmit parity configuration. More... | |
| __STATIC_INLINE void | DL_SPI_enableReceiveParity (SPI_Regs *spi) |
| Enables receive parity. More... | |
| __STATIC_INLINE void | DL_SPI_disableReceiveParity (SPI_Regs *spi) |
| Disables receive parity. More... | |
| __STATIC_INLINE bool | DL_SPI_isReceiveParityEnabled (const SPI_Regs *spi) |
| Checks if receive parity is enabled. More... | |
| __STATIC_INLINE void | DL_SPI_enableTransmitParity (SPI_Regs *spi) |
| Enables transmit parity. More... | |
| __STATIC_INLINE void | DL_SPI_disableTransmitParity (SPI_Regs *spi) |
| Disables transmit parity. More... | |
| __STATIC_INLINE bool | DL_SPI_isTransmitParityEnabled (const SPI_Regs *spi) |
| Checks if transmit parity is enabled. More... | |
| __STATIC_INLINE void | DL_SPI_setFrameFormat (SPI_Regs *spi, DL_SPI_FRAME_FORMAT frameFormat) |
| Set the frame format to use. More... | |
| __STATIC_INLINE DL_SPI_FRAME_FORMAT | DL_SPI_getFrameFormat (const SPI_Regs *spi) |
| Get the frame format configuration. More... | |
| __STATIC_INLINE void | DL_SPI_setDataSize (SPI_Regs *spi, DL_SPI_DATA_SIZE dataSize) |
| Set the size for transfers. More... | |
| __STATIC_INLINE DL_SPI_DATA_SIZE | DL_SPI_getDataSize (const SPI_Regs *spi) |
| Get the configured size for transfers. More... | |
| __STATIC_INLINE void | DL_SPI_setMode (SPI_Regs *spi, DL_SPI_MODE mode) |
| Set whether the device should be in controller/peripheral mode. More... | |
| __STATIC_INLINE DL_SPI_MODE | DL_SPI_getMode (const SPI_Regs *spi) |
| Get the current mode for the SPI (controller/peripheral) More... | |
| __STATIC_INLINE void | DL_SPI_setBitOrder (SPI_Regs *spi, DL_SPI_BIT_ORDER bitOrder) |
| Set the bit order used for transfers. More... | |
| __STATIC_INLINE DL_SPI_BIT_ORDER | DL_SPI_getBitOrder (const SPI_Regs *spi) |
| Get the current bit order used for transfers. More... | |
| __STATIC_INLINE void | DL_SPI_enableLoopbackMode (SPI_Regs *spi) |
| Enables loopback mode. More... | |
| __STATIC_INLINE void | DL_SPI_disableLoopbackMode (SPI_Regs *spi) |
| Disables loopback mode. More... | |
| __STATIC_INLINE bool | DL_SPI_isLoopbackModeEnabled (const SPI_Regs *spi) |
| Checks if the loopback mode is enabled. More... | |
| __STATIC_INLINE void | DL_SPI_setRepeatTransmit (SPI_Regs *spi, uint32_t numRepeats) |
| Set counter for repeated transmit. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getRepeatTransmit (const SPI_Regs *spi) |
| Get counter for repeated transmit. More... | |
| __STATIC_INLINE void | DL_SPI_enablePeripheralAlignDataOnChipSelect (SPI_Regs *spi) |
| Enables data alignment on chip select for peripherals. More... | |
| __STATIC_INLINE void | DL_SPI_disablePeripheralAlignDataOnChipSelect (SPI_Regs *spi) |
| Disables data alignment on chip select for peripherals. More... | |
| __STATIC_INLINE bool | DL_SPI_isPeripheralAlignDataOnChipSelectEnabled (const SPI_Regs *spi) |
| Checks if data alignment on chip select for peripherals is enabled. More... | |
| __STATIC_INLINE void | DL_SPI_enablePacking (SPI_Regs *spi) |
| Enables packing feature. More... | |
| __STATIC_INLINE void | DL_SPI_disablePacking (SPI_Regs *spi) |
| Disables packing feature. More... | |
| __STATIC_INLINE bool | DL_SPI_isPackingEnabled (const SPI_Regs *spi) |
| Checks if packing feature is enabled. More... | |
| __STATIC_INLINE void | DL_SPI_setChipSelect (SPI_Regs *spi, DL_SPI_CHIP_SELECT chipSelect) |
| Set chip select used for controller or peripheral mode. More... | |
| __STATIC_INLINE DL_SPI_CHIP_SELECT | DL_SPI_getChipSelect (const SPI_Regs *spi) |
| Get chip select used for controller or peripheral mode. More... | |
| __STATIC_INLINE void | DL_SPI_setPeripheralReceiveTimeout (SPI_Regs *spi, uint32_t timeout) |
| Set peripheral receive timeout. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getPeripheralReceiveTimeout (const SPI_Regs *spi) |
| Get peripheral receive timeout. More... | |
| __STATIC_INLINE void | DL_SPI_setControllerCommandDataModeConfig (SPI_Regs *spi, uint32_t config) |
| Configure the command/data mode. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getControllerCommandDataModeConfig (const SPI_Regs *spi) |
| Get the command/data mode configuration. More... | |
| __STATIC_INLINE void | DL_SPI_enableControllerCommandDataMode (SPI_Regs *spi) |
| Enables command/data mode. More... | |
| __STATIC_INLINE void | DL_SPI_disableControllerCommandDataMode (SPI_Regs *spi) |
| Disables command/data mode. More... | |
| __STATIC_INLINE bool | DL_SPI_isControllerCommandDataModeEnabled (const SPI_Regs *spi) |
| Checks if command/data mode is enabled. More... | |
| __STATIC_INLINE void | DL_SPI_enablePeripheralDataOutput (SPI_Regs *spi) |
| Enables peripheral data output. More... | |
| __STATIC_INLINE void | DL_SPI_disablePeripheralDataOutput (SPI_Regs *spi) |
| Disables peripheral data output. More... | |
| __STATIC_INLINE bool | DL_SPI_isPeripheralDataOutputEnabled (const SPI_Regs *spi) |
| Checks if peripheral data output is enabled. More... | |
| __STATIC_INLINE void | DL_SPI_setDelayedSampling (SPI_Regs *spi, uint32_t delay) |
| Set the delay sampling. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getDelayedSampling (const SPI_Regs *spi) |
| Get the delay sampling. More... | |
| __STATIC_INLINE void | DL_SPI_setFIFOThreshold (SPI_Regs *spi, DL_SPI_RX_FIFO_LEVEL rxThreshold, DL_SPI_TX_FIFO_LEVEL txThreshold) |
| Set the RX and TX FIFO interrupt threshold level. More... | |
| __STATIC_INLINE DL_SPI_TX_FIFO_LEVEL | DL_SPI_getTXFIFOThreshold (const SPI_Regs *spi) |
| Get the TX FIFO interrupt threshold level. More... | |
| __STATIC_INLINE DL_SPI_RX_FIFO_LEVEL | DL_SPI_getRXFIFOThreshold (const SPI_Regs *spi) |
| Get the RX FIFO interrupt threshold level. More... | |
| __STATIC_INLINE void | DL_SPI_setBitRateSerialClockDivider (SPI_Regs *spi, uint32_t SCR) |
| Set the SPI bit rate serial clock divider (SCR) More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getBitRateSerialClockDivider (const SPI_Regs *spi) |
| Get the SPI bit rate serial clock divider (SCR) More... | |
| __STATIC_INLINE void | DL_SPI_transmitData8 (SPI_Regs *spi, uint8_t data) |
| Writes 8-bit data into the TX FIFO for transmit. More... | |
| __STATIC_INLINE void | DL_SPI_transmitData16 (SPI_Regs *spi, uint16_t data) |
| Writes 16-bit data into the TX FIFO for transmit. More... | |
| __STATIC_INLINE void | DL_SPI_transmitData32 (SPI_Regs *spi, uint32_t data) |
| Writes 32-bit data into the TX FIFO for transmit. More... | |
| __STATIC_INLINE uint8_t | DL_SPI_receiveData8 (const SPI_Regs *spi) |
| Reads 8-bit data from the RX FIFO. More... | |
| __STATIC_INLINE uint16_t | DL_SPI_receiveData16 (const SPI_Regs *spi) |
| Reads 16-bit data from the RX FIFO. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_receiveData32 (const SPI_Regs *spi) |
| Reads 32-bit data from the RX FIFO. More... | |
| __STATIC_INLINE void | DL_SPI_enableInterrupt (SPI_Regs *spi, uint32_t interruptMask) |
| Enable SPI interrupts. More... | |
| __STATIC_INLINE void | DL_SPI_disableInterrupt (SPI_Regs *spi, uint32_t interruptMask) |
| Disable SPI interrupts. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getEnabledInterrupts (const SPI_Regs *spi, uint32_t interruptMask) |
| Check which SPI interrupts are enabled. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getEnabledInterruptStatus (const SPI_Regs *spi, uint32_t interruptMask) |
| Check interrupt flag of enabled SPI interrupts. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getRawInterruptStatus (const SPI_Regs *spi, uint32_t interruptMask) |
| Check interrupt flag of any SPI interrupt. More... | |
| __STATIC_INLINE DL_SPI_IIDX | DL_SPI_getPendingInterrupt (const SPI_Regs *spi) |
| Get highest priority pending SPI interrupt. More... | |
| __STATIC_INLINE void | DL_SPI_clearInterruptStatus (SPI_Regs *spi, uint32_t interruptMask) |
| Clear pending SPI interrupts. More... | |
| void | DL_SPI_transmitDataBlocking8 (SPI_Regs *spi, uint8_t data) |
| Blocks to ensure transmit is ready before sending data. More... | |
| void | DL_SPI_transmitDataBlocking16 (SPI_Regs *spi, uint16_t data) |
| Blocks to ensure transmit is ready before sending data. More... | |
| void | DL_SPI_transmitDataBlocking32 (SPI_Regs *spi, uint32_t data) |
| Blocks to ensure transmit is ready before sending data. More... | |
| uint8_t | DL_SPI_receiveDataBlocking8 (const SPI_Regs *spi) |
| Blocks to ensure receive is ready before reading data. More... | |
| uint16_t | DL_SPI_receiveDataBlocking16 (const SPI_Regs *spi) |
| Blocks to ensure receive is ready before reading data. More... | |
| uint32_t | DL_SPI_receiveDataBlocking32 (const SPI_Regs *spi) |
| Blocks to ensure receive is ready before reading data. More... | |
| bool | DL_SPI_transmitDataCheck8 (SPI_Regs *spi, uint8_t data) |
| Checks the TX FIFO before trying to transmit data. More... | |
| bool | DL_SPI_transmitDataCheck16 (SPI_Regs *spi, uint16_t data) |
| Checks the TX FIFO before trying to transmit data. More... | |
| bool | DL_SPI_transmitDataCheck32 (SPI_Regs *spi, uint32_t data) |
| Checks the TX FIFO before trying to transmit data. More... | |
| bool | DL_SPI_receiveDataCheck8 (const SPI_Regs *spi, uint8_t *buffer) |
| Checks the RX FIFO before trying to transmit data. More... | |
| bool | DL_SPI_receiveDataCheck16 (const SPI_Regs *spi, uint16_t *buffer) |
| Checks the RX FIFO before trying to transmit data. More... | |
| bool | DL_SPI_receiveDataCheck32 (const SPI_Regs *spi, uint32_t *buffer) |
| Checks the RX FIFO before trying to transmit data. More... | |
| uint32_t | DL_SPI_drainRXFIFO8 (const SPI_Regs *spi, uint8_t *buffer, uint32_t maxCount) |
| Read all available data out of the RX FIFO using 8 bit access. More... | |
| uint32_t | DL_SPI_drainRXFIFO16 (const SPI_Regs *spi, uint16_t *buffer, uint32_t maxCount) |
| Read all available data out of the RX FIFO using 16 bit access. More... | |
| uint32_t | DL_SPI_drainRXFIFO32 (const SPI_Regs *spi, uint32_t *buffer, uint32_t maxCount) |
| Read all available data out of the RX FIFO using 32 bit access. More... | |
| uint32_t | DL_SPI_fillTXFIFO8 (SPI_Regs *spi, const uint8_t *buffer, uint32_t count) |
| Fill the TX FIFO using 8 bit access. More... | |
| uint32_t | DL_SPI_fillTXFIFO16 (SPI_Regs *spi, const uint16_t *buffer, uint32_t count) |
| Fill the TX FIFO using 16 bit access. More... | |
| uint32_t | DL_SPI_fillTXFIFO32 (SPI_Regs *spi, const uint32_t *buffer, uint32_t count) |
| Fill the TX FIFO using 32 bit access. More... | |
| __STATIC_INLINE void | DL_SPI_enableDMAReceiveEvent (SPI_Regs *spi, uint32_t interrupt) |
| Enable SPI interrupt for triggering the DMA receive event. More... | |
| __STATIC_INLINE void | DL_SPI_enableDMATransmitEvent (SPI_Regs *spi) |
| Enable SPI interrupt for triggering the DMA transmit event. More... | |
| __STATIC_INLINE void | DL_SPI_disableDMAReceiveEvent (SPI_Regs *spi, uint32_t interrupt) |
| Disables SPI interrupt from triggering the DMA receive event. More... | |
| __STATIC_INLINE void | DL_SPI_disableDMATransmitEvent (SPI_Regs *spi) |
| Disables SPI interrupt from triggering the DMA transmit event. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getEnabledDMAReceiveEvent (const SPI_Regs *spi, uint32_t interruptMask) |
| Check which SPI interrupt for DMA receive events is enabled. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getEnabledDMATransmitEvent (const SPI_Regs *spi) |
| Check if SPI interrupt for DMA transmit event is enabled. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getEnabledDMAReceiveEventStatus (const SPI_Regs *spi, uint32_t interruptMask) |
| Check interrupt flag of enabled SPI interrupt for DMA receive event. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getEnabledDMATransmitEventStatus (const SPI_Regs *spi) |
| Check interrupt flag of enabled SPI interrupt for DMA transmit event. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getRawDMAReceiveEventStatus (const SPI_Regs *spi, uint32_t interruptMask) |
| Check interrupt flag of any SPI interrupt for DMA receive event. More... | |
| __STATIC_INLINE uint32_t | DL_SPI_getRawDMATransmitEventStatus (const SPI_Regs *spi) |
| Check interrupt flag of any SPI interrupt for DMA transmit event. More... | |
| __STATIC_INLINE DL_SPI_DMA_IIDX_RX | DL_SPI_getPendingDMAReceiveEvent (const SPI_Regs *spi) |
| Get highest priority pending SPI interrupt for DMA receive event. More... | |
| __STATIC_INLINE DL_SPI_DMA_IIDX_TX | DL_SPI_getPendingDMATransmitEvent (const SPI_Regs *spi) |
| Get highest priority pending SPI interrupt for DMA transmit event. More... | |
| __STATIC_INLINE void | DL_SPI_clearDMAReceiveEventStatus (SPI_Regs *spi, uint32_t interruptMask) |
| Clear pending SPI interrupts for DMA receive event. More... | |
| __STATIC_INLINE void | DL_SPI_clearDMATransmitEventStatus (SPI_Regs *spi) |
| Clear pending SPI interrupt for DMA transmit event. More... | |
| bool | DL_SPI_saveConfiguration (const SPI_Regs *spi, DL_SPI_backupConfig *ptr) |
| Save SPI configuration before entering a power loss state. More... | |
| bool | DL_SPI_restoreConfiguration (SPI_Regs *spi, DL_SPI_backupConfig *ptr) |
| Restore SPI configuration after leaving a power loss state. More... | |