MSPM0G3519SensoredFOCMotorControlLibrary  1.0
drv8323.h
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75 /*!****************************************************************************
76  * @file drv8323.h
77  * @brief DRV8323 gate driver Module
78  *
79  *
80  * @anchor drv8323_h
81  * # Overview
82  *
83  * defines APIs for drv8323 gate driver
84  *
85  * <hr>
86  ******************************************************************************/
87 
88 #ifndef DRV8323_H
89 #define DRV8323_H
90 
91 #include "stdint.h"
92 #include "main.h"
93 #include "appInputCtrlInterface.h"
94 
95 
96 #ifdef __cplusplus
97 extern "C" {
98 #endif
99 
100 #ifdef DRV8323
101 
103 #define DRV8323_ADDR_MASK (0x7800)
104 
106 #define DRV8323_DATA_MASK (0x07FF)
107 
109 #define DRV8323_RW_MASK (0x8000)
110 
112 #define DRV8323_REG_0 0x00
113 
114 #define DRV8323_REG_1 0x01
115 
116 #define DRV8323_REG_2 0x02
117 
118 #define DRV8323_REG_3 0x03
119 
120 #define DRV8323_REG_4 0x04
121 
122 #define DRV8323_REG_5 0x05
123 
124 #define DRV8323_REG_6 0x06
125 
127 #define DRV8323_FAULT_TYPE_MASK (0x07FF)
128 
130 #define DRV8323_STATUS00_VDS_LC_BITS (1 << 0)
131 
132 #define DRV8323_STATUS00_VDS_HC_BITS (1 << 1)
133 
134 #define DRV8323_STATUS00_VDS_LB_BITS (1 << 2)
135 
136 #define DRV8323_STATUS00_VDS_HB_BITS (1 << 3)
137 
138 #define DRV8323_STATUS00_VDS_LA_BITS (1 << 4)
139 
140 #define DRV8323_STATUS00_VDS_HA_BITS (1 << 5)
141 
142 #define DRV8323_STATUS00_OTSD_BITS (1 << 6)
143 
144 #define DRV8323_STATUS00_UVLO_BITS (1 << 7)
145 
146 #define DRV8323_STATUS00_GDF_BITS (1 << 8)
147 
148 #define DRV8323_STATUS00_VDS_OCP_BITS (1 << 9)
149 
150 #define DRV8323_STATUS00_FAULT_BITS (1 << 10)
151 
152 
154 #define DRV8323_STATUS01_VGS_LC_BITS (1 << 0)
155 
157 #define DRV8323_STATUS01_VGS_HC_BITS (1 << 1)
158 
160 #define DRV8323_STATUS01_VGS_LB_BITS (1 << 2)
161 
163 #define DRV8323_STATUS01_VGS_HB_BITS (1 << 3)
164 
166 #define DRV8323_STATUS01_VGS_LA_BITS (1 << 4)
167 
169 #define DRV8323_STATUS01_VGS_HA_BITS (1 << 5)
170 
172 #define DRV8323_STATUS01_CPUV_BITS (1 << 6)
173 
175 #define DRV8323_STATUS01_OTW_BITS (1 << 7)
176 
178 #define DRV8323_STATUS01_SC_OC_BITS (1 << 8)
179 
181 #define DRV8323_STATUS01_SB_OC_BITS (1 << 9)
182 
184 #define DRV8323_STATUS01_SA_OC_BITS (1 << 10)
185 
186 
187 
189 #define DRV8323_CTRL02_CLR_FLT_BITS (1 << 0)
190 
192 #define DRV8323_CTRL02_BRAKE_BITS (1 << 1)
193 
195 #define DRV8323_CTRL02_COAST_BITS (1 << 2)
196 
198 #define DRV8323_CTRL02_PWM1_DIR_BITS (1 << 3)
199 
201 #define DRV8323_CTRL02_PWM1_COM_BITS (1 << 4)
202 
204 #define DRV8323_CTRL02_PWM_MODE_BITS (3 << 5)
205 
207 #define DRV8323_CTRL02_OTW_REP_BITS (1 << 7)
208 
210 #define DRV8323_CTRL02_DIS_GDF_BITS (1 << 8)
211 
213 #define DRV8323_CTRL02_DIS_CPUV_BITS (1 << 9)
214 
216 #define DRV8323_CTRL02_RESERVED1_BITS (1 << 10)
217 
218 
220 #define DRV8323_CTRL03_IDRIVEN_HS_BITS (15 << 0)
221 
223 #define DRV8323_CTRL03_IDRIVEP_HS_BITS (15 << 4)
224 
226 #define DRV8323_CTRL03_LOCK_BITS (7 << 8)
227 
229 #define DRV8323_CTRL04_IDRIVEN_LS_BITS (15 << 0)
230 
232 #define DRV8323_CTRL04_IDRIVEP_LS_BITS (15 << 4)
233 
235 #define DRV8323_CTRL04_TDRIVE_BITS (3 << 8)
236 
238 #define DRV8323_CTRL04_CBC_BITS (1 << 10)
239 
240 
242 #define DRV8323_CTRL05_VDS_LVL_BITS (15 << 0)
243 
245 #define DRV8323_CTRL05_OCP_DEG_BITS (3 << 4)
246 
248 #define DRV8323_CTRL05_OCP_MODE_BITS (3 << 6)
249 
251 #define DRV8323_CTRL05_DEAD_TIME_BITS (3 << 8)
252 
254 #define DRV8323_CTRL05_TRETRY_BITS (1 << 10)
255 
256 
258 #define DRV8323_CTRL06_SEN_LVL_BITS (3 << 0)
259 
261 #define DRV8323_CTRL06_CSA_CAL_C_BITS (1 << 2)
262 
264 #define DRV8323_CTRL06_CSA_CAL_B_BITS (1 << 3)
265 
267 #define DRV8323_CTRL06_CSA_CAL_A_BITS (1 << 4)
268 
270 #define DRV8323_CTRL06_DIS_SEN_BITS (1 << 5)
271 
273 #define DRV8323_CTRL06_CSA_GAIN_BITS (3 << 6)
274 
276 #define DRV8323_CTRL06_LS_REF_BITS (1 << 8)
277 
279 #define DRV8323_CTRL06_VREF_DIV_BITS (1 << 9)
280 
282 #define DRV8323_CTRL06_CSA_FET_BITS (1 << 10)
283 
287 #define DRV8323_OTW_REP_POS 7
288 
289 #define DRV8323_DIS_GDF_POS 8
290 
291 #define DRV8323_DIS_CPUV_POS 9
292 
294 #define DRV8323_IDRIVEN_HS_POS 0
295 
296 #define DRV8323_IDRIVEP_HS_POS 4
297 
299 #define DRV8323_IDRIVEN_LS_POS 0
300 
301 #define DRV8323_IDRIVEP_LS_POS 4
302 
303 #define DRV8323_TDRIVE_POS 8
304 
305 #define DRV8323_CBC_POS 10
306 
308 #define DRV8323_VDS_LVL_POS 0
309 
310 #define DRV8323_OCP_DEG_POS 4
311 
312 #define DRV8323_OCP_MODE_POS 6
313 
314 #define DRV8323_DEAD_TIME_POS 8
315 
316 #define DRV8323_TRETRY_POS 10
317 
319 #define DRV8323_SEN_LVL_POS 0
320 
321 #define DRV8323_DIS_SEN_POS 5
322 
323 #define DRV8323_CSA_GAIN_POS 6
324 
325 #define DRV8323_LS_REF_POS 8
326 
327 #define DRV8323_VREF_DIV_POS 9
328 
329 #define DRV8323_CSA_FET_POS 10
330 /*************************************************************************/
331 
333 typedef enum
334 {
336  CtrlMode_Read = 1 << 15,
338  CtrlMode_Write = 0 << 15
339 } DRV8323_CtrlMode_e;
340 
342 typedef enum
343 {
345  VDS_LC = (1 << 0),
347  VDS_HC = (1 << 1),
349  VDS_LB = (1 << 2),
351  VDS_HB = (1 << 3),
353  VDS_LA = (1 << 4),
355  VDS_HA = (1 << 5),
357  OTSD = (1 << 6),
359  UVLO = (1 << 7),
361  GDF = (1 << 8),
363  VDS_OCP = (1 << 9),
365  FAULT1 = (1 << 10)
366 } DRV8323_STATUS00_WarningWatchdog_e;
367 
368 
370 typedef enum
371 {
373  VGS_LC = (1 << 0),
375  VGS_HC = (1 << 1),
377  VGS_LB = (1 << 2),
379  VGS_HB = (1 << 3),
381  VGS_LA = (1 << 4),
383  VGS_HA = (1 << 5),
385  CPUV = (1 << 6),
387  OTW = (1 << 7),
389  SC_OC = (1 << 8),
391  SB_OC = (1 << 9),
393  SA_OC = (1 << 10)
394 } DRV8323_STATUS01_OvVdsFaults_e;
395 
396 
398 typedef enum
399 {
401  PwmMode_6 = (0 << 5),
403  PwmMode_3 = (1 << 5),
405  PwmMode_1 = (2 << 5)
406 } DRV8323_CTRL02_PwmMode_e;
407 
408 
410 typedef enum
411 {
413  ISour_HS_0p010_A = (0 << 4),
415  ISour_HS_0p020_A = (1 << 4),
417  ISour_HS_0p030_A = (2 << 4),
419  ISour_HS_0p040_A = (3 << 4),
421  ISour_HS_0p050_A = (4 << 4),
423  ISour_HS_0p060_A = (5 << 4),
425  ISour_HS_0p070_A = (6 << 4),
427  ISour_HS_0p125_A = (7 << 4),
429  ISour_HS_0p250_A = (8 << 4),
431  ISour_HS_0p500_A = (9 << 4),
433  ISour_HS_0p750_A = (10 << 4),
435  ISour_HS_1p000_A = (11 << 4)
436 } DRV8323_CTRL03_PeakSourCurHS_e;
437 
438 
440 typedef enum
441 {
443  ISink_HS_0p020_A = (0 << 0),
445  ISink_HS_0p030_A = (1 << 0),
447  ISink_HS_0p040_A = (2 << 0),
449  ISink_HS_0p050_A = (3 << 0),
451  ISink_HS_0p060_A = (4 << 0),
453  ISink_HS_0p070_A = (5 << 0),
455  ISink_HS_0p125_A = (6 << 0),
457  ISink_HS_0p250_A = (7 << 0),
459  ISink_HS_0p500_A = (8 << 0),
461  ISink_HS_0p750_A = (9 << 0),
463  ISink_HS_1p000_A = (10 << 0),
465  ISink_HS_1p250_A = (11 << 0)
466 } DRV8323_CTRL03_PeakSinkCurHS_e;
467 
468 
470 typedef enum
471 {
473  Lock_lock = (6 << 8),
475  Lock_unlock = (3 << 8)
476 } DRV8323_CTRL03_Lock_e;
477 
478 
480 typedef enum
481 {
483  TSour_250_ns = (0 << 8),
485  TSour_500_ns = (1 << 8),
487  TSour_1000_ns = (2 << 8),
489  TSour_2000_ns = (3 << 8)
490 } DRV8323_CTRL04_PeakTime_e;
491 
492 
494 typedef enum
495 {
497  ISour_LS_0p010_A = (0 << 4),
499  ISour_LS_0p030_A = (1 << 4),
501  ISour_LS_0p060_A = (2 << 4),
503  ISour_LS_0p080_A = (3 << 4),
505  ISour_LS_0p120_A = (4 << 4),
507  ISour_LS_0p140_A = (5 << 4),
509  ISour_LS_0p170_A = (6 << 4),
511  ISour_LS_0p190_A = (7 << 4),
513  ISour_LS_0p250_A = (8 << 4),
515  ISour_LS_0p330_A = (9 << 4),
517  ISour_LS_0p370_A = (10 << 4),
519  ISour_LS_0p440_A = (11 << 4),
521  ISour_LS_0p570_A = (12 << 4),
523  ISour_LS_0p680_A = (13 << 4),
525  ISour_LS_0p820_A = (14 << 4),
527  ISour_LS_1p000_A = (15 << 4)
528 } DRV8323_CTRL04_PeakSourCurLS_e;
529 
530 
532 typedef enum
533 {
535  ISink_LS_0p020_A = (0 << 0),
537  ISink_LS_0p060_A = (1 << 0),
539  ISink_LS_0p120_A = (2 << 0),
541  ISink_LS_0p160_A = (3 << 0),
543  ISink_LS_0p240_A = (4 << 0),
545  ISink_LS_0p280_A = (5 << 0),
547  ISink_LS_0p340_A = (6 << 0),
549  ISink_LS_0p380_A = (7 << 0),
551  ISink_LS_0p520_A = (8 << 0),
553  ISink_LS_0p660_A = (9 << 0),
555  ISink_LS_0p740_A = (10 << 0),
557  ISink_LS_0p880_A = (11 << 0),
559  ISink_LS_1p140_A = (12 << 0),
561  ISink_LS_1p360_A = (13 << 0),
563  ISink_LS_1p640_A = (14 << 0),
565  ISink_LS_2p000_A = (15 << 0)
566 } DRV8323_CTRL04_PeakSinkCurLS_e;
567 
568 
570 typedef enum
571 {
573  VDS_Level_0p060_V = (0 << 0),
575  VDS_Level_0p130_V = (1 << 0),
577  VDS_Level_0p200_V = (2 << 0),
579  VDS_Level_0p260_V = (3 << 0),
581  VDS_Level_0p310_V = (4 << 0),
583  VDS_Level_0p450_V = (5 << 0),
585  VDS_Level_0p530_V = (6 << 0),
587  VDS_Level_0p600_V = (7 << 0),
589  VDS_Level_0p680_V = (8 << 0),
591  VDS_Level_0p750_V = (9 << 0),
593  VDS_Level_0p940_V = (10 << 0),
595  VDS_Level_1p130_V = (11 << 0),
597  VDS_Level_1p300_V = (12 << 0),
599  VDS_Level_1p500_V = (13 << 0),
601  VDS_Level_1p700_V = (14 << 0),
603  VDS_Level_1p880_V = (15 << 0)
604 } DRV8323_CTRL05_VDSLVL_e;
605 
606 
608 typedef enum
609 {
611  VDSDeg_0_us = (0 << 4),
613  VDSDeg_2_us = (1 << 4),
615  VDSDeg_4_us = (2 << 4),
617  VDSDeg_8_us = (3 << 4)
618 } DRV8323_CTRL05_OcpDeg_e;
619 
620 
622 typedef enum
623 {
625  Latched_Shutdown = (0 << 6),
627  Automatic_Retry = (1 << 6),
629  Report_Only = (2 << 6),
631  Disable_OCP = (3 << 6)
632 } DRV8323_CTRL05_OcpMode_e;
633 
634 
636 typedef enum
637 {
639  DeadTime_50_ns = (0 << 8),
641  DeadTime_100_ns = (1 << 8),
643  DeadTime_200_ns = (2 << 8),
645  DeadTime_400_ns = (3 << 8)
646 } DRV8323_CTRL05_DeadTime_e;
647 
648 
650 typedef enum
651 {
653  SEN_Lvl_Ocp_0p25 = (0 << 0),
655  SEN_Lvl_Ocp_0p50 = (1 << 0),
657  SEN_Lvl_Ocp_0p75 = (2 << 0),
659  SEN_Lvl_Ocp_1p00 = (3 << 0)
660 } DRV8323_CTRL06_SENLevel_e;
661 
662 
664 typedef enum
665 {
667  Gain_5VpV = (0 << 6),
669  Gain_10VpV = (1 << 6),
671  Gain_20VpV = (2 << 6),
673  Gain_40VpV = (3 << 6)
674 } DRV8323_CTRL06_CSAGain_e;
675 
676 
678 typedef enum
679 {
681  Address_Status_0 = 0 << 11,
683  Address_Status_1 = 1 << 11,
685  Address_Control_2 = 2 << 11,
687  Address_Control_3 = 3 << 11,
689  Address_Control_4 = 4 << 11,
691  Address_Control_5 = 5 << 11,
693  Address_Control_6 = 6 << 11
694 } DRV8323_Address_e;
695 
696 
698 typedef struct _DRV_SPI_8323_Stat00_t_
699 {
701  _Bool VDS_LC;
703  _Bool VDS_HC;
705  _Bool VDS_LB;
707  _Bool VDS_HB;
709  _Bool VDS_LA;
711  _Bool VDS_HA;
713  _Bool OTSD;
715  _Bool UVLO;
717  _Bool GDF;
719  _Bool VDS_OCP;
721  _Bool FAULT;
722 }DRV_SPI_8323_Stat00_t_;
723 
724 
726 typedef struct _DRV_SPI_8323_Stat01_t_
727 {
729  _Bool VGS_LC;
731  _Bool VGS_HC;
733  _Bool VGS_LB;
735  _Bool VGS_HB;
737  _Bool VGS_LA;
739  _Bool VGS_HA;
741  _Bool CPUV;
743  _Bool OTW;
745  _Bool SC_OC;
747  _Bool SB_OC;
749  _Bool SA_OC;
750 }DRV_SPI_8323_Stat01_t_;
751 
752 
754 typedef struct _DRV_SPI_8323_Ctrl02_t_
755 {
757  _Bool CLR_FLT;
759  _Bool BRAKE;
761  _Bool COAST;
763  _Bool PWM1_DIR;
765  _Bool PWM1_COM;
767  DRV8323_CTRL02_PwmMode_e PWM_MODE;
769  _Bool OTW_REP;
771  _Bool DIS_GDF;
773  _Bool DIS_CPUV;
775  _Bool CTRL02_RSV1;
776 }DRV_SPI_8323_Ctrl02_t_;
777 
778 
780 typedef struct _DRV_SPI_8323_Ctrl03_t_
781 {
783  DRV8323_CTRL03_PeakSinkCurHS_e IDRIVEN_HS;
785  DRV8323_CTRL03_PeakSourCurHS_e IDRIVEP_HS;
787  DRV8323_CTRL03_Lock_e LOCK;
788 }DRV_SPI_8323_Ctrl03_t_;
789 
790 
792 typedef struct _DRV_SPI_8323_Ctrl04_t_
793 {
795  DRV8323_CTRL04_PeakSinkCurLS_e IDRIVEN_LS;
797  DRV8323_CTRL04_PeakSourCurLS_e IDRIVEP_LS;
799  DRV8323_CTRL04_PeakTime_e TDRIVE;
801  _Bool CBC;
802 }DRV_SPI_8323_Ctrl04_t_;
803 
804 
806 typedef struct _DRV_SPI_8323_Ctrl05_t_
807 {
809  DRV8323_CTRL05_VDSLVL_e VDS_LVL;
811  DRV8323_CTRL05_OcpDeg_e OCP_DEG;
813  DRV8323_CTRL05_OcpMode_e OCP_MODE;
815  DRV8323_CTRL05_DeadTime_e DEAD_TIME;
817  _Bool TRETRY;
818 }DRV_SPI_8323_Ctrl05_t_;
819 
820 
822 typedef struct _DRV_SPI_8323_Ctrl06_t_
823 {
825  DRV8323_CTRL06_SENLevel_e SEN_LVL;
827  _Bool CSA_CAL_C;
829  _Bool CSA_CAL_B;
831  _Bool CSA_CAL_A;
833  _Bool DIS_SEN;
835  DRV8323_CTRL06_CSAGain_e CSA_GAIN;
837  _Bool LS_REF;
839  _Bool VREF_DIV;
841  _Bool CSA_FET;
842 }DRV_SPI_8323_Ctrl06_t_;
843 
845 typedef struct _DRV_SPI_8323_Vars_t_
846 {
848  DRV_SPI_8323_Stat00_t_ Stat_Reg_00;
850  DRV_SPI_8323_Stat01_t_ Stat_Reg_01;
852  DRV_SPI_8323_Ctrl02_t_ Ctrl_Reg_02;
854  DRV_SPI_8323_Ctrl03_t_ Ctrl_Reg_03;
856  DRV_SPI_8323_Ctrl04_t_ Ctrl_Reg_04;
858  DRV_SPI_8323_Ctrl05_t_ Ctrl_Reg_05;
860  DRV_SPI_8323_Ctrl06_t_ Ctrl_Reg_06;
861 } DRV_SPI_8323_Vars_t;
862 
865 typedef uint16_t DRV8323_Word_t;
866 
868 typedef union
869 {
870  struct DRV8323Cfg1
871  {
872  uint32_t
874  iDriveNLS: 4,
876  vdsLevel: 4,
878  ocpDeg: 2,
880  ocpMode: 2,
882  deadTime: 2,
884  tRetry: 1,
886  senLvl: 2,
888  csaCalC: 1,
890  csaCalB: 1,
892  csaCalA: 1,
894  disSen: 1,
896  csaGain: 2,
898  lsRef: 1,
900  vrefDiv: 1,
902  csaFET: 1,
904  reserved1: 5,
905  parity: 1;
906 
907  }b;
908  uint32_t w;
909 }GATE_DRIVE_8323_CFG1_T;
910 
912 typedef union
913 {
914  struct DRV8323Cfg2
915  {
916  uint32_t
918  clrFLT: 1,
920  brake: 1,
922  coast: 1,
924  pwmDir: 1,
926  pwmComm: 1,
928  pwmMode: 2,
930  repOTW: 1,
932  disGDF: 1,
934  disCPUV: 1,
936  reg2Rsvd: 1,
938  iDriveNHS: 4,
940  iDrivePHS: 4,
942  lock: 3,
944  iDrivePLS: 4,
946  tDrive: 2,
948  cbc: 1,
950  reserved: 2,
951  parity: 1;
952  }b;
953  uint32_t w;
954 }GATE_DRIVE_8323_CFG2_T;
955 
956 /*
957 typedef struct hvDie8323EEPROMInterface
958 {
960  GATE_DRIVE_8323_CFG1_T gateDrvCfg1;
962  GATE_DRIVE_8323_CFG2_T gateDrvCfg2;
963 
964 } HV_DIE_EEPROM_INTERFACE_T;
965 
966 extern HV_DIE_EEPROM_INTERFACE_T *pGateDriverConfig;
967 
972 uint32_t drv8323StatusRead(void);
973 
974 /******************************************************************************/
976 #define GD1_REG6_MASK 0x07FF8000
977 
979 #define GD1_REG6_POS 15
980 
982 #define DRV_REG6_WRITE_PROTECT_MASK 0x61C
983 
984 /******************************************************************************/
986 #define GD1_REG5_MASK 0x00007FF0
987 
989 #define GD1_REG5_POS 4
990 
992 #define DRV_REG5_WRITE_PROTECT_MASK 0x00000000
993 
994 /******************************************************************************/
996 #define GD2_REG4_MASK 0x1FC00000
997 
998 #define GD1_REG4_MASK 0x0000000F
999 
1001 #define GD2_REG4_POS 22
1002 
1004 #define GD2_REG4_DRV_POS 4
1005 
1007 #define GD1_REG4_POS 0
1008 
1010 #define DRV_REG4_WRITE_PROTECT_MASK 0x00000400
1011 
1012 /******************************************************************************/
1014 #define GD2_REG3_MASK 0x003FF800
1015 
1017 #define GD2_REG3_POS 11
1018 
1020 #define DRV_REG3_WRITE_PROTECT_MASK 0x00000700
1021 
1022 /******************************************************************************/
1024 #define GD2_REG2_MASK 0x000007FF
1025 
1027 #define GD2_REG2_POS 0
1028 
1030 #define DRV_REG2_WRITE_PROTECT_MASK 0x47F
1031 
1032 /******************************************************************************/
1033 
1034 /******************************************************************************/
1036 #define GD_UVLO_FAULT_MASK 0x10000000
1037 
1038 #define GD_UVLO_FAULT_POS 28U
1039 
1041 #define GD_OTSD_FAULT_MASK 0x08000000
1042 
1043 #define GD_OTSD_FAULT_POS 27U
1044 
1045 /******************************************************************************/
1046 
1047 #endif
1048 #ifdef __cplusplus
1049 }
1050 #endif
1051 #endif
appInputCtrlInterface.h
Application Defines Module.
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