MSPM0GX51X Driver Library  2.05.01.00
dl_mcan.h
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1 /*
2  * Copyright (c) 2021, Texas Instruments Incorporated
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
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10  * notice, this list of conditions and the following disclaimer.
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12  * * Redistributions in binary form must reproduce the above copyright
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14  * documentation and/or other materials provided with the distribution.
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17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
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31  */
32 /*!****************************************************************************
33  * @file dl_mcan.h
34  * @brief Modular Controller Area Network (MCAN) Driver Library
35  * @defgroup MCAN Modular Controller Area Network (MCAN)
36  *
37  * @anchor ti_dl_dl_mcan_Overview
38  * # Overview
39  *
40  * The MCAN Driver Library allows full configuration of the MSPM0 MCAN (CAN-FD)
41  * module.
42  * The Modular Controller Area Network (MCAN) peripheral supports both
43  * communication through classic CAN and CAN-FD protocols.
44  *
45  * <hr>
46  ******************************************************************************
47  */
51 #ifndef ti_dl_dl_mcan__include
52 #define ti_dl_dl_mcan__include
53 
54 #include <stdbool.h>
55 #include <stdint.h>
56 
57 #include <ti/devices/msp/msp.h>
58 #include <ti/driverlib/dl_common.h>
59 
60 #ifdef __MSPM0_HAS_MCAN__
61 
62 #ifdef __cplusplus
63 extern "C" {
64 #endif
65 
66 /* clang-format off */
67 
71 #define DL_MCAN_INTR_MASK_ALL (MCAN_IR_RF0N_MASK | \
72  MCAN_IR_RF0W_MASK | \
73  MCAN_IR_RF0F_MASK | \
74  MCAN_IR_RF0L_MASK | \
75  MCAN_IR_RF1N_MASK | \
76  MCAN_IR_RF1W_MASK | \
77  MCAN_IR_RF1F_MASK | \
78  MCAN_IR_RF1L_MASK | \
79  MCAN_IR_HPM_MASK | \
80  MCAN_IR_TC_MASK | \
81  MCAN_IR_TCF_MASK | \
82  MCAN_IR_TFE_MASK | \
83  MCAN_IR_TEFN_MASK | \
84  MCAN_IR_TEFW_MASK | \
85  MCAN_IR_TEFF_MASK | \
86  MCAN_IR_TEFL_MASK | \
87  MCAN_IR_TSW_MASK | \
88  MCAN_IR_MRAF_MASK | \
89  MCAN_IR_TOO_MASK | \
90  MCAN_IR_DRX_MASK | \
91  MCAN_IR_BEU_MASK | \
92  MCAN_IR_ELO_MASK | \
93  MCAN_IR_EP_MASK | \
94  MCAN_IR_EW_MASK | \
95  MCAN_IR_BO_MASK | \
96  MCAN_IR_WDI_MASK | \
97  MCAN_IR_PEA_MASK | \
98  MCAN_IR_PED_MASK | \
99  MCAN_IR_ARA_MASK)
100 
104 #define DL_MCAN_MAX_PAYLOAD_BYTES (64U)
105 
106 
113 #define DL_MCAN_INTERRUPT_ARA (MCAN_IR_ARA_MASK)
114 
118 #define DL_MCAN_INTERRUPT_PED (MCAN_IR_PED_MASK)
119 
123 #define DL_MCAN_INTERRUPT_PEA (MCAN_IR_PEA_MASK)
124 
128 #define DL_MCAN_INTERRUPT_WDI (MCAN_IR_WDI_MASK)
129 
133 #define DL_MCAN_INTERRUPT_BO (MCAN_IR_BO_MASK)
134 
138 #define DL_MCAN_INTERRUPT_EW (MCAN_IR_EW_MASK)
139 
143 #define DL_MCAN_INTERRUPT_EP (MCAN_IR_EP_MASK)
144 
148 #define DL_MCAN_INTERRUPT_ELO (MCAN_IR_ELO_MASK)
149 
153 #define DL_MCAN_INTERRUPT_BEU (MCAN_IR_BEU_MASK)
154 
158 #define DL_MCAN_INTERRUPT_DRX (MCAN_IR_DRX_MASK)
159 
163 #define DL_MCAN_INTERRUPT_TOO (MCAN_IR_TOO_MASK)
164 
168 #define DL_MCAN_INTERRUPT_MRAF (MCAN_IR_MRAF_MASK)
169 
173 #define DL_MCAN_INTERRUPT_TSW (MCAN_IR_TSW_MASK)
174 
178 #define DL_MCAN_INTERRUPT_TEFL (MCAN_IR_TEFL_MASK)
179 
183 #define DL_MCAN_INTERRUPT_TEFF (MCAN_IR_TEFF_MASK)
184 
188 #define DL_MCAN_INTERRUPT_TEFW (MCAN_IR_TEFW_MASK)
189 
193 #define DL_MCAN_INTERRUPT_TEFN (MCAN_IR_TEFN_MASK)
194 
198 #define DL_MCAN_INTERRUPT_TFE (MCAN_IR_TFE_MASK)
199 
203 #define DL_MCAN_INTERRUPT_TCF (MCAN_IR_TCF_MASK)
204 
208 #define DL_MCAN_INTERRUPT_TC (MCAN_IR_TC_MASK)
209 
213 #define DL_MCAN_INTERRUPT_HPM (MCAN_IR_HPM_MASK)
214 
218 #define DL_MCAN_INTERRUPT_RF1L (MCAN_IR_RF1L_MASK)
219 
223 #define DL_MCAN_INTERRUPT_RF1F (MCAN_IR_RF1F_MASK)
224 
228 #define DL_MCAN_INTERRUPT_RF1W (MCAN_IR_RF1W_MASK)
229 
233 #define DL_MCAN_INTERRUPT_RF1N (MCAN_IR_RF1N_MASK)
234 
238 #define DL_MCAN_INTERRUPT_RF0L (MCAN_IR_RF0L_MASK)
239 
243 #define DL_MCAN_INTERRUPT_RF0F (MCAN_IR_RF0F_MASK)
244 
248 #define DL_MCAN_INTERRUPT_RF0W (MCAN_IR_RF0W_MASK)
249 
253 #define DL_MCAN_INTERRUPT_RF0N (MCAN_IR_RF0N_MASK)
254 
263 #define DL_MCAN_MSP_INTERRUPT_WAKEUP (MCAN_IMASK_WAKEUP_SET)
264 
268 #define DL_MCAN_MSP_INTERRUPT_TIMESTAMP_OVERFLOW (MCAN_IMASK_EXT_TS_CNTR_OVFL_SET)
269 
273 #define DL_MCAN_MSP_INTERRUPT_DOUBLE_ERROR_DETECTION (MCAN_IMASK_DED_SET)
274 
278 #define DL_MCAN_MSP_INTERRUPT_SINGLE_ERROR_CORRECTION (MCAN_IMASK_SEC_SET)
279 
283 #define DL_MCAN_MSP_INTERRUPT_LINE1 (MCAN_IMASK_INTL1_SET)
284 
288 #define DL_MCAN_MSP_INTERRUPT_LINE0 (MCAN_IMASK_INTL0_SET)
289 
298 #define DL_MCAN_INTR_SRC_RX_FIFO0_NEW_MSG (MCAN_IR_RF0N_MASK)
299 
303 #define DL_MCAN_INTR_SRC_RX_FIFO0_WATERMARK (MCAN_IR_RF0W_MASK)
304 
308 #define DL_MCAN_INTR_SRC_RX_FIFO0_FULL (MCAN_IR_RF0F_MASK)
309 
313 #define DL_MCAN_INTR_SRC_RX_FIFO0_MSG_LOST (MCAN_IR_RF0L_MASK)
314 
318 #define DL_MCAN_INTR_SRC_RX_FIFO1_NEW_MSG (MCAN_IR_RF1N_MASK)
319 
323 #define DL_MCAN_INTR_SRC_RX_FIFO1_WATERMARK (MCAN_IR_RF1W_MASK)
324 
328 #define DL_MCAN_INTR_SRC_RX_FIFO1_FULL (MCAN_IR_RF1F_MASK)
329 
333 #define DL_MCAN_INTR_SRC_RX_FIFO1_MSG_LOST (MCAN_IR_RF1L_MASK)
334 
338 #define DL_MCAN_INTR_SRC_HIGH_PRIO_MSG (MCAN_IR_HPM_MASK)
339 
343 #define DL_MCAN_INTR_SRC_TRANS_COMPLETE (MCAN_IR_TC_MASK)
344 
348 #define DL_MCAN_INTR_SRC_TRANS_CANCEL_FINISH (MCAN_IR_TCF_MASK)
349 
353 #define DL_MCAN_INTR_SRC_TX_FIFO_EMPTY (MCAN_IR_TFE_MASK)
354 
358 #define DL_MCAN_INTR_SRC_TX_EVT_FIFO_NEW_ENTRY (MCAN_IR_TEFN_MASK)
359 
363 #define DL_MCAN_INTR_SRC_TX_EVT_FIFO_WATERMARK (MCAN_IR_TEFW_MASK)
364 
368 #define DL_MCAN_INTR_SRC_TX_EVT_FIFO_FULL (MCAN_IR_TEFF_MASK)
369 
373 #define DL_MCAN_INTR_SRC_TX_EVT_FIFO_ELEM_LOST (MCAN_IR_TEFL_MASK)
374 
378 #define DL_MCAN_INTR_SRC_TIMESTAMP_WRAPAROUND (MCAN_IR_TSW_MASK)
379 
383 #define DL_MCAN_INTR_SRC_MSG_RAM_ACCESS_FAILURE (MCAN_IR_MRAF_MASK)
384 
388 #define DL_MCAN_INTR_SRC_TIMEOUT (MCAN_IR_TOO_MASK)
389 
393 #define DL_MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG (MCAN_IR_DRX_MASK)
394 
398 #define DL_MCAN_INTR_SRC_BIT_ERR_UNCORRECTED (MCAN_IR_BEU_MASK)
399 
403 #define DL_MCAN_INTR_SRC_ERR_LOG_OVRFLW (MCAN_IR_ELO_MASK)
404 
408 #define DL_MCAN_INTR_SRC_ERR_PASSIVE (MCAN_IR_EP_MASK)
409 
413 #define DL_MCAN_INTR_SRC_WARNING_STATUS (MCAN_IR_EW_MASK)
414 
418 #define DL_MCAN_INTR_SRC_BUS_OFF_STATUS (MCAN_IR_BO_MASK)
419 
423 #define DL_MCAN_INTR_SRC_WATCHDOG (MCAN_IR_WDI_MASK)
424 
428 #define DL_MCAN_INTR_SRC_PROTOCOL_ERR_ARB (MCAN_IR_PEA_MASK)
429 
433 #define DL_MCAN_INTR_SRC_PROTOCOL_ERR_DATA (MCAN_IR_PED_MASK)
434 
438 #define DL_MCAN_INTR_SRC_RES_ADDR_ACCESS (MCAN_IR_ARA_MASK)
439 
442 /* User defined ranges */
446 #define DL_MCAN_DBTP_DSJW_MAX (0xFU)
447 
450 #define DL_MCAN_DBTP_DTSEG2_MAX (0xFU)
451 
454 #define DL_MCAN_DBTP_DTSEG1_MAX (0x1FU)
455 
458 #define DL_MCAN_DBTP_DBRP_MAX (0x1FU)
459 
462 #define DL_MCAN_NBTP_NSJW_MAX (0x7FU)
463 
466 #define DL_MCAN_NBTP_NTSEG2_MAX (0x7FU)
467 
470 #define DL_MCAN_NBTP_NTSEG1_MAX (0xFFU)
471 
474 #define DL_MCAN_NBTP_NBRP_MAX (0x1FFU)
475 
478 #define DL_MCAN_RWD_WDC_MAX (0xFFU)
479 
482 #define DL_MCAN_TDCR_TDCF_MAX (0x7FU)
483 
486 #define DL_MCAN_TDCR_TDCO_MAX (0x7FU)
487 
490 #define DL_MCAN_XIDAM_EIDM_MAX (0x1FFFFFFFU)
491 
494 #define DL_MCAN_TSCC_TCP_MAX (0xFU)
495 
498 #define DL_MCAN_TOCC_TOP_MAX (0xFFFFU)
499 
500 /* clang-format on */
501 
505 typedef enum {
507  DL_MCAN_INSTANCE_0 = SYSCTL_SYSSTATUS_MCAN0READY_MASK,
508 } DL_MCAN_INSTANCE;
509 
513 typedef enum {
515  DL_MCAN_FCLK_SYSPLLCLK1 = SYSCTL_GENCLKCFG_CANCLKSRC_SYSPLLOUT1,
517  DL_MCAN_FCLK_HFCLK = SYSCTL_GENCLKCFG_CANCLKSRC_HFCLK,
518 } DL_MCAN_FCLK;
519 
523 typedef enum {
525  DL_MCAN_FCLK_DIV_1 = MCAN_CLKDIV_RATIO_DIV_BY_1_,
527  DL_MCAN_FCLK_DIV_2 = MCAN_CLKDIV_RATIO_DIV_BY_2_,
529  DL_MCAN_FCLK_DIV_4 = MCAN_CLKDIV_RATIO_DIV_BY_4_,
530 } DL_MCAN_FCLK_DIV;
531 
535 typedef enum {
537  DL_MCAN_INTR_LINE_NUM_0 = 0U,
539  DL_MCAN_INTR_LINE_NUM_1 = 1U
540 
541 } DL_MCAN_INTR_LINE_NUM;
542 
546 typedef enum {
547 
549  DL_MCAN_ID_TYPE_11_BIT = 0U,
551  DL_MCAN_ID_TYPE_29_BIT = 1U
552 
553 } DL_MCAN_ID_TYPE;
554 
558 typedef enum {
560  DL_MCAN_OPERATION_MODE_NORMAL = 0U,
562  DL_MCAN_OPERATION_MODE_SW_INIT = 1U
563 
564 } DL_MCAN_OPERATION_MODE;
565 
569 typedef enum {
571  DL_MCAN_MEM_TYPE_BUF = 0U,
573  DL_MCAN_MEM_TYPE_FIFO = 1U
574 
575 } DL_MCAN_MEM_TYPE;
576 
580 typedef enum {
582  DL_MCAN_RX_FIFO_NUM_0 = 0U,
584  DL_MCAN_RX_FIFO_NUM_1 = 1U
585 } DL_MCAN_RX_FIFO_NUM;
586 
590 typedef enum {
592  DL_MCAN_PIN_TYPE_RX = 0U,
594  DL_MCAN_PIN_TYPE_TX = 1U
595 } DL_MCAN_PIN_TYPE;
596 
600 typedef enum {
602  DL_MCAN_ELEM_SIZE_8BYTES = 0U,
604  DL_MCAN_ELEM_SIZE_12BYTES = 1U,
606  DL_MCAN_ELEM_SIZE_16BYTES = 2U,
608  DL_MCAN_ELEM_SIZE_20BYTES = 3U,
610  DL_MCAN_ELEM_SIZE_24BYTES = 4U,
612  DL_MCAN_ELEM_SIZE_32BYTES = 5U,
614  DL_MCAN_ELEM_SIZE_48BYTES = 6U,
616  DL_MCAN_ELEM_SIZE_64BYTES = 7U
617 } DL_MCAN_ELEM_SIZE;
618 
622 typedef enum {
624  DL_MCAN_TIMEOUT_SELECT_CONT = 0U,
626  DL_MCAN_TIMEOUT_SELECT_TX_EVENT_FIFO = 1U,
628  DL_MCAN_TIMEOUT_SELECT_RX_FIFO0 = 2U,
630  DL_MCAN_TIMEOUT_SELECT_RX_FIFO1 = 3U
631 
632 } DL_MCAN_TIMEOUT_SELECT;
633 
637 typedef enum {
639  DL_MCAN_INTR_SRC_MCAN_EXT_TS = 0x0,
641  DL_MCAN_INTR_SRC_MCAN_LINE_0 = 0x1,
643  DL_MCAN_INTR_SRC_MCAN_LINE_1 = 0x2,
644 } DL_MCAN_INTR_SRC_MCAN;
645 
649 typedef enum {
651  DL_MCAN_ECC_ERR_TYPE_SEC = 0U,
653  DL_MCAN_ECC_ERR_TYPE_DED = 1U
654 
655 } DL_MCAN_ECC_ERR_TYPE;
656 
660 typedef enum {
665  DL_MCAN_LPBK_MODE_INTERNAL = 0U,
674  DL_MCAN_LPBK_MODE_EXTERNAL = 1U
675 
676 } DL_MCAN_LPBK_MODE;
677 
681 typedef enum {
683  DL_MCAN_COM_STATE_SYNCHRONIZING = 0U,
685  DL_MCAN_COM_STATE_IDLE = 1U,
687  DL_MCAN_COM_STATE_RECEIVER = 2U,
689  DL_MCAN_COM_STATE_TRANSMITTER = 3U
690 } DL_MCAN_COM_STATE;
691 
695 typedef enum {
699  DL_MCAN_ERR_CODE_NO_ERROR = 0U,
703  DL_MCAN_ERR_CODE_STUFF_ERROR = 1U,
705  DL_MCAN_ERR_CODE_FORM_ERROR = 2U,
709  DL_MCAN_ERR_CODE_ACK_ERROR = 3U,
715  DL_MCAN_ERR_CODE_BIT1_ERROR = 4U,
725  DL_MCAN_ERR_CODE_BIT0_ERROR = 5U,
730  DL_MCAN_ERR_CODE_CRC_ERROR = 6U,
735  DL_MCAN_ERR_CODE_NO_CHANGE = 7U
736 
737 } DL_MCAN_ERR_CODE;
738 
742 typedef struct {
745  DL_MCAN_FCLK clockSel;
747  DL_MCAN_FCLK_DIV divider;
748 } DL_MCAN_ClockConfig;
749 
755 typedef struct {
759  uint32_t nomRatePrescalar;
763  uint32_t nomTimeSeg1;
767  uint32_t nomTimeSeg2;
771  uint32_t nomSynchJumpWidth;
775  uint32_t dataRatePrescalar;
779  uint32_t dataTimeSeg1;
783  uint32_t dataTimeSeg2;
787  uint32_t dataSynchJumpWidth;
788 } DL_MCAN_BitTimingParams;
789 
793 typedef struct {
797  uint32_t tdcf;
801  uint32_t tdco;
802 } DL_MCAN_TDCConfig;
803 
807 typedef struct {
812  uint32_t rrfe;
817  uint32_t rrfs;
823  uint32_t anfe;
829  uint32_t anfs;
830 } DL_MCAN_GlobalFiltConfig;
831 
835 typedef struct {
840  uint32_t fdMode;
846  uint32_t brsEnable;
852  uint32_t txpEnable;
858  uint32_t efbi;
865  uint32_t pxhddisable;
871  uint32_t darEnable;
876  uint32_t wkupReqEnable;
881  uint32_t autoWkupEnable;
886  uint32_t emulationEnable;
890  uint32_t wdcPreload;
894  DL_MCAN_TDCConfig tdcConfig;
899  uint32_t tdcEnable;
900 } DL_MCAN_InitParams;
901 
905 typedef struct {
910  uint32_t monEnable;
916  uint32_t asmEnable;
920  uint32_t tsPrescalar;
927  uint32_t tsSelect;
931  uint32_t timeoutSelect;
937  uint32_t timeoutPreload;
942  uint32_t timeoutCntEnable;
946  DL_MCAN_GlobalFiltConfig filterConfig;
947 } DL_MCAN_ConfigParams;
948 
952 typedef struct {
954  uint32_t transErrLogCnt;
956  uint32_t recErrCnt;
961  uint32_t rpStatus;
963  uint32_t canErrLogCnt;
964 } DL_MCAN_ErrCntStatus;
965 
969 typedef struct {
973  uint32_t lastErrCode;
977  uint32_t act;
982  uint32_t errPassive;
988  uint32_t warningStatus;
993  uint32_t busOffStatus;
997  uint32_t dlec;
1002  uint32_t resi;
1007  uint32_t rbrs;
1013  uint32_t rfdf;
1018  uint32_t pxe;
1020  uint32_t tdcv;
1021 } DL_MCAN_ProtocolStatus;
1022 
1032 typedef struct {
1034  uint32_t flssa;
1040  uint32_t lss;
1042  uint32_t flesa;
1048  uint32_t lse;
1050  uint32_t txStartAddr;
1056  uint32_t txBufNum;
1062  uint32_t txFIFOSize;
1067  uint32_t txBufMode;
1069  uint32_t txBufElemSize;
1071  uint32_t txEventFIFOStartAddr;
1077  uint32_t txEventFIFOSize;
1083  uint32_t txEventFIFOWaterMark;
1085  uint32_t rxFIFO0startAddr;
1091  uint32_t rxFIFO0size;
1097  uint32_t rxFIFO0waterMark;
1102  uint32_t rxFIFO0OpMode;
1104  uint32_t rxFIFO1startAddr;
1110  uint32_t rxFIFO1size;
1116  uint32_t rxFIFO1waterMark;
1121  uint32_t rxFIFO1OpMode;
1123  uint32_t rxBufStartAddr;
1125  uint32_t rxBufElemSize;
1127  uint32_t rxFIFO0ElemSize;
1129  uint32_t rxFIFO1ElemSize;
1130 } DL_MCAN_MsgRAMConfigParams;
1131 
1135 typedef struct {
1139  uint32_t bufIdx;
1147  uint32_t msi;
1149  uint32_t filterIdx;
1154  uint32_t filterList;
1155 } DL_MCAN_HighPriorityMsgInfo;
1156 
1160 typedef struct {
1162  uint32_t statusLow;
1164  uint32_t statusHigh;
1165 } DL_MCAN_RxNewDataStatus;
1166 
1170 typedef struct {
1174  uint32_t num;
1176  uint32_t fillLvl;
1178  uint32_t getIdx;
1180  uint32_t putIdx;
1185  uint32_t fifoFull;
1187  uint32_t msgLost;
1188 } DL_MCAN_RxFIFOStatus;
1189 
1193 typedef struct {
1195  uint32_t freeLvl;
1199  uint32_t getIdx;
1201  uint32_t putIdx;
1206  uint32_t fifoFull;
1207 } DL_MCAN_TxFIFOStatus;
1208 
1212 typedef struct {
1214  uint32_t fillLvl;
1216  uint32_t getIdx;
1218  uint32_t putIdx;
1223  uint32_t fifoFull;
1229  uint32_t eleLost;
1230 } DL_MCAN_TxEventFIFOStatus;
1231 
1235 typedef struct {
1239  uint32_t errType;
1241  uint32_t rowNum;
1245  uint32_t bit1;
1247  uint32_t bit2;
1251  uint32_t errOnce;
1253  uint32_t errForce;
1254 } DL_MCAN_ECCErrForceParams;
1255 
1259 typedef struct {
1264  uint32_t secErr;
1269  uint32_t dedErr;
1273  uint32_t row;
1275  uint32_t bit1;
1276 
1277 } DL_MCAN_ECCErrStatus;
1278 
1283 typedef struct {
1285  uint32_t scheme;
1287  uint32_t modId;
1289  uint32_t major;
1291  uint32_t minor;
1293  uint32_t day;
1295  uint32_t mon;
1297  uint32_t year;
1299  uint32_t subStep;
1301  uint32_t step;
1303  uint32_t rel;
1304 } DL_MCAN_RevisionId;
1305 
1309 typedef struct {
1311  uint32_t scheme;
1313  uint32_t modId;
1315  uint32_t major;
1317  uint32_t minor;
1318 } DL_MCAN_ECCAggrRevisionId;
1319 
1323 typedef struct {
1328  uint32_t enable;
1333  uint32_t enableChk;
1338  uint32_t enableRdModWr;
1339 } DL_MCAN_ECCConfigParams;
1340 
1344 typedef struct {
1346  uint32_t scheme;
1348  uint32_t modId;
1350  uint32_t major;
1352  uint32_t minor;
1353 } DL_MCAN_ECCWrapRevisionId;
1354 
1358 typedef struct {
1360  uint32_t id;
1365  uint32_t rtr;
1370  uint32_t xtd;
1375  uint32_t esi;
1381  uint32_t dlc;
1386  uint32_t brs;
1391  uint32_t fdf;
1396  uint32_t efc;
1398  uint32_t mm;
1402  uint8_t data[DL_MCAN_MAX_PAYLOAD_BYTES];
1403 } DL_MCAN_TxBufElement;
1404 
1408 typedef struct {
1410  uint32_t id;
1415  uint32_t rtr;
1420  uint32_t xtd;
1425  uint32_t esi;
1427  uint32_t rxts;
1433  uint32_t dlc;
1438  uint32_t brs;
1443  uint32_t fdf;
1445  uint32_t fidx;
1450  uint32_t anmf;
1454  uint8_t data[DL_MCAN_MAX_PAYLOAD_BYTES];
1455 } DL_MCAN_RxBufElement;
1456 
1460 typedef struct {
1462  uint32_t id;
1467  uint32_t rtr;
1472  uint32_t xtd;
1477  uint32_t esi;
1479  uint32_t txts;
1485  uint32_t dlc;
1490  uint32_t brs;
1495  uint32_t fdf;
1503  uint32_t et;
1505  uint32_t mm;
1506 } DL_MCAN_TxEventFIFOElement;
1507 
1511 typedef struct {
1513  uint32_t sfid2;
1515  uint32_t sfid1;
1529  uint32_t sfec;
1536  uint32_t sft;
1537 } DL_MCAN_StdMsgIDFilterElement;
1538 
1542 typedef struct {
1544  uint32_t efid1;
1558  uint32_t efec;
1560  uint32_t efid2;
1568  uint32_t eft;
1569 } DL_MCAN_ExtMsgIDFilterElement;
1570 
1576 typedef struct {
1578  uint32_t clkDivConf;
1579 
1581  uint32_t clkConf;
1582 
1584  uint32_t clkEnConf;
1585 
1587  uint32_t ctrlConf;
1588 
1590  uint32_t nomBitTimeConf;
1591 
1593  uint32_t dataBitTimeConf;
1594 
1596  uint32_t timeCntConf;
1597 
1599  uint32_t timeCntVal;
1600 
1602  uint32_t timeOutConf;
1603 
1605  uint32_t timeOutCntVal;
1606 
1608  uint32_t txDelCompConf;
1609 
1611  uint32_t intEnConf;
1612 
1614  uint32_t intLnSelConf;
1615 
1617  uint32_t intLnEnableConf;
1618 
1620  uint32_t globFiltIDConf;
1621 
1623  uint32_t stdFiltIDConf;
1624 
1626  uint32_t exFiltIDConf;
1627 
1629  uint32_t exFiltIDMsk;
1630 
1632  uint32_t rxFIFO0Conf;
1633 
1635  uint32_t rxBuffConf;
1636 
1638  uint32_t rxFIFO1Conf;
1639 
1641  uint32_t rxDataSize;
1642 
1644  uint32_t txBuffConf;
1645 
1647  uint32_t txDataSize;
1648 
1650  uint32_t txBuffTxIntConf;
1651 
1653  uint32_t txBuffCancIntConf;
1654 
1656  uint32_t txEvntFIFOConf;
1657 
1659  uint32_t ssCtrlConf;
1660 
1662  uint32_t ssIntEnConf;
1663 
1665  uint32_t preSclConf;
1666 
1668  uint32_t edcVecConf;
1669 
1671  uint32_t edcConf2;
1672 
1674  uint32_t edcConf1;
1675 
1677  uint32_t edcConf0;
1678 
1680  uint32_t intEvnt0Conf;
1681 
1683  uint32_t ramWDConf;
1684 
1686  uint32_t testConf;
1687 
1690  bool backupRdy;
1691 } DL_MCAN_backupConfig;
1692 
1694 typedef enum {
1696  DL_MCAN_CLOCK_DIVIDE_1 = MCAN_CLKDIV_RATIO_DIV_BY_1_,
1698  DL_MCAN_CLOCK_DIVIDE_2 = MCAN_CLKDIV_RATIO_DIV_BY_2_,
1700  DL_MCAN_CLOCK_DIVIDE_4 = MCAN_CLKDIV_RATIO_DIV_BY_4_
1701 } DL_MCAN_CLOCK_DIVIDE;
1702 
1704 typedef enum {
1706  DL_MCAN_IIDX_WAKEUP = MCAN_IIDX_STAT_WAKEUP,
1709  DL_MCAN_IIDX_TIMESTAMP_OVERFLOW = MCAN_IIDX_STAT_EXT_TS_CNTR_OVFL,
1712  DL_MCAN_IIDX_DOUBLE_ERROR_DETECTION = MCAN_IIDX_STAT_DED,
1715  DL_MCAN_IIDX_SINGLE_ERROR_CORRECTION = MCAN_IIDX_STAT_SEC,
1717  DL_MCAN_IIDX_LINE1 = MCAN_IIDX_STAT_INTL1,
1719  DL_MCAN_IIDX_LINE0 = MCAN_IIDX_STAT_INTL0
1720 } DL_MCAN_IIDX;
1721 
1731 bool DL_MCAN_isReady(DL_MCAN_INSTANCE instance);
1732 
1740 void DL_MCAN_setClockConfig(
1741  MCAN_Regs *mcan, const DL_MCAN_ClockConfig *config);
1742 
1750 void DL_MCAN_getClockConfig(MCAN_Regs *mcan, DL_MCAN_ClockConfig *config);
1759 bool DL_MCAN_isInReset(const MCAN_Regs *mcan);
1760 
1770 bool DL_MCAN_isFDOpEnable(const MCAN_Regs *mcan);
1771 
1781 bool DL_MCAN_isMemInitDone(const MCAN_Regs *mcan);
1782 
1791 void DL_MCAN_setOpMode(MCAN_Regs *mcan, uint32_t mode);
1792 
1800 uint32_t DL_MCAN_getOpMode(const MCAN_Regs *mcan);
1801 
1811 int32_t DL_MCAN_init(MCAN_Regs *mcan, const DL_MCAN_InitParams *initParams);
1812 
1822 int32_t DL_MCAN_config(
1823  MCAN_Regs *mcan, const DL_MCAN_ConfigParams *configParams);
1824 
1834 void DL_MCAN_eccConfig(
1835  MCAN_Regs *mcan, const DL_MCAN_ECCConfigParams *configParams);
1836 
1846 int32_t DL_MCAN_setBitTime(
1847  MCAN_Regs *mcan, const DL_MCAN_BitTimingParams *configParams);
1848 
1859 int32_t DL_MCAN_msgRAMConfig(
1860  MCAN_Regs *mcan, const DL_MCAN_MsgRAMConfigParams *msgRAMConfigParams);
1861 
1871 int32_t DL_MCAN_setExtIDAndMask(MCAN_Regs *mcan, uint32_t idMask);
1872 
1886 void DL_MCAN_writeMsgRam(MCAN_Regs *mcan, uint32_t memType, uint32_t bufNum,
1887  const DL_MCAN_TxBufElement *elem);
1888 
1897 int32_t DL_MCAN_TXBufAddReq(MCAN_Regs *mcan, uint32_t bufNum);
1898 
1908 void DL_MCAN_getNewDataStatus(
1909  const MCAN_Regs *mcan, DL_MCAN_RxNewDataStatus *newDataStatus);
1910 
1920 void DL_MCAN_clearNewDataStatus(
1921  MCAN_Regs *mcan, const DL_MCAN_RxNewDataStatus *newDataStatus);
1922 
1939 void DL_MCAN_readMsgRam(const MCAN_Regs *mcan, uint32_t memType,
1940  uint32_t bufNum, uint32_t fifoNum, DL_MCAN_RxBufElement *elem);
1941 
1951 void DL_MCAN_readTxEventFIFO(
1952  const MCAN_Regs *mcan, DL_MCAN_TxEventFIFOElement *txEventElem);
1953 
1968 void DL_MCAN_addStdMsgIDFilter(MCAN_Regs *mcan, uint32_t filtNum,
1969  const DL_MCAN_StdMsgIDFilterElement *elem);
1970 
1985 void DL_MCAN_addExtMsgIDFilter(MCAN_Regs *mcan, uint32_t filtNum,
1986  const DL_MCAN_ExtMsgIDFilterElement *elem);
1987 
2002 void DL_MCAN_lpbkModeEnable(MCAN_Regs *mcan, uint32_t lpbkMode, bool enable);
2003 
2012 void DL_MCAN_getErrCounters(
2013  const MCAN_Regs *mcan, DL_MCAN_ErrCntStatus *errCounter);
2014 
2023 void DL_MCAN_getProtocolStatus(
2024  const MCAN_Regs *mcan, DL_MCAN_ProtocolStatus *protStatus);
2025 
2036 void DL_MCAN_enableIntr(MCAN_Regs *mcan, uint32_t intrMask, bool enable);
2037 
2049 void DL_MCAN_selectIntrLine(
2050  MCAN_Regs *mcan, uint32_t intrMask, uint32_t lineNum);
2051 
2059 uint32_t DL_MCAN_getIntrLineSelectStatus(const MCAN_Regs *mcan);
2060 
2072 void DL_MCAN_enableIntrLine(MCAN_Regs *mcan, uint32_t lineNum, bool enable);
2073 
2081 uint32_t DL_MCAN_getIntrStatus(const MCAN_Regs *mcan);
2082 
2092 void DL_MCAN_clearIntrStatus(
2093  MCAN_Regs *mcan, uint32_t intrMask, DL_MCAN_INTR_SRC_MCAN eoi);
2094 
2104 void DL_MCAN_getHighPriorityMsgStatus(
2105  const MCAN_Regs *mcan, DL_MCAN_HighPriorityMsgInfo *hpm);
2106 
2115 void DL_MCAN_getRxFIFOStatus(
2116  const MCAN_Regs *mcan, DL_MCAN_RxFIFOStatus *fifoStatus);
2117 
2127 int32_t DL_MCAN_writeRxFIFOAck(
2128  MCAN_Regs *mcan, uint32_t fifoNum, uint32_t idx);
2129 
2138 void DL_MCAN_getTxFIFOQueStatus(
2139  const MCAN_Regs *mcan, DL_MCAN_TxFIFOStatus *fifoStatus);
2140 
2148 uint32_t DL_MCAN_getTxBufReqPend(const MCAN_Regs *mcan);
2149 
2158 int32_t DL_MCAN_txBufCancellationReq(MCAN_Regs *mcan, uint32_t buffNum);
2159 
2167 uint32_t DL_MCAN_getTxBufTransmissionStatus(const MCAN_Regs *mcan);
2168 
2176 uint32_t DL_MCAN_txBufCancellationStatus(const MCAN_Regs *mcan);
2177 
2188 int32_t DL_MCAN_TXBufTransIntrEnable(
2189  MCAN_Regs *mcan, uint32_t bufNum, bool enable);
2190 
2202 int32_t DL_MCAN_getTxBufCancellationIntrEnable(
2203  const MCAN_Regs *mcan, uint32_t bufNum, bool enable);
2204 
2216 void DL_MCAN_addClockStopRequest(MCAN_Regs *mcan, bool enable);
2217 
2227 void DL_MCAN_getTxEventFIFOStatus(
2228  const MCAN_Regs *mcan, DL_MCAN_TxEventFIFOStatus *fifoStatus);
2229 
2238 int32_t DL_MCAN_writeTxEventFIFOAck(MCAN_Regs *mcan, uint32_t idx);
2239 
2249 void DL_MCAN_eccForceError(
2250  MCAN_Regs *mcan, const DL_MCAN_ECCErrForceParams *eccErr);
2251 
2260 void DL_MCAN_eccGetErrorStatus(MCAN_Regs *mcan, DL_MCAN_ECCErrStatus *eccErr);
2261 
2271 void DL_MCAN_eccClearErrorStatus(MCAN_Regs *mcan, uint32_t errType);
2272 
2281 void DL_MCAN_eccWriteEOI(MCAN_Regs *mcan, uint32_t errType);
2282 
2293 void DL_MCAN_eccEnableIntr(MCAN_Regs *mcan, uint32_t errType, bool enable);
2294 
2304 uint32_t DL_MCAN_eccGetIntrStatus(const MCAN_Regs *mcan, uint32_t errType);
2305 
2315 void DL_MCAN_eccClearIntrStatus(MCAN_Regs *mcan, uint32_t errType);
2316 
2327 void DL_MCAN_extTSCounterConfig(MCAN_Regs *mcan, uint32_t prescalar);
2328 
2339 void DL_MCAN_extTSCounterEnable(MCAN_Regs *mcan, bool enable);
2340 
2353 void DL_MCAN_extTSEnableIntr(MCAN_Regs *mcan, bool enable);
2354 
2363 void DL_MCAN_extTSWriteEOI(MCAN_Regs *mcan);
2364 
2375 uint32_t DL_MCAN_extTSGetUnservicedIntrCount(const MCAN_Regs *mcan);
2376 
2377 /* ========================================================================== */
2378 /* Advance Functions */
2379 /* ========================================================================== */
2380 
2390 void DL_MCAN_getRevisionId(const MCAN_Regs *mcan, DL_MCAN_RevisionId *revId);
2391 
2402 uint32_t DL_MCAN_getClockStopAck(const MCAN_Regs *mcan);
2403 
2412 void DL_MCAN_extTSSetRawStatus(MCAN_Regs *mcan);
2413 
2422 void DL_MCAN_extTSClearRawStatus(MCAN_Regs *mcan);
2423 
2433 uint32_t DL_MCAN_getRxPinState(const MCAN_Regs *mcan);
2434 
2448 void DL_MCAN_setTxPinState(MCAN_Regs *mcan, uint32_t state);
2449 
2461 uint32_t DL_MCAN_getTxPinState(const MCAN_Regs *mcan);
2462 
2470 uint32_t DL_MCAN_getTSCounterVal(const MCAN_Regs *mcan);
2471 
2482 uint32_t DL_MCAN_getClkStopAck(const MCAN_Regs *mcan);
2483 
2493 void DL_MCAN_getBitTime(
2494  const MCAN_Regs *mcan, DL_MCAN_BitTimingParams *configParams);
2495 
2503 void DL_MCAN_resetTSCounter(MCAN_Regs *mcan);
2504 
2512 uint32_t DL_MCAN_getTOCounterVal(const MCAN_Regs *mcan);
2513 
2523 void DL_MCAN_eccAggrGetRevisionId(
2524  const MCAN_Regs *mcan, DL_MCAN_ECCAggrRevisionId *revId);
2525 
2535 void DL_MCAN_eccWrapGetRevisionId(
2536  MCAN_Regs *mcan, DL_MCAN_ECCWrapRevisionId *revId);
2537 
2548 bool DL_MCAN_extTSIsIntrEnable(const MCAN_Regs *mcan);
2549 
2557 uint32_t DL_MCAN_getEndianVal(const MCAN_Regs *mcan);
2558 
2566 uint32_t DL_MCAN_getExtIDANDMask(const MCAN_Regs *mcan);
2567 
2577 __STATIC_INLINE void DL_MCAN_enablePower(MCAN_Regs *mcan)
2578 {
2579  mcan->MCANSS.PWREN = (MCAN_PWREN_KEY_UNLOCK_W | MCAN_PWREN_ENABLE_ENABLE);
2580 }
2581 
2592 __STATIC_INLINE void DL_MCAN_disablePower(MCAN_Regs *mcan)
2593 {
2594  mcan->MCANSS.PWREN = (MCAN_PWREN_KEY_UNLOCK_W | MCAN_PWREN_ENABLE_DISABLE);
2595 }
2596 
2613 __STATIC_INLINE bool DL_MCAN_isPowerEnabled(const MCAN_Regs *mcan)
2614 {
2615  return ((mcan->MCANSS.PWREN & MCAN_PWREN_ENABLE_MASK) ==
2616  MCAN_PWREN_ENABLE_ENABLE);
2617 }
2618 
2624 __STATIC_INLINE void DL_MCAN_reset(MCAN_Regs *mcan)
2625 {
2626  mcan->MCANSS.RSTCTL =
2627  (MCAN_RSTCTL_KEY_UNLOCK_W | MCAN_RSTCTL_RESETSTKYCLR_CLR |
2628  MCAN_RSTCTL_RESETASSERT_ASSERT);
2629 }
2630 
2640 __STATIC_INLINE bool DL_MCAN_isReset(const MCAN_Regs *mcan)
2641 {
2642  return ((mcan->MCANSS.STAT & MCAN_STAT_RESETSTKY_MASK) ==
2643  MCAN_STAT_RESETSTKY_RESET);
2644 }
2645 
2654 __STATIC_INLINE void DL_MCAN_enableInterrupt(
2655  MCAN_Regs *mcan, uint32_t interruptMask)
2656 {
2657  mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.IMASK |= interruptMask;
2658 }
2659 
2668 __STATIC_INLINE void DL_MCAN_disableInterrupt(
2669  MCAN_Regs *mcan, uint32_t interruptMask)
2670 {
2671  mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.IMASK &= ~(interruptMask);
2672 }
2673 
2686 __STATIC_INLINE uint32_t DL_MCAN_getEnabledInterrupts(
2687  const MCAN_Regs *mcan, uint32_t interruptMask)
2688 {
2689  return (mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.IMASK & interruptMask);
2690 }
2691 
2707 __STATIC_INLINE uint32_t DL_MCAN_getEnabledInterruptStatus(
2708  const MCAN_Regs *mcan, uint32_t interruptMask)
2709 {
2710  return (mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.MIS & interruptMask);
2711 }
2712 
2728 __STATIC_INLINE uint32_t DL_MCAN_getRawInterruptStatus(
2729  const MCAN_Regs *mcan, uint32_t interruptMask)
2730 {
2731  return (mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.RIS & interruptMask);
2732 }
2733 
2746 __STATIC_INLINE DL_MCAN_IIDX DL_MCAN_getPendingInterrupt(const MCAN_Regs *mcan)
2747 {
2748  // TODO: Need to figure out return values for this.
2749  return ((DL_MCAN_IIDX) mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.IIDX);
2750 }
2751 
2760 __STATIC_INLINE void DL_MCAN_clearInterruptStatus(
2761  MCAN_Regs *mcan, uint32_t interruptMask)
2762 {
2763  mcan->MCANSS.TI_WRAPPER.MSP.CPU_INT.ICLR = interruptMask;
2764 }
2765 
2774 __STATIC_INLINE bool DL_MCAN_isModuleClockEnabled(const MCAN_Regs *mcan)
2775 {
2776  return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKEN &
2777  MCAN_CLKEN_CLK_REQEN_MASK) == MCAN_CLKEN_CLK_REQEN_SET);
2778 }
2779 
2786 __STATIC_INLINE void DL_MCAN_enableModuleClock(MCAN_Regs *mcan)
2787 {
2788  mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKEN = MCAN_CLKEN_CLK_REQEN_SET;
2789 }
2790 
2797 __STATIC_INLINE void DL_MCAN_disableModuleClock(MCAN_Regs *mcan)
2798 {
2799  mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKEN = MCAN_CLKEN_CLK_REQEN_CLR;
2800 }
2801 
2810 __STATIC_INLINE uint32_t DL_MCAN_getModuleClockDivider(const MCAN_Regs *mcan)
2811 {
2812  return (
2813  mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKDIV & MCAN_CLKDIV_RATIO_MASK);
2814 }
2815 
2825 __STATIC_INLINE void DL_MCAN_setModuleClockDivider(
2826  MCAN_Regs *mcan, uint32_t clkdiv)
2827 {
2828  DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKDIV, clkdiv,
2829  MCAN_CLKDIV_RATIO_MASK);
2830 }
2831 
2840 __STATIC_INLINE bool DL_MCAN_isClockStopGateRequestEnabled(
2841  const MCAN_Regs *mcan)
2842 {
2843  return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL &
2844  MCAN_CLKCTL_STOPREQ_MASK) == MCAN_CLKCTL_STOPREQ_ENABLE);
2845 }
2846 
2853 __STATIC_INLINE void DL_MCAN_enableClockStopGateRequest(MCAN_Regs *mcan)
2854 {
2855  DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
2856  MCAN_CLKCTL_STOPREQ_ENABLE, MCAN_CLKCTL_STOPREQ_MASK);
2857 }
2858 
2865 __STATIC_INLINE void DL_MCAN_disableClockStopGateRequest(MCAN_Regs *mcan)
2866 {
2867  DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
2868  MCAN_CLKCTL_STOPREQ_DISABLE, MCAN_CLKCTL_STOPREQ_MASK);
2869 }
2870 
2880 __STATIC_INLINE bool DL_MCAN_isClockStopWakeupInterruptEnabled(
2881  const MCAN_Regs *mcan)
2882 {
2883  return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL &
2884  MCAN_CLKCTL_WAKEUP_INT_EN_MASK) ==
2885  MCAN_CLKCTL_WAKEUP_INT_EN_ENABLE);
2886 }
2887 
2894 __STATIC_INLINE void DL_MCAN_enableClockStopWakeupInterrupt(MCAN_Regs *mcan)
2895 {
2896  DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
2897  MCAN_CLKCTL_WAKEUP_INT_EN_ENABLE, MCAN_CLKCTL_WAKEUP_INT_EN_MASK);
2898 }
2899 
2906 __STATIC_INLINE void DL_MCAN_disableClockStopWakeupInterrupt(MCAN_Regs *mcan)
2907 {
2908  DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
2909  MCAN_CLKCTL_WAKEUP_INT_EN_DISABLE, MCAN_CLKCTL_WAKEUP_INT_EN_MASK);
2910 }
2911 
2923 __STATIC_INLINE bool DL_MCAN_isGlitchFilterWakeupEnabled(const MCAN_Regs *mcan)
2924 {
2925  return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL &
2926  MCAN_CLKCTL_WKUP_GLTFLT_EN_MASK) ==
2927  MCAN_CLKCTL_WKUP_GLTFLT_EN_ENABLE);
2928 }
2929 
2939 __STATIC_INLINE void DL_MCAN_enableGlitchFilterWakeup(MCAN_Regs *mcan)
2940 {
2941  DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
2942  MCAN_CLKCTL_WKUP_GLTFLT_EN_ENABLE, MCAN_CLKCTL_WKUP_GLTFLT_EN_MASK);
2943 }
2944 
2954 __STATIC_INLINE void DL_MCAN_disableGlitchFilterWakeup(MCAN_Regs *mcan)
2955 {
2956  DL_Common_updateReg(&mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKCTL,
2957  MCAN_CLKCTL_WKUP_GLTFLT_EN_DISABLE, MCAN_CLKCTL_WKUP_GLTFLT_EN_MASK);
2958 }
2959 
2968 __STATIC_INLINE bool DL_MCAN_getClockStopAcknowledgeStatus(
2969  const MCAN_Regs *mcan)
2970 {
2971  return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKSTS &
2972  MCAN_CLKSTS_CLKSTOP_ACKSTS_MASK) ==
2973  MCAN_CLKSTS_CLKSTOP_ACKSTS_SET);
2974 }
2975 
2987 __STATIC_INLINE bool DL_MCAN_getClockStopHardwareOverrideStatus(
2988  const MCAN_Regs *mcan)
2989 {
2990  return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKSTS &
2991  MCAN_CLKSTS_STOPREQ_HW_OVR_MASK) ==
2992  MCAN_CLKSTS_STOPREQ_HW_OVR_SET);
2993 }
2994 
3003 __STATIC_INLINE bool DL_MCAN_getControllerClockRequestStatus(
3004  const MCAN_Regs *mcan)
3005 {
3006  return ((mcan->MCANSS.TI_WRAPPER.MSP.MCANSS_CLKSTS &
3007  MCAN_CLKSTS_CCLKDONE_MASK) == MCAN_CLKSTS_CCLKDONE_SET);
3008 }
3009 
3022 bool DL_MCAN_saveConfiguration(
3023  const MCAN_Regs *mcan, DL_MCAN_backupConfig *ptr);
3024 
3037 bool DL_MCAN_restoreConfiguration(MCAN_Regs *mcan, DL_MCAN_backupConfig *ptr);
3038 
3039 #ifdef __cplusplus
3040 }
3041 #endif
3042 
3043 #endif /* __MSPM0_HAS_MCAN__ */
3044 
3045 #endif /* ti_dl_dl_mcan__include */
3046 
DL_Common_updateReg
__STATIC_INLINE void DL_Common_updateReg(volatile uint32_t *reg, uint32_t val, uint32_t mask)
Writes value to specified register - retaining bits unaffected by mask.
Definition: dl_common.h:63
dl_common.h
DriverLib Common APIs.
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