dl_dac12.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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 */
/*!****************************************************************************
 *  @file dl_dac12.h
 *  @brief 12-bit DAC Driver Library
 *  @defgroup   DAC12 Digital to Analog Converter (DAC12)
 *
 *  @anchor ti_dl_dl_dac12_Overview
 *  # Overview
 *
 *  The Digital to Analog Converter Driver Library allows full configuration of
 *  the MSPM0 DAC12 module. The DAC module is a 12-bit voltage-output
 *  digital-to-analog converter (DAC).
 *
 *  <hr>
 ******************************************************************************
 */
#ifndef ti_dl_dl_dac12__include
#define ti_dl_dl_dac12__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#ifdef __MSPM0_HAS_DAC12__

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

typedef enum {
    DL_DAC12_OUTPUT_DISABLED = DAC12_CTL1_OPS_NOC0,
    DL_DAC12_OUTPUT_ENABLED = DAC12_CTL1_OPS_OUT0,
} DL_DAC12_OUTPUT;

typedef enum {
    DL_DAC12_REPRESENTATION_BINARY = DAC12_CTL0_DFM_BINARY,
    DL_DAC12_REPRESENTATION_TWOS_COMPLEMENT = DAC12_CTL0_DFM_TWOS_COMP,
} DL_DAC12_REPRESENTATION;

typedef enum {
    DL_DAC12_RESOLUTION_12BIT = DAC12_CTL0_RES__12BITS,
    DL_DAC12_RESOLUTION_8BIT = DAC12_CTL0_RES__8BITS,
} DL_DAC12_RESOLUTION;

typedef enum {
    DL_DAC12_AMP_OFF_TRISTATE = DAC12_CTL1_AMPHIZ_HIZ,
    DL_DAC12_AMP_OFF_0V = DAC12_CTL1_AMPHIZ_PULLDOWN,
    DL_DAC12_AMP_ON = DAC12_CTL1_AMPEN_ENABLE,
} DL_DAC12_AMP;

typedef enum {
    DL_DAC12_VREF_SOURCE_VDDA_VEREFN = (DAC12_CTL1_REFSP_VDDA |
                                        DAC12_CTL1_REFSN_VEREFN) ,
    DL_DAC12_VREF_SOURCE_VEREFP_VEREFN = (DAC12_CTL1_REFSP_VEREFP |
                                          DAC12_CTL1_REFSN_VEREFN),
    DL_DAC12_VREF_SOURCE_VDDA_VSSA = (DAC12_CTL1_REFSP_VDDA |
                                      DAC12_CTL1_REFSN_VSSA),
    DL_DAC12_VREF_SOURCE_VEREFP_VSSA = (DAC12_CTL1_REFSP_VEREFP |
                                        DAC12_CTL1_REFSN_VSSA),
} DL_DAC12_VREF_SOURCE;

typedef enum {
    DL_DAC12_SAMPLETIMER_DISABLE = DAC12_CTL3_STIMEN_CLR,
    DL_DAC12_SAMPLETIMER_ENABLE = DAC12_CTL3_STIMEN_SET,
} DL_DAC12_SAMPLETIMER;


typedef enum {
    DL_DAC12_SAMPLES_PER_SECOND_500 = DAC12_CTL3_STIMCONFIG__500SPS,
    DL_DAC12_SAMPLES_PER_SECOND_1K = DAC12_CTL3_STIMCONFIG__1KSPS,
    DL_DAC12_SAMPLES_PER_SECOND_2K = DAC12_CTL3_STIMCONFIG__2KSPS,
    DL_DAC12_SAMPLES_PER_SECOND_4K = DAC12_CTL3_STIMCONFIG__4KSPS,
    DL_DAC12_SAMPLES_PER_SECOND_8K = DAC12_CTL3_STIMCONFIG__8KSPS,
    DL_DAC12_SAMPLES_PER_SECOND_16K = DAC12_CTL3_STIMCONFIG__16KSPS,
    DL_DAC12_SAMPLES_PER_SECOND_100K = DAC12_CTL3_STIMCONFIG__100KSPS,
    DL_DAC12_SAMPLES_PER_SECOND_200K = DAC12_CTL3_STIMCONFIG__200KSPS,
    DL_DAC12_SAMPLES_PER_SECOND_500K = DAC12_CTL3_STIMCONFIG__500KSPS,
    DL_DAC12_SAMPLES_PER_SECOND_1M = DAC12_CTL3_STIMCONFIG__1MSPS,
} DL_DAC12_SAMPLES_PER_SECOND;

typedef enum {
    DL_DAC12_FIFO_DISABLED = DAC12_CTL2_FIFOEN_CLR,
    DL_DAC12_FIFO_ENABLED = DAC12_CTL2_FIFOEN_SET,
} DL_DAC12_FIFO;


typedef enum {
    DL_DAC12_FIFO_THRESHOLD_ONE_QTR_EMPTY = DAC12_CTL2_FIFOTH_LOW,
    DL_DAC12_FIFO_THRESHOLD_TWO_QTRS_EMPTY = DAC12_CTL2_FIFOTH_MED,
    DL_DAC12_FIFO_THRESHOLD_THREE_QTRS_EMPTY = DAC12_CTL2_FIFOTH_HIGH,
} DL_DAC12_FIFO_THRESHOLD;

typedef enum {
    DL_DAC12_FIFO_TRIGGER_SAMPLETIMER = DAC12_CTL2_FIFOTRIGSEL_STIM,
    DL_DAC12_FIFO_TRIGGER_HWTRIG0 = DAC12_CTL2_FIFOTRIGSEL_TRIG0,
} DL_DAC12_FIFO_TRIGGER;

typedef enum {
    DL_DAC12_DMA_TRIGGER_DISABLED = DAC12_CTL2_DMATRIGEN_CLR,
    DL_DAC12_DMA_TRIGGER_ENABLED = DAC12_CTL2_DMATRIGEN_SET,
} DL_DAC12_DMA_TRIGGER;

typedef enum {

    DL_DAC12_CALIBRATION_FACTORY = DAC12_CALCTL_CALSEL_FACTORYTRIM,
    DL_DAC12_CALIBRATION_SELF = DAC12_CALCTL_CALSEL_SELFCALIBRATIONTRIM,

} DL_DAC12_CALIBRATION;

#define DL_DAC12_INTERRUPT_MODULE_READY             (DAC12_GEN_EVENT_IMASK_MODRDYIFG_SET)

#define DL_DAC12_INTERRUPT_FIFO_EMPTY            (DAC12_GEN_EVENT_IMASK_FIFOEMPTYIFG_SET)

#define DL_DAC12_INTERRUPT_FIFO_THREE_QTRS_EMPTY   (DAC12_GEN_EVENT_IMASK_FIFO3B4IFG_SET)

#define DL_DAC12_INTERRUPT_FIFO_TWO_QTRS_EMPTY     (DAC12_GEN_EVENT_IMASK_FIFO1B2IFG_SET)

#define DL_DAC12_INTERRUPT_FIFO_ONE_QTR_EMPTY      (DAC12_GEN_EVENT_IMASK_FIFO1B4IFG_SET)

#define DL_DAC12_INTERRUPT_FIFO_FULL              (DAC12_GEN_EVENT_IMASK_FIFOFULLIFG_SET)

#define DL_DAC12_INTERRUPT_FIFO_UNDERRUN          (DAC12_GEN_EVENT_IMASK_FIFOURUNIFG_SET)

#define DL_DAC12_INTERRUPT_DMA_DONE                (DAC12_GEN_EVENT_IMASK_DMADONEIFG_SET)

#define DL_DAC12_EVENT_MODULE_READY             (DAC12_GEN_EVENT_IMASK_MODRDYIFG_SET)

#define DL_DAC12_EVENT_FIFO_EMPTY            (DAC12_GEN_EVENT_IMASK_FIFOEMPTYIFG_SET)

#define DL_DAC12_EVENT_FIFO_THREE_QTRS_EMPTY   (DAC12_GEN_EVENT_IMASK_FIFO3B4IFG_SET)

#define DL_DAC12_EVENT_FIFO_TWO_QTRS_EMPTY     (DAC12_GEN_EVENT_IMASK_FIFO1B2IFG_SET)

#define DL_DAC12_EVENT_FIFO_ONE_QTR_EMPTY      (DAC12_GEN_EVENT_IMASK_FIFO1B4IFG_SET)

#define DL_DAC12_EVENT_FIFO_FULL              (DAC12_GEN_EVENT_IMASK_FIFOFULLIFG_SET)

#define DL_DAC12_EVENT_FIFO_UNDERRUN          (DAC12_GEN_EVENT_IMASK_FIFOURUNIFG_SET)

#define DL_DAC12_EVENT_DMA_DONE                (DAC12_GEN_EVENT_IMASK_DMADONEIFG_SET)

/* clang-format on */

typedef enum {
    DL_DAC12_IIDX_NO_INT = DAC12_CPU_INT_IIDX_STAT_NO_INTR,
    DL_DAC12_IIDX_MODULE_READY = DAC12_CPU_INT_IIDX_STAT_MODRDYIFG,
    DL_DAC12_IIDX_FIFO_FULL = DAC12_CPU_INT_IIDX_STAT_FIFOFULLIFG,
    DL_DAC12_IIDX_FIFO_1_4_EMPTY = DAC12_CPU_INT_IIDX_STAT_FIFO1B4IFG,
    DL_DAC12_IIDX_FIFO_1_2_EMPTY = DAC12_CPU_INT_IIDX_STAT_FIFO1B2IFG,
    DL_DAC12_IIDX_FIFO_3_4_EMPTY = DAC12_CPU_INT_IIDX_STAT_FIFO3B4IFG,
    DL_DAC12_IIDX_FIFO_EMPTY = DAC12_CPU_INT_IIDX_STAT_FIFOEMPTYIFG,
    DL_DAC12_IIDX_FIFO_UNDERRUN = DAC12_CPU_INT_IIDX_STAT_FIFOURUNIFG,
    DL_DAC12_IIDX_DMA_DONE = DAC12_CPU_INT_IIDX_STAT_DMADONEIFG
} DL_DAC12_IIDX;

typedef enum {
    DL_DAC12_SUBSCRIBER_INDEX_0 = 0,
} DL_DAC12_SUBSCRIBER_INDEX;

typedef enum {
    DL_DAC12_EVENT_ROUTE_1 = 0,
} DL_DAC12_EVENT_ROUTE;

typedef struct {
    DL_DAC12_OUTPUT outputEnable;

    DL_DAC12_RESOLUTION resolution;

    DL_DAC12_REPRESENTATION representation;

    DL_DAC12_VREF_SOURCE voltageReferenceSource;

    DL_DAC12_AMP amplifierSetting;

    DL_DAC12_FIFO fifoEnable;

    DL_DAC12_FIFO_TRIGGER fifoTriggerSource;

    DL_DAC12_DMA_TRIGGER dmaTriggerEnable;

    DL_DAC12_FIFO_THRESHOLD dmaTriggerThreshold;

    DL_DAC12_SAMPLETIMER sampleTimeGeneratorEnable;

    DL_DAC12_SAMPLES_PER_SECOND sampleRate;
} DL_DAC12_Config;

void DL_DAC12_init(DAC12_Regs *dac12, const DL_DAC12_Config *config);

__STATIC_INLINE void DL_DAC12_enablePower(DAC12_Regs *dac12)
{
    dac12->GPRCM.PWREN =
        (DAC12_PWREN_KEY_UNLOCK_W | DAC12_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_DAC12_disablePower(DAC12_Regs *dac12)
{
    dac12->GPRCM.PWREN =
        (DAC12_PWREN_KEY_UNLOCK_W | DAC12_PWREN_ENABLE_DISABLE);
}

__STATIC_INLINE bool DL_DAC12_isPowerEnabled(const DAC12_Regs *dac12)
{
    return ((dac12->GPRCM.PWREN & DAC12_PWREN_ENABLE_MASK) ==
            DAC12_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_DAC12_reset(DAC12_Regs *dac12)
{
    dac12->GPRCM.RSTCTL =
        (DAC12_RSTCTL_KEY_UNLOCK_W | DAC12_RSTCTL_RESETSTKYCLR_CLR |
            DAC12_RSTCTL_RESETASSERT_ASSERT);
}

__STATIC_INLINE bool DL_DAC12_isReset(const DAC12_Regs *dac12)
{
    return ((dac12->GPRCM.STAT & DAC12_STAT_RESETSTKY_MASK) ==
            DAC12_STAT_RESETSTKY_RESET);
}

__STATIC_INLINE void DL_DAC12_enable(DAC12_Regs *dac12)
{
    dac12->CTL0 |= DAC12_CTL0_ENABLE_SET;
}

__STATIC_INLINE void DL_DAC12_disable(DAC12_Regs *dac12)
{
    dac12->CTL0 &= ~DAC12_CTL0_ENABLE_MASK;
}

__STATIC_INLINE bool DL_DAC12_isEnabled(const DAC12_Regs *dac12)
{
    uint32_t t = (dac12->CTL0 & DAC12_CTL0_ENABLE_MASK);
    return (t == DAC12_CTL0_ENABLE_SET);
}

__STATIC_INLINE void DL_DAC12_configDataFormat(
    DAC12_Regs *dac12, DL_DAC12_REPRESENTATION rep, DL_DAC12_RESOLUTION res)
{
    DL_Common_updateReg(&dac12->CTL0, ((uint32_t) rep | (uint32_t) res),
        DAC12_CTL0_RES_MASK | DAC12_CTL0_DFM_MASK);
}

__STATIC_INLINE DL_DAC12_AMP DL_DAC12_getAmplifier(const DAC12_Regs *dac12)
{
    uint32_t ampVal =
        (dac12->CTL1 & (DAC12_CTL1_AMPEN_MASK | DAC12_CTL1_AMPHIZ_MASK));

    return (DL_DAC12_AMP)(ampVal);
}

__STATIC_INLINE void DL_DAC12_setAmplifier(
    DAC12_Regs *dac12, DL_DAC12_AMP ampVal)
{
    DL_Common_updateReg(&dac12->CTL1, (uint32_t) ampVal,
        (DAC12_CTL1_AMPEN_MASK | DAC12_CTL1_AMPHIZ_MASK));
}

__STATIC_INLINE DL_DAC12_VREF_SOURCE DL_DAC12_getReferenceVoltageSource(
    const DAC12_Regs *dac12)
{
    uint32_t refsVal =
        (dac12->CTL1 & (DAC12_CTL1_REFSP_MASK | DAC12_CTL1_REFSN_MASK));

    return (DL_DAC12_VREF_SOURCE)(refsVal);
}

__STATIC_INLINE void DL_DAC12_setReferenceVoltageSource(
    DAC12_Regs *dac12, DL_DAC12_VREF_SOURCE refsVal)
{
    DL_Common_updateReg(&dac12->CTL1, (uint32_t) refsVal,
        (DAC12_CTL1_REFSP_MASK | DAC12_CTL1_REFSN_MASK));
}

__STATIC_INLINE void DL_DAC12_enableOutputPin(DAC12_Regs *dac12)
{
    dac12->CTL1 |= DAC12_CTL1_OPS_OUT0;
}

__STATIC_INLINE void DL_DAC12_disableOutputPin(DAC12_Regs *dac12)
{
    dac12->CTL1 &= ~DAC12_CTL1_OPS_MASK;
}

__STATIC_INLINE bool DL_DAC12_isOutputPinEnabled(const DAC12_Regs *dac12)
{
    return ((dac12->CTL1 & DAC12_CTL1_OPS_MASK) == DAC12_CTL1_OPS_OUT0);
}

__STATIC_INLINE void DL_DAC12_enableFIFO(DAC12_Regs *dac12)
{
    /* Insert value */
    dac12->CTL2 |= DAC12_CTL2_FIFOEN_SET;
}

__STATIC_INLINE void DL_DAC12_disableFIFO(DAC12_Regs *dac12)
{
    /* Clear out the bit */
    dac12->CTL2 &= ~DAC12_CTL2_FIFOEN_MASK;
}

__STATIC_INLINE bool DL_DAC12_isFIFOEnabled(const DAC12_Regs *dac12)
{
    uint32_t t = (dac12->CTL2 & DAC12_CTL2_FIFOEN_MASK);
    return (t == DAC12_CTL2_FIFOEN_SET);
}

__STATIC_INLINE DL_DAC12_FIFO_THRESHOLD DL_DAC12_getFIFOThreshold(
    const DAC12_Regs *dac12)
{
    uint32_t fifoThreshold = (dac12->CTL2 & DAC12_CTL2_FIFOTH_MASK);

    return (DL_DAC12_FIFO_THRESHOLD)(fifoThreshold);
}

__STATIC_INLINE void DL_DAC12_setFIFOThreshold(
    DAC12_Regs *dac12, DL_DAC12_FIFO_THRESHOLD fifoThreshold)
{
    DL_Common_updateReg(
        &dac12->CTL2, (uint32_t) fifoThreshold, DAC12_CTL2_FIFOTH_MASK);
}

__STATIC_INLINE DL_DAC12_FIFO_TRIGGER DL_DAC12_getFIFOTriggerSource(
    const DAC12_Regs *dac12)
{
    uint32_t fifoTrig = (dac12->CTL2 & DAC12_CTL2_FIFOTRIGSEL_MASK);

    return (DL_DAC12_FIFO_TRIGGER)(fifoTrig);
}

__STATIC_INLINE void DL_DAC12_setFIFOTriggerSource(
    DAC12_Regs *dac12, DL_DAC12_FIFO_TRIGGER fifoTrig)
{
    DL_Common_updateReg(
        &dac12->CTL2, (uint32_t) fifoTrig, DAC12_CTL2_FIFOTRIGSEL_MASK);
}

__STATIC_INLINE void DL_DAC12_enableDMATrigger(DAC12_Regs *dac12)
{
    /* Insert value */
    dac12->CTL2 |= DAC12_CTL2_DMATRIGEN_SET;
}

__STATIC_INLINE void DL_DAC12_disableDMATrigger(DAC12_Regs *dac12)
{
    /* Clear out the bit */
    dac12->CTL2 &= ~DAC12_CTL2_DMATRIGEN_MASK;
}

__STATIC_INLINE bool DL_DAC12_isDMATriggerEnabled(const DAC12_Regs *dac12)
{
    uint32_t t = (dac12->CTL2 & DAC12_CTL2_DMATRIGEN_MASK);
    return (t == DAC12_CTL2_DMATRIGEN_SET);
}

__STATIC_INLINE void DL_DAC12_enableSampleTimeGenerator(DAC12_Regs *dac12)
{
    /* Insert value */
    dac12->CTL3 |= DAC12_CTL3_STIMEN_SET;
}

__STATIC_INLINE void DL_DAC12_disableSampleTimeGenerator(DAC12_Regs *dac12)
{
    /* Clear out the bit */
    dac12->CTL3 &= ~DAC12_CTL3_STIMEN_MASK;
}

__STATIC_INLINE bool DL_DAC12_isSampleTimeGeneratorEnabled(
    const DAC12_Regs *dac12)
{
    uint32_t t = (dac12->CTL3 & DAC12_CTL3_STIMEN_MASK);
    return (t == DAC12_CTL3_STIMEN_SET);
}

__STATIC_INLINE DL_DAC12_SAMPLES_PER_SECOND DL_DAC12_getSampleRate(
    const DAC12_Regs *dac12)
{
    uint32_t sampleRate = (dac12->CTL3 & DAC12_CTL3_STIMCONFIG_MASK);

    return (DL_DAC12_SAMPLES_PER_SECOND)(sampleRate);
}

__STATIC_INLINE void DL_DAC12_setSampleRate(
    DAC12_Regs *dac12, DL_DAC12_SAMPLES_PER_SECOND sampleRate)
{
    DL_Common_updateReg(
        &dac12->CTL3, (uint32_t) sampleRate, DAC12_CTL3_STIMCONFIG_MASK);
}

__STATIC_INLINE bool DL_DAC12_isCalibrationRunning(const DAC12_Regs *dac12)
{
    uint32_t t = (dac12->CALCTL & DAC12_CALCTL_CALON_MASK);
    return (t == DAC12_CALCTL_CALON_ACTIVE);
}

__STATIC_INLINE void DL_DAC12_startCalibration(DAC12_Regs *dac12)
{
    dac12->CALCTL =
        (DAC12_CALCTL_CALON_ACTIVE | DAC12_CALCTL_CALSEL_SELFCALIBRATIONTRIM);
}

__STATIC_INLINE uint32_t DL_DAC12_getCalibrationData(const DAC12_Regs *dac12)
{
    return (dac12->CALDATA & DAC12_CALDATA_DATA_MASK);
}

void DL_DAC12_performSelfCalibrationBlocking(DAC12_Regs *dac12);

__STATIC_INLINE void DL_DAC12_output8(DAC12_Regs *dac12, uint8_t dataValue)
{
    dac12->DATA0 = dataValue;
}

__STATIC_INLINE void DL_DAC12_output12(DAC12_Regs *dac12, uint32_t dataValue)
{
    dac12->DATA0 = (dataValue & DAC12_DATA0_DATA_VALUE_MASK);
}

uint32_t DL_DAC12_fillFIFO8(
    DAC12_Regs *dac12, const uint8_t *buffer, uint32_t count);

uint32_t DL_DAC12_fillFIFO12(
    DAC12_Regs *dac12, const uint16_t *buffer, uint32_t count);

void DL_DAC12_outputBlocking8(DAC12_Regs *dac12, uint8_t data);

void DL_DAC12_outputBlocking12(DAC12_Regs *dac12, uint16_t data);

__STATIC_INLINE uint32_t DL_DAC12_getInterruptStatus(
    const DAC12_Regs *dac12, uint32_t interruptMask)
{
    return (dac12->CPU_INT.RIS & interruptMask);
}

__STATIC_INLINE void DL_DAC12_clearInterruptStatus(
    DAC12_Regs *dac12, uint32_t interruptMask)
{
    dac12->CPU_INT.ICLR = interruptMask;
}

__STATIC_INLINE void DL_DAC12_enableInterrupt(
    DAC12_Regs *dac12, uint32_t interruptMask)
{
    dac12->CPU_INT.IMASK |= interruptMask;
}

__STATIC_INLINE void DL_DAC12_disableInterrupt(
    DAC12_Regs *dac12, uint32_t interruptMask)
{
    dac12->CPU_INT.IMASK &= ~interruptMask;
}

__STATIC_INLINE DL_DAC12_IIDX DL_DAC12_getPendingInterrupt(
    const DAC12_Regs *dac12)
{
    return ((DL_DAC12_IIDX) dac12->CPU_INT.IIDX);
}

__STATIC_INLINE bool DL_DAC12_isFIFOFull(const DAC12_Regs *dac12)
{
    uint32_t t =
        DL_DAC12_getInterruptStatus(dac12, DL_DAC12_INTERRUPT_FIFO_FULL);
    return (t == DL_DAC12_INTERRUPT_FIFO_FULL);
}

__STATIC_INLINE void DL_DAC12_setPublisherChanID(
    DAC12_Regs *dac12, uint8_t chanID)
{
    dac12->FPUB_1 = (chanID & DAC12_FPUB_1_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_DAC12_getPublisherChanID(const DAC12_Regs *dac12)
{
    return ((uint8_t)((dac12->FPUB_1) & DAC12_FPUB_1_CHANID_MASK));
}

__STATIC_INLINE void DL_DAC12_setSubscriberChanID(
    DAC12_Regs *dac12, DL_DAC12_SUBSCRIBER_INDEX index, uint8_t chanID)
{
    volatile uint32_t *pReg = &dac12->FSUB_0;

    *(pReg + (uint32_t) index) = (chanID & DAC12_FSUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_DAC12_getSubscriberChanID(
    DAC12_Regs *dac12, DL_DAC12_SUBSCRIBER_INDEX index)
{
    volatile uint32_t *pReg = &dac12->FSUB_0;

    return ((uint8_t)(*(pReg + (uint32_t) index) & DAC12_FSUB_0_CHANID_MASK));
}

__STATIC_INLINE void DL_DAC12_enableEvent(
    DAC12_Regs *dac12, uint32_t eventMask)
{
    dac12->GEN_EVENT.IMASK |= (eventMask);
}

__STATIC_INLINE void DL_DAC12_disableEvent(
    DAC12_Regs *dac12, uint32_t eventMask)
{
    dac12->GEN_EVENT.IMASK &= ~(eventMask);
}

__STATIC_INLINE uint32_t DL_DAC12_getEnabledEvents(
    const DAC12_Regs *dac12, uint32_t eventMask)
{
    return ((dac12->GEN_EVENT.IMASK) & (eventMask));
}

__STATIC_INLINE uint32_t DL_DAC12_getEnabledEventStatus(
    const DAC12_Regs *dac12, uint32_t eventMask)
{
    return ((dac12->GEN_EVENT.MIS) & eventMask);
}

__STATIC_INLINE uint32_t DL_DAC12_getRawEventsStatus(
    const DAC12_Regs *dac12, uint32_t eventMask)
{
    return ((dac12->GEN_EVENT.RIS) & eventMask);
}

__STATIC_INLINE void DL_DAC12_clearEventsStatus(
    DAC12_Regs *dac12, uint32_t eventMask)
{
    dac12->GEN_EVENT.ICLR |= (eventMask);
}

#ifdef __cplusplus
}
#endif
#endif /* __MSPM0_HAS_DAC12__ */

#endif /* ti_dl_dl_dac12__include */