dl_aes.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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 */
/*!****************************************************************************
 *  @file       dl_aes.h
 *  @brief      Advanced Encryption Standard (AES) Driver Library
 *  @defgroup   AES Advanced Encryption Standard (AES)
 *
 *  @anchor ti_dl_dl_aes_Overview
 *  # Overview
 *
 *  The AES DriverLib allows full configuration of the MSPM0 AES module.
 *  The AES accelerator module accelerates encryption and decryption operations in hardware based
 *  on the FIPS PUB 197 advanced encryption standard (AES).
 *
 *  <hr>
 ******************************************************************************/
#ifndef ti_dl_dl_aes__include
#define ti_dl_dl_aes__include

#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#ifdef __MSPM0_HAS_AES__

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

#define DL_AES_INTERRUPT_AES_READY            (AES_CPU_INT_IMASK_AESRDY_MASK)

#define DL_AES_EVENT_AES_DMA_TRIGGER0           (AES_DMA_TRIG0_IMASK_DMA0_MASK)

#define DL_AES_EVENT_AES_DMA_TRIGGER1            (AES_DMA_TRIG1_IMASK_DMA1_SET)

#define DL_AES_EVENT_AES_DMA_TRIGGER2            (AES_DMA_TRIG2_IMASK_DMA2_SET)

/* clang-format on */

typedef enum {
    DL_AES_MODE_ENCRYPT_ECB_MODE =
        (AES_AESACTL0_OPX_OP0 | AES_AESACTL0_CMX_ECB),

    DL_AES_MODE_ENCRYPT_CBC_MODE =
        (AES_AESACTL0_OPX_OP0 | AES_AESACTL0_CMX_CBC),

    DL_AES_MODE_ENCRYPT_OFB_MODE =
        (AES_AESACTL0_OPX_OP0 | AES_AESACTL0_CMX_OFB),

    DL_AES_MODE_ENCRYPT_CFB_MODE =
        (AES_AESACTL0_OPX_OP0 | AES_AESACTL0_CMX_CFB),

    DL_AES_MODE_DECRYPT_SAME_KEY_ECB_MODE =
        (AES_AESACTL0_OPX_OP1 | AES_AESACTL0_CMX_ECB),

    DL_AES_MODE_DECRYPT_SAME_KEY_CBC_MODE =
        (AES_AESACTL0_OPX_OP1 | AES_AESACTL0_CMX_CBC),

    DL_AES_MODE_DECRYPT_SAME_KEY_OFB_MODE =
        (AES_AESACTL0_OPX_OP1 | AES_AESACTL0_CMX_OFB),

    DL_AES_MODE_DECRYPT_SAME_KEY_CFB_MODE =
        (AES_AESACTL0_OPX_OP1 | AES_AESACTL0_CMX_CFB),

    DL_AES_MODE_GEN_FIRST_ROUND_KEY_ECB_MODE =
        (AES_AESACTL0_OPX_OP2 | AES_AESACTL0_CMX_ECB),

    DL_AES_MODE_GEN_FIRST_ROUND_KEY_CBC_MODE =
        (AES_AESACTL0_OPX_OP2 | AES_AESACTL0_CMX_CBC),

    DL_AES_MODE_GEN_FIRST_ROUND_KEY_OFB_MODE =
        (AES_AESACTL0_OPX_OP2 | AES_AESACTL0_CMX_OFB),

    DL_AES_MODE_GEN_FIRST_ROUND_KEY_CFB_MODE =
        (AES_AESACTL0_OPX_OP2 | AES_AESACTL0_CMX_CFB),

    DL_AES_MODE_DECRYPT_KEY_IS_FIRST_ROUND_KEY_ECB_MODE =
        (AES_AESACTL0_OPX_OP3 | AES_AESACTL0_CMX_ECB),

    DL_AES_MODE_DECRYPT_KEY_IS_FIRST_ROUND_KEY_CBC_MODE =
        (AES_AESACTL0_OPX_OP3 | AES_AESACTL0_CMX_CBC),

    DL_AES_MODE_DECRYPT_KEY_IS_FIRST_ROUND_KEY_OFB_MODE =
        (AES_AESACTL0_OPX_OP3 | AES_AESACTL0_CMX_OFB),

    DL_AES_MODE_DECRYPT_KEY_IS_FIRST_ROUND_KEY_CFB_MODE =
        (AES_AESACTL0_OPX_OP3 | AES_AESACTL0_CMX_CFB),
} DL_AES_MODE;

typedef enum {
    DL_AES_IIDX_AES_READY = AES_CPU_INT_IIDX_STAT_AESRDY,
    DL_AES_IIDX_AES_DMA_TRIGGER0 = AES_DMA_TRIG0_IIDX_STAT_DMA0,
    DL_AES_IIDX_AES_DMA_TRIGGER1 = AES_DMA_TRIG1_IIDX_STAT_DMA1,
    DL_AES_IIDX_AES_DMA_TRIGGER2 = AES_DMA_TRIG2_IIDX_STAT_DMA2
} DL_AES_IIDX;

typedef enum {
    DL_AES_OPERATION_ENC = AES_AESACTL0_OPX_OP0,
    DL_AES_OPERATION_DEC_SAME_KEY = AES_AESACTL0_OPX_OP1,
    DL_AES_OPERATION_GEN_FIRST_ROUND = AES_AESACTL0_OPX_OP2,
    DL_AES_OPERATION_DEC_KEY_IS_FIRST_ROUND = AES_AESACTL0_OPX_OP3,
} DL_AES_OPERATION;

typedef enum {
    DL_AES_KEY_LENGTH_128 = AES_AESACTL0_KLX_AES128,
    DL_AES_KEY_LENGTH_256 = AES_AESACTL0_KLX_AES256,
} DL_AES_KEY_LENGTH;

typedef enum {
    DL_AES_STATUS_SUCCESS,
    DL_AES_STATUS_UNALIGNED_ACCESS,
} DL_AES_STATUS;

typedef struct {
    uint32_t controlWord0;
    uint32_t controlWord1;
    uint32_t interruptMask0;
    uint32_t interruptMask1;
    uint32_t interruptMask2;
    uint32_t interruptMask3;
    bool backupRdy;
} DL_AES_backupConfig;

__STATIC_INLINE void DL_AES_enablePower(AES_Regs *aes)
{
    aes->GPRCM.PWREN = (AES_PWREN_KEY_UNLOCK_W | AES_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_AES_disablePower(AES_Regs *aes)
{
    aes->GPRCM.PWREN = (AES_PWREN_KEY_UNLOCK_W | AES_PWREN_ENABLE_DISABLE);
}

__STATIC_INLINE bool DL_AES_isPowerEnabled(const AES_Regs *aes)
{
    return (
        (aes->GPRCM.PWREN & AES_PWREN_ENABLE_MASK) == AES_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_AES_reset(AES_Regs *aes)
{
    aes->GPRCM.RSTCTL =
        (AES_RSTCTL_KEY_UNLOCK_W | AES_RSTCTL_RESETSTKYCLR_CLR |
            AES_RSTCTL_RESETASSERT_ASSERT);
}

__STATIC_INLINE bool DL_AES_isReset(const AES_Regs *aes)
{
    return ((aes->GPRCM.STAT & AES_STAT_RESETSTKY_MASK) ==
            AES_STAT_RESETSTKY_RESET);
}

__STATIC_INLINE void DL_AES_init(
    AES_Regs *aes, DL_AES_MODE aesConfig, DL_AES_KEY_LENGTH keyLength)
{
    DL_Common_updateReg(&aes->AESACTL0,
        ((uint32_t) aesConfig | (uint32_t) keyLength),
        (uint32_t)(AES_AESACTL0_OPX_MASK | AES_AESACTL0_CMX_MASK |
                   AES_AESACTL0_KLX_MASK));
}

__STATIC_INLINE void DL_AES_softwareReset(AES_Regs *aes)
{
    aes->AESACTL0 |= (AES_AESACTL0_SWRST_RST);
}

__STATIC_INLINE bool DL_AES_isFaultFlagSet(const AES_Regs *aes)
{
    return (
        (aes->AESACTL0 & AES_AESACTL0_ERRFG_MASK) == AES_AESACTL0_ERRFG_ERR);
}

__STATIC_INLINE void DL_AES_clearFaultFlag(AES_Regs *aes)
{
    aes->AESACTL0 &= ~(AES_AESACTL0_ERRFG_ERR);
}

__STATIC_INLINE void DL_AES_enableCipherMode(AES_Regs *aes)
{
    aes->AESACTL0 |= (AES_AESACTL0_CMEN_ENABLE);
}

__STATIC_INLINE void DL_AES_disablesCipherMode(AES_Regs *aes)
{
    aes->AESACTL0 &= ~(AES_AESACTL0_CMEN_ENABLE);
}

__STATIC_INLINE void DL_AES_setCipherBlockCounter(
    AES_Regs *aes, uint32_t count)
{
    DL_Common_updateReg(&aes->AESACTL1, count, AES_AESACTL1_BLKCNTX_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getCipherBlockCounter(const AES_Regs *aes)
{
    return (aes->AESACTL1 & AES_AESACTL1_BLKCNTX_MASK);
}

__STATIC_INLINE bool DL_AES_isBusy(const AES_Regs *aes)
{
    return (
        (aes->AESASTAT & AES_AESASTAT_BUSY_MASK) == AES_AESASTAT_BUSY_BUSY);
}

__STATIC_INLINE bool DL_AES_getDataOutReadStatus(const AES_Regs *aes)
{
    return (
        (aes->AESASTAT & AES_AESASTAT_DOUTRD_MASK) == AES_AESASTAT_DOUTRD_ALL);
}

__STATIC_INLINE uint8_t DL_AES_getKeyBytesCount(const AES_Regs *aes)
{
    return ((uint8_t)((aes->AESASTAT & AES_AESASTAT_KEYCNTX_MAXNUM) >> 4));
}

__STATIC_INLINE uint8_t DL_AES_getDataInBytesCount(const AES_Regs *aes)
{
    return ((uint8_t)((aes->AESASTAT & AES_AESASTAT_DINCNTX_MAXNUM) >> 8));
}

__STATIC_INLINE uint8_t DL_AES_getDataOutBytesCount(const AES_Regs *aes)
{
    return ((uint8_t)((aes->AESASTAT & AES_AESASTAT_DOUTCNTX_MAXNUM) >> 12));
}

__STATIC_INLINE void DL_AES_setAllDataWritten(AES_Regs *aes)
{
    aes->AESASTAT |= AES_AESASTAT_DINWR_ALL;
}

__STATIC_INLINE void DL_AES_setAllKeyWritten(AES_Regs *aes)
{
    aes->AESASTAT |= AES_AESASTAT_KEYWR_ALL;
}

__STATIC_INLINE bool DL_AES_isAllDataWritten(const AES_Regs *aes)
{
    return (aes->AESASTAT & AES_AESASTAT_DINWR_MASK) == AES_AESASTAT_DINWR_ALL;
}

__STATIC_INLINE bool DL_AES_isAllKeysWritten(const AES_Regs *aes)
{
    return (aes->AESASTAT & AES_AESASTAT_KEYWR_MASK) == AES_AESASTAT_KEYWR_ALL;
}

DL_AES_STATUS DL_AES_setKey(
    AES_Regs *aes, const uint8_t *key, DL_AES_KEY_LENGTH keyLength);

void DL_AES_setKeyAligned(
    AES_Regs *aes, const uint32_t *keyAligned, DL_AES_KEY_LENGTH keyLength);

DL_AES_STATUS DL_AES_xorData(
    const uint8_t *data, const uint8_t *xorData, uint8_t *xorOutputData);

void DL_AES_xorDataAligned(uint32_t *dataAligned, uint32_t *xorDataAligned,
    uint32_t *xorOutputDataAligned);

DL_AES_STATUS DL_AES_loadDataIn(AES_Regs *aes, const uint8_t *data);

void DL_AES_loadDataInAligned(AES_Regs *aes, const uint32_t *dataAligned);

DL_AES_STATUS DL_AES_getDataOut(const AES_Regs *aes, uint8_t *data);

void DL_AES_getDataOutAligned(const AES_Regs *aes, uint32_t *dataAligned);

DL_AES_STATUS DL_AES_loadXORDataIn(AES_Regs *aes, const uint8_t *data);

void DL_AES_loadXORDataInAligned(AES_Regs *aes, const uint32_t *dataAligned);

DL_AES_STATUS DL_AES_loadXORDataInWithoutTrigger(
    AES_Regs *aes, const uint8_t *data);

void DL_AES_loadXORDataInWithoutTriggerAligned(
    AES_Regs *aes, const uint32_t *dataAligned);

__STATIC_INLINE void DL_AES_enableInterrupt(AES_Regs *aes)
{
    aes->CPU_INT.IMASK |= DL_AES_INTERRUPT_AES_READY;
}

__STATIC_INLINE void DL_AES_enableDMATrigger0Interrupt(AES_Regs *aes)
{
    aes->DMA_TRIG0.IMASK |= DL_AES_EVENT_AES_DMA_TRIGGER0;
}

__STATIC_INLINE void DL_AES_enableDMATrigger1Interrupt(AES_Regs *aes)
{
    aes->DMA_TRIG1.IMASK |= DL_AES_EVENT_AES_DMA_TRIGGER1;
}

__STATIC_INLINE void DL_AES_enableDMATrigger2Interrupt(AES_Regs *aes)
{
    aes->DMA_TRIG2.IMASK |= DL_AES_EVENT_AES_DMA_TRIGGER2;
}

__STATIC_INLINE void DL_AES_disableInterrupt(AES_Regs *aes)
{
    aes->CPU_INT.IMASK &= ~(AES_CPU_INT_IMASK_AESRDY_MASK);
}

__STATIC_INLINE void DL_AES_disableDMATrigger0Event(AES_Regs *aes)
{
    aes->DMA_TRIG0.IMASK &= ~(AES_DMA_TRIG0_IMASK_DMA0_MASK);
}

__STATIC_INLINE void DL_AES_disableDMATrigger1Event(AES_Regs *aes)
{
    aes->DMA_TRIG1.IMASK &= ~(AES_DMA_TRIG1_IMASK_DMA1_MASK);
}

__STATIC_INLINE void DL_AES_disableDMATrigger2Event(AES_Regs *aes)
{
    aes->DMA_TRIG2.IMASK &= ~(AES_DMA_TRIG2_IMASK_DMA2_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getEnabledInterrupts(const AES_Regs *aes)
{
    return (aes->CPU_INT.IMASK & AES_CPU_INT_IMASK_AESRDY_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger0Event(const AES_Regs *aes)
{
    return (aes->DMA_TRIG0.IMASK & AES_DMA_TRIG0_IMASK_DMA0_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger1Event(const AES_Regs *aes)
{
    return (aes->DMA_TRIG1.IMASK & AES_DMA_TRIG1_IMASK_DMA1_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger2Event(const AES_Regs *aes)
{
    return (aes->DMA_TRIG2.IMASK & AES_DMA_TRIG2_IMASK_DMA2_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getEnabledInterruptStatus(const AES_Regs *aes)
{
    return (aes->CPU_INT.MIS & AES_CPU_INT_IMASK_AESRDY_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger0EventStatus(
    const AES_Regs *aes)
{
    return (aes->DMA_TRIG0.MIS & AES_DMA_TRIG0_IMASK_DMA0_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger1EventStatus(
    const AES_Regs *aes)
{
    return (aes->DMA_TRIG1.MIS & AES_DMA_TRIG1_IMASK_DMA1_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getEnabledDMATrigger2EventStatus(
    const AES_Regs *aes)
{
    return (aes->DMA_TRIG2.MIS & AES_DMA_TRIG2_IMASK_DMA2_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getRawInterruptStatus(const AES_Regs *aes)
{
    return (aes->CPU_INT.RIS & AES_CPU_INT_IMASK_AESRDY_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getRawDMATrigger0EventStatus(
    const AES_Regs *aes)
{
    return (aes->DMA_TRIG0.RIS & AES_DMA_TRIG0_IMASK_DMA0_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getRawDMATrigger1EventStatus(
    const AES_Regs *aes)
{
    return (aes->DMA_TRIG1.RIS & AES_DMA_TRIG1_IMASK_DMA1_MASK);
}

__STATIC_INLINE uint32_t DL_AES_getRawDMATrigger2EventStatus(
    const AES_Regs *aes)
{
    return (aes->DMA_TRIG2.RIS & AES_DMA_TRIG2_IMASK_DMA2_MASK);
}

__STATIC_INLINE DL_AES_IIDX DL_AES_getPendingInterrupt(const AES_Regs *aes)
{
    uint32_t interruptIdx = (uint32_t) aes->CPU_INT.IIDX;

    return (DL_AES_IIDX) interruptIdx;
}

__STATIC_INLINE DL_AES_IIDX DL_AES_getPendingDMATrigger0Event(
    const AES_Regs *aes)
{
    uint32_t eventIdx = (uint32_t) aes->DMA_TRIG0.IIDX;

    return (DL_AES_IIDX) eventIdx;
}

__STATIC_INLINE DL_AES_IIDX DL_AES_getPendingDMATrigger1Event(
    const AES_Regs *aes)
{
    uint32_t eventIdx = (uint32_t) aes->DMA_TRIG1.IIDX;

    return (DL_AES_IIDX) eventIdx;
}

__STATIC_INLINE DL_AES_IIDX DL_AES_getPendingDMATrigger2Event(
    const AES_Regs *aes)
{
    uint32_t eventIdx = (uint32_t) aes->DMA_TRIG2.IIDX;

    return (DL_AES_IIDX) eventIdx;
}

__STATIC_INLINE void DL_AES_clearInterruptStatus(AES_Regs *aes)
{
    aes->CPU_INT.ICLR |= AES_CPU_INT_IMASK_AESRDY_MASK;
}

__STATIC_INLINE void DL_AES_clearDMATrigger0EventStatus(AES_Regs *aes)
{
    aes->DMA_TRIG0.ICLR |= AES_DMA_TRIG0_IMASK_DMA0_MASK;
}

__STATIC_INLINE void DL_AES_clearDMATrigger1EventStatus(AES_Regs *aes)
{
    aes->DMA_TRIG1.ICLR |= AES_DMA_TRIG1_IMASK_DMA1_MASK;
}

__STATIC_INLINE void DL_AES_clearDMATrigger2EventStatus(AES_Regs *aes)
{
    aes->DMA_TRIG2.ICLR |= AES_DMA_TRIG2_IMASK_DMA2_MASK;
}

bool DL_AES_saveConfiguration(const AES_Regs *aes, DL_AES_backupConfig *ptr);

bool DL_AES_restoreConfiguration(AES_Regs *aes, DL_AES_backupConfig *ptr);

#ifdef __cplusplus
}
#endif

#endif /* __MSPM0_HAS_AES__ */

#endif /* ti_dl_dl_aes__include */