dl_dma.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/*!****************************************************************************
 *  @file       dl_dma.h
 *  @brief      Direct Memory Access (DMA) Driver Library
 *  @defgroup   DMA Direct Memory Access (DMA)
 *
 *  @anchor ti_dl_dl_m0p_dma_Overview
 *  # Overview
 *
 *  The Direct Memory Access (DMA) Library allows full configuration of
 *  the MSPM0 DMA module.
 *  The DMA controller transfers data from one address to another, without CPU
 *  intervention, across the entire address range.
 *  DMA controllers have multiple channels that can be configured independently
 *
 ******************************************************************************
 */
#ifndef ti_dl_dl_m0p_dma__include
#define ti_dl_dl_m0p_dma__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#ifdef __cplusplus
extern "C" {
#endif

#if (DMA_SYS_N_DMA_FULL_CHANNEL > 0)

#define DEVICE_HAS_DMA_FULL_CHANNEL
#endif

#ifdef DMA_SYS_MMR_LLONG

#define DEVICE_HAS_LLONG_ACCESS

#define DEVICE_HAS_AUTO_AND_GATHER
#endif

/* clang-format off */

#define DL_DMA_INTERRUPT_CHANNEL0                        (DMA_CPU_INT_IMASK_DMACH0_SET)

#define DL_DMA_INTERRUPT_CHANNEL1                        (DMA_CPU_INT_IMASK_DMACH1_SET)

#define DL_DMA_INTERRUPT_CHANNEL2                        (DMA_CPU_INT_IMASK_DMACH2_SET)

#define DL_DMA_INTERRUPT_CHANNEL3                        (DMA_CPU_INT_IMASK_DMACH3_SET)

#define DL_DMA_INTERRUPT_CHANNEL4                        (DMA_CPU_INT_IMASK_DMACH4_SET)

#define DL_DMA_INTERRUPT_CHANNEL5                        (DMA_CPU_INT_IMASK_DMACH5_SET)

#define DL_DMA_INTERRUPT_CHANNEL6                        (DMA_CPU_INT_IMASK_DMACH6_SET)

#define DL_DMA_INTERRUPT_CHANNEL7                        (DMA_CPU_INT_IMASK_DMACH7_SET)

#define DL_DMA_INTERRUPT_CHANNEL8                        (DMA_CPU_INT_IMASK_DMACH8_SET)

#define DL_DMA_INTERRUPT_CHANNEL9                        (DMA_CPU_INT_IMASK_DMACH9_SET)

#define DL_DMA_INTERRUPT_CHANNEL10                      (DMA_CPU_INT_IMASK_DMACH10_SET)

#define DL_DMA_INTERRUPT_CHANNEL12                      (DMA_CPU_INT_IMASK_DMACH12_SET)

#define DL_DMA_INTERRUPT_CHANNEL13                      (DMA_CPU_INT_IMASK_DMACH13_SET)

#define DL_DMA_INTERRUPT_CHANNEL14                      (DMA_CPU_INT_IMASK_DMACH14_SET)

#define DL_DMA_INTERRUPT_CHANNEL15                      (DMA_CPU_INT_IMASK_DMACH15_SET)

#ifdef DEVICE_HAS_DMA_FULL_CHANNEL

#define DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL0        (DMA_CPU_INT_IMASK_PREIRQCH0_SET)

#define DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL1        (DMA_CPU_INT_IMASK_PREIRQCH1_SET)

#define DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL2        (DMA_CPU_INT_IMASK_PREIRQCH2_SET)

#define DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL3        (DMA_CPU_INT_IMASK_PREIRQCH3_SET)

#define DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL4        (DMA_CPU_INT_IMASK_PREIRQCH4_SET)

#define DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL5        (DMA_CPU_INT_IMASK_PREIRQCH5_SET)

#define DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL6        (DMA_CPU_INT_IMASK_PREIRQCH6_SET)

#define DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL7        (DMA_CPU_INT_IMASK_PREIRQCH7_SET)
#endif /* DEVICE_HAS_DMA_FULL_CHANNEL */

#define DL_DMA_INTERRUPT_ADDR_ERROR                      (DMA_CPU_INT_IMASK_ADDRERR_SET)

#define DL_DMA_INTERRUPT_DATA_ERROR                      (DMA_CPU_INT_IMASK_DATAERR_SET)

#define DL_DMA_EVENT_CHANNEL0                             (DMA_GEN_EVENT_IMASK_DMACH0_SET)

#define DL_DMA_EVENT_CHANNEL1                             (DMA_GEN_EVENT_IMASK_DMACH1_SET)

#define DL_DMA_EVENT_CHANNEL2                             (DMA_GEN_EVENT_IMASK_DMACH2_SET)

#define DL_DMA_EVENT_CHANNEL3                             (DMA_GEN_EVENT_IMASK_DMACH3_SET)

#define DL_DMA_EVENT_CHANNEL4                             (DMA_GEN_EVENT_IMASK_DMACH4_SET)

#define DL_DMA_EVENT_CHANNEL5                             (DMA_GEN_EVENT_IMASK_DMACH5_SET)

#define DL_DMA_EVENT_CHANNEL6                             (DMA_GEN_EVENT_IMASK_DMACH6_SET)

#define DL_DMA_EVENT_CHANNEL7                             (DMA_GEN_EVENT_IMASK_DMACH7_SET)

#define DL_DMA_EVENT_CHANNEL8                             (DMA_GEN_EVENT_IMASK_DMACH8_SET)

#define DL_DMA_EVENT_CHANNEL9                             (DMA_GEN_EVENT_IMASK_DMACH9_SET)

#define DL_DMA_EVENT_CHANNEL10                           (DMA_GEN_EVENT_IMASK_DMACH10_SET)

#define DL_DMA_EVENT_CHANNEL12                           (DMA_GEN_EVENT_IMASK_DMACH12_SET)

#define DL_DMA_EVENT_CHANNEL13                           (DMA_GEN_EVENT_IMASK_DMACH13_SET)

#define DL_DMA_EVENT_CHANNEL14                           (DMA_GEN_EVENT_IMASK_DMACH14_SET)

#define DL_DMA_EVENT_CHANNEL15                           (DMA_GEN_EVENT_IMASK_DMACH15_SET)

#ifdef DEVICE_HAS_DMA_FULL_CHANNEL

#define DL_DMA_FULL_CH_EVENT_EARLY_CHANNEL0            (DMA_GEN_EVENT_IMASK_PREIRQCH0_SET)

#define DL_DMA_FULL_CH_EVENT_EARLY_CHANNEL1            (DMA_GEN_EVENT_IMASK_PREIRQCH1_SET)

#define DL_DMA_FULL_CH_EVENT_EARLY_CHANNEL2            (DMA_GEN_EVENT_IMASK_PREIRQCH2_SET)

#define DL_DMA_FULL_CH_EVENT_EARLY_CHANNEL3            (DMA_GEN_EVENT_IMASK_PREIRQCH3_SET)

#define DL_DMA_FULL_CH_EVENT_EARLY_CHANNEL4            (DMA_GEN_EVENT_IMASK_PREIRQCH4_SET)

#define DL_DMA_FULL_CH_EVENT_EARLY_CHANNEL5            (DMA_GEN_EVENT_IMASK_PREIRQCH5_SET)

#define DL_DMA_FULL_CH_EVENT_EARLY_CHANNEL6            (DMA_GEN_EVENT_IMASK_PREIRQCH6_SET)

#define DL_DMA_FULL_CH_EVENT_EARLY_CHANNEL7            (DMA_GEN_EVENT_IMASK_PREIRQCH7_SET)
#endif /* DEVICE_HAS_DMA_FULL_CHANNEL */

#define DL_DMA_EVENT_ADDR_ERROR                     (DMA_GEN_EVENT_IMASK_ADDRERR_SET)

#define DL_DMA_EVENT_DATA_ERROR                     (DMA_GEN_EVENT_IMASK_DATAERR_SET)

typedef enum {
    DL_DMA_SINGLE_TRANSFER_MODE = DMA_DMACTL_DMATM_SINGLE,
    DL_DMA_SINGLE_BLOCK_TRANSFER_MODE = DMA_DMACTL_DMATM_BLOCK,
#ifdef DEVICE_HAS_DMA_FULL_CHANNEL

    DL_DMA_FULL_CH_REPEAT_SINGLE_TRANSFER_MODE = DMA_DMACTL_DMATM_RPTSNGL,
    DL_DMA_FULL_CH_REPEAT_BLOCK_TRANSFER_MODE = DMA_DMACTL_DMATM_RPTBLCK,
#endif /* DEVICE_HAS_DMA_FULL_CHANNEL */
} DL_DMA_TRANSFER_MODE;

typedef enum {
    DL_DMA_NORMAL_MODE = DMA_DMACTL_DMAEM_NORMAL,
#ifdef DEVICE_HAS_DMA_FULL_CHANNEL
#ifdef DEVICE_HAS_AUTO_AND_GATHER

    DL_DMA_FULL_CH_GATHER_MODE = DMA_DMACTL_DMAEM_GATHERMODE,
#endif /* DEVICE_HAS_AUTO_AND_GATHER */

    DL_DMA_FULL_CH_FILL_MODE = DMA_DMACTL_DMAEM_FILLMODE,
    DL_DMA_FULL_CH_TABLE_MODE = DMA_DMACTL_DMAEM_TABLEMODE,
#endif /* DEVICE_HAS_DMA_FULL_CHANNEL */
} DL_DMA_EXTENDED_MODE;

typedef enum {
    DL_DMA_ADDR_UNCHANGED = DMA_DMACTL_DMASRCINCR_UNCHANGED,
    DL_DMA_ADDR_DECREMENT = DMA_DMACTL_DMASRCINCR_DECREMENT,
    DL_DMA_ADDR_INCREMENT = DMA_DMACTL_DMASRCINCR_INCREMENT,
    DL_DMA_ADDR_STRIDE_2 = DMA_DMACTL_DMASRCINCR_STRIDE_2,
    DL_DMA_ADDR_STRIDE_3 = DMA_DMACTL_DMASRCINCR_STRIDE_3,
    DL_DMA_ADDR_STRIDE_4 = DMA_DMACTL_DMASRCINCR_STRIDE_4,
    DL_DMA_ADDR_STRIDE_5 = DMA_DMACTL_DMASRCINCR_STRIDE_5,
    DL_DMA_ADDR_STRIDE_6 = DMA_DMACTL_DMASRCINCR_STRIDE_6,
    DL_DMA_ADDR_STRIDE_7 = DMA_DMACTL_DMASRCINCR_STRIDE_7,
    DL_DMA_ADDR_STRIDE_8 = DMA_DMACTL_DMASRCINCR_STRIDE_8,
    DL_DMA_ADDR_STRIDE_9 = DMA_DMACTL_DMASRCINCR_STRIDE_9,
} DL_DMA_INCREMENT;

typedef enum {
    DL_DMA_EARLY_INTERRUPT_THRESHOLD_DISABLED = DMA_DMACTL_DMAPREIRQ_PREIRQ_DISABLE,
    DL_DMA_EARLY_INTERRUPT_THRESHOLD_1 = DMA_DMACTL_DMAPREIRQ_PREIRQ_1,
    DL_DMA_EARLY_INTERRUPT_THRESHOLD_2 = DMA_DMACTL_DMAPREIRQ_PREIRQ_2,
    DL_DMA_EARLY_INTERRUPT_THRESHOLD_4 = DMA_DMACTL_DMAPREIRQ_PREIRQ_4,
    DL_DMA_EARLY_INTERRUPT_THRESHOLD_8 = DMA_DMACTL_DMAPREIRQ_PREIRQ_8,
    DL_DMA_EARLY_INTERRUPT_THRESHOLD_32 = DMA_DMACTL_DMAPREIRQ_PREIRQ_32,
    DL_DMA_EARLY_INTERRUPT_THRESHOLD_64 = DMA_DMACTL_DMAPREIRQ_PREIRQ_64,
    DL_DMA_EARLY_INTERRUPT_THRESHOLD_HALF = DMA_DMACTL_DMAPREIRQ_PREIRQ_HALF,
} DL_DMA_EARLY_INTERRUPT_THRESHOLD;

typedef enum {
    DL_DMA_BURST_SIZE_INFINITY = DMA_DMAPRIO_BURSTSZ_INFINITI,
    DL_DMA_BURST_SIZE_8 = DMA_DMAPRIO_BURSTSZ_BURST_8,
    DL_DMA_BURST_SIZE_16 = DMA_DMAPRIO_BURSTSZ_BUSRT_16,
    DL_DMA_BURST_SIZE_32 = DMA_DMAPRIO_BURSTSZ_BURST_32,
} DL_DMA_BURST_SIZE;

typedef enum {
    DL_DMA_TRIGGER_TYPE_INTERNAL = DMA_DMATCTL_DMATINT_INTERNAL,
    DL_DMA_TRIGGER_TYPE_EXTERNAL = DMA_DMATCTL_DMATINT_EXTERNAL,
} DL_DMA_TRIGGER_TYPE;

typedef enum {
    DL_DMA_WIDTH_BYTE = DMA_DMACTL_DMASRCWDTH_BYTE,
    DL_DMA_WIDTH_HALF_WORD = DMA_DMACTL_DMASRCWDTH_HALF,
    DL_DMA_WIDTH_WORD = DMA_DMACTL_DMASRCWDTH_WORD,
    DL_DMA_WIDTH_LONG = DMA_DMACTL_DMASRCWDTH_LONG,
    #ifdef DEVICE_HAS_LLONG_ACCESS

    DL_DMA_WIDTH_LONG_LONG = DMA_DMACTL_DMASRCWDTH_LONGLONG,
    #endif /* DEVICE_HAS_LLONG_ACCESS*/
} DL_DMA_WIDTH;

typedef enum {
    DL_DMA_EVENT_IIDX_NO_INTR = DMA_GEN_EVENT_IIDX_STAT_NO_INTR,
    DL_DMA_EVENT_IIDX_DMACH0 = DMA_GEN_EVENT_IIDX_STAT_DMACH0,
    DL_DMA_EVENT_IIDX_DMACH1 = DMA_GEN_EVENT_IIDX_STAT_DMACH1,
    DL_DMA_EVENT_IIDX_DMACH2 = DMA_GEN_EVENT_IIDX_STAT_DMACH2,
    DL_DMA_EVENT_IIDX_DMACH3 = DMA_GEN_EVENT_IIDX_STAT_DMACH3,
    DL_DMA_EVENT_IIDX_DMACH4 = DMA_GEN_EVENT_IIDX_STAT_DMACH4,
    DL_DMA_EVENT_IIDX_DMACH5 = DMA_GEN_EVENT_IIDX_STAT_DMACH5,
    DL_DMA_EVENT_IIDX_DMACH6 = DMA_GEN_EVENT_IIDX_STAT_DMACH6,
    DL_DMA_EVENT_IIDX_DMACH7 = DMA_GEN_EVENT_IIDX_STAT_DMACH7,
    DL_DMA_EVENT_IIDX_DMACH8 = DMA_GEN_EVENT_IIDX_STAT_DMACH8,
    DL_DMA_EVENT_IIDX_DMACH9 = DMA_GEN_EVENT_IIDX_STAT_DMACH9,
    DL_DMA_EVENT_IIDX_DMACH10 = DMA_GEN_EVENT_IIDX_STAT_DMACH10,
    DL_DMA_EVENT_IIDX_DMACH11 = DMA_GEN_EVENT_IIDX_STAT_DMACH11,
    DL_DMA_EVENT_IIDX_DMACH12 = DMA_GEN_EVENT_IIDX_STAT_DMACH12,
    DL_DMA_EVENT_IIDX_DMACH13 = DMA_GEN_EVENT_IIDX_STAT_DMACH13,
    DL_DMA_EVENT_IIDX_DMACH14 = DMA_GEN_EVENT_IIDX_STAT_DMACH14,
    DL_DMA_EVENT_IIDX_DMACH15 = DMA_GEN_EVENT_IIDX_STAT_DMACH15,
#ifdef DEVICE_HAS_DMA_FULL_CHANNEL

    DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH0 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH0,
    DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH1 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH1,
    DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH2 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH2,
    DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH3 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH3,
    DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH4 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH4,
    DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH5 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH5,
    DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH6 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH6,
    DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH7 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH7,
#endif /* DEVICE_HAS_DMA_FULL_CHANNEL */

    DL_DMA_EVENT_IIDX_ADDR_ERROR = DMA_GEN_EVENT_IIDX_STAT_ADDRERR,

    DL_DMA_EVENT_IIDX_DATA_ERROR = DMA_GEN_EVENT_IIDX_STAT_DATAERR
} DL_DMA_EVENT_IIDX;

typedef enum {
    DL_DMA_PUBLISHER_INDEX_0 = 0,
} DL_DMA_PUBLISHER_INDEX;

typedef enum {
    DL_DMA_SUBSCRIBER_INDEX_0 = 0,
    DL_DMA_SUBSCRIBER_INDEX_1 = 1
} DL_DMA_SUBSCRIBER_INDEX;

typedef enum {
    DL_DMA_AUTOEN_DISABLE = DMA_DMACTL_DMAAUTOEN_DISABLE,
    #ifdef DEVICE_HAS_AUTO_AND_GATHER

    DL_DMA_AUTOEN_DMASA = DMA_DMACTL_DMAAUTOEN_DMASA,
    DL_DMA_AUTOEN_DMADA = DMA_DMACTL_DMAAUTOEN_DMADA,
    DL_DMA_AUTOEN_DMASZ = DMA_DMACTL_DMAAUTOEN_DMASZ,
    #endif /* DEVICE_HAS_AUTO_AND_GATHER*/
} DL_DMA_AUTOEN;

/* clang-format on */

typedef struct {
    uint8_t trigger;

    DL_DMA_TRIGGER_TYPE triggerType;

    DL_DMA_TRANSFER_MODE transferMode;

    DL_DMA_EXTENDED_MODE extendedMode;

    DL_DMA_WIDTH srcWidth;

    DL_DMA_WIDTH destWidth;

    DL_DMA_INCREMENT srcIncrement;

    DL_DMA_INCREMENT destIncrement;
} DL_DMA_Config;

void DL_DMA_initChannel(
    DMA_Regs *dma, uint8_t channelNum, const DL_DMA_Config *config);

__STATIC_INLINE void DL_DMA_configTransfer(DMA_Regs *dma, uint8_t channelNum,
    DL_DMA_TRANSFER_MODE transferMode, DL_DMA_EXTENDED_MODE extendedMode,
    DL_DMA_WIDTH srcWidth, DL_DMA_WIDTH destWidth,
    DL_DMA_INCREMENT srcIncrement, DL_DMA_INCREMENT destIncrement)
{
    dma->DMACHAN[channelNum].DMACTL =
        ((uint32_t) transferMode | (uint32_t) extendedMode |
            (((uint32_t) destIncrement) << 4) | (uint32_t) srcIncrement |
            ((uint32_t) destWidth << 4) | (uint32_t) srcWidth);
}

__STATIC_INLINE void DL_DMA_enableRoundRobinPriority(DMA_Regs *dma)
{
    dma->DMAPRIO |= DMA_DMAPRIO_ROUNDROBIN_ENABLE;
}

__STATIC_INLINE void DL_DMA_disableRoundRobinPriority(DMA_Regs *dma)
{
    dma->DMAPRIO &= ~(DMA_DMAPRIO_ROUNDROBIN_MASK);
}

__STATIC_INLINE bool DL_DMA_isRoundRobinPriorityEnabled(const DMA_Regs *dma)
{
    return ((dma->DMAPRIO & DMA_DMAPRIO_ROUNDROBIN_MASK) ==
            DMA_DMAPRIO_ROUNDROBIN_ENABLE);
}

__STATIC_INLINE void DL_DMA_setBurstSize(
    DMA_Regs *dma, DL_DMA_BURST_SIZE burstSize)
{
    DL_Common_updateReg(
        &dma->DMAPRIO, (uint32_t) burstSize, DMA_DMAPRIO_BURSTSZ_MASK);
}

__STATIC_INLINE DL_DMA_BURST_SIZE DL_DMA_getBurstSize(const DMA_Regs *dma)
{
    uint32_t burstSize = dma->DMAPRIO & DMA_DMAPRIO_BURSTSZ_MASK;

    return (DL_DMA_BURST_SIZE)(burstSize);
}

__STATIC_INLINE void DL_DMA_enableChannel(DMA_Regs *dma, uint8_t channelNum)
{
    dma->DMACHAN[channelNum].DMACTL |= DMA_DMACTL_DMAEN_ENABLE;
}

__STATIC_INLINE void DL_DMA_disableChannel(DMA_Regs *dma, uint8_t channelNum)
{
    dma->DMACHAN[channelNum].DMACTL &= ~(DMA_DMACTL_DMAEN_MASK);
}

__STATIC_INLINE bool DL_DMA_isChannelEnabled(
    const DMA_Regs *dma, uint8_t channelNum)
{
    return ((dma->DMACHAN[channelNum].DMACTL & DMA_DMACTL_DMAEN_MASK) ==
            DMA_DMACTL_DMAEN_ENABLE);
}

__STATIC_INLINE void DL_DMA_configMode(DMA_Regs *dma, uint8_t channelNum,
    DL_DMA_TRANSFER_MODE transferMode, DL_DMA_EXTENDED_MODE extendedMode)
{
    DL_Common_updateReg(&dma->DMACHAN[channelNum].DMACTL,
        (uint32_t) transferMode | (uint32_t) extendedMode,
        DMA_DMACTL_DMATM_MASK | DMA_DMACTL_DMAEM_MASK);
}

__STATIC_INLINE void DL_DMA_setTransferMode(
    DMA_Regs *dma, uint8_t channelNum, DL_DMA_TRANSFER_MODE transferMode)
{
    DL_Common_updateReg(&dma->DMACHAN[channelNum].DMACTL,
        (uint32_t) transferMode, DMA_DMACTL_DMATM_MASK);
}

__STATIC_INLINE DL_DMA_TRANSFER_MODE DL_DMA_getTransferMode(
    const DMA_Regs *dma, uint8_t channelNum)
{
    uint32_t mode = (dma->DMACHAN[channelNum].DMACTL & DMA_DMACTL_DMATM_MASK);

    return (DL_DMA_TRANSFER_MODE)(mode);
}

__STATIC_INLINE void DL_DMA_setExtendedMode(
    DMA_Regs *dma, uint8_t channelNum, DL_DMA_EXTENDED_MODE extendedMode)
{
    DL_Common_updateReg(&dma->DMACHAN[channelNum].DMACTL,
        (uint32_t) extendedMode, DMA_DMACTL_DMAEM_MASK);
}

__STATIC_INLINE DL_DMA_EXTENDED_MODE DL_DMA_getExtendedMode(
    const DMA_Regs *dma, uint8_t channelNum)
{
    uint32_t mode = (dma->DMACHAN[channelNum].DMACTL & DMA_DMACTL_DMAEM_MASK);

    return (DL_DMA_EXTENDED_MODE)(mode);
}

__STATIC_INLINE void DL_DMA_startTransfer(DMA_Regs *dma, uint8_t channelNum)
{
    dma->DMACHAN[channelNum].DMACTL |= DMA_DMACTL_DMAREQ_REQUEST;
}

__STATIC_INLINE void DL_DMA_setTrigger(DMA_Regs *dma, uint8_t channelNum,
    uint8_t trigger, DL_DMA_TRIGGER_TYPE triggerType)
{
    DL_Common_updateReg(&dma->DMATRIG[channelNum].DMATCTL,
        trigger | (uint32_t) triggerType,
        DMA_DMATCTL_DMATSEL_MASK | DMA_DMATCTL_DMATINT_MASK);
}

__STATIC_INLINE uint32_t DL_DMA_getTrigger(
    const DMA_Regs *dma, uint8_t channelNum)
{
    return (dma->DMATRIG[channelNum].DMATCTL & DMA_DMATCTL_DMATSEL_MASK);
}

__STATIC_INLINE DL_DMA_TRIGGER_TYPE DL_DMA_getTriggerType(
    const DMA_Regs *dma, uint8_t channelNum)
{
    uint32_t triggerType =
        (dma->DMATRIG[channelNum].DMATCTL & DMA_DMATCTL_DMATINT_MASK);

    return (DL_DMA_TRIGGER_TYPE)(triggerType);
}

__STATIC_INLINE void DL_DMA_setSrcAddr(
    DMA_Regs *dma, uint8_t channelNum, uint32_t srcAddr)
{
    dma->DMACHAN[channelNum].DMASA = srcAddr;
}

__STATIC_INLINE uint32_t DL_DMA_getSrcAddr(
    const DMA_Regs *dma, uint8_t channelNum)
{
    return dma->DMACHAN[channelNum].DMASA;
}

__STATIC_INLINE void DL_DMA_setDestAddr(
    DMA_Regs *dma, uint8_t channelNum, uint32_t destAddr)
{
    dma->DMACHAN[channelNum].DMADA = destAddr;
}

__STATIC_INLINE uint32_t DL_DMA_getDestAddr(
    const DMA_Regs *dma, uint8_t channelNum)
{
    return dma->DMACHAN[channelNum].DMADA;
}

__STATIC_INLINE void DL_DMA_setTransferSize(
    DMA_Regs *dma, uint8_t channelNum, uint16_t size)
{
    dma->DMACHAN[channelNum].DMASZ = size;
}

__STATIC_INLINE uint16_t DL_DMA_getTransferSize(
    const DMA_Regs *dma, uint8_t channelNum)
{
    return (uint16_t)(dma->DMACHAN[channelNum].DMASZ & DMA_DMASZ_SIZE_MASK);
}

__STATIC_INLINE void DL_DMA_setSrcIncrement(
    DMA_Regs *dma, uint8_t channelNum, DL_DMA_INCREMENT srcIncrement)
{
    DL_Common_updateReg(&dma->DMACHAN[channelNum].DMACTL,
        (uint32_t) srcIncrement, DMA_DMACTL_DMASRCINCR_MASK);
}

__STATIC_INLINE DL_DMA_INCREMENT DL_DMA_getSrcIncrement(
    const DMA_Regs *dma, uint8_t channelNum)
{
    uint32_t incrementAmount =
        (dma->DMACHAN[channelNum].DMACTL & DMA_DMACTL_DMASRCINCR_MASK);

    return (DL_DMA_INCREMENT)(incrementAmount);
}

__STATIC_INLINE void DL_DMA_setDestIncrement(
    DMA_Regs *dma, uint8_t channelNum, DL_DMA_INCREMENT destIncrement)
{
    /* Left shifted by 4 so the defines align with bitfield */
    DL_Common_updateReg(&dma->DMACHAN[channelNum].DMACTL,
        ((uint32_t) destIncrement) << 4, DMA_DMACTL_DMADSTINCR_MASK);
}

__STATIC_INLINE DL_DMA_INCREMENT DL_DMA_getDestIncrement(
    const DMA_Regs *dma, uint8_t channelNum)
{
    /* Right shifted by 4 to align with provided defines */
    uint32_t incrementAmount =
        (dma->DMACHAN[channelNum].DMACTL & DMA_DMACTL_DMADSTINCR_MASK) >> 4;

    return (DL_DMA_INCREMENT)(incrementAmount);
}

__STATIC_INLINE void DL_DMA_setSrcWidth(
    DMA_Regs *dma, uint8_t channelNum, DL_DMA_WIDTH srcWidth)
{
    DL_Common_updateReg(&dma->DMACHAN[channelNum].DMACTL, (uint32_t) srcWidth,
        DMA_DMACTL_DMASRCWDTH_MASK);
}

__STATIC_INLINE DL_DMA_WIDTH DL_DMA_getSrcWidth(
    const DMA_Regs *dma, uint8_t channelNum)
{
    uint32_t width =
        (dma->DMACHAN[channelNum].DMACTL & DMA_DMACTL_DMASRCWDTH_MASK);

    return (DL_DMA_WIDTH)(width);
}

__STATIC_INLINE void DL_DMA_setDestWidth(
    DMA_Regs *dma, uint8_t channelNum, DL_DMA_WIDTH destWidth)
{
    /* Left shifted by 4 to align with provided defines */
    DL_Common_updateReg(&dma->DMACHAN[channelNum].DMACTL,
        ((uint32_t) destWidth) << 4, DMA_DMACTL_DMADSTWDTH_MASK);
}

__STATIC_INLINE DL_DMA_WIDTH DL_DMA_getDestWidth(
    const DMA_Regs *dma, uint8_t channelNum)
{
    /* Right shifted by 4 to align with provided defines */
    uint32_t width =
        (dma->DMACHAN[channelNum].DMACTL & DMA_DMACTL_DMADSTWDTH_MASK) >> 4;

    return (DL_DMA_WIDTH)(width);
}
#ifdef DEVICE_HAS_DMA_FULL_CHANNEL

__STATIC_INLINE void DL_DMA_Full_Ch_setEarlyInterruptThreshold(DMA_Regs *dma,
    uint8_t channelNum, DL_DMA_EARLY_INTERRUPT_THRESHOLD threshold)
{
    DL_Common_updateReg(&dma->DMACHAN[channelNum].DMACTL, (uint32_t) threshold,
        DMA_DMACTL_DMAPREIRQ_MASK);
}

__STATIC_INLINE DL_DMA_EARLY_INTERRUPT_THRESHOLD
DL_DMA_Full_Ch_getEarlyInterruptThreshold(
    const DMA_Regs *dma, uint8_t channelNum)
{
    uint32_t threshold =
        dma->DMACHAN[channelNum].DMACTL & DMA_DMACTL_DMAPREIRQ_MASK;

    return (DL_DMA_EARLY_INTERRUPT_THRESHOLD)(threshold);
}
#endif /* DEVICE_HAS_DMA_FULL_CHANNEL */

__STATIC_INLINE void DL_DMA_enableInterrupt(
    DMA_Regs *dma, uint32_t interruptMask)
{
    dma->CPU_INT.IMASK |= interruptMask;
}

__STATIC_INLINE void DL_DMA_disableInterrupt(
    DMA_Regs *dma, uint32_t interruptMask)
{
    dma->CPU_INT.IMASK &= ~(interruptMask);
}

__STATIC_INLINE uint32_t DL_DMA_getEnabledInterrupts(
    const DMA_Regs *dma, uint32_t interruptMask)
{
    return (dma->CPU_INT.IMASK & interruptMask);
}

__STATIC_INLINE uint32_t DL_DMA_getEnabledInterruptStatus(
    const DMA_Regs *dma, uint32_t interruptMask)
{
    return (dma->CPU_INT.MIS & interruptMask);
}

__STATIC_INLINE uint32_t DL_DMA_getRawInterruptStatus(
    const DMA_Regs *dma, uint32_t interruptMask)
{
    return (dma->CPU_INT.RIS & interruptMask);
}

__STATIC_INLINE DL_DMA_EVENT_IIDX DL_DMA_getPendingInterrupt(
    const DMA_Regs *dma)
{
    return (DL_DMA_EVENT_IIDX) dma->CPU_INT.IIDX;
}

__STATIC_INLINE void DL_DMA_clearInterruptStatus(
    DMA_Regs *dma, uint32_t interruptMask)
{
    dma->CPU_INT.ICLR = interruptMask;
}

__STATIC_INLINE void DL_DMA_setPublisherChanID(
    DMA_Regs *dma, DL_DMA_PUBLISHER_INDEX index, uint8_t chanID)
{
    volatile uint32_t *pReg = &dma->FPUB_1;

    *(pReg + (uint32_t) index) = (chanID & DMA_FPUB_1_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_DMA_getPublisherChanID(
    DMA_Regs *dma, DL_DMA_PUBLISHER_INDEX index)
{
    volatile uint32_t *pReg = &dma->FPUB_1;

    return ((uint8_t)(*(pReg + (uint32_t) index) & DMA_FPUB_1_CHANID_MASK));
}

__STATIC_INLINE void DL_DMA_setSubscriberChanID(
    DMA_Regs *dma, DL_DMA_SUBSCRIBER_INDEX index, uint8_t chanID)
{
    volatile uint32_t *pReg = &dma->FSUB_0;

    *(pReg + (uint32_t) index) = (chanID & DMA_FSUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_DMA_getSubscriberChanID(
    DMA_Regs *dma, DL_DMA_SUBSCRIBER_INDEX index)
{
    volatile uint32_t *pReg = &dma->FSUB_0;

    return ((uint8_t)(*(pReg + (uint32_t) index) & DMA_FSUB_0_CHANID_MASK));
}

__STATIC_INLINE void DL_DMA_enableEvent(DMA_Regs *dma, uint32_t eventMask)
{
    dma->GEN_EVENT.IMASK |= (eventMask);
}

__STATIC_INLINE void DL_DMA_disableEvent(DMA_Regs *dma, uint32_t eventMask)
{
    dma->GEN_EVENT.IMASK &= ~(eventMask);
}

__STATIC_INLINE uint32_t DL_DMA_getEnabledEvents(
    const DMA_Regs *dma, uint32_t eventMask)
{
    return (dma->GEN_EVENT.IMASK & eventMask);
}

__STATIC_INLINE uint32_t DL_DMA_getEnabledEventStatus(
    const DMA_Regs *dma, uint32_t eventMask)
{
    return (dma->GEN_EVENT.MIS & ~(eventMask));
}

__STATIC_INLINE uint32_t DL_DMA_getRawEventsStatus(
    const DMA_Regs *dma, uint32_t eventMask)
{
    return (dma->GEN_EVENT.RIS & ~(eventMask));
}

__STATIC_INLINE void DL_DMA_clearEventsStatus(
    DMA_Regs *dma, uint32_t eventMask)
{
    dma->GEN_EVENT.ICLR |= (eventMask);
}

#ifdef DEVICE_HAS_AUTO_AND_GATHER

__STATIC_INLINE void DL_DMA_enableAutoEnable(
    DMA_Regs *dma, DL_DMA_AUTOEN mode, uint8_t channelNum)
{
    dma->DMACHAN[channelNum].DMACTL |= mode;
}

__STATIC_INLINE void DL_DMA_disableAutoEnable(
    DMA_Regs *dma, uint8_t channelNum)
{
    dma->DMACHAN[channelNum].DMACTL &= ~(DMA_DMACTL_DMAAUTOEN_MASK);
}

__STATIC_INLINE bool DL_DMA_isAutoEnableEnabled(
    const DMA_Regs *dma, uint8_t channelNum)
{
    return ((dma->DMACHAN[channelNum].DMACTL & DMA_DMACTL_DMAAUTOEN_MASK) !=
            DMA_DMACTL_DMAAUTOEN_DISABLE);
}
#endif /* DEVICE_HAS_AUTO_AND_GATHER*/

#ifdef __cplusplus
}
#endif

#endif /* ti_dl_dl_m0p_dma__include */