MSPM0L111X Driver Library  2.05.00.05
dl_aesadv.h
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32 /*!****************************************************************************
33  * @file dl_aesadv.h
34  * @brief Advanced Encryption Standard Advanced (AESADV) Driver Library
35  * @defgroup AESADV Advanced Encryption Standard Advanced (AESADV)
36  *
37  * @anchor ti_dl_dl_aesadv_Overview
38  * # Overview
39  *
40  * The AESADV DriverLib allows full configuration of the MSPM0 AESADV module.
41  * The AESADV accelerator module accelerates encryption and decryption
42  * operations in hardware based on the FIPS PUB 197 advanced encryption
43  * standard (AES).
44  *
45  * <hr>
46  ******************************************************************************/
50 #ifndef ti_dl_dl_aesadv__include
51 #define ti_dl_dl_aesadv__include
52 
53 #include <stdbool.h>
54 #include <stddef.h>
55 #include <stdint.h>
56 
57 #include <ti/devices/msp/msp.h>
58 #include <ti/driverlib/dl_common.h>
59 
60 #ifdef __MSPM0_HAS_AESADV__
61 
62 #ifdef __cplusplus
63 extern "C" {
64 #endif
65 
66 /* clang-format off */
67 
77 #define DL_AESADV_INTERRUPT_OUTPUT_READY \
78  (AESADV_CPU_INT_IMASK_OUTPUTRDY_SET)
79 
85 #define DL_AESADV_INTERRUPT_INPUT_READY \
86  (AESADV_CPU_INT_IMASK_INPUTRDY_SET)
87 
92 #define DL_AESADV_INTERRUPT_SAVED_OUTPUT_CONTEXT_READY \
93  (AESADV_CPU_INT_IMASK_SAVEDCNTXTRDY_SET)
94 
98 #define DL_AESADV_INTERRUPT_INPUT_CONTEXT_READY \
99  (AESADV_CPU_INT_IMASK_CNTXTRDY_SET)
100 
110 #define DL_AESADV_EVENT_DMA_DATA_INPUT_TRIGGER \
111  (AESADV_DMA_TRIG_DATAIN_IMASK_TRIG0_SET)
112 
116 #define DL_AESADV_EVENT_DMA_DATA_OUTPUT_TRIGGER \
117  (AESADV_DMA_TRIG_DATAOUT_IMASK_TRIG1_SET)
118 
124 #define DL_AESADV_MODE_MASK ((AESADV_CTRL_CBC_MASK) | \
125  (AESADV_CTRL_CTR_MASK) | (AESADV_CTRL_ICM_MASK) | \
126  (AESADV_CTRL_CFB_MASK) | (AESADV_CTRL_CBCMAC_MASK) | \
127  (AESADV_CTRL_GCM_MASK) | (AESADV_CTRL_CCM_MASK) | \
128  (AESADV_CTRL_OFB_GCM_CCM_CONT_MASK) | 0x02000000)
129 
130 /* TODO: create define once XCBC-MAC MASK defined in IPXACT */
131 
132 /* clang-format on */
133 
135 typedef enum {
137  DL_AESADV_IIDX_INPUT_CONTEXT_READY = AESADV_CPU_INT_IIDX_STAT_CNTXTRDY,
140  AESADV_CPU_INT_IIDX_STAT_SAVEDCNTXTRDY,
143  DL_AESADV_IIDX_INPUT_READY = AESADV_CPU_INT_IIDX_STAT_INPUTRDY,
146  DL_AESADV_IIDX_OUTPUT_READY = AESADV_CPU_INT_IIDX_STAT_OUTPUTRDY,
148  DL_AESADV_IIDX_DMA_INPUT_TRIGGER = AESADV_DMA_TRIG_DATAIN_IIDX_STAT_TRIG0,
151  AESADV_DMA_TRIG_DATAOUT_IIDX_STAT_TRIG1,
153 
155 typedef enum {
159  DL_AESADV_MODE_CBC = (AESADV_CTRL_CBC_ENABLE),
161  DL_AESADV_MODE_CTR = (AESADV_CTRL_CTR_ENABLE),
164  DL_AESADV_MODE_ICM = (AESADV_CTRL_ICM_ENABLE),
166  DL_AESADV_MODE_CFB = (AESADV_CTRL_CFB_ENABLE),
168  DL_AESADV_MODE_OFB = (AESADV_CTRL_OFB_GCM_CCM_CONT_OFB),
171  (0x02000000 |
172  AESADV_CTRL_CBC_ENABLE), /* TODO: add CMAC-define when given */
174  DL_AESADV_MODE_CBCMAC = (AESADV_CTRL_CBCMAC_ENABLE),
175  /* TODO: Update GCM values once new defines in place */
179  (AESADV_CTRL_GCM_FORCE_ZERO) | (AESADV_CTRL_CTR_ENABLE),
183  (AESADV_CTRL_GCM_LOAD_HASH_KEY) | (AESADV_CTRL_CTR_ENABLE),
187  (AESADV_CTRL_GCM_AUTONOMOUS) | (AESADV_CTRL_CTR_ENABLE),
189  DL_AESADV_MODE_GCM_GHASH_ONLY = (AESADV_CTRL_GCM_FORCE_ZERO),
191  DL_AESADV_MODE_CCM = (AESADV_CTRL_CCM_ENABLE) | (AESADV_CTRL_CTR_ENABLE),
193 
195 typedef enum {
197  DL_AESADV_KEY_SIZE_128_BIT = AESADV_CTRL_KEYSIZE_K128,
199  DL_AESADV_KEY_SIZE_256_BIT = AESADV_CTRL_KEYSIZE_K256,
201 
203 typedef enum {
205  DL_AESADV_DIR_ENCRYPT = AESADV_CTRL_DIR_ENCRYPT,
207  DL_AESADV_DIR_DECRYPT = AESADV_CTRL_DIR_DECRYPT,
208 } DL_AESADV_DIR;
209 
211 typedef enum {
213  DL_AESADV_CTR_WIDTH_32_BIT = AESADV_CTRL_CTR_WIDTH_CTR32,
215  DL_AESADV_CTR_WIDTH_64_BIT = AESADV_CTRL_CTR_WIDTH_CTR64,
217  DL_AESADV_CTR_WIDTH_96_BIT = AESADV_CTRL_CTR_WIDTH_CTR96,
219  DL_AESADV_CTR_WIDTH_128_BIT = AESADV_CTRL_CTR_WIDTH_CTR128,
221 
223 typedef enum {
224  DL_AESADV_FB_WIDTH_128 = AESADV_CTRL_CTR_WIDTH_CFB128,
226 
228 typedef enum {
230  DL_AESADV_CCM_CTR_WIDTH_2_BYTES = ((uint32_t) 1U << AESADV_CTRL_CCML_OFS),
232  DL_AESADV_CCM_CTR_WIDTH_3_BYTES = ((uint32_t) 2 << AESADV_CTRL_CCML_OFS),
234  DL_AESADV_CCM_CTR_WIDTH_4_BYTES = ((uint32_t) 3 << AESADV_CTRL_CCML_OFS),
236  DL_AESADV_CCM_CTR_WIDTH_5_BYTES = ((uint32_t) 4 << AESADV_CTRL_CCML_OFS),
238  DL_AESADV_CCM_CTR_WIDTH_6_BYTES = ((uint32_t) 5 << AESADV_CTRL_CCML_OFS),
240  DL_AESADV_CCM_CTR_WIDTH_7_BYTES = ((uint32_t) 6 << AESADV_CTRL_CCML_OFS),
242  DL_AESADV_CCM_CTR_WIDTH_8_BYTES = ((uint32_t) 7 << AESADV_CTRL_CCML_OFS),
244 
246 typedef enum {
248  DL_AESADV_CCM_TAG_WIDTH_1_BYTE = ((uint32_t) 0 << AESADV_CTRL_CCMM_OFS),
250  DL_AESADV_CCM_TAG_WIDTH_2_BYTES = ((uint32_t) 1 << AESADV_CTRL_CCMM_OFS),
252  DL_AESADV_CCM_TAG_WIDTH_3_BYTES = ((uint32_t) 2 << AESADV_CTRL_CCMM_OFS),
254  DL_AESADV_CCM_TAG_WIDTH_4_BYTES = ((uint32_t) 3 << AESADV_CTRL_CCMM_OFS),
256  DL_AESADV_CCM_TAG_WIDTH_5_BYTES = ((uint32_t) 4 << AESADV_CTRL_CCMM_OFS),
258  DL_AESADV_CCM_TAG_WIDTH_6_BYTES = ((uint32_t) 5 << AESADV_CTRL_CCMM_OFS),
260  DL_AESADV_CCM_TAG_WIDTH_7_BYTES = ((uint32_t) 6 << AESADV_CTRL_CCMM_OFS),
262  DL_AESADV_CCM_TAG_WIDTH_8_BYTES = ((uint32_t) 7 << AESADV_CTRL_CCMM_OFS),
264 
266 typedef enum {
272 
277 typedef struct {
282  DL_AESADV_DIR direction;
285  DL_AESADV_CTR_WIDTH ctr_ctrWidth;
287  DL_AESADV_FB_WIDTH cfb_fbWidth;
296  uint8_t *iv;
300  uint8_t *nonce;
303  uint8_t *k1;
306  uint8_t *k2;
314  uint32_t aadLength;
316 
326 __STATIC_INLINE void DL_AESADV_enablePower(AESADV_Regs *aesadv)
327 {
328  aesadv->GPRCM.PWREN =
329  (AESADV_PWREN_KEY_UNLOCK_W | AESADV_PWREN_ENABLE_ENABLE);
330 }
331 
342 __STATIC_INLINE void DL_AESADV_disablePower(AESADV_Regs *aesadv)
343 {
344  aesadv->GPRCM.PWREN =
345  (AESADV_PWREN_KEY_UNLOCK_W | AESADV_PWREN_ENABLE_DISABLE);
346 }
347 
364 __STATIC_INLINE bool DL_AESADV_isPowerEnabled(const AESADV_Regs *aesadv)
365 {
366  return ((aesadv->GPRCM.PWREN & AESADV_PWREN_ENABLE_MASK) ==
367  AESADV_PWREN_ENABLE_ENABLE);
368 }
369 
375 __STATIC_INLINE void DL_AESADV_reset(AESADV_Regs *aesadv)
376 {
377  aesadv->GPRCM.RSTCTL =
378  (AESADV_RSTCTL_KEY_UNLOCK_W | AESADV_RSTCTL_RESETSTKYCLR_CLR |
379  AESADV_RSTCTL_RESETASSERT_ASSERT);
380 }
381 
390 __STATIC_INLINE bool DL_AESADV_isReset(const AESADV_Regs *aesadv)
391 {
392  return ((aesadv->GPRCM.STAT & AESADV_STAT_RESETSTKY_MASK) ==
393  AESADV_STAT_RESETSTKY_RESET);
394 }
395 
404 __STATIC_INLINE bool DL_AESADV_isOutputReady(const AESADV_Regs *aesadv)
405 {
406  return ((aesadv->CTRL & AESADV_CTRL_OUTPUT_RDY_MASK) ==
407  AESADV_CTRL_OUTPUT_RDY_READY);
408 }
409 
418 __STATIC_INLINE bool DL_AESADV_isInputReady(const AESADV_Regs *aesadv)
419 {
420  return ((aesadv->CTRL & AESADV_CTRL_INPUT_RDY_MASK) ==
421  AESADV_CTRL_INPUT_RDY_EMPTY);
422 }
423 
432 __STATIC_INLINE void DL_AESADV_setDirection(
433  AESADV_Regs *aesadv, DL_AESADV_DIR direction)
434 {
436  &aesadv->CTRL, (uint32_t) direction, AESADV_CTRL_DIR_MASK);
437 }
438 
446 __STATIC_INLINE DL_AESADV_DIR DL_AESADV_getDirection(const AESADV_Regs *aesadv)
447 {
448  uint32_t direction = (aesadv->CTRL & AESADV_CTRL_DIR_MASK);
449 
450  return (DL_AESADV_DIR)(direction);
451 }
452 
459 __STATIC_INLINE void DL_AESADV_setKeySize(
460  AESADV_Regs *aesadv, DL_AESADV_KEY_SIZE size)
461 {
463  &aesadv->CTRL, (uint32_t) size, AESADV_CTRL_KEYSIZE_MASK);
464 }
465 
473 __STATIC_INLINE DL_AESADV_KEY_SIZE DL_AESADV_getKeySize(
474  const AESADV_Regs *aesadv)
475 {
476  uint32_t keySize = (aesadv->CTRL & AESADV_CTRL_KEYSIZE_MASK);
477 
478  return (DL_AESADV_KEY_SIZE)(keySize);
479 }
480 
496 __STATIC_INLINE void DL_AESADV_setMode(
497  AESADV_Regs *aesadv, DL_AESADV_MODE mode)
498 {
499  DL_Common_updateReg(&aesadv->CTRL, (uint32_t) mode, DL_AESADV_MODE_MASK);
500 }
501 
515 __STATIC_INLINE DL_AESADV_MODE DL_AESADV_getMode(const AESADV_Regs *aesadv)
516 {
517  uint32_t mode = (aesadv->CTRL & DL_AESADV_MODE_MASK);
518  return (DL_AESADV_MODE)(mode);
519 }
520 
530 __STATIC_INLINE void DL_AESADV_setFeedbackWidth(
531  AESADV_Regs *aesadv, DL_AESADV_FB_WIDTH fbWidth)
532 {
534  &aesadv->CTRL, (uint32_t) fbWidth, AESADV_CTRL_CTR_WIDTH_MASK);
535 }
536 
546 __STATIC_INLINE DL_AESADV_FB_WIDTH DL_AESADV_getFeedbackWidth(
547  const AESADV_Regs *aesadv)
548 {
549  uint32_t fbWidth = (aesadv->CTRL & AESADV_CTRL_CTR_WIDTH_MASK);
550 
551  return (DL_AESADV_FB_WIDTH)(fbWidth);
552 }
553 
568 __STATIC_INLINE void DL_AESADV_setCounterWidth(
569  AESADV_Regs *aesadv, DL_AESADV_CTR_WIDTH ctrWidth)
570 {
572  &aesadv->CTRL, (uint32_t) ctrWidth, AESADV_CTRL_CTR_WIDTH_MASK);
573 }
574 
584 __STATIC_INLINE DL_AESADV_CTR_WIDTH DL_AESADV_getCounterWidth(
585  const AESADV_Regs *aesadv)
586 {
587  uint32_t ctrWidth = (aesadv->CTRL & AESADV_CTRL_CTR_WIDTH_MASK);
588 
589  return (DL_AESADV_CTR_WIDTH)(ctrWidth);
590 }
591 
621 __STATIC_INLINE void DL_AESADV_setCCMCounterWidth(
622  AESADV_Regs *aesadv, DL_AESADV_CCM_CTR_WIDTH ccm_ctrWidth)
623 {
625  &aesadv->CTRL, (uint32_t) ccm_ctrWidth, AESADV_CTRL_CCML_MASK);
626 }
627 
638  const AESADV_Regs *aesadv)
639 {
640  uint32_t ccm_ctrWidth = (aesadv->CTRL & AESADV_CTRL_CCML_MASK);
641 
642  return (DL_AESADV_CCM_CTR_WIDTH)(ccm_ctrWidth);
643 }
644 
658 __STATIC_INLINE void DL_AESADV_setCCMTagWidth(
659  AESADV_Regs *aesadv, DL_AESADV_CCM_TAG_WIDTH ccm_tagWidth)
660 {
662  &aesadv->CTRL, (uint32_t) ccm_tagWidth, AESADV_CTRL_CCMM_MASK);
663 }
664 
675  const AESADV_Regs *aesadv)
676 {
677  uint32_t ccm_tagWidth = (aesadv->CTRL & AESADV_CTRL_CCMM_MASK);
678 
679  return (DL_AESADV_CCM_TAG_WIDTH)(ccm_tagWidth);
680 }
681 
700  AESADV_Regs *aesadv)
701 {
702  aesadv->CTRL |= AESADV_CTRL_GET_DIGEST_ENABLE;
703 }
704 
720 __STATIC_INLINE void DL_AESADV_resumeAADPhase(
721  AESADV_Regs *aesadv, DL_AESADV_MODE mode)
722 {
723  DL_Common_updateReg(&aesadv->CTRL,
724  (((uint32_t) mode) |
725  ((uint32_t) AESADV_CTRL_OFB_GCM_CCM_CONT_GCM_CCM_CONTINUE)),
726  (DL_AESADV_MODE_MASK | AESADV_CTRL_OFB_GCM_CCM_CONT_MASK));
727 }
728 
745 __STATIC_INLINE void DL_AESADV_resumeDataPhase(
746  AESADV_Regs *aesadv, DL_AESADV_MODE mode)
747 {
748  DL_Common_updateReg(&aesadv->CTRL,
749  ((uint32_t) mode | AESADV_CTRL_GCM_CONT_ENABLE),
750  ((uint32_t) DL_AESADV_MODE_MASK | AESADV_CTRL_GCM_CONT_MASK));
751 }
752 
770 __STATIC_INLINE void DL_AESADV_enableSavedOutputContext(AESADV_Regs *aesadv)
771 {
772  aesadv->CTRL |= AESADV_CTRL_SAVE_CNTXT_ENABLE;
773 }
774 
791 __STATIC_INLINE void DL_AESADV_disableSavedOutputContext(AESADV_Regs *aesadv)
792 {
793  aesadv->CTRL &= ~(AESADV_CTRL_SAVE_CNTXT_ENABLE);
794 }
795 
807  const AESADV_Regs *aesadv)
808 {
809  return ((aesadv->CTRL & AESADV_CTRL_SAVE_CNTXT_MASK) ==
810  AESADV_CTRL_SAVE_CNTXT_ENABLE);
811 }
812 
828  const AESADV_Regs *aesadv)
829 {
830  return ((aesadv->CTRL & AESADV_CTRL_SAVED_CNTXT_RDY_MASK) ==
831  AESADV_CTRL_SAVED_CNTXT_RDY_READY);
832 }
833 
851  const AESADV_Regs *aesadv)
852 {
853  return ((aesadv->CTRL & AESADV_CTRL_CNTXT_RDY_MASK) ==
854  AESADV_CTRL_CNTXT_RDY_READY);
855 }
856 
883 __STATIC_INLINE void DL_AESADV_setLowerCryptoLength(
884  AESADV_Regs *aesadv, uint32_t lowerLength)
885 {
886  aesadv->C_LENGTH_0 = lowerLength;
887 }
888 
906 __STATIC_INLINE void DL_AESADV_setUpperCryptoLength(
907  AESADV_Regs *aesadv, uint32_t upperLength)
908 {
909  aesadv->C_LENGTH_1 = upperLength & 0x1FFFFFFFU;
910 }
911 
927 __STATIC_INLINE void DL_AESADV_setAADLength(
928  AESADV_Regs *aesadv, uint32_t aadLength)
929 {
930  aesadv->AAD_LENGTH = aadLength;
931 }
932 
943 __STATIC_INLINE void DL_AESADV_enableDMAOperation(AESADV_Regs *aesadv)
944 {
945  aesadv->DMA_HS = (AESADV_DMA_HS_DMA_DATA_ACK_DMA_ENABLE);
946 }
947 
956 __STATIC_INLINE void DL_AESADV_disableDMAOperation(AESADV_Regs *aesadv)
957 {
958  aesadv->DMA_HS = (AESADV_DMA_HS_DMA_DATA_ACK_DMA_DISABLE);
959 }
960 
969 __STATIC_INLINE bool DL_AESADV_isDMAOperationEnabled(const AESADV_Regs *aesadv)
970 {
971  return ((aesadv->DMA_HS & AESADV_DMA_HS_DMA_DATA_ACK_MASK) ==
972  AESADV_DMA_HS_DMA_DATA_ACK_DMA_ENABLE);
973 }
974 
986 __STATIC_INLINE bool DL_AESADV_isUserKeyWriteEnabled(const AESADV_Regs *aesadv)
987 {
988  return ((aesadv->STATUS & AESADV_STATUS_KEYWR_MASK) ==
989  AESADV_STATUS_KEYWR_ENABLED);
990 }
991 
1007 DL_AESADV_STATUS DL_AESADV_setKey(
1008  AESADV_Regs *aesadv, const uint8_t *key, DL_AESADV_KEY_SIZE keySize);
1009 
1020 void DL_AESADV_setKeyAligned(AESADV_Regs *aesadv, const uint32_t *keyAligned,
1021  DL_AESADV_KEY_SIZE keySize);
1022 
1040 DL_AESADV_STATUS DL_AESADV_setGCMHashKey(
1041  AESADV_Regs *aesadv, const uint8_t *hashKey);
1042 
1057  AESADV_Regs *aesadv, const uint32_t *hashKeyAligned);
1058 
1076 DL_AESADV_STATUS DL_AESADV_setSecondKey(
1077  AESADV_Regs *aesadv, const uint8_t *secondKey);
1078 
1093  AESADV_Regs *aesadv, const uint32_t *secondKeyAligned);
1094 
1112 DL_AESADV_STATUS DL_AESADV_setThirdKey(
1113  AESADV_Regs *aesadv, const uint8_t *thirdKey);
1114 
1129  AESADV_Regs *aesadv, const uint32_t *thirdKeyAligned);
1130 
1150 DL_AESADV_STATUS DL_AESADV_loadIntermediateTAG(
1151  AESADV_Regs *aesadv, const uint8_t *tag);
1152 
1168  AESADV_Regs *aesadv, const uint32_t *tagAligned);
1169 
1194 DL_AESADV_STATUS DL_AESADV_loadInitializationVector(
1195  AESADV_Regs *aesadv, const uint8_t *iv);
1196 
1216  AESADV_Regs *aesadv, const uint32_t *ivAligned);
1217 
1236 DL_AESADV_STATUS DL_AESADV_readInitializationVector(
1237  AESADV_Regs *aesadv, const uint8_t *iv);
1238 
1253  AESADV_Regs *aesadv, uint32_t *ivAligned);
1254 
1304  AESADV_Regs *aesadv, uint8_t *nonce, DL_AESADV_CCM_CTR_WIDTH ctrWidth);
1305 
1331 DL_AESADV_STATUS DL_AESADV_loadInputData(
1332  AESADV_Regs *aesadv, const uint8_t *data);
1333 
1354  AESADV_Regs *aesadv, const uint32_t *dataAligned);
1355 
1378 DL_AESADV_STATUS DL_AESADV_readOutputData(
1379  const AESADV_Regs *aesadv, const uint8_t *data);
1380 
1399  const AESADV_Regs *aesadv, uint32_t *dataAligned);
1400 
1422 DL_AESADV_STATUS DL_AESADV_readTAG(
1423  const AESADV_Regs *aesadv, const uint8_t *tag);
1424 
1439 void DL_AESADV_readTAGAligned(const AESADV_Regs *aesadv, uint32_t *tagAligned);
1440 
1451 __STATIC_INLINE void DL_AESADV_forceInputDataAvailable(AESADV_Regs *aesadv)
1452 {
1453  aesadv->FORCE_IN_AV = 0x0123CAFE;
1454 }
1455 
1466 __STATIC_INLINE void DL_AESADV_setCCMAlignWord(
1467  AESADV_Regs *aesadv, uint32_t alignWord)
1468 {
1469  aesadv->CCM_ALN_WRD = alignWord;
1470 }
1471 
1482 __STATIC_INLINE uint32_t DL_AESADV_getCCMAlignWord(const AESADV_Regs *aesadv)
1483 {
1484  return (aesadv->CCM_ALN_WRD);
1485 }
1486 
1503 __STATIC_INLINE void DL_AESADV_setLowerBlockCount(
1504  AESADV_Regs *aesadv, uint32_t lowerBlockCount)
1505 {
1506  aesadv->BLK_CNT0 = lowerBlockCount;
1507 }
1508 
1523 __STATIC_INLINE uint32_t DL_AESADV_getLowerBlockCount(
1524  const AESADV_Regs *aesadv)
1525 {
1526  return aesadv->BLK_CNT0;
1527 }
1528 
1545 __STATIC_INLINE void DL_AESADV_setUpperBlockCount(
1546  AESADV_Regs *aesadv, uint32_t upperBlockCount)
1547 {
1548  aesadv->BLK_CNT1 = (upperBlockCount & 0x01FFFFFFU);
1549 }
1550 
1565 __STATIC_INLINE uint32_t DL_AESADV_getUpperBlockCount(
1566  const AESADV_Regs *aesadv)
1567 {
1568  return (aesadv->BLK_CNT1 & 0x01FFFFFFU);
1569 }
1570 
1578 __STATIC_INLINE void DL_AESADV_enableInterrupt(
1579  AESADV_Regs *aesadv, uint32_t interruptMask)
1580 {
1581  aesadv->CPU_INT.IMASK |= interruptMask;
1582 }
1583 
1592 __STATIC_INLINE void DL_AESADV_disableInterrupt(
1593  AESADV_Regs *aesadv, uint32_t interruptMask)
1594 {
1595  aesadv->CPU_INT.IMASK &= ~(interruptMask);
1596 }
1597 
1610 __STATIC_INLINE uint32_t DL_AESADV_getEnabledInterrupts(
1611  const AESADV_Regs *aesadv, uint32_t interruptMask)
1612 {
1613  return (aesadv->CPU_INT.IMASK & interruptMask);
1614 }
1615 
1633 __STATIC_INLINE uint32_t DL_AESADV_getEnabledInterruptStatus(
1634  const AESADV_Regs *aesadv, uint32_t interruptMask)
1635 {
1636  return (aesadv->CPU_INT.MIS & interruptMask);
1637 }
1638 
1654 __STATIC_INLINE uint32_t DL_AESADV_getRawInterruptStatus(
1655  const AESADV_Regs *aesadv, uint32_t interruptMask)
1656 {
1657  return (aesadv->CPU_INT.RIS & interruptMask);
1658 }
1659 
1672 __STATIC_INLINE DL_AESADV_IIDX DL_AESADV_getPendingInterrupt(
1673  const AESADV_Regs *aesadv)
1674 {
1675  return ((DL_AESADV_IIDX) aesadv->CPU_INT.IIDX);
1676 }
1677 
1686 __STATIC_INLINE void DL_AESADV_clearInterruptStatus(
1687  AESADV_Regs *aesadv, uint32_t interruptMask)
1688 {
1689  aesadv->CPU_INT.ICLR = interruptMask;
1690 }
1691 
1698 __STATIC_INLINE void DL_AESADV_enableDMAInputTriggerEvent(AESADV_Regs *aesadv)
1699 {
1700  aesadv->DMA_TRIG_DATAIN.IMASK |= DL_AESADV_EVENT_DMA_DATA_INPUT_TRIGGER;
1701 }
1702 
1709 __STATIC_INLINE void DL_AESADV_enableDMAOutputTriggerEvent(AESADV_Regs *aesadv)
1710 {
1711  aesadv->DMA_TRIG_DATAOUT.IMASK |= DL_AESADV_EVENT_DMA_DATA_OUTPUT_TRIGGER;
1712 }
1713 
1719 __STATIC_INLINE void DL_AESADV_disableDMAInputTriggerEvent(AESADV_Regs *aesadv)
1720 {
1721  aesadv->DMA_TRIG_DATAIN.IMASK &= ~(DL_AESADV_EVENT_DMA_DATA_INPUT_TRIGGER);
1722 }
1723 
1730  AESADV_Regs *aesadv)
1731 {
1732  aesadv->DMA_TRIG_DATAOUT.IMASK &=
1734 }
1735 
1748  const AESADV_Regs *aesadv)
1749 {
1750  return (aesadv->DMA_TRIG_DATAIN.IMASK &
1752 }
1753 
1766  const AESADV_Regs *aesadv)
1767 {
1768  return (aesadv->DMA_TRIG_DATAOUT.IMASK &
1770 }
1771 
1788  const AESADV_Regs *aesadv)
1789 {
1790  return (
1791  aesadv->DMA_TRIG_DATAIN.MIS & DL_AESADV_EVENT_DMA_DATA_INPUT_TRIGGER);
1792 }
1793 
1810  const AESADV_Regs *aesadv)
1811 {
1812  return (aesadv->DMA_TRIG_DATAOUT.MIS &
1814 }
1815 
1831  const AESADV_Regs *aesadv)
1832 {
1833  return (
1834  aesadv->DMA_TRIG_DATAIN.RIS & DL_AESADV_EVENT_DMA_DATA_INPUT_TRIGGER);
1835 }
1836 
1852  const AESADV_Regs *aesadv)
1853 {
1854  return (aesadv->DMA_TRIG_DATAOUT.RIS &
1856 }
1857 
1868 __STATIC_INLINE DL_AESADV_IIDX DL_AESADV_getPendingDMAInputTriggerEvent(
1869  const AESADV_Regs *aesadv)
1870 {
1871  uint32_t eventIIDX = aesadv->DMA_TRIG_DATAIN.IIDX;
1872 
1873  return (DL_AESADV_IIDX) eventIIDX;
1874 }
1875 
1886 __STATIC_INLINE DL_AESADV_IIDX DL_AESADV_getPendingDMAOutputTriggerEvent(
1887  const AESADV_Regs *aesadv)
1888 {
1889  uint32_t eventIIDX = aesadv->DMA_TRIG_DATAOUT.IIDX;
1890 
1891  return (DL_AESADV_IIDX)(eventIIDX);
1892 }
1893 
1900  AESADV_Regs *aesadv)
1901 {
1902  aesadv->DMA_TRIG_DATAIN.ICLR = DL_AESADV_EVENT_DMA_DATA_INPUT_TRIGGER;
1903 }
1904 
1911  AESADV_Regs *aesadv)
1912 {
1913  aesadv->DMA_TRIG_DATAOUT.ICLR = DL_AESADV_EVENT_DMA_DATA_OUTPUT_TRIGGER;
1914 }
1915 
1932 __STATIC_INLINE uintptr_t DL_AESADV_getDATAINAddr(const AESADV_Regs *aesadv)
1933 {
1934  return ((uintptr_t) &aesadv->DATA0);
1935 }
1936 
1953 __STATIC_INLINE uintptr_t DL_AESADV_getDATAOUTAddr(const AESADV_Regs *aesadv)
1954 {
1955  return ((uintptr_t) &aesadv->DATA0);
1956 }
1957 
1973 void DL_AESADV_initECB(AESADV_Regs *aesadv, const DL_AESADV_Config *config);
1974 
1991 void DL_AESADV_initCBC(AESADV_Regs *aesadv, const DL_AESADV_Config *config);
1992 
2009 void DL_AESADV_initCFB(AESADV_Regs *aesadv, const DL_AESADV_Config *config);
2010 
2027 void DL_AESADV_initOFB(AESADV_Regs *aesadv, const DL_AESADV_Config *config);
2028 
2046 void DL_AESADV_initCTR(AESADV_Regs *aesadv, const DL_AESADV_Config *config);
2047 
2065 void DL_AESADV_initICM(AESADV_Regs *aesadv, const DL_AESADV_Config *config);
2066 
2089 void DL_AESADV_initCMAC(AESADV_Regs *aesadv, const DL_AESADV_Config *config);
2090 
2108 void DL_AESADV_initCBCMAC(AESADV_Regs *aesadv, const DL_AESADV_Config *config);
2109 
2134 void DL_AESADV_initGCM(AESADV_Regs *aesadv, const DL_AESADV_Config *config);
2135 
2157 void DL_AESADV_initCCM(AESADV_Regs *aesadv, DL_AESADV_Config *config);
2158 
2159 #ifdef __cplusplus
2160 }
2161 #endif
2162 
2163 #endif /* __MSPM0_HAS_AESADV__ */
2164 
2165 #endif /* ti_dl_dl_aesadv__include */
2166 
__STATIC_INLINE bool DL_AESADV_isUserKeyWriteEnabled(const AESADV_Regs *aesadv)
Returns if User Writes to the Key Registers on the AESADV are allowed.
Definition: dl_aesadv.h:986
__STATIC_INLINE bool DL_AESADV_isReset(const AESADV_Regs *aesadv)
Returns if AESADV module was reset.
Definition: dl_aesadv.h:390
__STATIC_INLINE void DL_AESADV_resumeDataPhase(AESADV_Regs *aesadv, DL_AESADV_MODE mode)
Resume GCM or CCM operation in the Data phase.
Definition: dl_aesadv.h:745
Definition: dl_aesadv.h:232
DL_AESADV_STATUS DL_AESADV_loadInputData(AESADV_Regs *aesadv, const uint8_t *data)
loads 128 bits (4 words) of input data
void DL_AESADV_setGCMHashKeyAligned(AESADV_Regs *aesadv, const uint32_t *hashKeyAligned)
set the hash key
__STATIC_INLINE void DL_Common_updateReg(volatile uint32_t *reg, uint32_t val, uint32_t mask)
Writes value to specified register - retaining bits unaffected by mask.
Definition: dl_common.h:63
__STATIC_INLINE void DL_AESADV_setAADLength(AESADV_Regs *aesadv, uint32_t aadLength)
Sets the length of additional authentication data (AAD)
Definition: dl_aesadv.h:927
__STATIC_INLINE uint32_t DL_AESADV_getLowerBlockCount(const AESADV_Regs *aesadv)
Gets the lower 32-bits of the data blocks remaining in an operation.
Definition: dl_aesadv.h:1523
Definition: dl_aesadv.h:234
__STATIC_INLINE DL_AESADV_IIDX DL_AESADV_getPendingDMAInputTriggerEvent(const AESADV_Regs *aesadv)
Get highest priority pending DMA input trigger event.
Definition: dl_aesadv.h:1868
Definition: dl_aesadv.h:213
__STATIC_INLINE void DL_AESADV_haltOperationAndGenerateDigest(AESADV_Regs *aesadv)
Halt operation and generate intermediate Digest for CCM/GCM.
Definition: dl_aesadv.h:699
uint8_t * k2
Definition: dl_aesadv.h:306
__STATIC_INLINE void DL_AESADV_disableDMAOperation(AESADV_Regs *aesadv)
Disables DMA Operation for the AESADV module.
Definition: dl_aesadv.h:956
__STATIC_INLINE bool DL_AESADV_isSavedOutputContextReady(const AESADV_Regs *aesadv)
Returns whether additional output context is available to be read.
Definition: dl_aesadv.h:827
__STATIC_INLINE void DL_AESADV_enablePower(AESADV_Regs *aesadv)
Enables the Peripheral Write Enable (PWREN) register for the AESADV.
Definition: dl_aesadv.h:326
__STATIC_INLINE void DL_AESADV_setFeedbackWidth(AESADV_Regs *aesadv, DL_AESADV_FB_WIDTH fbWidth)
Sets the feedback width of the AESADV peripheral.
Definition: dl_aesadv.h:530
Definition: dl_aesadv.h:164
__STATIC_INLINE DL_AESADV_IIDX DL_AESADV_getPendingInterrupt(const AESADV_Regs *aesadv)
Get highest priority pending AESADV interrupt.
Definition: dl_aesadv.h:1672
DL_AESADV_STATUS DL_AESADV_setThirdKey(AESADV_Regs *aesadv, const uint8_t *thirdKey)
Loads the CBC-MAC third key.
DL_AESADV_MODE
Definition: dl_aesadv.h:155
Definition: dl_aesadv.h:191
Definition: dl_aesadv.h:150
Definition: dl_aesadv.h:207
Definition: dl_aesadv.h:270
Definition: dl_aesadv.h:254
__STATIC_INLINE void DL_AESADV_setCCMCounterWidth(AESADV_Regs *aesadv, DL_AESADV_CCM_CTR_WIDTH ccm_ctrWidth)
Sets the CCM counter width of the AESADV peripheral.
Definition: dl_aesadv.h:621
__STATIC_INLINE void DL_AESADV_enableDMAOperation(AESADV_Regs *aesadv)
Enables DMA Operation for the AESADV module.
Definition: dl_aesadv.h:943
Definition: dl_aesadv.h:250
DL_AESADV_FB_WIDTH
Definition: dl_aesadv.h:223
DL_AESADV_STATUS DL_AESADV_loadInitializationVector(AESADV_Regs *aesadv, const uint8_t *iv)
Loads the 128-bit initialization vector to the AESADV module.
Definition: dl_aesadv.h:166
__STATIC_INLINE bool DL_AESADV_isInputContextWriteable(const AESADV_Regs *aesadv)
Returns whether the input context can be written by the application.
Definition: dl_aesadv.h:850
__STATIC_INLINE void DL_AESADV_enableInterrupt(AESADV_Regs *aesadv, uint32_t interruptMask)
Enable AESADV interrupts.
Definition: dl_aesadv.h:1578
uint32_t aadLength
Definition: dl_aesadv.h:314
Definition: dl_aesadv.h:268
Definition: dl_aesadv.h:248
Definition: dl_aesadv.h:197
uint8_t * nonce
Definition: dl_aesadv.h:300
void DL_AESADV_initCFB(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
Initializes the engine in the Cipher Feedback (CFB) mode.
Configuration structure for the AESADV module. It contains the superset of configurable information f...
Definition: dl_aesadv.h:277
void DL_AESADV_initECB(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
Initializes the engine in the Electronic Codebook (ECB) mode.
__STATIC_INLINE DL_AESADV_DIR DL_AESADV_getDirection(const AESADV_Regs *aesadv)
Returns the direction of the AESADV peripheral (encrypt/decrypt)
Definition: dl_aesadv.h:446
__STATIC_INLINE void DL_AESADV_disableInterrupt(AESADV_Regs *aesadv, uint32_t interruptMask)
Disable AESADV interrupts.
Definition: dl_aesadv.h:1592
__STATIC_INLINE DL_AESADV_CCM_CTR_WIDTH DL_AESADV_getCCMCounterWidth(const AESADV_Regs *aesadv)
Returns the current CCM-specific counter width.
Definition: dl_aesadv.h:637
Definition: dl_aesadv.h:161
uint8_t * k1
Definition: dl_aesadv.h:303
__STATIC_INLINE uintptr_t DL_AESADV_getDATAINAddr(const AESADV_Regs *aesadv)
Returns the address of the AESADV input data register.
Definition: dl_aesadv.h:1932
void DL_AESADV_readInitializationVectorAligned(AESADV_Regs *aesadv, uint32_t *ivAligned)
Reads the 128-bit initialization vector from the AES Module.
__STATIC_INLINE uint32_t DL_AESADV_getEnabledDMAOutputTriggerEvent(const AESADV_Regs *aesadv)
Check if the DMA output trigger event is enabled.
Definition: dl_aesadv.h:1765
__STATIC_INLINE void DL_AESADV_clearInterruptStatus(AESADV_Regs *aesadv, uint32_t interruptMask)
Clear pending AESADV Interrupts.
Definition: dl_aesadv.h:1686
__STATIC_INLINE void DL_AESADV_setLowerBlockCount(AESADV_Regs *aesadv, uint32_t lowerBlockCount)
Sets the lower 32-bits of the data blocks remaining in an operation.
Definition: dl_aesadv.h:1503
__STATIC_INLINE void DL_AESADV_setCCMTagWidth(AESADV_Regs *aesadv, DL_AESADV_CCM_TAG_WIDTH ccm_tagWidth)
Sets the CCM authentication tag width of the AESADV peripheral.
Definition: dl_aesadv.h:658
__STATIC_INLINE void DL_AESADV_enableDMAInputTriggerEvent(AESADV_Regs *aesadv)
Enables DMA input trigger to publish AESADV write requests to the DMA.
Definition: dl_aesadv.h:1698
DL_AESADV_STATUS DL_AESADV_setSecondKey(AESADV_Regs *aesadv, const uint8_t *secondKey)
Loads the CBC-MAC second key.
Definition: dl_aesadv.h:236
Definition: dl_aesadv.h:189
void DL_AESADV_readTAGAligned(const AESADV_Regs *aesadv, uint32_t *tagAligned)
reads 128-bit output tag at the conclusion of operation/halt
DL_AESADV_STATUS DL_AESADV_readInitializationVector(AESADV_Regs *aesadv, const uint8_t *iv)
Reads the 128-bit initialization vector from the AES Module.
DL_AESADV_STATUS DL_AESADV_setGCMHashKey(AESADV_Regs *aesadv, const uint8_t *hashKey)
set the hash key
Definition: dl_aesadv.h:170
DL_AESADV_CTR_WIDTH ctr_ctrWidth
Definition: dl_aesadv.h:285
__STATIC_INLINE uint32_t DL_AESADV_getCCMAlignWord(const AESADV_Regs *aesadv)
Get the CCM AAD align data word.
Definition: dl_aesadv.h:1482
__STATIC_INLINE uint32_t DL_AESADV_getEnabledInterruptStatus(const AESADV_Regs *aesadv, uint32_t interruptMask)
Check interrupt flag of enabled AESADV interrupts.
Definition: dl_aesadv.h:1633
Definition: dl_aesadv.h:157
__STATIC_INLINE void DL_AESADV_setCCMAlignWord(AESADV_Regs *aesadv, uint32_t alignWord)
Set the CCM AAD align data word.
Definition: dl_aesadv.h:1466
Definition: dl_aesadv.h:217
__STATIC_INLINE DL_AESADV_CTR_WIDTH DL_AESADV_getCounterWidth(const AESADV_Regs *aesadv)
Returns the current counter width.
Definition: dl_aesadv.h:584
DL_AESADV_CCM_CTR_WIDTH
Definition: dl_aesadv.h:228
DriverLib Common APIs.
__STATIC_INLINE void DL_AESADV_disableSavedOutputContext(AESADV_Regs *aesadv)
Disables the storage and return of a tag or result IV.
Definition: dl_aesadv.h:791
__STATIC_INLINE void DL_AESADV_enableSavedOutputContext(AESADV_Regs *aesadv)
Enables the storage and return of a tag or result IV.
Definition: dl_aesadv.h:770
Definition: dl_aesadv.h:143
Definition: dl_aesadv.h:182
__STATIC_INLINE void DL_AESADV_disableDMAOutputTriggerEvent(AESADV_Regs *aesadv)
Disable DMA output trigger event.
Definition: dl_aesadv.h:1729
__STATIC_INLINE void DL_AESADV_setDirection(AESADV_Regs *aesadv, DL_AESADV_DIR direction)
Sets the direction of the engine (encrypt/decrypt)
Definition: dl_aesadv.h:432
Definition: dl_aesadv.h:186
void DL_AESADV_initOFB(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
Initializes the engine in the Output Feedback (OFB) mode.
__STATIC_INLINE uint32_t DL_AESADV_getEnabledInterrupts(const AESADV_Regs *aesadv, uint32_t interruptMask)
Check if AES Ready interrupt is enabled.
Definition: dl_aesadv.h:1610
__STATIC_INLINE uint32_t DL_AESADV_getRawInterruptStatus(const AESADV_Regs *aesadv, uint32_t interruptMask)
Check interrupt flag of any AESADV interrupts.
Definition: dl_aesadv.h:1654
Definition: dl_aesadv.h:174
Definition: dl_aesadv.h:205
uint8_t * iv
Definition: dl_aesadv.h:296
void DL_AESADV_initCBC(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
Initializes the engine in the Cipher-Block Chaining (CBC) mode.
__STATIC_INLINE bool DL_AESADV_isInputReady(const AESADV_Regs *aesadv)
Returns if the input buffer is empty, and more data can be written.
Definition: dl_aesadv.h:418
void DL_AESADV_initCCM(AESADV_Regs *aesadv, DL_AESADV_Config *config)
Initializes the engine in the Counter & CBC-MAC (CCM)mode.
Definition: dl_aesadv.h:242
DL_AESADV_CCM_TAG_WIDTH ccm_tagWidth
Definition: dl_aesadv.h:294
__STATIC_INLINE void DL_AESADV_reset(AESADV_Regs *aesadv)
Resets AESADV module.
Definition: dl_aesadv.h:375
DL_AESADV_STATUS DL_AESADV_readOutputData(const AESADV_Regs *aesadv, const uint8_t *data)
reads 128-bits of output data that has been encrypted/decrypted.
__STATIC_INLINE void DL_AESADV_disableDMAInputTriggerEvent(AESADV_Regs *aesadv)
Disable DMA input trigger event.
Definition: dl_aesadv.h:1719
Definition: dl_aesadv.h:258
__STATIC_INLINE void DL_AESADV_setMode(AESADV_Regs *aesadv, DL_AESADV_MODE mode)
Sets the AES algorithm mode.
Definition: dl_aesadv.h:496
Definition: dl_aesadv.h:215
Definition: dl_aesadv.h:159
void DL_AESADV_readOutputDataAligned(const AESADV_Regs *aesadv, uint32_t *dataAligned)
reads 128-bits of output data that has been encrypted/decrypted.
__STATIC_INLINE bool DL_AESADV_isOutputReady(const AESADV_Regs *aesadv)
Returns if an AES output block is available to be read.
Definition: dl_aesadv.h:404
__STATIC_INLINE uint32_t DL_AESADV_getRawDMAOutputTriggerEventStatus(const AESADV_Regs *aesadv)
Check interrupt flag of DMA output trigger event.
Definition: dl_aesadv.h:1851
__STATIC_INLINE void DL_AESADV_enableDMAOutputTriggerEvent(AESADV_Regs *aesadv)
Enables DMA output trigger to publish AESADV read requests to the DMA.
Definition: dl_aesadv.h:1709
DL_AESADV_STATUS DL_AESADV_readTAG(const AESADV_Regs *aesadv, const uint8_t *tag)
reads 128-bit output tag at the conclusion of operation/halt
Definition: dl_aesadv.h:178
__STATIC_INLINE uint32_t DL_AESADV_getRawDMAInputTriggerEventStatus(const AESADV_Regs *aesadv)
Check interrupt flag of DMA input trigger event.
Definition: dl_aesadv.h:1830
DL_AESADV_CTR_WIDTH
Definition: dl_aesadv.h:211
__STATIC_INLINE DL_AESADV_FB_WIDTH DL_AESADV_getFeedbackWidth(const AESADV_Regs *aesadv)
Returns the current feedback width.
Definition: dl_aesadv.h:546
__STATIC_INLINE void DL_AESADV_forceInputDataAvailable(AESADV_Regs *aesadv)
Forces AESADV to begin processing input data.
Definition: dl_aesadv.h:1451
DL_AESADV_STATUS DL_AESADV_setKey(AESADV_Regs *aesadv, const uint8_t *key, DL_AESADV_KEY_SIZE keySize)
Loads a 128 or 256 bit regular key to the AESADV module.
__STATIC_INLINE DL_AESADV_CCM_TAG_WIDTH DL_AESADV_getCCMTagWidth(const AESADV_Regs *aesadv)
Returns the current CCM-specific authentication tag width.
Definition: dl_aesadv.h:674
#define DL_AESADV_MODE_MASK
AESADV Mode mask for all modes.
Definition: dl_aesadv.h:124
__STATIC_INLINE void DL_AESADV_setLowerCryptoLength(AESADV_Regs *aesadv, uint32_t lowerLength)
Sets the lower 32 bits of the crypto input data length in bytes.
Definition: dl_aesadv.h:883
__STATIC_INLINE void DL_AESADV_resumeAADPhase(AESADV_Regs *aesadv, DL_AESADV_MODE mode)
Resume GCM or CCM operation in the AAD phase.
Definition: dl_aesadv.h:720
void DL_AESADV_setKeyAligned(AESADV_Regs *aesadv, const uint32_t *keyAligned, DL_AESADV_KEY_SIZE keySize)
Loads a 128 or 256 bit regular key to the AESADV module.
uint32_t upperCryptoLength
Definition: dl_aesadv.h:312
Definition: dl_aesadv.h:137
DL_AESADV_MODE mode
Definition: dl_aesadv.h:279
__STATIC_INLINE void DL_AESADV_setUpperCryptoLength(AESADV_Regs *aesadv, uint32_t upperLength)
Sets the upper 29 bits of the crypto input data length in bytes.
Definition: dl_aesadv.h:906
Definition: dl_aesadv.h:260
Definition: dl_aesadv.h:256
void DL_AESADV_setThirdKeyAligned(AESADV_Regs *aesadv, const uint32_t *thirdKeyAligned)
Loads the CBC-MAC third key.
__STATIC_INLINE uintptr_t DL_AESADV_getDATAOUTAddr(const AESADV_Regs *aesadv)
Returns the address of the AESADV output data register.
Definition: dl_aesadv.h:1953
DL_AESADV_CCM_TAG_WIDTH
Definition: dl_aesadv.h:246
Definition: dl_aesadv.h:148
__STATIC_INLINE DL_AESADV_IIDX DL_AESADV_getPendingDMAOutputTriggerEvent(const AESADV_Regs *aesadv)
Get highest priority pending DMA output trigger event.
Definition: dl_aesadv.h:1886
__STATIC_INLINE void DL_AESADV_clearDMAInputTriggerEventStatus(AESADV_Regs *aesadv)
Clear pending DMA input trigger event.
Definition: dl_aesadv.h:1899
DL_AESADV_DIR
Definition: dl_aesadv.h:203
DL_AESADV_DIR direction
Definition: dl_aesadv.h:282
__STATIC_INLINE bool DL_AESADV_isSavedOutputContextEnabled(const AESADV_Regs *aesadv)
Returns whether the storage of additional context is enabled.
Definition: dl_aesadv.h:806
void DL_AESADV_initICM(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
Initializes the engine in the Integer Counter Mode (ICM)
Definition: dl_aesadv.h:199
__STATIC_INLINE DL_AESADV_KEY_SIZE DL_AESADV_getKeySize(const AESADV_Regs *aesadv)
Returns the current key size of the AESADV peripheral.
Definition: dl_aesadv.h:473
DL_AESADV_IIDX
Definition: dl_aesadv.h:135
Definition: dl_aesadv.h:146
void DL_AESADV_initCMAC(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
Initializes the engine in the block cipher-based Message Authentication Code (CMAC) ...
DL_AESADV_STATUS
Definition: dl_aesadv.h:266
void DL_AESADV_initCBCMAC(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
Initializes the engine in the Cipher Block Chaining Message Authenication Code (CBC-MAC) ...
Definition: dl_aesadv.h:252
void DL_AESADV_initCTR(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
Initializes the engine in the Counter (CTR) mode.
Definition: dl_aesadv.h:262
DL_AESADV_CCM_CTR_WIDTH ccm_ctrWidth
Definition: dl_aesadv.h:291
DL_AESADV_KEY_SIZE
Definition: dl_aesadv.h:195
Definition: dl_aesadv.h:230
void DL_AESADV_loadCCMNonceAndCounter(AESADV_Regs *aesadv, uint8_t *nonce, DL_AESADV_CCM_CTR_WIDTH ctrWidth)
Loads the CCM Nonce And Counter IV, also called A0.
uint32_t lowerCryptoLength
Definition: dl_aesadv.h:309
Definition: dl_aesadv.h:238
void DL_AESADV_initGCM(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
Initializes the engine in the Galois/Counter Mode (GCM)
__STATIC_INLINE bool DL_AESADV_isDMAOperationEnabled(const AESADV_Regs *aesadv)
Returns if DMA Operation is enabled.
Definition: dl_aesadv.h:969
__STATIC_INLINE uint32_t DL_AESADV_getEnabledDMAInputTriggerEvent(const AESADV_Regs *aesadv)
Check if the DMA input trigger event is enabled.
Definition: dl_aesadv.h:1747
__STATIC_INLINE uint32_t DL_AESADV_getUpperBlockCount(const AESADV_Regs *aesadv)
Gets the upper 25-bits of the data blocks remaining in an operation.
Definition: dl_aesadv.h:1565
__STATIC_INLINE void DL_AESADV_clearDMAOutputTriggerEventStatus(AESADV_Regs *aesadv)
Clear pending DMA output trigger event.
Definition: dl_aesadv.h:1910
__STATIC_INLINE void DL_AESADV_setCounterWidth(AESADV_Regs *aesadv, DL_AESADV_CTR_WIDTH ctrWidth)
Sets the counter width of the AESADV peripheral.
Definition: dl_aesadv.h:568
__STATIC_INLINE bool DL_AESADV_isPowerEnabled(const AESADV_Regs *aesadv)
Returns if the Peripheral Write Enable (PWREN) register for the AESADV is enabled.
Definition: dl_aesadv.h:364
#define DL_AESADV_EVENT_DMA_DATA_OUTPUT_TRIGGER
DMA Trigger Event used to request the DMA read from DATAOUT.
Definition: dl_aesadv.h:116
__STATIC_INLINE uint32_t DL_AESADV_getEnabledDMAOutputTriggerEventStatus(const AESADV_Regs *aesadv)
Check interrupt flag of DMA output trigger event.
Definition: dl_aesadv.h:1809
void DL_AESADV_loadInputDataAligned(AESADV_Regs *aesadv, const uint32_t *dataAligned)
loads 128 bits (4 words) of input data
__STATIC_INLINE void DL_AESADV_setKeySize(AESADV_Regs *aesadv, DL_AESADV_KEY_SIZE size)
Sets the key size of the AESADV peripheral.
Definition: dl_aesadv.h:459
DL_AESADV_FB_WIDTH cfb_fbWidth
Definition: dl_aesadv.h:287
DL_AESADV_STATUS DL_AESADV_loadIntermediateTAG(AESADV_Regs *aesadv, const uint8_t *tag)
Loads either zero or an intermediate 128-bit TAG to resume GCM/CCM.
Definition: dl_aesadv.h:240
__STATIC_INLINE void DL_AESADV_setUpperBlockCount(AESADV_Regs *aesadv, uint32_t upperBlockCount)
Sets the upper 25-bits of the data blocks remaining in an operation.
Definition: dl_aesadv.h:1545
__STATIC_INLINE uint32_t DL_AESADV_getEnabledDMAInputTriggerEventStatus(const AESADV_Regs *aesadv)
Check interrupt flag of DMA input trigger event.
Definition: dl_aesadv.h:1787
void DL_AESADV_loadInitializationVectorAligned(AESADV_Regs *aesadv, const uint32_t *ivAligned)
Loads the 128-bit initialization vector to the AESADV module.
Definition: dl_aesadv.h:219
Definition: dl_aesadv.h:168
#define DL_AESADV_EVENT_DMA_DATA_INPUT_TRIGGER
DMA Trigger Event used to request the DMA write to DATAIN.
Definition: dl_aesadv.h:110
__STATIC_INLINE void DL_AESADV_disablePower(AESADV_Regs *aesadv)
Disables the Peripheral Write Enable (PWREN) register for the AESADV.
Definition: dl_aesadv.h:342
void DL_AESADV_loadIntermediateTAGAligned(AESADV_Regs *aesadv, const uint32_t *tagAligned)
Loads either zero or an intermediate 128-bit TAG to resume GCM/CCM.
void DL_AESADV_setSecondKeyAligned(AESADV_Regs *aesadv, const uint32_t *secondKeyAligned)
Loads the CBC-MAC second key.
__STATIC_INLINE DL_AESADV_MODE DL_AESADV_getMode(const AESADV_Regs *aesadv)
Returns the current selected mode.
Definition: dl_aesadv.h:515
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