dl_i2c.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/*!****************************************************************************
 *  @file       dl_i2c.h
 *  @brief      Inter-Integrated Circuit (I2C) Driver Library
 *  @defgroup   I2C  Inter-Integrated Circuit (I2C)
 *
 *  @anchor ti_dl_dl_i2c_Overview
 *  # Overview
 *
 *   The I2C Library allows full configuration of the MSPM0 I2C module.
 *   The I2C module provides a standardized serial interface to transfer data
 *   between MSP devices and other external I2C devices (such as a sensors,
 *   memory, or DACs).
 *
 *  <hr>
 ******************************************************************************
 */
#ifndef ti_dl_dl_i2c__include
#define ti_dl_dl_i2c__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#ifdef __MSPM0_HAS_I2C__

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

#define DL_I2C_TX_FIFO_COUNT_MAXIMUM          ((uint32_t)I2C_SYS_FENTRIES << 8)

#define DL_I2C_RX_FIFO_COUNT_MAXIMUM               ((uint32_t)I2C_SYS_FENTRIES)

#define DL_I2C_CONTROLLER_STATUS_BUSY                       (I2C_MSR_BUSY_MASK)

#define DL_I2C_CONTROLLER_STATUS_ERROR                       (I2C_MSR_ERR_MASK)

#define DL_I2C_CONTROLLER_STATUS_ADDR_ACK                 (I2C_MSR_ADRACK_MASK)

#define DL_I2C_CONTROLLER_STATUS_DATA_ACK                 (I2C_MSR_DATACK_MASK)

#define DL_I2C_CONTROLLER_STATUS_ARBITRATION_LOST         (I2C_MSR_ARBLST_MASK)

#define DL_I2C_CONTROLLER_STATUS_IDLE                       (I2C_MSR_IDLE_MASK)

#define DL_I2C_CONTROLLER_STATUS_BUSY_BUS                 (I2C_MSR_BUSBSY_MASK)

#define DL_I2C_TARGET_STATUS_ADDRESS_MATCH             (I2C_SSR_ADDRMATCH_MASK)

#define DL_I2C_TARGET_STATUS_STALE_TX_FIFO          (I2C_SSR_STALE_TXFIFO_MASK)

#define DL_I2C_TARGET_STATUS_TX_MODE                      (I2C_SSR_TXMODE_MASK)

#define DL_I2C_TARGET_STATUS_BUS_BUSY                     (I2C_SSR_BUSBSY_MASK)

#define DL_I2C_TARGET_STATUS_RX_MODE                      (I2C_SSR_RXMODE_MASK)


#define DL_I2C_TARGET_STATUS_QUICK_COMMAND_READ_WRITE     (I2C_SSR_QCMDRW_MASK)

#define DL_I2C_TARGET_STATUS_QUICK_COMMAND_STATUS         (I2C_SSR_QCMDST_MASK)

#define DL_I2C_TARGET_STATUS_OWN_ADDR_ALTERNATE_MATCHED  (I2C_SSR_OAR2SEL_MASK)

#define DL_I2C_TARGET_STATUS_TRANSMIT_REQUEST               (I2C_SSR_TREQ_MASK)

#define DL_I2C_TARGET_STATUS_RECEIVE_REQUEST                (I2C_SSR_RREQ_MASK)

#define DL_I2C_INTERRUPT_CONTROLLER_RX_DONE  (I2C_CPU_INT_IMASK_MRXDONE_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_TX_DONE  (I2C_CPU_INT_IMASK_MTXDONE_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_RXFIFO_TRIGGER                            \
                                          (I2C_CPU_INT_IMASK_MRXFIFOTRG_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_TXFIFO_TRIGGER                            \
                                          (I2C_CPU_INT_IMASK_MTXFIFOTRG_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_RXFIFO_FULL                               \
                                         (I2C_CPU_INT_IMASK_MRXFIFOFULL_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_TXFIFO_EMPTY                              \
                                            (I2C_CPU_INT_IMASK_MTXEMPTY_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_NACK       (I2C_CPU_INT_IMASK_MNACK_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_START     (I2C_CPU_INT_IMASK_MSTART_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_STOP       (I2C_CPU_INT_IMASK_MSTOP_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_ARBITRATION_LOST                          \
                                            (I2C_CPU_INT_IMASK_MARBLOST_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_EVENT1_DMA_DONE                           \
                                       (I2C_CPU_INT_IMASK_MDMA_DONE_TX_SET)

#define DL_I2C_INTERRUPT_CONTROLLER_EVENT2_DMA_DONE                           \
                                       (I2C_CPU_INT_IMASK_MDMA_DONE_RX_SET)


#define DL_I2C_INTERRUPT_CONTROLLER_PEC_RX_ERROR                              \
                                         (I2C_CPU_INT_IMASK_MPEC_RX_ERR_SET)


#define DL_I2C_INTERRUPT_TARGET_RX_DONE      (I2C_CPU_INT_IMASK_SRXDONE_SET)

#define DL_I2C_INTERRUPT_TARGET_TX_DONE      (I2C_CPU_INT_IMASK_STXDONE_SET)

#define DL_I2C_INTERRUPT_TARGET_RXFIFO_TRIGGER                                \
                                          (I2C_CPU_INT_IMASK_SRXFIFOTRG_SET)

#define DL_I2C_INTERRUPT_TARGET_TXFIFO_TRIGGER                                \
                                          (I2C_CPU_INT_IMASK_STXFIFOTRG_SET)

#define DL_I2C_INTERRUPT_TARGET_RXFIFO_FULL                                   \
                                         (I2C_CPU_INT_IMASK_SRXFIFOFULL_SET)

#define DL_I2C_INTERRUPT_TARGET_TXFIFO_EMPTY                                  \
                                            (I2C_CPU_INT_IMASK_STXEMPTY_SET)

#define DL_I2C_INTERRUPT_TARGET_START                                         \
                                              (I2C_CPU_INT_IMASK_SSTART_SET)

#define DL_I2C_INTERRUPT_TARGET_STOP           (I2C_CPU_INT_IMASK_SSTOP_SET)

#define DL_I2C_INTERRUPT_TARGET_GENERAL_CALL                                  \
                                            (I2C_CPU_INT_IMASK_SGENCALL_SET)

#define DL_I2C_INTERRUPT_TARGET_EVENT1_DMA_DONE                               \
                                        (I2C_CPU_INT_IMASK_SDMA_DONE_TX_SET)

#define DL_I2C_INTERRUPT_TARGET_EVENT2_DMA_DONE                               \
                                        (I2C_CPU_INT_IMASK_SDMA_DONE_RX_SET)


#define DL_I2C_INTERRUPT_TARGET_PEC_RX_ERROR                                  \
                                         (I2C_CPU_INT_IMASK_SPEC_RX_ERR_SET)

#define DL_I2C_INTERRUPT_TARGET_TXFIFO_UNDERFLOW                              \
                                            (I2C_CPU_INT_IMASK_STX_UNFL_SET)

#define DL_I2C_INTERRUPT_TARGET_RXFIFO_OVERFLOW                              \
                                            (I2C_CPU_INT_IMASK_SRX_OVFL_SET)

#define DL_I2C_INTERRUPT_TARGET_ARBITRATION_LOST                              \
                                            (I2C_CPU_INT_IMASK_SARBLOST_SET)

#define DL_I2C_TARGET_INTERRUPT_OVERFLOW   (I2C_CPU_INT_IMASK_INTR_OVFL_SET)

#define DL_I2C_INTERRUPT_TIMEOUT_A          (I2C_CPU_INT_IMASK_TIMEOUTA_SET)

#define DL_I2C_INTERRUPT_TIMEOUT_B          (I2C_CPU_INT_IMASK_TIMEOUTB_SET)


#define DL_I2C_DMA_INTERRUPT_TARGET_TXFIFO_TRIGGER                            \
                                          (I2C_DMA_TRIG1_IMASK_STXFIFOTRG_SET)

#define DL_I2C_DMA_INTERRUPT_TARGET_RXFIFO_TRIGGER                            \
                                          (I2C_DMA_TRIG1_IMASK_SRXFIFOTRG_SET)

#define DL_I2C_DMA_INTERRUPT_CONTROLLER_TXFIFO_TRIGGER                        \
                                          (I2C_DMA_TRIG1_IMASK_MTXFIFOTRG_SET)

#define DL_I2C_DMA_INTERRUPT_CONTROLLER_RXFIFO_TRIGGER                        \
                                          (I2C_DMA_TRIG1_IMASK_MRXFIFOTRG_SET)

/* clang-format on */

typedef enum {
    DL_I2C_DMA_IIDX_TARGET_TXFIFO_TRIGGER = I2C_DMA_TRIG1_IIDX_STAT_MTXFIFOTRG,
    DL_I2C_DMA_IIDX_TARGET_RXFIFO_TRIGGER = I2C_DMA_TRIG1_IIDX_STAT_MRXFIFOTRG,
    DL_I2C_DMA_IIDX_CONTROLLER_TXFIFO_TRIGGER =
        I2C_DMA_TRIG1_IIDX_STAT_STXFIFOTRG,
    DL_I2C_DMA_IIDX_CONTROLLER_RXFIFO_TRIGGER =
        I2C_DMA_TRIG1_IIDX_STAT_SRXFIFOTRG
} DL_I2C_DMA_IIDX;

typedef enum {
    DL_I2C_EVENT_ROUTE_1 = 0,
    DL_I2C_EVENT_ROUTE_2 = 12
} DL_I2C_EVENT_ROUTE;

typedef enum {
    DL_I2C_CLOCK_BUSCLK = I2C_CLKSEL_BUSCLK_SEL_ENABLE,
    DL_I2C_CLOCK_MFCLK = I2C_CLKSEL_MFCLK_SEL_ENABLE,
} DL_I2C_CLOCK;

typedef enum {
    DL_I2C_CLOCK_DIVIDE_1 = I2C_CLKDIV_RATIO_DIV_BY_1,
    DL_I2C_CLOCK_DIVIDE_2 = I2C_CLKDIV_RATIO_DIV_BY_2,
    DL_I2C_CLOCK_DIVIDE_3 = I2C_CLKDIV_RATIO_DIV_BY_3,
    DL_I2C_CLOCK_DIVIDE_4 = I2C_CLKDIV_RATIO_DIV_BY_4,
    DL_I2C_CLOCK_DIVIDE_5 = I2C_CLKDIV_RATIO_DIV_BY_5,
    DL_I2C_CLOCK_DIVIDE_6 = I2C_CLKDIV_RATIO_DIV_BY_6,
    DL_I2C_CLOCK_DIVIDE_7 = I2C_CLKDIV_RATIO_DIV_BY_7,
    DL_I2C_CLOCK_DIVIDE_8 = I2C_CLKDIV_RATIO_DIV_BY_8,
} DL_I2C_CLOCK_DIVIDE;

typedef enum {
    DL_I2C_TARGET_ADDRESSING_MODE_7_BIT = I2C_SOAR_SMODE_MODE7,
    DL_I2C_TARGET_ADDRESSING_MODE_10_BIT = I2C_SOAR_SMODE_MODE10,
} DL_I2C_TARGET_ADDRESSING_MODE;

typedef enum {
    DL_I2C_TARGET_PEC_STATUS_CHECKED = I2C_TARGET_PECSR_PECSTS_CHECK_SET,
    DL_I2C_TARGET_PEC_STATUS_NOT_CHECKED =
        I2C_TARGET_PECSR_PECSTS_CHECK_CLEARED,
} DL_I2C_TARGET_PEC_STATUS;

typedef enum {
    DL_I2C_TARGET_PEC_CHECK_ERROR_CLEARED =
        I2C_TARGET_PECSR_PECSTS_ERROR_CLEARED,
    DL_I2C_TARGET_PEC_CHECK_ERROR_SET = I2C_TARGET_PECSR_PECSTS_ERROR_SET,
} DL_I2C_TARGET_PEC_CHECK_ERROR;

typedef enum {
    DL_I2C_ANALOG_GLITCH_FILTER_WIDTH_5NS = I2C_GFCTL_AGFSEL_AGLIT_5,
    DL_I2C_ANALOG_GLITCH_FILTER_WIDTH_10NS = I2C_GFCTL_AGFSEL_AGLIT_10,
    DL_I2C_ANALOG_GLITCH_FILTER_WIDTH_25NS = I2C_GFCTL_AGFSEL_AGLIT_25,
    DL_I2C_ANALOG_GLITCH_FILTER_WIDTH_50NS = I2C_GFCTL_AGFSEL_AGLIT_50,
} DL_I2C_ANALOG_GLITCH_FILTER_WIDTH;

typedef enum {
    DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_DISABLED = I2C_GFCTL_DGFSEL_DISABLED,
    DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_1 = I2C_GFCTL_DGFSEL_CLK_1,
    DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_2 = I2C_GFCTL_DGFSEL_CLK_2,
    DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_3 = I2C_GFCTL_DGFSEL_CLK_3,
    DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_4 = I2C_GFCTL_DGFSEL_CLK_4,
    DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_8 = I2C_GFCTL_DGFSEL_CLK_8,
    DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_16 = I2C_GFCTL_DGFSEL_CLK_16,
    DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_31 = I2C_GFCTL_DGFSEL_CLK_31,
} DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH;

typedef enum {
    DL_I2C_CONTROLLER_DIRECTION_TX = I2C_MSA_DIR_TRANSMIT,
    DL_I2C_CONTROLLER_DIRECTION_RX = I2C_MSA_DIR_RECEIVE,
} DL_I2C_CONTROLLER_DIRECTION;

typedef enum {
    DL_I2C_CONTROLLER_ADDRESSING_MODE_7_BIT = I2C_MSA_MMODE_MODE7,
    DL_I2C_CONTROLLER_ADDRESSING_MODE_10_BIT = I2C_MSA_MMODE_MODE10,
} DL_I2C_CONTROLLER_ADDRESSING_MODE;

typedef enum {
    DL_I2C_CONTROLLER_PEC_STATUS_CHECKED =
        I2C_CONTROLLER_PECSR_PECSTS_CHECK_SET,
    DL_I2C_CONTROLLER_PEC_STATUS_NOT_CHECKED =
        I2C_CONTROLLER_PECSR_PECSTS_CHECK_CLEARED,
} DL_I2C_CONTROLLER_PEC_STATUS;

typedef enum {
    DL_I2C_CONTROLLER_PEC_CHECK_ERROR_SET =
        I2C_CONTROLLER_PECSR_PECSTS_ERROR_SET,
    DL_I2C_CONTROLLER_PEC_CHECK_ERROR_CLEARED =
        I2C_CONTROLLER_PECSR_PECSTS_ERROR_CLEARED,
} DL_I2C_CONTROLLER_PEC_CHECK_ERROR;

typedef enum {
    DL_I2C_CONTROLLER_SCL_HIGH = I2C_MBMON_SCL_SET,
    DL_I2C_CONTROLLER_SCL_LOW = I2C_MBMON_SCL_CLEARED,
} DL_I2C_CONTROLLER_SCL;

typedef enum {
    DL_I2C_CONTROLLER_SDA_HIGH = I2C_MBMON_SDA_SET,
    DL_I2C_CONTROLLER_SDA_LOW = I2C_MBMON_SDA_CLEARED,
} DL_I2C_CONTROLLER_SDA;

typedef enum {
    DL_I2C_CONTROLLER_START_ENABLE = I2C_MCTR_START_ENABLE,
    DL_I2C_CONTROLLER_START_DISABLE = I2C_MCTR_START_DISABLE,
} DL_I2C_CONTROLLER_START;

typedef enum {
    DL_I2C_CONTROLLER_STOP_ENABLE = I2C_MCTR_STOP_ENABLE,
    DL_I2C_CONTROLLER_STOP_DISABLE = I2C_MCTR_STOP_DISABLE,
} DL_I2C_CONTROLLER_STOP;

typedef enum {
    DL_I2C_CONTROLLER_ACK_ENABLE = I2C_MCTR_ACK_ENABLE,
    DL_I2C_CONTROLLER_ACK_DISABLE = I2C_MCTR_ACK_DISABLE,
} DL_I2C_CONTROLLER_ACK;

typedef enum {
    DL_I2C_TX_FIFO_LEVEL_EMPTY = I2C_MFIFOCTL_TXTRIG_EMPTY,
    DL_I2C_TX_FIFO_LEVEL_BYTES_1 = I2C_MFIFOCTL_TXTRIG_LEVEL_1,
    DL_I2C_TX_FIFO_LEVEL_BYTES_2 = I2C_MFIFOCTL_TXTRIG_LEVEL_2,
    DL_I2C_TX_FIFO_LEVEL_BYTES_3 = I2C_MFIFOCTL_TXTRIG_LEVEL_3,
    DL_I2C_TX_FIFO_LEVEL_BYTES_4 = I2C_MFIFOCTL_TXTRIG_LEVEL_4,
    DL_I2C_TX_FIFO_LEVEL_BYTES_5 = I2C_MFIFOCTL_TXTRIG_LEVEL_5,
    DL_I2C_TX_FIFO_LEVEL_BYTES_6 = I2C_MFIFOCTL_TXTRIG_LEVEL_6,
    DL_I2C_TX_FIFO_LEVEL_BYTES_7 = I2C_MFIFOCTL_TXTRIG_LEVEL_7,
} DL_I2C_TX_FIFO_LEVEL;

typedef enum {
    DL_I2C_RX_FIFO_LEVEL_BYTES_1 = I2C_MFIFOCTL_RXTRIG_LEVEL_1,
    DL_I2C_RX_FIFO_LEVEL_BYTES_2 = I2C_MFIFOCTL_RXTRIG_LEVEL_2,
    DL_I2C_RX_FIFO_LEVEL_BYTES_3 = I2C_MFIFOCTL_RXTRIG_LEVEL_3,
    DL_I2C_RX_FIFO_LEVEL_BYTES_4 = I2C_MFIFOCTL_RXTRIG_LEVEL_4,
    DL_I2C_RX_FIFO_LEVEL_BYTES_5 = I2C_MFIFOCTL_RXTRIG_LEVEL_5,
    DL_I2C_RX_FIFO_LEVEL_BYTES_6 = I2C_MFIFOCTL_RXTRIG_LEVEL_6,
    DL_I2C_RX_FIFO_LEVEL_BYTES_7 = I2C_MFIFOCTL_RXTRIG_LEVEL_7,
    DL_I2C_RX_FIFO_LEVEL_BYTES_8 = I2C_MFIFOCTL_RXTRIG_LEVEL_8,
} DL_I2C_RX_FIFO_LEVEL;

typedef enum {
    DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE_ACK = I2C_SACKCTL_ACKOVAL_DISABLE,
    DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE_NACK = I2C_SACKCTL_ACKOVAL_ENABLE,
} DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE;

typedef enum {
    DL_I2C_IIDX_NO_INT = I2C_CPU_INT_IIDX_STAT_NO_INTR,
    DL_I2C_IIDX_CONTROLLER_RX_DONE = I2C_CPU_INT_IIDX_STAT_MRXDONEFG,
    DL_I2C_IIDX_CONTROLLER_TX_DONE = I2C_CPU_INT_IIDX_STAT_MTXDONEFG,
    DL_I2C_IIDX_CONTROLLER_RXFIFO_TRIGGER = I2C_CPU_INT_IIDX_STAT_MRXFIFOTRG,
    DL_I2C_IIDX_CONTROLLER_TXFIFO_TRIGGER = I2C_CPU_INT_IIDX_STAT_MTXFIFOTRG,
    DL_I2C_IIDX_CONTROLLER_RXFIFO_FULL = I2C_CPU_INT_IIDX_STAT_MRXFIFOFULL,
    DL_I2C_IIDX_CONTROLLER_TXFIFO_EMPTY = I2C_CPU_INT_IIDX_STAT_MTX_EMPTY,
    DL_I2C_IIDX_CONTROLLER_NACK = I2C_CPU_INT_IIDX_STAT_MNACKFG,
    DL_I2C_IIDX_CONTROLLER_START = I2C_CPU_INT_IIDX_STAT_MSTARTFG,
    DL_I2C_IIDX_CONTROLLER_STOP = I2C_CPU_INT_IIDX_STAT_MSTOPFG,
    DL_I2C_IIDX_CONTROLLER_ARBITRATION_LOST = I2C_CPU_INT_IIDX_STAT_MARBLOSTFG,
    DL_I2C_IIDX_CONTROLLER_EVENT1_DMA_DONE =
        I2C_CPU_INT_IIDX_STAT_MDMA_DONE_TX,
    DL_I2C_IIDX_CONTROLLER_EVENT2_DMA_DONE =
        I2C_CPU_INT_IIDX_STAT_MDMA_DONE_RX,

    DL_I2C_IIDX_CONTROLLER_PEC_RX_ERROR = I2C_CPU_INT_IIDX_STAT_MPEC_RX_ERR,
    DL_I2C_IIDX_TIMEOUT_A = I2C_CPU_INT_IIDX_STAT_TIMEOUTA,
    DL_I2C_IIDX_TIMEOUT_B = I2C_CPU_INT_IIDX_STAT_TIMEOUTB,

    DL_I2C_IIDX_TARGET_RX_DONE = I2C_CPU_INT_IIDX_STAT_SRXDONEFG,
    DL_I2C_IIDX_TARGET_TX_DONE = I2C_CPU_INT_IIDX_STAT_STXDONEFG,
    DL_I2C_IIDX_TARGET_RXFIFO_TRIGGER = I2C_CPU_INT_IIDX_STAT_SRXFIFOTRG,
    DL_I2C_IIDX_TARGET_TXFIFO_TRIGGER = I2C_CPU_INT_IIDX_STAT_STXFIFOTRG,
    DL_I2C_IIDX_TARGET_RXFIFO_FULL = I2C_CPU_INT_IIDX_STAT_SRXFIFOFULL,
    DL_I2C_IIDX_TARGET_TXFIFO_EMPTY = I2C_CPU_INT_IIDX_STAT_STXEMPTY,
    DL_I2C_IIDX_TARGET_START = I2C_CPU_INT_IIDX_STAT_SSTARTFG,
    DL_I2C_IIDX_TARGET_STOP = I2C_CPU_INT_IIDX_STAT_SSTOPFG,
    DL_I2C_IIDX_TARGET_GENERAL_CALL = I2C_CPU_INT_IIDX_STAT_SGENCALL,
    DL_I2C_IIDX_TARGET_EVENT1_DMA_DONE = I2C_CPU_INT_IIDX_STAT_SDMA_DONE_TX,
    DL_I2C_IIDX_TARGET_EVENT2_DMA_DONE = I2C_CPU_INT_IIDX_STAT_SDMA_DONE_RX,

    DL_I2C_IIDX_TARGET_PEC_RX_ERROR = I2C_CPU_INT_IIDX_STAT_SPEC_RX_ERR,
    DL_I2C_IIDX_TARGET_TXFIFO_UNDERFLOW = I2C_CPU_INT_IIDX_STAT_STX_UNFL,
    DL_I2C_IIDX_TARGET_RXFIFO_OVERFLOW = I2C_CPU_INT_IIDX_STAT_SRX_OVFL,
    DL_I2C_IIDX_TARGET_ARBITRATION_LOST = I2C_CPU_INT_IIDX_STAT_SARBLOST,
    DL_I2C_IIDX_INTERRUPT_OVERFLOW = I2C_CPU_INT_IIDX_STAT_INTR_OVFL,

} DL_I2C_IIDX;

typedef struct {
    DL_I2C_CLOCK clockSel;
    DL_I2C_CLOCK_DIVIDE divideRatio;
} DL_I2C_ClockConfig;

void DL_I2C_setClockConfig(I2C_Regs *i2c, const DL_I2C_ClockConfig *config);

void DL_I2C_getClockConfig(const I2C_Regs *i2c, DL_I2C_ClockConfig *config);

uint16_t DL_I2C_fillControllerTXFIFO(
    I2C_Regs *i2c, const uint8_t *buffer, uint16_t count);

void DL_I2C_flushControllerTXFIFO(I2C_Regs *i2c);

void DL_I2C_flushControllerRXFIFO(I2C_Regs *i2c);

__STATIC_INLINE bool DL_I2C_isControllerTXFIFOFull(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_TXFIFOCNT_MASK) ==
            I2C_MFIFOSR_TXFIFOCNT_MINIMUM);
}

__STATIC_INLINE bool DL_I2C_isControllerTXFIFOEmpty(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_TXFIFOCNT_MASK) ==
            DL_I2C_TX_FIFO_COUNT_MAXIMUM);
}

__STATIC_INLINE bool DL_I2C_isControllerRXFIFOEmpty(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_RXFIFOCNT_MASK) ==
            I2C_MFIFOSR_RXFIFOCNT_MINIMUM);
}

__STATIC_INLINE void DL_I2C_resetControllerTransfer(I2C_Regs *i2c)
{
    // Resets all Controller functionality
    i2c->MASTER.MCTR = 0x00;
}

__STATIC_INLINE void DL_I2C_startControllerTransfer(I2C_Regs *i2c,
    uint32_t targetAddr, DL_I2C_CONTROLLER_DIRECTION direction,
    uint16_t length)
{
    // Specify target address and read/write mode
    DL_Common_updateReg(&i2c->MASTER.MSA,
        ((targetAddr << I2C_MSA_SADDR_OFS) | (uint32_t) direction),
        (I2C_MSA_SADDR_MASK | I2C_MSA_DIR_MASK));

    // STOP bit is generated after burst length number of bytes transferred
    DL_Common_updateReg(&i2c->MASTER.MCTR,
        (((uint32_t) length << I2C_MCTR_MBLEN_OFS) | I2C_MCTR_BURSTRUN_ENABLE |
            I2C_MCTR_START_ENABLE | I2C_MCTR_STOP_ENABLE),
        (I2C_MCTR_MBLEN_MASK | I2C_MCTR_BURSTRUN_MASK | I2C_MCTR_START_MASK |
            I2C_MCTR_STOP_MASK));
}

__STATIC_INLINE void DL_I2C_startControllerTransferAdvanced(I2C_Regs *i2c,
    uint32_t targetAddr, DL_I2C_CONTROLLER_DIRECTION direction,
    uint16_t length, DL_I2C_CONTROLLER_START start,
    DL_I2C_CONTROLLER_STOP stop, DL_I2C_CONTROLLER_ACK ack)
{
    // Specify target address and read/write mode
    DL_Common_updateReg(&i2c->MASTER.MSA,
        ((targetAddr << I2C_MSA_SADDR_OFS) | (uint32_t) direction),
        (I2C_MSA_SADDR_MASK | I2C_MSA_DIR_MASK));

    DL_Common_updateReg(&i2c->MASTER.MCTR,
        (((uint32_t) length << I2C_MCTR_MBLEN_OFS) | I2C_MCTR_BURSTRUN_ENABLE |
            (uint32_t) start | (uint32_t) stop | (uint32_t) ack),
        (I2C_MCTR_MBLEN_MASK | I2C_MCTR_BURSTRUN_MASK | I2C_MCTR_START_MASK |
            I2C_MCTR_STOP_MASK | I2C_MCTR_ACK_MASK));
}

__STATIC_INLINE bool DL_I2C_isTargetTXFIFOFull(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_TXFIFOCNT_MASK) ==
            I2C_SFIFOSR_TXFIFOCNT_MINIMUM);
}

__STATIC_INLINE bool DL_I2C_isTargetTXFIFOEmpty(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_TXFIFOCNT_MASK) ==
            DL_I2C_TX_FIFO_COUNT_MAXIMUM);
}

__STATIC_INLINE bool DL_I2C_isTargetRXFIFOEmpty(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_RXFIFOCNT_MASK) ==
            I2C_SFIFOSR_RXFIFOCNT_MINIMUM);
}

uint8_t DL_I2C_fillTargetTXFIFO(
    I2C_Regs *i2c, const uint8_t *buffer, uint8_t count);

void DL_I2C_flushTargetTXFIFO(I2C_Regs *i2c);

void DL_I2C_flushTargetRXFIFO(I2C_Regs *i2c);

void DL_I2C_transmitTargetDataBlocking(I2C_Regs *i2c, uint8_t data);

bool DL_I2C_transmitTargetDataCheck(I2C_Regs *i2c, uint8_t data);

uint8_t DL_I2C_receiveTargetDataBlocking(const I2C_Regs *i2c);

bool DL_I2C_receiveTargetDataCheck(const I2C_Regs *i2c, uint8_t *buffer);

__STATIC_INLINE void DL_I2C_enablePower(I2C_Regs *i2c)
{
    i2c->GPRCM.PWREN = (I2C_PWREN_KEY_UNLOCK_W | I2C_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_I2C_disablePower(I2C_Regs *i2c)
{
    i2c->GPRCM.PWREN = (I2C_PWREN_KEY_UNLOCK_W | I2C_PWREN_ENABLE_DISABLE);
}

__STATIC_INLINE bool DL_I2C_isPowerEnabled(const I2C_Regs *i2c)
{
    return (
        (i2c->GPRCM.PWREN & I2C_PWREN_ENABLE_MASK) == I2C_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_I2C_reset(I2C_Regs *i2c)
{
    i2c->GPRCM.RSTCTL =
        (I2C_RSTCTL_KEY_UNLOCK_W | I2C_RSTCTL_RESETSTKYCLR_CLR |
            I2C_RSTCTL_RESETASSERT_ASSERT);
}

__STATIC_INLINE bool DL_I2C_isReset(const I2C_Regs *i2c)
{
    return ((i2c->GPRCM.STAT & I2C_STAT_RESETSTKY_MASK) ==
            I2C_STAT_RESETSTKY_RESET);
}

__STATIC_INLINE void DL_I2C_selectClockSource(
    I2C_Regs *i2c, DL_I2C_CLOCK clockSource)
{
    DL_Common_updateReg(&i2c->CLKSEL, (uint32_t) clockSource,
        I2C_CLKSEL_BUSCLK_SEL_MASK | I2C_CLKSEL_MFCLK_SEL_MASK);
}

__STATIC_INLINE void DL_I2C_selectClockDivider(
    I2C_Regs *i2c, DL_I2C_CLOCK_DIVIDE clockDivider)
{
    DL_Common_updateReg(
        &i2c->CLKDIV, (uint32_t) clockDivider, I2C_CLKDIV_RATIO_MASK);
}

__STATIC_INLINE DL_I2C_ANALOG_GLITCH_FILTER_WIDTH
DL_I2C_getAnalogGlitchFilterPulseWidth(const I2C_Regs *i2c)
{
    uint32_t filterWidth = i2c->GFCTL & I2C_GFCTL_AGFSEL_MASK;

    return (DL_I2C_ANALOG_GLITCH_FILTER_WIDTH)(filterWidth);
}

__STATIC_INLINE void DL_I2C_setAnalogGlitchFilterPulseWidth(
    I2C_Regs *i2c, DL_I2C_ANALOG_GLITCH_FILTER_WIDTH filterWidth)
{
    DL_Common_updateReg(
        &i2c->GFCTL, (uint32_t) filterWidth, I2C_GFCTL_AGFSEL_MASK);
}

__STATIC_INLINE DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH
DL_I2C_getDigitalGlitchFilterPulseWidth(const I2C_Regs *i2c)
{
    uint32_t filterWidth = i2c->GFCTL & I2C_GFCTL_DGFSEL_MASK;

    return (DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH)(filterWidth);
}

__STATIC_INLINE void DL_I2C_setDigitalGlitchFilterPulseWidth(
    I2C_Regs *i2c, DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH filterWidth)
{
    DL_Common_updateReg(
        &i2c->GFCTL, (uint32_t) filterWidth, I2C_GFCTL_DGFSEL_MASK);
}

__STATIC_INLINE void DL_I2C_disableAnalogGlitchFilter(I2C_Regs *i2c)
{
    i2c->GFCTL &= ~(I2C_GFCTL_AGFEN_MASK);
}

__STATIC_INLINE bool DL_I2C_isAnalogGlitchFilterEnabled(const I2C_Regs *i2c)
{
    return ((i2c->GFCTL & I2C_GFCTL_AGFEN_MASK) == I2C_GFCTL_AGFEN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableAnalogGlitchFilter(I2C_Regs *i2c)
{
    i2c->GFCTL |= I2C_GFCTL_AGFEN_ENABLE;
}

__STATIC_INLINE DL_I2C_CONTROLLER_DIRECTION DL_I2C_getControllerDirection(
    const I2C_Regs *i2c)
{
    uint32_t direction = i2c->MASTER.MSA & I2C_MSA_DIR_MASK;

    return (DL_I2C_CONTROLLER_DIRECTION)(direction);
}

__STATIC_INLINE void DL_I2C_setControllerDirection(
    I2C_Regs *i2c, DL_I2C_CONTROLLER_DIRECTION direction)
{
    DL_Common_updateReg(
        &i2c->MASTER.MSA, (uint32_t) direction, I2C_MSA_DIR_MASK);
}

__STATIC_INLINE uint32_t DL_I2C_getTargetAddress(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MSA & I2C_MSA_SADDR_MASK) >> I2C_MSA_SADDR_OFS);
}

__STATIC_INLINE void DL_I2C_setTargetAddress(
    I2C_Regs *i2c, uint32_t targetAddress)
{
    DL_Common_updateReg(&i2c->MASTER.MSA, (targetAddress << I2C_MSA_SADDR_OFS),
        I2C_MSA_SADDR_MASK);
}

__STATIC_INLINE DL_I2C_CONTROLLER_ADDRESSING_MODE
DL_I2C_getControllerAddressingMode(const I2C_Regs *i2c)
{
    uint32_t mode = i2c->MASTER.MSA & I2C_MSA_MMODE_MASK;

    return (DL_I2C_CONTROLLER_ADDRESSING_MODE)(mode);
}

__STATIC_INLINE void DL_I2C_setControllerAddressingMode(
    I2C_Regs *i2c, DL_I2C_CONTROLLER_ADDRESSING_MODE mode)
{
    DL_Common_updateReg(&i2c->MASTER.MSA, (uint32_t) mode, I2C_MSA_MMODE_MASK);
}

__STATIC_INLINE void DL_I2C_disableControllerACKOverride(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR &= ~(I2C_MCTR_MACKOEN_MASK);
}

__STATIC_INLINE bool DL_I2C_isControllerACKOverrideEnabled(const I2C_Regs *i2c)
{
    return (
        (i2c->MASTER.MCTR & I2C_MCTR_MACKOEN_MASK) == I2C_MCTR_MACKOEN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableControllerACKOverride(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR |= I2C_MCTR_MACKOEN_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableControllerReadOnTXEmpty(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR &= ~(I2C_MCTR_RD_ON_TXEMPTY_MASK);
}

__STATIC_INLINE bool DL_I2C_isControllerReadOnTXEmptyEnabled(
    const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MCTR & I2C_MCTR_RD_ON_TXEMPTY_MASK) ==
            I2C_MCTR_RD_ON_TXEMPTY_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableControllerReadOnTXEmpty(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR |= I2C_MCTR_RD_ON_TXEMPTY_ENABLE;
}

__STATIC_INLINE uint32_t DL_I2C_getControllerPECCountValue(const I2C_Regs *i2c)
{
    return (i2c->MASTER.CONTROLLER_I2CPECCTL &
            I2C_CONTROLLER_I2CPECCTL_PECCNT_MASK);
}

__STATIC_INLINE void DL_I2C_setControllerPECCountValue(
    I2C_Regs *i2c, uint32_t count)
{
    DL_Common_updateReg(&i2c->MASTER.CONTROLLER_I2CPECCTL, count,
        I2C_CONTROLLER_I2CPECCTL_PECCNT_MASK);
}

__STATIC_INLINE void DL_I2C_disableControllerPEC(I2C_Regs *i2c)
{
    i2c->MASTER.CONTROLLER_I2CPECCTL &= ~(I2C_CONTROLLER_I2CPECCTL_PECEN_MASK);
}

__STATIC_INLINE bool DL_I2C_isControllerPECEnabled(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.CONTROLLER_I2CPECCTL &
                I2C_CONTROLLER_I2CPECCTL_PECEN_MASK) ==
            I2C_CONTROLLER_I2CPECCTL_PECEN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableControllerPEC(I2C_Regs *i2c)
{
    i2c->MASTER.CONTROLLER_I2CPECCTL |= I2C_CONTROLLER_I2CPECCTL_PECEN_ENABLE;
}

__STATIC_INLINE uint32_t DL_I2C_getControllerCurrentPECCount(
    const I2C_Regs *i2c)
{
    return (
        i2c->MASTER.CONTROLLER_PECSR & I2C_CONTROLLER_PECSR_PECSTS_CHECK_MASK);
}

__STATIC_INLINE DL_I2C_CONTROLLER_PEC_STATUS
DL_I2C_getControllerPECCheckedStatus(const I2C_Regs *i2c)
{
    uint32_t status =
        i2c->MASTER.CONTROLLER_PECSR & I2C_CONTROLLER_PECSR_PECSTS_CHECK_MASK;

    return (DL_I2C_CONTROLLER_PEC_STATUS)(status);
}

__STATIC_INLINE DL_I2C_CONTROLLER_PEC_CHECK_ERROR
DL_I2C_getControllerPECCheckError(const I2C_Regs *i2c)
{
    uint32_t error =
        i2c->MASTER.CONTROLLER_PECSR & I2C_CONTROLLER_PECSR_PECSTS_ERROR_MASK;

    return (DL_I2C_CONTROLLER_PEC_CHECK_ERROR)(error);
}

__STATIC_INLINE void DL_I2C_disableControllerBurst(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR &= ~(I2C_MCTR_BURSTRUN_MASK);
}

__STATIC_INLINE bool DL_I2C_isControllerBurstEnabled(const I2C_Regs *i2c)
{
    return ((i2c->GFCTL & I2C_MCTR_BURSTRUN_MASK) == I2C_MCTR_BURSTRUN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableControllerBurst(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR |= I2C_MCTR_BURSTRUN_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableStartCondition(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR &= ~(I2C_MCTR_START_MASK);
}

__STATIC_INLINE bool DL_I2C_isStartConditionEnabled(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MCTR & I2C_MCTR_START_MASK) == I2C_MCTR_START_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableStartCondition(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR |= I2C_MCTR_START_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableStopCondition(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR &= ~(I2C_MCTR_STOP_MASK);
}

__STATIC_INLINE bool DL_I2C_isStopConditionEnabled(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MCTR & I2C_MCTR_STOP_MASK) == I2C_MCTR_STOP_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableStopCondition(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR |= I2C_MCTR_STOP_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableControllerACK(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR &= ~(I2C_MCTR_ACK_MASK);
}

__STATIC_INLINE bool DL_I2C_isControllerACKEnabled(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MCTR & I2C_MCTR_ACK_MASK) == I2C_MCTR_ACK_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableControllerACK(I2C_Regs *i2c)
{
    i2c->MASTER.MCTR |= I2C_MCTR_ACK_MASK;
}

__STATIC_INLINE uint32_t DL_I2C_getTransactionLength(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MCTR & I2C_MCTR_MBLEN_MASK) >> I2C_MCTR_MBLEN_OFS);
}

__STATIC_INLINE void DL_I2C_setTransactionLength(
    I2C_Regs *i2c, uint32_t length)
{
    DL_Common_updateReg(&i2c->MASTER.MCTR, (length << I2C_MCTR_MBLEN_OFS),
        I2C_MCTR_MBLEN_MASK);
}

__STATIC_INLINE uint32_t DL_I2C_getControllerStatus(const I2C_Regs *i2c)
{
    return (i2c->MASTER.MSR);
}

__STATIC_INLINE uint16_t DL_I2C_getTransactionCount(const I2C_Regs *i2c)
{
    return ((uint16_t)(
        (i2c->MASTER.MSR & I2C_MSR_MBCNT_MASK) >> I2C_MSR_MBCNT_OFS));
}

__STATIC_INLINE uint8_t DL_I2C_receiveControllerData(const I2C_Regs *i2c)
{
    return ((uint8_t)(i2c->MASTER.MRXDATA & I2C_MRXDATA_VALUE_MASK));
}

__STATIC_INLINE void DL_I2C_transmitControllerData(I2C_Regs *i2c, uint8_t data)
{
    i2c->MASTER.MTXDATA = data;
}

__STATIC_INLINE uint8_t DL_I2C_getTimerPeriod(const I2C_Regs *i2c)
{
    return ((uint8_t)(i2c->MASTER.MTPR & I2C_MTPR_TPR_MASK));
}

__STATIC_INLINE void DL_I2C_setTimerPeriod(I2C_Regs *i2c, uint8_t period)
{
    i2c->MASTER.MTPR = period;
}

__STATIC_INLINE void DL_I2C_disableLoopbackMode(I2C_Regs *i2c)
{
    i2c->MASTER.MCR &= ~(I2C_MCR_LPBK_MASK);
}

__STATIC_INLINE bool DL_I2C_isLoopbackModeEnabled(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MCR & I2C_MCR_LPBK_MASK) == I2C_MCR_LPBK_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableLoopbackMode(I2C_Regs *i2c)
{
    i2c->MASTER.MCR |= I2C_MCR_LPBK_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableMultiControllerMode(I2C_Regs *i2c)
{
    i2c->MASTER.MCR &= ~(I2C_MCR_MMST_MASK);
}

__STATIC_INLINE bool DL_I2C_isMultiControllerModeEnabled(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MCR & I2C_MCR_MMST_MASK) == I2C_MCR_MMST_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableMultiControllerMode(I2C_Regs *i2c)
{
    i2c->MASTER.MCR |= I2C_MCR_MMST_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableController(I2C_Regs *i2c)
{
    i2c->MASTER.MCR &= ~(I2C_MCR_ACTIVE_MASK);
}

__STATIC_INLINE bool DL_I2C_isControllerEnabled(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MCR & I2C_MCR_ACTIVE_MASK) == I2C_MCR_ACTIVE_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableController(I2C_Regs *i2c)
{
    i2c->MASTER.MCR |= I2C_MCR_ACTIVE_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableControllerClockStretching(I2C_Regs *i2c)
{
    i2c->MASTER.MCR &= ~(I2C_MCR_CLKSTRETCH_MASK);
}

__STATIC_INLINE bool DL_I2C_isControllerClockStretchingEnabled(
    const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MCR & I2C_MCR_CLKSTRETCH_MASK) ==
            I2C_MCR_CLKSTRETCH_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableControllerClockStretching(I2C_Regs *i2c)
{
    i2c->MASTER.MCR |= I2C_MCR_CLKSTRETCH_ENABLE;
}

__STATIC_INLINE DL_I2C_CONTROLLER_SCL DL_I2C_getSCLStatus(const I2C_Regs *i2c)
{
    uint32_t sclStatus = i2c->MASTER.MBMON & I2C_MBMON_SCL_MASK;

    return (DL_I2C_CONTROLLER_SCL)(sclStatus);
}

__STATIC_INLINE DL_I2C_CONTROLLER_SDA DL_I2C_getSDAStatus(const I2C_Regs *i2c)
{
    uint32_t sdaStatus = i2c->MASTER.MBMON & I2C_MBMON_SDA_MASK;

    return (DL_I2C_CONTROLLER_SDA)(sdaStatus);
}

__STATIC_INLINE DL_I2C_TX_FIFO_LEVEL DL_I2C_getControllerTXFIFOThreshold(
    const I2C_Regs *i2c)
{
    uint32_t level = i2c->MASTER.MFIFOCTL & I2C_MFIFOCTL_TXTRIG_MASK;

    return (DL_I2C_TX_FIFO_LEVEL)(level);
}

__STATIC_INLINE void DL_I2C_setControllerTXFIFOThreshold(
    I2C_Regs *i2c, DL_I2C_TX_FIFO_LEVEL level)
{
    DL_Common_updateReg(
        &i2c->MASTER.MFIFOCTL, (uint32_t) level, I2C_MFIFOCTL_TXTRIG_MASK);
}

__STATIC_INLINE void DL_I2C_stopFlushControllerTXFIFO(I2C_Regs *i2c)
{
    i2c->MASTER.MFIFOCTL &= ~(I2C_MFIFOCTL_TXFLUSH_MASK);
}

__STATIC_INLINE void DL_I2C_startFlushControllerTXFIFO(I2C_Regs *i2c)
{
    i2c->MASTER.MFIFOCTL |= I2C_MFIFOCTL_TXFLUSH_MASK;
}

__STATIC_INLINE DL_I2C_RX_FIFO_LEVEL DL_I2C_getControllerRXFIFOThreshold(
    const I2C_Regs *i2c)
{
    uint32_t level = i2c->MASTER.MFIFOCTL & I2C_MFIFOCTL_RXTRIG_MASK;

    return (DL_I2C_RX_FIFO_LEVEL)(level);
}

__STATIC_INLINE void DL_I2C_setControllerRXFIFOThreshold(
    I2C_Regs *i2c, DL_I2C_RX_FIFO_LEVEL level)
{
    DL_Common_updateReg(
        &i2c->MASTER.MFIFOCTL, (uint32_t) level, I2C_MFIFOCTL_RXTRIG_MASK);
}

__STATIC_INLINE void DL_I2C_stopFlushControllerRXFIFO(I2C_Regs *i2c)
{
    i2c->MASTER.MFIFOCTL &= ~(I2C_MFIFOCTL_RXFLUSH_MASK);
}

__STATIC_INLINE void DL_I2C_startFlushControllerRXFIFO(I2C_Regs *i2c)
{
    i2c->MASTER.MFIFOCTL |= I2C_MFIFOCTL_RXFLUSH_MASK;
}

__STATIC_INLINE uint32_t DL_I2C_getControllerRXFIFOCounter(const I2C_Regs *i2c)
{
    return (i2c->MASTER.MFIFOSR & I2C_MFIFOSR_RXFIFOCNT_MASK);
}

__STATIC_INLINE uint32_t DL_I2C_getControllerTXFIFOCounter(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_TXFIFOCNT_MASK) >>
            I2C_MFIFOSR_TXFIFOCNT_OFS);
}

__STATIC_INLINE bool DL_I2C_isControllerRXFIFOFlushActive(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_RXFLUSH_MASK) ==
            I2C_MFIFOSR_RXFLUSH_ACTIVE);
}

__STATIC_INLINE bool DL_I2C_isControllerTXFIFOFlushActive(const I2C_Regs *i2c)
{
    return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_TXFLUSH_MASK) ==
            I2C_MFIFOSR_TXFLUSH_ACTIVE);
}

__STATIC_INLINE void DL_I2C_setTargetOwnAddress(I2C_Regs *i2c, uint32_t addr)
{
    DL_Common_updateReg(&i2c->SLAVE.SOAR, addr, I2C_SOAR_OAR_MASK);
}

__STATIC_INLINE uint32_t DL_I2C_getTargetOwnAddress(const I2C_Regs *i2c)
{
    return (i2c->SLAVE.SOAR & I2C_SOAR_OAR_MASK);
}

__STATIC_INLINE void DL_I2C_enableTargetOwnAddress(I2C_Regs *i2c)
{
    i2c->SLAVE.SOAR |= I2C_SOAR_OAREN_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableTargetOwnAddress(I2C_Regs *i2c)
{
    i2c->SLAVE.SOAR &= ~(I2C_SOAR_OAREN_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetOwnAddressEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SOAR & I2C_SOAR_OAREN_MASK) == I2C_SOAR_OAREN_ENABLE);
}

__STATIC_INLINE void DL_I2C_setTargetAddressingMode(
    I2C_Regs *i2c, DL_I2C_TARGET_ADDRESSING_MODE mode)
{
    DL_Common_updateReg(
        &i2c->SLAVE.SOAR, (uint32_t) mode, I2C_SOAR_SMODE_MASK);
}

__STATIC_INLINE DL_I2C_TARGET_ADDRESSING_MODE DL_I2C_getTargetAddressingMode(
    const I2C_Regs *i2c)
{
    uint32_t mode = i2c->SLAVE.SOAR & I2C_SOAR_SMODE_MASK;

    return (DL_I2C_TARGET_ADDRESSING_MODE)(mode);
}

__STATIC_INLINE uint32_t I2C_getTargetOwnAddressAlternate(const I2C_Regs *i2c)
{
    return (i2c->SLAVE.SOAR2 & I2C_SOAR2_OAR2_MASK);
}

__STATIC_INLINE void DL_I2C_setTargetOwnAddressAlternate(
    I2C_Regs *i2c, uint32_t addr)
{
    DL_Common_updateReg(&i2c->SLAVE.SOAR2, addr, I2C_SOAR2_OAR2_MASK);
}

__STATIC_INLINE uint32_t I2C_getTargetOwnAddressAlternateMask(
    const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SOAR2 & I2C_SOAR2_OAR2_MASK_MASK) >>
            I2C_SOAR2_OAR2_MASK_OFS);
}

__STATIC_INLINE void DL_I2C_setTargetOwnAddressAlternateMask(
    I2C_Regs *i2c, uint32_t addressMask)
{
    DL_Common_updateReg(&i2c->SLAVE.SOAR2,
        addressMask << I2C_SOAR2_OAR2_MASK_OFS, I2C_SOAR2_OAR2_MASK_MASK);
}

__STATIC_INLINE void DL_I2C_disableTargetOwnAddressAlternate(I2C_Regs *i2c)
{
    i2c->SLAVE.SOAR2 &= ~(I2C_SOAR2_OAR2EN_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetOwnAddressAlternateEnabled(
    const I2C_Regs *i2c)
{
    return (
        (i2c->SLAVE.SOAR2 & I2C_SOAR2_OAR2EN_MASK) == I2C_SOAR2_OAR2EN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTargetOwnAddressAlternate(I2C_Regs *i2c)
{
    i2c->SLAVE.SOAR2 |= I2C_SOAR2_OAR2EN_ENABLE;
}

__STATIC_INLINE uint32_t DL_I2C_getTargetAddressMatch(const I2C_Regs *i2c)
{
    return (
        (i2c->SLAVE.SSR & I2C_SSR_ADDRMATCH_MASK) >> I2C_SSR_ADDRMATCH_OFS);
}

__STATIC_INLINE void DL_I2C_disableTargetClockStretching(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_SCLKSTRETCH_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetClockStretchingEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SCTR & I2C_SCTR_SCLKSTRETCH_MASK) ==
            I2C_SCTR_SCLKSTRETCH_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTargetClockStretching(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_SCLKSTRETCH_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableTargetTXEmptyOnTXRequest(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_TXEMPTY_ON_TREQ_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetTXEmptyOnTXRequestEnabled(
    const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SCTR & I2C_SCTR_TXEMPTY_ON_TREQ_MASK) ==
            I2C_SCTR_TXEMPTY_ON_TREQ_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTargetTXEmptyOnTXRequest(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_TXEMPTY_ON_TREQ_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableTargetTXTriggerInTXMode(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_TXTRIG_TXMODE_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetTXTriggerInTXModeEnabled(
    const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SCTR & I2C_SCTR_TXTRIG_TXMODE_MASK) ==
            I2C_SCTR_TXTRIG_TXMODE_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTargetTXTriggerInTXMode(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_TXTRIG_TXMODE_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableTargetTXWaitWhenTXFIFOStale(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_TXWAIT_STALE_TXFIFO_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetTXWaitWhenTXFIFOStaleEnabled(
    const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SCTR & I2C_SCTR_TXWAIT_STALE_TXFIFO_MASK) ==
            I2C_SCTR_TXWAIT_STALE_TXFIFO_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTargetTXWaitWhenTXFIFOStale(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_TXWAIT_STALE_TXFIFO_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableTargetRXFullOnRXRequest(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_RXFULL_ON_RREQ_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetRXFullOnRXRequestEnabled(
    const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SCTR & I2C_SCTR_RXFULL_ON_RREQ_MASK) ==
            I2C_SCTR_RXFULL_ON_RREQ_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTargetRXFullOnRXRequest(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_RXFULL_ON_RREQ_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableDefaultHostAddress(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_EN_DEFHOSTADR_MASK);
}

__STATIC_INLINE bool DL_I2C_isDefaultHostAddressEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SCTR & I2C_SCTR_EN_DEFHOSTADR_MASK) ==
            I2C_SCTR_EN_DEFHOSTADR_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableDefaultHostAddress(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_EN_DEFHOSTADR_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableAlertResponseAddress(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_EN_ALRESPADR_MASK);
}

__STATIC_INLINE bool DL_I2C_isAlertResponseAddressEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SCTR & I2C_SCTR_EN_ALRESPADR_MASK) ==
            I2C_SCTR_EN_ALRESPADR_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableAlertResponseAddress(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_EN_ALRESPADR_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableDefaultDeviceAddress(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_EN_DEFDEVADR_MASK);
}

__STATIC_INLINE bool DL_I2C_isDefaultDeviceAddressEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SCTR & I2C_SCTR_EN_DEFDEVADR_MASK) ==
            I2C_SCTR_EN_DEFDEVADR_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableDefaultDeviceAddress(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_EN_DEFDEVADR_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableTargetWakeup(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_SWUEN_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetWakeupEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SCTR & I2C_SCTR_SWUEN_MASK) == I2C_SCTR_SWUEN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTargetWakeup(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_SWUEN_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableTarget(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_ACTIVE_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetEnabled(const I2C_Regs *i2c)
{
    return (
        (i2c->SLAVE.SCTR & I2C_SCTR_ACTIVE_MASK) == I2C_SCTR_ACTIVE_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTarget(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_ACTIVE_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableGeneralCall(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR &= ~(I2C_SCTR_GENCALL_MASK);
}

__STATIC_INLINE bool DL_I2C_isGeneralCallEnabled(const I2C_Regs *i2c)
{
    return (
        (i2c->SLAVE.SCTR & I2C_SCTR_GENCALL_MASK) == I2C_SCTR_GENCALL_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableGeneralCall(I2C_Regs *i2c)
{
    i2c->SLAVE.SCTR |= I2C_SCTR_GENCALL_ENABLE;
}

__STATIC_INLINE uint32_t DL_I2C_getTargetStatus(const I2C_Regs *i2c)
{
    return (i2c->SLAVE.SSR);
}

__STATIC_INLINE uint8_t DL_I2C_receiveTargetData(const I2C_Regs *i2c)
{
    return (uint8_t)(i2c->SLAVE.SRXDATA & I2C_SRXDATA_VALUE_MASK);
}

__STATIC_INLINE void DL_I2C_transmitTargetData(I2C_Regs *i2c, uint8_t data)
{
    i2c->SLAVE.STXDATA = data;
}

__STATIC_INLINE void DL_I2C_disableTargetACKOverride(I2C_Regs *i2c)
{
    i2c->SLAVE.SACKCTL &= ~(I2C_SACKCTL_ACKOEN_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetACKOverrideEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SACKCTL & I2C_SACKCTL_ACKOEN_MASK) ==
            I2C_SACKCTL_ACKOEN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTargetACKOverride(I2C_Regs *i2c)
{
    i2c->SLAVE.SACKCTL |= I2C_SACKCTL_ACKOEN_ENABLE;
}

__STATIC_INLINE DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE
DL_I2C_getTargetACKOverrideValue(const I2C_Regs *i2c)
{
    uint32_t value = i2c->SLAVE.SACKCTL & I2C_SACKCTL_ACKOVAL_MASK;

    return (DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE)(value);
}

__STATIC_INLINE void DL_I2C_setTargetACKOverrideValue(
    I2C_Regs *i2c, DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE value)
{
    DL_Common_updateReg(
        &i2c->SLAVE.SACKCTL, (uint32_t) value, I2C_SACKCTL_ACKOVAL_MASK);
}

__STATIC_INLINE void DL_I2C_disableACKOverrideOnStart(I2C_Regs *i2c)
{
    i2c->SLAVE.SACKCTL &= ~(I2C_SACKCTL_ACKOEN_ON_START_MASK);
}

__STATIC_INLINE bool DL_I2C_isACKOverrideOnStartEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SACKCTL & I2C_SACKCTL_ACKOEN_ON_START_MASK) ==
            I2C_SACKCTL_ACKOEN_ON_START_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableACKOverrideOnStart(I2C_Regs *i2c)
{
    i2c->SLAVE.SACKCTL |= I2C_SACKCTL_ACKOEN_ON_START_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableACKOverrideOnPECNext(I2C_Regs *i2c)
{
    i2c->SLAVE.SACKCTL &= ~(I2C_SACKCTL_ACKOEN_ON_PECNEXT_MASK);
}

__STATIC_INLINE bool DL_I2C_isACKOverrideOnPECNextEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SACKCTL & I2C_SACKCTL_ACKOEN_ON_PECNEXT_MASK) ==
            I2C_SACKCTL_ACKOEN_ON_PECNEXT_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableACKOverrideOnPECNext(I2C_Regs *i2c)
{
    i2c->SLAVE.SACKCTL |= I2C_SACKCTL_ACKOEN_ON_PECNEXT_ENABLE;
}

__STATIC_INLINE void DL_I2C_disableACKOverrideOnPECDone(I2C_Regs *i2c)
{
    i2c->SLAVE.SACKCTL &= ~(I2C_SACKCTL_ACKOEN_ON_PECDONE_MASK);
}

__STATIC_INLINE bool DL_I2C_isACKOverrideOnPECDoneEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SACKCTL & I2C_SACKCTL_ACKOEN_ON_PECDONE_MASK) ==
            I2C_SACKCTL_ACKOEN_ON_PECDONE_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableACKOverrideOnPECDone(I2C_Regs *i2c)
{
    i2c->SLAVE.SACKCTL |= I2C_SACKCTL_ACKOEN_ON_PECDONE_ENABLE;
}

__STATIC_INLINE uint32_t DL_I2C_getTargetPECCountValue(const I2C_Regs *i2c)
{
    return (i2c->SLAVE.TARGET_PECCTL & I2C_TARGET_PECCTL_PECCNT_MASK);
}

__STATIC_INLINE void DL_I2C_setTargetPECCountValue(
    I2C_Regs *i2c, uint32_t count)
{
    DL_Common_updateReg(
        &i2c->SLAVE.TARGET_PECCTL, count, I2C_TARGET_PECCTL_PECCNT_MASK);
}

__STATIC_INLINE void DL_I2C_disableTargetPEC(I2C_Regs *i2c)
{
    i2c->SLAVE.TARGET_PECCTL &= ~(I2C_TARGET_PECCTL_PECEN_MASK);
}

__STATIC_INLINE bool DL_I2C_isTargetPECEnabled(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.TARGET_PECCTL & I2C_TARGET_PECCTL_PECEN_MASK) ==
            I2C_TARGET_PECCTL_PECEN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTargetPEC(I2C_Regs *i2c)
{
    i2c->SLAVE.TARGET_PECCTL |= I2C_TARGET_PECCTL_PECEN_ENABLE;
}

__STATIC_INLINE uint32_t DL_I2C_getTargetCurrentPECCount(const I2C_Regs *i2c)
{
    return (i2c->SLAVE.TARGET_PECCTL & I2C_TARGET_PECSR_PECBYTECNT_MASK);
}

__STATIC_INLINE DL_I2C_TARGET_PEC_STATUS DL_I2C_getTargetPECCheckedStatus(
    const I2C_Regs *i2c)
{
    uint32_t status =
        i2c->SLAVE.TARGET_PECSR & I2C_TARGET_PECSR_PECSTS_CHECK_MASK;

    return (DL_I2C_TARGET_PEC_STATUS)(status);
}

__STATIC_INLINE DL_I2C_TARGET_PEC_CHECK_ERROR DL_I2C_getTargetPECCheckError(
    const I2C_Regs *i2c)
{
    uint32_t status =
        i2c->SLAVE.TARGET_PECSR & I2C_TARGET_PECSR_PECSTS_ERROR_MASK;

    return (DL_I2C_TARGET_PEC_CHECK_ERROR)(status);
}

__STATIC_INLINE DL_I2C_TX_FIFO_LEVEL DL_I2C_getTargetTXFIFOThreshold(
    const I2C_Regs *i2c)
{
    uint32_t level = i2c->SLAVE.SFIFOCTL & I2C_SFIFOCTL_TXTRIG_MASK;

    return (DL_I2C_TX_FIFO_LEVEL)(level);
}

__STATIC_INLINE void DL_I2C_setTargetTXFIFOThreshold(
    I2C_Regs *i2c, DL_I2C_TX_FIFO_LEVEL level)
{
    DL_Common_updateReg(&i2c->SLAVE.SFIFOCTL, (uint32_t) level,
        (uint32_t) I2C_SFIFOCTL_TXTRIG_MASK);
}

__STATIC_INLINE void DL_I2C_stopFlushTargetTXFIFO(I2C_Regs *i2c)
{
    i2c->SLAVE.SFIFOCTL &= ~(I2C_SFIFOCTL_TXFLUSH_MASK);
}

__STATIC_INLINE void DL_I2C_startFlushTargetTXFIFO(I2C_Regs *i2c)
{
    i2c->SLAVE.SFIFOCTL |= I2C_SFIFOCTL_TXFLUSH_MASK;
}

__STATIC_INLINE void DL_I2C_stopFlushTargetRXFIFO(I2C_Regs *i2c)
{
    i2c->SLAVE.SFIFOCTL &= ~(I2C_SFIFOCTL_RXFLUSH_MASK);
}

__STATIC_INLINE void DL_I2C_startFlushTargetRXFIFO(I2C_Regs *i2c)
{
    i2c->SLAVE.SFIFOCTL |= I2C_SFIFOCTL_RXFLUSH_MASK;
}

__STATIC_INLINE DL_I2C_RX_FIFO_LEVEL DL_I2C_getTargetRXFIFOThreshold(
    const I2C_Regs *i2c)
{
    uint32_t level = i2c->SLAVE.SFIFOCTL & I2C_SFIFOCTL_RXTRIG_MASK;

    return (DL_I2C_RX_FIFO_LEVEL)(level);
}

__STATIC_INLINE void DL_I2C_setTargetRXFIFOThreshold(
    I2C_Regs *i2c, DL_I2C_RX_FIFO_LEVEL level)
{
    DL_Common_updateReg(
        &i2c->SLAVE.SFIFOCTL, (uint32_t) level, I2C_SFIFOCTL_RXTRIG_MASK);
}

__STATIC_INLINE uint32_t DL_I2C_getTargetRXFIFOCounter(const I2C_Regs *i2c)
{
    return (i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_RXFIFOCNT_MASK);
}

__STATIC_INLINE uint32_t DL_I2C_getTargetTXFIFOCounter(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_TXFIFOCNT_MASK) >>
            I2C_SFIFOSR_TXFIFOCNT_OFS);
}

__STATIC_INLINE bool DL_I2C_isTargetRXFIFOFlushActive(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_RXFLUSH_MASK) ==
            I2C_SFIFOSR_RXFLUSH_ACTIVE);
}

__STATIC_INLINE bool DL_I2C_isTargetTXFIFOFlushActive(const I2C_Regs *i2c)
{
    return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_TXFLUSH_MASK) ==
            I2C_SFIFOSR_TXFLUSH_ACTIVE);
}

__STATIC_INLINE void DL_I2C_enableInterrupt(
    I2C_Regs *i2c, uint32_t interruptMask)
{
    i2c->CPU_INT.IMASK |= interruptMask;
}

__STATIC_INLINE void DL_I2C_disableInterrupt(
    I2C_Regs *i2c, uint32_t interruptMask)
{
    i2c->CPU_INT.IMASK &= ~(interruptMask);
}

__STATIC_INLINE uint32_t DL_I2C_getEnabledInterrupts(
    const I2C_Regs *i2c, uint32_t interruptMask)
{
    return (i2c->CPU_INT.IMASK & interruptMask);
}

__STATIC_INLINE uint32_t DL_I2C_getEnabledInterruptStatus(
    const I2C_Regs *i2c, uint32_t interruptMask)
{
    return (i2c->CPU_INT.MIS & interruptMask);
}

__STATIC_INLINE uint32_t DL_I2C_getRawInterruptStatus(
    const I2C_Regs *i2c, uint32_t interruptMask)
{
    return (i2c->CPU_INT.RIS & interruptMask);
}

__STATIC_INLINE DL_I2C_IIDX DL_I2C_getPendingInterrupt(const I2C_Regs *i2c)
{
    return ((DL_I2C_IIDX) i2c->CPU_INT.IIDX);
}

__STATIC_INLINE void DL_I2C_clearInterruptStatus(
    I2C_Regs *i2c, uint32_t interruptMask)
{
    i2c->CPU_INT.ICLR = interruptMask;
}

__STATIC_INLINE void DL_I2C_enableDMAEvent(
    I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interrupt)
{
    switch (index) {
        case DL_I2C_EVENT_ROUTE_1:
            i2c->DMA_TRIG1.IMASK = interrupt;
            break;
        case DL_I2C_EVENT_ROUTE_2:
            i2c->DMA_TRIG0.IMASK = interrupt;
            break;
        default:
            break;
    }
}

__STATIC_INLINE void DL_I2C_disableDMAEvent(
    I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interrupt)
{
    switch (index) {
        case DL_I2C_EVENT_ROUTE_1:
            i2c->DMA_TRIG1.IMASK &= ~(interrupt);
            break;
        case DL_I2C_EVENT_ROUTE_2:
            i2c->DMA_TRIG0.IMASK &= ~(interrupt);
            break;
        default:
            break;
    }
}

__STATIC_INLINE uint32_t DL_I2C_getEnabledDMAEvents(
    I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interruptMask)
{
    volatile uint32_t *pReg = &i2c->DMA_TRIG1.IMASK;

    return ((*(pReg + (uint32_t) index) & interruptMask));
}

__STATIC_INLINE uint32_t DL_I2C_getEnabledDMAEventStatus(
    const I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interruptMask)
{
    const volatile uint32_t *pReg = &i2c->DMA_TRIG1.MIS;

    return ((*(pReg + (uint32_t) index) & interruptMask));
}

__STATIC_INLINE uint32_t DL_I2C_getRawDMAEventStatus(
    const I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interruptMask)
{
    const volatile uint32_t *pReg = &i2c->DMA_TRIG1.RIS;

    return ((*(pReg + (uint32_t) index) & interruptMask));
}

__STATIC_INLINE DL_I2C_DMA_IIDX DL_I2C_getPendingDMAEvent(
    const I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index)
{
    const volatile uint32_t *pReg = &i2c->DMA_TRIG1.IIDX;

    return (DL_I2C_DMA_IIDX)((*(pReg + (uint32_t) index)));
}

__STATIC_INLINE void DL_I2C_clearDMAEvent(
    I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interrupt)
{
    switch (index) {
        case DL_I2C_EVENT_ROUTE_1:
            i2c->DMA_TRIG1.ICLR |= interrupt;
            break;
        case DL_I2C_EVENT_ROUTE_2:
            i2c->DMA_TRIG0.ICLR |= interrupt;
            break;
        default:
            break;
    }
}

__STATIC_INLINE void DL_I2C_disableGlitchFilterChaining(I2C_Regs *i2c)
{
    i2c->GFCTL &= ~(I2C_GFCTL_CHAIN_MASK);
}

__STATIC_INLINE bool DL_I2C_isGlitchFilterChainingEnabled(const I2C_Regs *i2c)
{
    return ((i2c->GFCTL & I2C_GFCTL_CHAIN_MASK) == I2C_GFCTL_CHAIN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableGlitchFilterChaining(I2C_Regs *i2c)
{
    i2c->GFCTL |= I2C_GFCTL_CHAIN_ENABLE;
}

__STATIC_INLINE uint32_t DL_I2C_getTimeoutACount(const I2C_Regs *i2c)
{
    return (i2c->TIMEOUT_CTL & I2C_TIMEOUT_CTL_TCNTLA_MASK);
}

__STATIC_INLINE void DL_I2C_setTimeoutACount(I2C_Regs *i2c, uint32_t count)
{
    DL_Common_updateReg(&i2c->TIMEOUT_CTL, count, I2C_TIMEOUT_CTL_TCNTLA_MASK);
}

__STATIC_INLINE void DL_I2C_disableTimeoutA(I2C_Regs *i2c)
{
    i2c->TIMEOUT_CTL &= ~(I2C_TIMEOUT_CTL_TCNTAEN_MASK);
}

__STATIC_INLINE bool DL_I2C_isTimeoutAEnabled(const I2C_Regs *i2c)
{
    return ((i2c->TIMEOUT_CTL & I2C_TIMEOUT_CTL_TCNTAEN_MASK) ==
            I2C_TIMEOUT_CTL_TCNTAEN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTimeoutA(I2C_Regs *i2c)
{
    i2c->TIMEOUT_CTL |= I2C_TIMEOUT_CTL_TCNTAEN_ENABLE;
}

__STATIC_INLINE uint32_t DL_I2C_getCurrentTimeoutACounter(const I2C_Regs *i2c)
{
    return (i2c->TIMEOUT_CNT & I2C_TIMEOUT_CNT_TCNTA_MASK);
}

__STATIC_INLINE uint32_t DL_I2C_getTimeoutBCount(const I2C_Regs *i2c)
{
    return ((i2c->TIMEOUT_CTL & I2C_TIMEOUT_CTL_TCNTLB_MASK) >>
            I2C_TIMEOUT_CTL_TCNTLB_OFS);
}

__STATIC_INLINE void DL_I2C_setTimeoutBCount(I2C_Regs *i2c, uint32_t count)
{
    DL_Common_updateReg(&i2c->TIMEOUT_CTL,
        (count << I2C_TIMEOUT_CTL_TCNTLB_OFS), I2C_TIMEOUT_CTL_TCNTLB_MASK);
}

__STATIC_INLINE void DL_I2C_disableTimeoutB(I2C_Regs *i2c)
{
    i2c->TIMEOUT_CTL &= ~(I2C_TIMEOUT_CTL_TCNTBEN_MASK);
}

__STATIC_INLINE bool DL_I2C_isTimeoutBEnabled(const I2C_Regs *i2c)
{
    return ((i2c->TIMEOUT_CTL & I2C_TIMEOUT_CTL_TCNTBEN_MASK) ==
            I2C_TIMEOUT_CTL_TCNTBEN_ENABLE);
}

__STATIC_INLINE void DL_I2C_enableTimeoutB(I2C_Regs *i2c)
{
    i2c->TIMEOUT_CTL |= I2C_TIMEOUT_CTL_TCNTBEN_ENABLE;
}

__STATIC_INLINE uint32_t DL_I2C_getCurrentTimeoutBCounter(const I2C_Regs *i2c)
{
    return (i2c->TIMEOUT_CNT & I2C_TIMEOUT_CNT_TCNTB_MASK);
}

#ifdef __cplusplus
}
#endif

#endif /* __MSPM0_HAS_I2C__ */

#endif /* ti_dl_dl_i2c__include */