dl_factoryregion.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/*!****************************************************************************
 *  @file       dl_factoryregion.h
 *  @brief      Factory Region Driver Library
 *  @defgroup   FACTORYREGION Factory Region (FACTORYREGION)
 *
 *  @anchor ti_dl_dl_factoryregion_Overview
 *  # Overview
 *
 *  <hr>
 ******************************************************************************
 */
#ifndef ti_dl_dl_factoryregion__include
#define ti_dl_dl_factoryregion__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>
#include <ti/driverlib/m0p/dl_core.h>

#ifdef __cplusplus
extern "C" {
#endif

#ifdef __MSPM0GX51X_TRIM_CACHE__

#define DL_FACTORYREGION_TRIM_FLAG_IS_SET (0xCAFECAFE)

typedef struct {
    uint32_t TRACEID;
    uint32_t DEVICEID;
    uint32_t USERID;
    uint32_t BSLPIN_UART;
    uint32_t BSLPIN_I2C;
    uint32_t BSLPIN_INVOKE;
    uint32_t SRAMFLASH;
    uint32_t PLLSTARTUP0_4_8MHZ;
    uint32_t PLLSTARTUP1_4_8MHZ;
    uint32_t PLLSTARTUP0_8_16MHZ;
    uint32_t PLLSTARTUP1_8_16MHZ;
    uint32_t PLLSTARTUP0_16_32MHZ;
    uint32_t PLLSTARTUP1_16_32MHZ;
    uint32_t PLLSTARTUP0_32_48MHZ;
    uint32_t PLLSTARTUP1_32_48MHZ;
    uint32_t TEMP_SENSE0;
    uint32_t DATA_SET;
} DL_FACTORYREGION_TrimValues;

extern DL_FACTORYREGION_TrimValues *FACTORYVALUE;

__STATIC_INLINE bool DL_FactoryRegion_isTrimTableInSram(void)
{
    return (FACTORYVALUE->DATA_SET == DL_FACTORYREGION_TRIM_FLAG_IS_SET);
}
#endif

__STATIC_INLINE uint16_t DL_FactoryRegion_getMAINFlashSize(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint16_t flashSize;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        flashSize = FACTORYVALUE->SRAMFLASH &
                    FACTORYREGION_SRAMFLASH_MAINFLASH_SZ_MASK;
    } else {
        flashSize = FACTORYREGION->SRAMFLASH &
                    FACTORYREGION_SRAMFLASH_MAINFLASH_SZ_MASK;
    }
#else
    uint16_t flashSize =
        FACTORYREGION->SRAMFLASH & FACTORYREGION_SRAMFLASH_MAINFLASH_SZ_MASK;
#endif
    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return flashSize;
}

__STATIC_INLINE uint16_t DL_FactoryRegion_getSRAMFlashSize(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint16_t flashSize;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        flashSize =
            (FACTORYVALUE->SRAMFLASH & FACTORYREGION_SRAMFLASH_SRAM_SZ_MASK) >>
            FACTORYREGION_SRAMFLASH_SRAM_SZ_OFS;
    } else {
        flashSize = (FACTORYREGION->SRAMFLASH &
                        FACTORYREGION_SRAMFLASH_SRAM_SZ_MASK) >>
                    FACTORYREGION_SRAMFLASH_SRAM_SZ_OFS;
    }
#else
    uint16_t flashSize =
        (FACTORYREGION->SRAMFLASH & FACTORYREGION_SRAMFLASH_SRAM_SZ_MASK) >>
        FACTORYREGION_SRAMFLASH_SRAM_SZ_OFS;
#endif
    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return flashSize;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getDATAFlashSize(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint16_t flashSize;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        flashSize = (FACTORYVALUE->SRAMFLASH &
                        FACTORYREGION_SRAMFLASH_DATAFLASH_SZ_MASK) >>
                    FACTORYREGION_SRAMFLASH_DATAFLASH_SZ_OFS;
    } else {
        flashSize = (FACTORYREGION->SRAMFLASH &
                        FACTORYREGION_SRAMFLASH_DATAFLASH_SZ_MASK) >>
                    FACTORYREGION_SRAMFLASH_DATAFLASH_SZ_OFS;
    }
#else
    uint16_t flashSize = (FACTORYREGION->SRAMFLASH &
                             FACTORYREGION_SRAMFLASH_DATAFLASH_SZ_MASK) >>
                         FACTORYREGION_SRAMFLASH_DATAFLASH_SZ_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return flashSize;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getNumBanks(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t numBanks;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        numBanks = ((FACTORYVALUE->SRAMFLASH &
                        FACTORYREGION_SRAMFLASH_MAINNUMBANKS_MASK) >>
                       FACTORYREGION_SRAMFLASH_MAINNUMBANKS_OFS) +
                   (uint8_t) 1;
    } else {
        numBanks = ((FACTORYREGION->SRAMFLASH &
                        FACTORYREGION_SRAMFLASH_MAINNUMBANKS_MASK) >>
                       FACTORYREGION_SRAMFLASH_MAINNUMBANKS_OFS) +
                   (uint8_t) 1;
    }
#else
    uint8_t numBanks = ((FACTORYREGION->SRAMFLASH &
                            FACTORYREGION_SRAMFLASH_MAINNUMBANKS_MASK) >>
                           FACTORYREGION_SRAMFLASH_MAINNUMBANKS_OFS) +
                       (uint8_t) 1;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return numBanks;
}

__STATIC_INLINE uint32_t DL_FactoryRegion_getTraceID(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint32_t traceID;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        traceID = FACTORYVALUE->TRACEID & FACTORYREGION_TRACEID_DATA_MASK;
    } else {
        traceID = FACTORYREGION->TRACEID & FACTORYREGION_TRACEID_DATA_MASK;
    }
#else
    uint32_t traceID =
        FACTORYREGION->TRACEID & FACTORYREGION_TRACEID_DATA_MASK;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return traceID;
}

__STATIC_INLINE uint16_t DL_FactoryRegion_getManufacturerCode(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint16_t manufacturerCode;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        manufacturerCode = (FACTORYVALUE->DEVICEID &
                               FACTORYREGION_DEVICEID_MANUFACTURER_MASK) >>
                           FACTORYREGION_DEVICEID_MANUFACTURER_OFS;
    } else {
        manufacturerCode = (FACTORYREGION->DEVICEID &
                               FACTORYREGION_DEVICEID_MANUFACTURER_MASK) >>
                           FACTORYREGION_DEVICEID_MANUFACTURER_OFS;
    }
#else
    uint16_t manufacturerCode =
        (FACTORYREGION->DEVICEID & FACTORYREGION_DEVICEID_MANUFACTURER_MASK) >>
        FACTORYREGION_DEVICEID_MANUFACTURER_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return manufacturerCode;
}

__STATIC_INLINE uint16_t DL_FactoryRegion_getPartNumber(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint16_t partNumber;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        partNumber =
            (FACTORYVALUE->DEVICEID & FACTORYREGION_DEVICEID_PARTNUM_MASK) >>
            FACTORYREGION_DEVICEID_PARTNUM_OFS;
    } else {
        partNumber =
            (FACTORYREGION->DEVICEID & FACTORYREGION_DEVICEID_PARTNUM_MASK) >>
            FACTORYREGION_DEVICEID_PARTNUM_OFS;
    }
#else
    uint16_t partNumber =
        (FACTORYREGION->DEVICEID & FACTORYREGION_DEVICEID_PARTNUM_MASK) >>
        FACTORYREGION_DEVICEID_PARTNUM_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return partNumber;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getVersion(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t version;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        version =
            (FACTORYVALUE->DEVICEID & FACTORYREGION_DEVICEID_VERSION_MASK) >>
            FACTORYREGION_DEVICEID_VERSION_OFS;
    } else {
        version =
            (FACTORYREGION->DEVICEID & FACTORYREGION_DEVICEID_VERSION_MASK) >>
            FACTORYREGION_DEVICEID_VERSION_OFS;
    }
#else
    uint8_t version =
        (FACTORYREGION->DEVICEID & FACTORYREGION_DEVICEID_VERSION_MASK) >>
        FACTORYREGION_DEVICEID_VERSION_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return version;
}

__STATIC_INLINE uint16_t DL_FactoryRegion_getUserIDPart(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint16_t userIDPart;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        userIDPart = (FACTORYVALUE->USERID & FACTORYREGION_USERID_PART_MASK) >>
                     FACTORYREGION_USERID_PART_OFS;
    } else {
        userIDPart =
            (FACTORYREGION->USERID & FACTORYREGION_USERID_PART_MASK) >>
            FACTORYREGION_USERID_PART_OFS;
    }
#else
    uint16_t userIDPart =
        (FACTORYREGION->USERID & FACTORYREGION_USERID_PART_MASK) >>
        FACTORYREGION_USERID_PART_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return userIDPart;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getUserIDVariant(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t userIDVariant;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        userIDVariant =
            (FACTORYVALUE->USERID & FACTORYREGION_USERID_VARIANT_MASK) >>
            FACTORYREGION_USERID_VARIANT_OFS;
    } else {
        userIDVariant =
            (FACTORYREGION->USERID & FACTORYREGION_USERID_VARIANT_MASK) >>
            FACTORYREGION_USERID_VARIANT_OFS;
    }
#else
    uint8_t userIDVariant =
        (FACTORYREGION->USERID & FACTORYREGION_USERID_VARIANT_MASK) >>
        FACTORYREGION_USERID_VARIANT_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return userIDVariant;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getUserIDMinorRev(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t minorRev;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        minorRev =
            (FACTORYVALUE->USERID & FACTORYREGION_USERID_MINORREV_MASK) >>
            FACTORYREGION_USERID_MINORREV_OFS;
    } else {
        minorRev =
            (FACTORYREGION->USERID & FACTORYREGION_USERID_MINORREV_MASK) >>
            FACTORYREGION_USERID_MINORREV_OFS;
    }
#else
    uint8_t minorRev =
        (FACTORYREGION->USERID & FACTORYREGION_USERID_MINORREV_MASK) >>
        FACTORYREGION_USERID_MINORREV_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return minorRev;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getUserIDMajorRev(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t majorRev;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        majorRev =
            (FACTORYVALUE->USERID & FACTORYREGION_USERID_MAJORREV_MASK) >>
            FACTORYREGION_USERID_MAJORREV_OFS;
    } else {
        majorRev =
            (FACTORYREGION->USERID & FACTORYREGION_USERID_MAJORREV_MASK) >>
            FACTORYREGION_USERID_MAJORREV_OFS;
    }
#else
    uint8_t majorRev =
        (FACTORYREGION->USERID & FACTORYREGION_USERID_MAJORREV_MASK) >>
        FACTORYREGION_USERID_MAJORREV_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return majorRev;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinUARTRXDPad(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslUARTRXDPad;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslUARTRXDPad = (FACTORYVALUE->BSLPIN_UART &
                            FACTORYREGION_BSLPIN_UART_UART_RXD_PAD_MASK) >>
                        FACTORYREGION_BSLPIN_UART_UART_RXD_PAD_OFS;
    } else {
        bslUARTRXDPad = (FACTORYREGION->BSLPIN_UART &
                            FACTORYREGION_BSLPIN_UART_UART_RXD_PAD_MASK) >>
                        FACTORYREGION_BSLPIN_UART_UART_RXD_PAD_OFS;
    }
#else
    uint8_t bslUARTRXDPad = (FACTORYREGION->BSLPIN_UART &
                                FACTORYREGION_BSLPIN_UART_UART_RXD_PAD_MASK) >>
                            FACTORYREGION_BSLPIN_UART_UART_RXD_PAD_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslUARTRXDPad;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinUARTRXDFunction(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslUARTRXDFunction;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslUARTRXDFunction = (FACTORYVALUE->BSLPIN_UART &
                                 FACTORYREGION_BSLPIN_UART_UART_RXD_PF_MASK) >>
                             FACTORYREGION_BSLPIN_UART_UART_RXD_PF_OFS;
    } else {
        bslUARTRXDFunction = (FACTORYREGION->BSLPIN_UART &
                                 FACTORYREGION_BSLPIN_UART_UART_RXD_PF_MASK) >>
                             FACTORYREGION_BSLPIN_UART_UART_RXD_PF_OFS;
    }
#else
    uint8_t bslUARTRXDFunction =
        (FACTORYREGION->BSLPIN_UART &
            FACTORYREGION_BSLPIN_UART_UART_RXD_PF_MASK) >>
        FACTORYREGION_BSLPIN_UART_UART_RXD_PF_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslUARTRXDFunction;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinUARTTXDPad(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslUARTTXDPad;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslUARTTXDPad = (FACTORYVALUE->BSLPIN_UART &
                            FACTORYREGION_BSLPIN_UART_UART_TXD_PAD_MASK) >>
                        FACTORYREGION_BSLPIN_UART_UART_TXD_PAD_OFS;
    } else {
        bslUARTTXDPad = (FACTORYREGION->BSLPIN_UART &
                            FACTORYREGION_BSLPIN_UART_UART_TXD_PAD_MASK) >>
                        FACTORYREGION_BSLPIN_UART_UART_TXD_PAD_OFS;
    }
#else
    uint8_t bslUARTTXDPad = (FACTORYREGION->BSLPIN_UART &
                                FACTORYREGION_BSLPIN_UART_UART_TXD_PAD_MASK) >>
                            FACTORYREGION_BSLPIN_UART_UART_TXD_PAD_OFS;
#endif
    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslUARTTXDPad;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinUARTTXDFunction(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslUARTTXDFunction;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslUARTTXDFunction = (FACTORYVALUE->BSLPIN_UART &
                                 FACTORYREGION_BSLPIN_UART_UART_TXD_PF_MASK) >>
                             FACTORYREGION_BSLPIN_UART_UART_TXD_PF_OFS;
    } else {
        bslUARTTXDFunction = (FACTORYREGION->BSLPIN_UART &
                                 FACTORYREGION_BSLPIN_UART_UART_TXD_PF_MASK) >>
                             FACTORYREGION_BSLPIN_UART_UART_TXD_PF_OFS;
    }
#else
    uint8_t bslUARTTXDFunction =
        (FACTORYREGION->BSLPIN_UART &
            FACTORYREGION_BSLPIN_UART_UART_TXD_PF_MASK) >>
        FACTORYREGION_BSLPIN_UART_UART_TXD_PF_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslUARTTXDFunction;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinI2CSDAPad(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslI2CSDAPad;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslI2CSDAPad = (FACTORYVALUE->BSLPIN_I2C &
                           FACTORYREGION_BSLPIN_I2C_I2C_SDA_PAD_MASK) >>
                       FACTORYREGION_BSLPIN_I2C_I2C_SDA_PAD_OFS;
    } else {
        bslI2CSDAPad = (FACTORYREGION->BSLPIN_I2C &
                           FACTORYREGION_BSLPIN_I2C_I2C_SDA_PAD_MASK) >>
                       FACTORYREGION_BSLPIN_I2C_I2C_SDA_PAD_OFS;
    }
#else
    uint8_t bslI2CSDAPad = (FACTORYREGION->BSLPIN_I2C &
                               FACTORYREGION_BSLPIN_I2C_I2C_SDA_PAD_MASK) >>
                           FACTORYREGION_BSLPIN_I2C_I2C_SDA_PAD_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslI2CSDAPad;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinI2CSDAFunction(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslI2CSDAFunction;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslI2CSDAFunction = (FACTORYVALUE->BSLPIN_I2C &
                                FACTORYREGION_BSLPIN_I2C_I2C_SDA_PF_MASK) >>
                            FACTORYREGION_BSLPIN_I2C_I2C_SDA_PF_OFS;
    } else {
        bslI2CSDAFunction = (FACTORYREGION->BSLPIN_I2C &
                                FACTORYREGION_BSLPIN_I2C_I2C_SDA_PF_MASK) >>
                            FACTORYREGION_BSLPIN_I2C_I2C_SDA_PF_OFS;
    }
#else
    uint8_t bslI2CSDAFunction =
        (FACTORYREGION->BSLPIN_I2C &
            FACTORYREGION_BSLPIN_I2C_I2C_SDA_PF_MASK) >>
        FACTORYREGION_BSLPIN_I2C_I2C_SDA_PF_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslI2CSDAFunction;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinI2CSCLPad(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslI2CSCLPad;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslI2CSCLPad = (FACTORYVALUE->BSLPIN_I2C &
                           FACTORYREGION_BSLPIN_I2C_I2C_SCL_PAD_MASK) >>
                       FACTORYREGION_BSLPIN_I2C_I2C_SCL_PAD_OFS;
    } else {
        bslI2CSCLPad = (FACTORYREGION->BSLPIN_I2C &
                           FACTORYREGION_BSLPIN_I2C_I2C_SCL_PAD_MASK) >>
                       FACTORYREGION_BSLPIN_I2C_I2C_SCL_PAD_OFS;
    }
#else
    uint8_t bslI2CSCLPad = (FACTORYREGION->BSLPIN_I2C &
                               FACTORYREGION_BSLPIN_I2C_I2C_SCL_PAD_MASK) >>
                           FACTORYREGION_BSLPIN_I2C_I2C_SCL_PAD_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslI2CSCLPad;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinI2CSCLFunction(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslI2CSCLFunction;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslI2CSCLFunction = (FACTORYVALUE->BSLPIN_I2C &
                                FACTORYREGION_BSLPIN_I2C_I2C_SCL_PF_MASK) >>
                            FACTORYREGION_BSLPIN_I2C_I2C_SCL_PF_OFS;
    } else {
        bslI2CSCLFunction = (FACTORYREGION->BSLPIN_I2C &
                                FACTORYREGION_BSLPIN_I2C_I2C_SCL_PF_MASK) >>
                            FACTORYREGION_BSLPIN_I2C_I2C_SCL_PF_OFS;
    }
#else
    uint8_t bslI2CSCLFunction =
        (FACTORYREGION->BSLPIN_I2C &
            FACTORYREGION_BSLPIN_I2C_I2C_SCL_PF_MASK) >>
        FACTORYREGION_BSLPIN_I2C_I2C_SCL_PF_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslI2CSCLFunction;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinInvokeGPIOLevel(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslInvokeGPIOLevel;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslInvokeGPIOLevel =
            (FACTORYVALUE->BSLPIN_INVOKE &
                FACTORYREGION_BSLPIN_INVOKE_GPIO_LEVEL_MASK) >>
            FACTORYREGION_BSLPIN_INVOKE_GPIO_LEVEL_OFS;
    } else {
        bslInvokeGPIOLevel =
            (FACTORYREGION->BSLPIN_INVOKE &
                FACTORYREGION_BSLPIN_INVOKE_GPIO_LEVEL_MASK) >>
            FACTORYREGION_BSLPIN_INVOKE_GPIO_LEVEL_OFS;
    }
#else
    uint8_t bslInvokeGPIOLevel =
        (FACTORYREGION->BSLPIN_INVOKE &
            FACTORYREGION_BSLPIN_INVOKE_GPIO_LEVEL_MASK) >>
        FACTORYREGION_BSLPIN_INVOKE_GPIO_LEVEL_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslInvokeGPIOLevel;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinInvokeGPIOPin(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslInvokeGPIOPin;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslInvokeGPIOPin =
            (FACTORYVALUE->BSLPIN_INVOKE &
                FACTORYREGION_BSLPIN_INVOKE_GPIO_PIN_SEL_MASK) >>
            FACTORYREGION_BSLPIN_INVOKE_GPIO_PIN_SEL_OFS;
    } else {
        bslInvokeGPIOPin =
            (FACTORYREGION->BSLPIN_INVOKE &
                FACTORYREGION_BSLPIN_INVOKE_GPIO_PIN_SEL_MASK) >>
            FACTORYREGION_BSLPIN_INVOKE_GPIO_PIN_SEL_OFS;
    }
#else
    uint8_t bslInvokeGPIOPin =
        (FACTORYREGION->BSLPIN_INVOKE &
            FACTORYREGION_BSLPIN_INVOKE_GPIO_PIN_SEL_MASK) >>
        FACTORYREGION_BSLPIN_INVOKE_GPIO_PIN_SEL_OFS;
#endif
    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslInvokeGPIOPin;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinInvokeGPIOModule(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslInvokeGPIOModule;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslInvokeGPIOModule =
            (FACTORYVALUE->BSLPIN_INVOKE &
                FACTORYREGION_BSLPIN_INVOKE_GPIO_REG_SEL_MASK) >>
            FACTORYREGION_BSLPIN_INVOKE_GPIO_REG_SEL_OFS;
    } else {
        bslInvokeGPIOModule =
            (FACTORYREGION->BSLPIN_INVOKE &
                FACTORYREGION_BSLPIN_INVOKE_GPIO_REG_SEL_MASK) >>
            FACTORYREGION_BSLPIN_INVOKE_GPIO_REG_SEL_OFS;
    }
#else
    uint8_t bslInvokeGPIOModule =
        (FACTORYREGION->BSLPIN_INVOKE &
            FACTORYREGION_BSLPIN_INVOKE_GPIO_REG_SEL_MASK) >>
        FACTORYREGION_BSLPIN_INVOKE_GPIO_REG_SEL_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslInvokeGPIOModule;
}

__STATIC_INLINE uint8_t DL_FactoryRegion_getBSLPinInvokeGPIOModulePad(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint8_t bslInvokeGPIOModulePad;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        bslInvokeGPIOModulePad =
            (FACTORYVALUE->BSLPIN_INVOKE &
                FACTORYREGION_BSLPIN_INVOKE_BSL_PAD_MASK) >>
            FACTORYREGION_BSLPIN_INVOKE_BSL_PAD_OFS;
    } else {
        bslInvokeGPIOModulePad =
            (FACTORYREGION->BSLPIN_INVOKE &
                FACTORYREGION_BSLPIN_INVOKE_BSL_PAD_MASK) >>
            FACTORYREGION_BSLPIN_INVOKE_BSL_PAD_OFS;
    }
#else
    uint8_t bslInvokeGPIOModulePad =
        (FACTORYREGION->BSLPIN_INVOKE &
            FACTORYREGION_BSLPIN_INVOKE_BSL_PAD_MASK) >>
        FACTORYREGION_BSLPIN_INVOKE_BSL_PAD_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return bslInvokeGPIOModulePad;
}

__STATIC_INLINE uint32_t DL_FactoryRegion_getTemperatureVoltage(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

#ifdef __MSPM0GX51X_TRIM_CACHE__
    uint32_t tempVoltage;
    if (DL_FactoryRegion_isTrimTableInSram()) {
        tempVoltage = (FACTORYVALUE->TEMP_SENSE0 &
                          FACTORYREGION_TEMP_SENSE0_DATA_MASK) >>
                      FACTORYREGION_TEMP_SENSE0_DATA_OFS;
    } else {
        tempVoltage = (FACTORYREGION->TEMP_SENSE0 &
                          FACTORYREGION_TEMP_SENSE0_DATA_MASK) >>
                      FACTORYREGION_TEMP_SENSE0_DATA_OFS;
    }
#else
    uint32_t tempVoltage =
        (FACTORYREGION->TEMP_SENSE0 & FACTORYREGION_TEMP_SENSE0_DATA_MASK) >>
        FACTORYREGION_TEMP_SENSE0_DATA_OFS;
#endif

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return tempVoltage;
}

__STATIC_INLINE uint32_t DL_FactoryRegion_getBOOTCRCData(void)
{
    /* Save CPUSS state and then disable the cache before TRIM access */
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

    uint32_t BOOTCRCData =
        (FACTORYREGION->BOOTCRC & FACTORYREGION_BOOTCRC_DATA_MASK) >>
        FACTORYREGION_BOOTCRC_DATA_OFS;

    /* Restore CPUSS state */
    CPUSS->CTL = ctlTemp;

    return BOOTCRCData;
}

#ifdef __MSPM0GX51X_TRIM_CACHE__

void DL_FactoryRegion_initTrimTable(void);
#endif

#ifdef __MSPM0C110X_ADC_ERR_06__

__STATIC_INLINE float DL_FactoryRegion_getADCOffset(void)
{
    return ((float) (*(int16_t *) (0x41C40040)));
}
#endif

#ifdef __cplusplus
}
#endif

#endif /* ti_dl_dl_factoryregion__include */