ADCMSPM0.h

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/*
 * Copyright (c) 2022-2023, Texas Instruments Incorporated
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 *    notice, this list of conditions and the following disclaimer.
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 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
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 *    from this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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/*!****************************************************************************
 *  @file       ADCMSPM0.h
 *  @brief      ADC driver implementation for the ADC peripheral on MSPM0
 *              devices
 *  @defgroup   ADCMSPM0 ADC driver APIs
 *
 *  This ADC driver implementation is designed to operate on a ADC peripheral
 *  for MSPM0 devices.
 *
 *  Refer to ADC.h for a complete description of APIs & example of use.
 *
 ******************************************************************************
 */
/* clang-format off */
#ifndef ti_drivers_adc_ADCMSPM0__include
#define ti_drivers_adc_ADCMSPM0__include

#include <stdint.h>
#include <stdbool.h>


#include <ti/drivers/ADC.h>
#include <ti/driverlib/dl_adc12.h>

#ifdef POWER_MANAGEMENT_MSPM0
#include <ti/drivers/Power.h>
#endif
#include <ti/devices/DeviceFamily.h>

#ifdef __cplusplus
extern "C" {
#endif

#define ADC_ALL_INTERRUPTS_MASK     0xFFFFFFFFUL

typedef enum
{
    ADCMSPM0_RESOLUTION_12_BIT = DL_ADC12_SAMP_CONV_RES_12_BIT,
    ADCMSPM0_RESOLUTION_10_BIT = DL_ADC12_SAMP_CONV_RES_10_BIT,
    ADCMSPM0_RESOLUTION_8_BIT  = DL_ADC12_SAMP_CONV_RES_8_BIT,
} ADCMSPM0_Resolution_Bits;

typedef enum
{
    ADCMSPM0_VDDA_REFERENCE      = DL_ADC12_REFERENCE_VOLTAGE_VDDA,
    ADCMSPM0_INTERNAL_REFERENCE  = DL_ADC12_REFERENCE_VOLTAGE_INTREF,
    ADCMSPM0_EXTERNAL_REFERENCE  = DL_ADC12_REFERENCE_VOLTAGE_EXTREF
} ADCMSPM0_Reference_Source;

typedef enum
{
    ADCMSPM0_CLKDIV_1  = DL_ADC12_CLOCK_DIVIDE_1,
    ADCMSPM0_CLKDIV_2  = DL_ADC12_CLOCK_DIVIDE_2,
    ADCMSPM0_CLKDIV_4  = DL_ADC12_CLOCK_DIVIDE_4,
    ADCMSPM0_CLKDIV_8  = DL_ADC12_CLOCK_DIVIDE_8,
    ADCMSPM0_CLKDIV_16 = DL_ADC12_CLOCK_DIVIDE_16,
    ADCMSPM0_CLKDIV_24 = DL_ADC12_CLOCK_DIVIDE_24,
    ADCMSPM0_CLKDIV_32 = DL_ADC12_CLOCK_DIVIDE_32,
    ADCMSPM0_CLKDIV_48 = DL_ADC12_CLOCK_DIVIDE_48
} ADCMSPM0_Clock_Divider;

typedef enum
{
    ADCMSPM0_CLK_SYSOSC = DL_ADC12_CLOCK_SYSOSC,
    ADCMSPM0_CLK_ULPCLK = DL_ADC12_CLOCK_ULPCLK,
    ADCMSPM0_CLK_HFCLK  = DL_ADC12_CLOCK_HFCLK,
}ADCMSPM0_Clock_Select;

typedef enum
{
    ADCMSPM0_CLK_FREQ_RANGE_1TO4    = DL_ADC12_CLOCK_FREQ_RANGE_1_TO_4,
    ADCMSPM0_CLK_FREQ_RANGE_4TO8    = DL_ADC12_CLOCK_FREQ_RANGE_4_TO_8,
    ADCMSPM0_CLK_FREQ_RANGE_8TO16   = DL_ADC12_CLOCK_FREQ_RANGE_8_TO_16,
    ADCMSPM0_CLK_FREQ_RANGE_16TO20  = DL_ADC12_CLOCK_FREQ_RANGE_16_TO_20,
    ADCMSPM0_CLK_FREQ_RANGE_20TO24  = DL_ADC12_CLOCK_FREQ_RANGE_20_TO_24,
    ADCMSPM0_CLK_FREQ_RANGE_24TO32  = DL_ADC12_CLOCK_FREQ_RANGE_24_TO_32,
    ADCMSPM0_CLK_FREQ_RANGE_32TO40  = DL_ADC12_CLOCK_FREQ_RANGE_32_TO_40,
    ADCMSPM0_CLK_FREQ_RANGE_40TO48  = DL_ADC12_CLOCK_FREQ_RANGE_40_TO_48,
}ADCMSPM0_Freq_Range;

typedef enum
{
    ADCMSPM0_SINGLE_CH_SINGLE_CONV          = DL_ADC12_SAMP_MODE_SINGLE,
    ADCMSPM0_MULTI_CH_SEQUENCE_CONV         = DL_ADC12_SAMP_MODE_SEQUENCE,
}ADCMSPM0_Conversion_Mode;

typedef enum
{
    ADCMSPM0_REPEAT_MODE_ENABLED          = DL_ADC12_REPEAT_MODE_ENABLED,
    ADCMSPM0_REPEAT_MODE_DISABLED         = DL_ADC12_REPEAT_MODE_DISABLED,
}ADCMSPM0_Repeat_Conversion_Mode;

typedef enum
{
    ADCMSPM0_SAMPLING_MODE_AUTO   = DL_ADC12_SAMPLING_SOURCE_AUTO,
    ADCMSPM0_SAMPLING_MODE_MANUAL = DL_ADC12_SAMPLING_SOURCE_MANUAL,
} ADCMSPM0_Sampling_Mode;

typedef enum
{
    ADCMSPM0_SAMPLING_TRIG_SW    = DL_ADC12_TRIG_SRC_SOFTWARE,
    ADCMSPM0_SAMPLING_TRIG_EVENT = DL_ADC12_TRIG_SRC_EVENT,
} ADCMSPM0_Sampling_Trg;

typedef enum
{
    ADCMSPM0_CONV_DATA_FORMAT_UNSIGNED    = DL_ADC12_SAMP_CONV_DATA_FORMAT_UNSIGNED,
    ADCMSPM0_CONV_DATA_FORMAT_SIGNED      = DL_ADC12_SAMP_CONV_DATA_FORMAT_SIGNED,
} ADCMSPM0_Conv_Data_Format;

typedef enum
{
    ADCMSPM0_SAMP_TMR_SOURCE_SCOMP0    = DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0,
    ADCMSPM0_SAMP_TMR_SOURCE_SCOMP1    = DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP1,
} ADCMSPM0_Sample_Timer_Source;

typedef enum
{
    ADCMSPM0_NEXT_CONV_AUTO         = DL_ADC12_TRIGGER_MODE_AUTO_NEXT,
    ADCMSPM0_NEXT_CONV_WITH_TRIG    = DL_ADC12_TRIGGER_MODE_TRIGGER_NEXT,
} ADCMSPM0_Conv_Trig_Src;

typedef enum
{
    ADCMSPM0_HW_AVG_ENABLED     = DL_ADC12_AVERAGING_MODE_ENABLED,
    ADCMSPM0_HW_AVG_DISABLED    = DL_ADC12_AVERAGING_MODE_DISABLED,
} ADCMSPM0_HW_Avg;

typedef enum
{
    ADCMSPM0_HW_AVG_NUM_ACC_DISABLED = DL_ADC12_HW_AVG_NUM_ACC_DISABLED,
    ADCMSPM0_HW_AVG_NUM_ACC_2        = DL_ADC12_HW_AVG_NUM_ACC_2,
    ADCMSPM0_HW_AVG_NUM_ACC_4        = DL_ADC12_HW_AVG_NUM_ACC_4,
    ADCMSPM0_HW_AVG_NUM_ACC_8        = DL_ADC12_HW_AVG_NUM_ACC_8,
    ADCMSPM0_HW_AVG_NUM_ACC_16       = DL_ADC12_HW_AVG_NUM_ACC_16,
    ADCMSPM0_HW_AVG_NUM_ACC_32       = DL_ADC12_HW_AVG_NUM_ACC_32,
    ADCMSPM0_HW_AVG_NUM_ACC_64       = DL_ADC12_HW_AVG_NUM_ACC_64,
    ADCMSPM0_HW_AVG_NUM_ACC_128      = DL_ADC12_HW_AVG_NUM_ACC_128,
}ADCMSPM0_AVGN;

typedef enum
{
    ADCMSPM0_HW_AVG_DEN_DIV_BY_1     = DL_ADC12_HW_AVG_DEN_DIV_BY_1,
    ADCMSPM0_HW_AVG_DEN_DIV_BY_2     = DL_ADC12_HW_AVG_DEN_DIV_BY_2,
    ADCMSPM0_HW_AVG_DEN_DIV_BY_4     = DL_ADC12_HW_AVG_DEN_DIV_BY_4,
    ADCMSPM0_HW_AVG_DEN_DIV_BY_8     = DL_ADC12_HW_AVG_DEN_DIV_BY_8,
    ADCMSPM0_HW_AVG_DEN_DIV_BY_16    = DL_ADC12_HW_AVG_DEN_DIV_BY_16,
    ADCMSPM0_HW_AVG_DEN_DIV_BY_32    = DL_ADC12_HW_AVG_DEN_DIV_BY_32,
    ADCMSPM0_HW_AVG_DEN_DIV_BY_64    = DL_ADC12_HW_AVG_DEN_DIV_BY_64,
    ADCMSPM0_HW_AVG_DEN_DIV_BY_128   = DL_ADC12_HW_AVG_DEN_DIV_BY_128,
}ADCMSPM0_AVGD;

typedef enum
{
    ADCMSPM0_Pwr_Dn_MODE_AUTO     = DL_ADC12_POWER_DOWN_MODE_AUTO,
    ADCMSPM0_Pwr_Dn_MODE_MANUAL   = DL_ADC12_POWER_DOWN_MODE_MANUAL,
} ADCMSPM0_Pwr_Dn_Mode;

typedef enum
{
    ADCMSPM0_SEQ_START_ADDR_00 = DL_ADC12_SEQ_START_ADDR_00,
    ADCMSPM0_SEQ_START_ADDR_01 = DL_ADC12_SEQ_START_ADDR_01,
    ADCMSPM0_SEQ_START_ADDR_02 = DL_ADC12_SEQ_START_ADDR_02,
    ADCMSPM0_SEQ_START_ADDR_03 = DL_ADC12_SEQ_START_ADDR_03,
    ADCMSPM0_SEQ_START_ADDR_04 = DL_ADC12_SEQ_START_ADDR_04,
    ADCMSPM0_SEQ_START_ADDR_05 = DL_ADC12_SEQ_START_ADDR_05,
    ADCMSPM0_SEQ_START_ADDR_06 = DL_ADC12_SEQ_START_ADDR_06,
    ADCMSPM0_SEQ_START_ADDR_07 = DL_ADC12_SEQ_START_ADDR_07,
    ADCMSPM0_SEQ_START_ADDR_08 = DL_ADC12_SEQ_START_ADDR_08,
    ADCMSPM0_SEQ_START_ADDR_09 = DL_ADC12_SEQ_START_ADDR_09,
    ADCMSPM0_SEQ_START_ADDR_10 = DL_ADC12_SEQ_START_ADDR_10,
    ADCMSPM0_SEQ_START_ADDR_11 = DL_ADC12_SEQ_START_ADDR_11,
}ADCMSPM0_CONV_START_ADDRESS;

typedef enum
{
    ADCMSPM0_SEQ_END_ADDR_00 = DL_ADC12_SEQ_END_ADDR_00,
    ADCMSPM0_SEQ_END_ADDR_01 = DL_ADC12_SEQ_END_ADDR_01,
    ADCMSPM0_SEQ_END_ADDR_02 = DL_ADC12_SEQ_END_ADDR_02,
    ADCMSPM0_SEQ_END_ADDR_03 = DL_ADC12_SEQ_END_ADDR_03,
    ADCMSPM0_SEQ_END_ADDR_04 = DL_ADC12_SEQ_END_ADDR_04,
    ADCMSPM0_SEQ_END_ADDR_05 = DL_ADC12_SEQ_END_ADDR_05,
    ADCMSPM0_SEQ_END_ADDR_06 = DL_ADC12_SEQ_END_ADDR_06,
    ADCMSPM0_SEQ_END_ADDR_07 = DL_ADC12_SEQ_END_ADDR_07,
    ADCMSPM0_SEQ_END_ADDR_08 = DL_ADC12_SEQ_END_ADDR_08,
    ADCMSPM0_SEQ_END_ADDR_09 = DL_ADC12_SEQ_END_ADDR_09,
    ADCMSPM0_SEQ_END_ADDR_10 = DL_ADC12_SEQ_END_ADDR_10,
    ADCMSPM0_SEQ_END_ADDR_11 = DL_ADC12_SEQ_END_ADDR_11,
}ADCMSPM0_CONV_END_ADDRESS;

typedef struct
{
    ADC12_Regs *adc;
    uint8_t adcInputDIO;
    uint8_t adcInputPincm;
    uint32_t adcInputPinMux;
    uint8_t adcPosRefDIO;
    uint8_t adcPosRefPincm;
    uint32_t adcPosRefPinMux;
    uint8_t adcNegRefDIO;
    uint8_t adcNegRefPincm;
    uint32_t adcNegRefPinMux;
    uint8_t adcChannel;
    uint_fast32_t refVoltage;
    ADCMSPM0_Reference_Source refSource;
    uint16_t samplingDuration;
    ADCMSPM0_Resolution_Bits resolutionBits;
    ADCMSPM0_Clock_Divider adcClkkDivider;
    ADCMSPM0_Clock_Select adcClkSelect;
    ADCMSPM0_Freq_Range adcClkFreqRange;

    ADCMSPM0_Conversion_Mode conversionMode;
    ADCMSPM0_CONV_START_ADDRESS conversionStartAddr;
    ADCMSPM0_CONV_END_ADDRESS conversionEndAddr;
    ADCMSPM0_Repeat_Conversion_Mode repeatConversionMode;
    ADCMSPM0_Sampling_Mode samplingMode;
    ADCMSPM0_Sampling_Trg sampleTrigger;
    ADCMSPM0_Conv_Data_Format conversionDataFormat;
    ADCMSPM0_Sample_Timer_Source sampleTimerSrc;
    ADCMSPM0_Conv_Trig_Src conversionTrigger;
    ADCMSPM0_HW_Avg adcHWAveraging;
    ADCMSPM0_AVGD adcHwAvgDenominator;
    ADCMSPM0_AVGN adcHwAvgNumerator;
    uint8_t idxMEMCTLx;
} ADCMSPM0_HWAttrs;

typedef struct
{
    bool isOpen;
    bool isProtected;
} ADCMSPM0_Object;

#ifdef __cplusplus
}
#endif

#endif /* ti_drivers_adc_ADCMSPM0__include */
/* clang-format on */