|
Pre-compile switches for enabling/disabling DEM events
|
| enum | Mcu_ResetType {
MCU_POWER_ON_RESET_MAIN_DOMAIN = 0
, MCU_POWER_ON_RESET_MCU_DOMAIN
, MCU_WATCHDOG_RESET
, MCU_DEBUG_RESET
,
MCU_MAIN_WARM_RESET_MAIN_DOMAIN
, MCU_MAIN_WARM_RESET_MCU_DOMAIN
, MCU_RESET_UNDEFINED
, MCU_RESET_CLEAR
} |
| | This is the type of the reset enumerator containing the subset of reset types.
It is not required that all reset types are supported by hardware. More...
|
| |
| enum | Mcu_DomainType { MCU
, MAIN
, WKUP
} |
| |
| enum | Mcu_ModuleName {
Mcan
, Mcspi
, Gpt
, Gpio
,
Rti
, I2c
, Uart
, Eth
,
Ospi
, Epwm
, Ecap
} |
| |
| enum | Mcu_ClkModuleIdType {
MCU_CLKSRC_MODULE_ID_MCU_MCAN0 = 188
, MCU_CLKSRC_MODULE_ID_MCU_MCAN1 = 189
, MCU_CLKSRC_MODULE_ID_MCAN0 = 98
, MCU_CLKSRC_MODULE_ID_MCU_MCSPI0 = 147
,
MCU_CLKSRC_MODULE_ID_MCU_MCSPI1 = 148
, MCU_CLKSRC_MODULE_ID_MCSPI0 = 141
, MCU_CLKSRC_MODULE_ID_MCSPI1 = 142
, MCU_CLKSRC_MODULE_ID_MCSPI2 = 143
,
MCU_CLKSRC_MODULE_ID_MCU_GPT0 = 35
, MCU_CLKSRC_MODULE_ID_MCU_GPT1 = 48
, MCU_CLKSRC_MODULE_ID_MCU_GPT2 = 49
, MCU_CLKSRC_MODULE_ID_MCU_GPT3 = 50
,
MCU_CLKSRC_MODULE_ID_GPT0 = 36
, MCU_CLKSRC_MODULE_ID_GPT1 = 37
, MCU_CLKSRC_MODULE_ID_GPT2 = 38
, MCU_CLKSRC_MODULE_ID_GPT3 = 39
,
MCU_CLKSRC_MODULE_ID_GPT4 = 40
, MCU_CLKSRC_MODULE_ID_GPT5 = 41
, MCU_CLKSRC_MODULE_ID_GPT6 = 42
, MCU_CLKSRC_MODULE_ID_GPT7 = 43
,
MCU_CLKSRC_MODULE_ID_WKUP_GPT0 = 110
, MCU_CLKSRC_MODULE_ID_WKUP_GPT1 = 111
, MCU_CLKSRC_MODULE_ID_MCU_GPIO0 = 79
, MCU_CLKSRC_MODULE_ID_MCU_RTI0 = 131
,
MCU_CLKSRC_MODULE_ID_MCU_I2C0 = 106
, MCU_CLKSRC_MODULE_ID_MCU_UART0 = 149
, MCU_CLKSRC_MODULE_ID_UART0 = 146
, MCU_CLKSRC_MODULE_ID_UART1 = 152
,
MCU_CLKSRC_MODULE_ID_UART2 = 153
, MCU_CLKSRC_MODULE_ID_UART3 = 154
, MCU_CLKSRC_MODULE_ID_UART4 = 155
, MCU_CLKSRC_MODULE_ID_UART5 = 156
,
MCU_CLKSRC_MODULE_ID_UART6 = 158
, MCU_CLKSRC_MODULE_ID_WKUP_UART0 = 114
, MCU_CLKSRC_MODULE_ID_OSPI0 = 75
, MCU_CLKSRC_MODULE_ID_ETH0 = 13
,
MCU_CLKSRC_MODULE_ID_EPWM0 = 86
, MCU_CLKSRC_MODULE_ID_EPWM1 = 87
, MCU_CLKSRC_MODULE_ID_EPWM2 = 88
, MCU_CLKSRC_MODULE_ID_ECAP0 = 51
,
MCU_CLKSRC_MODULE_ID_ECAP1 = 52
, MCU_CLKSRC_MODULE_ID_ECAP2 = 53
, MCU_CLKSRC_MODULE_ID_MAX = 190
} |
| | Clock source config modules id enum. More...
|
| |
| enum | Mcu_ClkSourceIdType {
MCU_CLKSRC_0 = 0
, MCU_CLKSRC_1
, MCU_CLKSRC_2
, MCU_CLKSRC_3
,
MCU_CLKSRC_4
, MCU_CLKSRC_5
, MCU_CLKSRC_6
, MCU_CLKSRC_7
,
MCU_CLKSRC_MAX
} |
| | This is the type of the clock source in clock tree that is selectable for peripheral. Please see TRM to map clock source to module. More...
|
| |
| enum | Mcu_PllStatusType { MCU_PLL_LOCKED = 0
, MCU_PLL_UNLOCKED
, MCU_PLL_STATUS_UNDEFINED
} |
| | This is a status value returned by the function Mcu_GetPllStatus() of the MCU module. More...
|
| |
| enum | Mcu_PllSourceIdType { MCU_CLKSRC_DPLL = 0
, MCU_CLKSRC_APLL
} |
| | Type for PLL source selection. More...
|
| |
| enum | Mcu_RamStateType { MCU_RAMSTATE_INVALID
, MCU_RAMSTATE_VALID
} |
| | Enumeration of ranstate queried by Mcu_GetRamState() More...
|
| |
| typedef const Mcu_RamSectionConfigType * | Mcu_RamConfigPtrType |
| | Pointer to RamConfig structure.
|
| |
| typedef const Mcu_PllConfigType * | Mcu_PllConfigPtrType |
| | Pointer to PLL Config structure.
|
| |
| typedef Std_ReturnType(* | Mcu_CBKFunctionPtrType) (uint32 moduleId, uint32 clkId, uint64 ParentId) |
| | Pointer to Callback function.
|
| |
| const Mcu_ResetStatusMap | Mcu_ResetStatusMapTbl [MCU_RESET_STATUS_NUMBER] |
| |
| const Mcu_ResetInfo | Mcu_ResetInfoTbl |
| |
| const struct Mcu_ConfigType_s | McuModuleConfiguration |
| | MCU Configuration struct declaration.
|
| |
| #define | DemConf_DemEventParameter_MCU_DEM_NO_EVENT (0xFFFFU) |
| |
| #define | MCU_DEM_NO_EVENT DemConf_DemEventParameter_MCU_DEM_NO_EVENT |
| |
| #define | ARRAYSIZE(array) |
| |
| #define | McuConf_McuModeSettingConf_McuModeSettingConf_0 (0U) |
| |
| #define | McuConf_McuClockSettingConfig_MCU_MCAN0 (0U) |
| |
| #define | McuConf_McuClockSettingConfig_MCU_MCAN1 (1U) |
| |
| #define | McuConf_McuClockSettingConfig_MCAN0 (2U) |
| |
| #define | McuConf_McuClockSettingConfig_MCU_MCSPI0 (3U) |
| |
| #define | McuConf_McuClockSettingConfig_MCU_MCSPI1 (4U) |
| |
| #define | McuConf_McuClockSettingConfig_MCSPI0 (5U) |
| |
| #define | McuConf_McuClockSettingConfig_MCSPI1 (6U) |
| |
| #define | McuConf_McuClockSettingConfig_MCSPI2 (7U) |
| |
| #define | McuConf_McuClockSettingConfig_MCU_GPT0 (8U) |
| |
| #define | McuConf_McuClockSettingConfig_MCU_GPT1 (9U) |
| |
| #define | McuConf_McuClockSettingConfig_MCU_GPT2 (10U) |
| |
| #define | McuConf_McuClockSettingConfig_MCU_GPT3 (11U) |
| |
| #define | McuConf_McuClockSettingConfig_GPT0 (12U) |
| |
| #define | McuConf_McuClockSettingConfig_GPT1 (13U) |
| |
| #define | McuConf_McuClockSettingConfig_GPT2 (14U) |
| |
| #define | McuConf_McuClockSettingConfig_GPT3 (15U) |
| |
| #define | McuConf_McuClockSettingConfig_GPT4 (16U) |
| |
| #define | McuConf_McuClockSettingConfig_GPT5 (17U) |
| |
| #define | McuConf_McuClockSettingConfig_GPT6 (18U) |
| |
| #define | McuConf_McuClockSettingConfig_GPT7 (19U) |
| |
| #define | McuConf_McuClockSettingConfig_WKUP_GPT0 (20U) |
| |
| #define | McuConf_McuClockSettingConfig_WKUP_GPT1 (21U) |
| |
| #define | McuConf_McuClockSettingConfig_RTI0 (22U) |
| |
| #define | McuConf_McuClockSettingConfig_MCU_UART0 (23U) |
| |
| #define | McuConf_McuClockSettingConfig_UART0 (24U) |
| |
| #define | McuConf_McuClockSettingConfig_UART1 (25U) |
| |
| #define | McuConf_McuClockSettingConfig_UART2 (26U) |
| |
| #define | McuConf_McuClockSettingConfig_UART3 (27U) |
| |
| #define | McuConf_McuClockSettingConfig_UART4 (28U) |
| |
| #define | McuConf_McuClockSettingConfig_UART5 (29U) |
| |
| #define | McuConf_McuClockSettingConfig_UART6 (30U) |
| |
| #define | McuConf_McuClockSettingConfig_WKUPUART0 (31U) |
| |
| #define | McuConf_McuClockSettingConfig_ETH0 (32U) |
| |
| #define | McuConf_McuClockSettingConfig_EPWM0 (33U) |
| |
| #define | McuConf_McuClockSettingConfig_EPWM1 (34U) |
| |
| #define | McuConf_McuClockSettingConfig_EPWM2 (35U) |
| |
| #define | McuConf_McuClockSettingConfig_ECAP0 (36U) |
| |
| #define | McuConf_McuClockSettingConfig_ECAP1 (37U) |
| |
| #define | McuConf_McuClockSettingConfig_ECAP2 (38U) |
| |
| #define | McuConf_McuClockSettingConfig_OSPI0 (39U) |
| |
| #define | McuConf_McuResetReasonConf_MCU_POWER_ON_RESET (0U) |
| |
| #define | McuConf_McuResetReasonConf_MCU_WATCHDOG_RESET (1U) |
| |
| #define | McuConf_McuResetReasonConf_MCU_SW_RESET (2U) |
| |
| #define | McuConf_McuResetReasonConf_MCU_RESET_UNDEFINED (3U) |
| |
| #define | MCU_PERFORM_RESET_MASK ((uint32)0x60U) |
| | Reset Reason Mask.
|
| |
| #define | DM_WDT_RST ((uint32)0x400000U) |
| |
| #define | SRC_DEBUG_RST ((uint32)0x100U) |
| |
| #define | SW_MAIN_POR_FROM_MAIN_DOMAIN ((uint32)0x2003000U) |
| |
| #define | SW_MAIN_POR_FROM_MCU_DOMAIN ((uint32)0x1003000U) |
| |
| #define | SW_MAIN_WARMRST_FROM_MAIN_DOMAIN ((uint32)0x200000U) |
| |
| #define | SW_MAIN_WARMRST_FROM_MCU_DOMAIN ((uint32)0x10000U) |
| |
| #define | MCU_PERFORM_RESET_VAL ((uint32)0x6U) |
| | Perform Reset Value.
|
| |
| #define | rstaddr ((LLD_wkup_ctrl_mmr_cfg0Regs*)0x43000000U) |
| |
| #define | RSTADDR_MCU_CTRL_MMR ((LLD_mcu_ctrl_mmr_cfg0Regs*)0x04500000U) |
| |
| #define | MCU_ERRORRST_MASK ((Mcu_RawResetType)0xFFFF0000U) |
| | Reset Reason Error Mask.
|
| |
| #define | MCU_UTILS_ARRAYSIZE(array) |
| |
| #define | MCU_RESET_STATUS_NUMBER ((uint8)0x7) |
| |
1.12.0