Introduction

This files defines ETH MCAL configuration structures

Data Structures
struct	Eth_CpswConfigType
	Eth Cpsw Configurations type Configuration related to Cpsw data. More...

struct	Eth_Udma_RingCfgType
	Eth Udma ring Configurations type Configuration related to Udma ring. More...

struct	Eth_Udma_ProxyCfgType
	Eth Udma Proxy Configurations type Configuration related to Udma proxy. More...

struct	Eth_Udma_EventCfgType
	Eth Udma event Configurations type Configuration related to Udma event. More...

struct	Eth_Udma_RingEventCfgType
	Eth ring event configuration type Configuration related to ring event. More...

struct	Eth_FifoRingMapCfgType
	Eth Fifo ring map configuration type Configuration related to fifo map to ring. More...

struct	Eth_ChannelCfgType
	Eth channel configuration type Configuration related to channel. More...

struct	Eth_FlowCfgType
	Eth flow configuration type Configuration related to flow. More...

struct	Eth_ChannelFlowCfgType
	Eth channel flow configuration type Configuration related to channel flow. More...

struct	Eth_FifoHandleType
	Eth Fifo configuration type Configuration related to Fifo. More...

struct	Eth_Udma_CfgType
	Eth Udma configuration type Configuration related to Udma. More...

struct	Eth_VirtualMacConfigType
	Eth driver virtual mac configuration data Configuration related to virtual MAC configuration. More...

struct	Eth_HwTimerConfigType
	Eth driver hardware timer configuration data Configuration related to hardware timer. More...

struct	Eth_ControlerConfigType
	Eth controller configuration type Configuration related to Eth controller configuration. More...

struct	Eth_ConfigType
	Eth configuration type Configuration data of all controller. More...

Variables
uint32	Eth_CpswConfigType::phyMacAddr

uint32	Eth_CpswConfigType::aleAddr

uint32	Eth_CpswConfigType::cptsAddr

uint32	Eth_CpswConfigType::mdioAddr

uint32	Eth_CpswConfigType::ctrlAddr

uint32	Eth_CpswConfigType::cppiClockFreqHz

boolean	Eth_CpswConfigType::enableMdioIrq

uint32	Eth_CpswConfigType::mdioBusFreqHz

Eth_MdioOperModeType	Eth_CpswConfigType::mdioOpMode

uint32	Eth_CpswConfigType::cptsRefClockFreq

uint64 *	Eth_Udma_RingCfgType::memPtr

uint32	Eth_Udma_RingCfgType::hwId

uint32	Eth_Udma_RingCfgType::size

uint32	Eth_Udma_RingCfgType::priority

uint32	Eth_Udma_RingCfgType::proxyIdx

uint32	Eth_Udma_RingCfgType::ringMode

uint32	Eth_Udma_ProxyCfgType::proxyId

uint32	Eth_Udma_ProxyCfgType::targetNumRingId

uint32	Eth_Udma_EventCfgType::coreIntrNum

uint32	Eth_Udma_EventCfgType::virtIntrNum

uint32	Eth_Udma_EventCfgType::IrIntrNum

uint8	Eth_Udma_RingEventCfgType::ringIdx

uint8	Eth_Udma_RingEventCfgType::eventIdx

uint8	Eth_Udma_RingEventCfgType::virtBitNum

uint32	Eth_Udma_RingEventCfgType::globalEvent

uint32	Eth_Udma_RingEventCfgType::srcOffset

uint8	Eth_FifoRingMapCfgType::cqRingIdx

uint8	Eth_FifoRingMapCfgType::fqRingIdx

uint8	Eth_ChannelCfgType::tdCqRingIdx

uint16	Eth_ChannelCfgType::chId

uint8	Eth_FlowCfgType::cqRingIdx

uint8	Eth_FlowCfgType::fqRingIdx

uint16	Eth_FlowCfgType::flowId

uint8	Eth_ChannelFlowCfgType::flowNum

uint16	Eth_ChannelFlowCfgType::startFlowId

uint8 *	Eth_FifoHandleType::fifoBufferPtr

Eth_DescType *	Eth_FifoHandleType::descPtr

Eth_QueueType *	Eth_FifoHandleType::queuePtr

uint8 *	Eth_FifoHandleType::bufferState

uint16	Eth_FifoHandleType::fifoNum

uint16	Eth_FifoHandleType::elemSize

uint16	Eth_FifoHandleType::pktSize

uint32	Eth_FifoHandleType::totalSize

Eth_Udma_EventCfgType *	Eth_Udma_CfgType::eventCfgPtr

Eth_Udma_RingCfgType *	Eth_Udma_CfgType::ringCfgPtr

Eth_Udma_RingDynType *	Eth_Udma_CfgType::ringDynPtr

Eth_Udma_RingEventCfgType *	Eth_Udma_CfgType::ringEvenCfgPtr

Eth_FifoHandleType *	Eth_Udma_CfgType::egressFifoCfgPtr

Eth_FifoHandleType *	Eth_Udma_CfgType::ingressFifoCfgPtr

Eth_FifoRingMapCfgType *	Eth_Udma_CfgType::egressFifoRingMapCfgPtr

Eth_FifoRingMapCfgType *	Eth_Udma_CfgType::ingressFifoRingMapCfgPtr

uint8 *	Eth_Udma_CfgType::egressFifoPrioAssignCfgPtr

uint8 *	Eth_Udma_CfgType::ingressFifoPrioAssignCfgPtr

Eth_ChannelCfgType *	Eth_Udma_CfgType::txChanCfgPtr

Eth_ChannelCfgType *	Eth_Udma_CfgType::rxChanCfgPtr

Eth_ChannelFlowCfgType *	Eth_Udma_CfgType::rxChanFlowCfgPtr

Eth_FlowCfgType *	Eth_Udma_CfgType::flowCfgPtr

Eth_Udma_ProxyCfgType *	Eth_Udma_CfgType::proxyCfgPtr

uint16	Eth_Udma_CfgType::startTxNum

uint16	Eth_Udma_CfgType::startRxNum

uint8	Eth_Udma_CfgType::totalEventNum

uint8	Eth_Udma_CfgType::totalRingNum

uint8	Eth_Udma_CfgType::totalRingEventNum

uint8	Eth_Udma_CfgType::txThresholdNum

uint8	Eth_Udma_CfgType::rxThresholdNum

uint8	Eth_Udma_CfgType::totalEgressFifoNum

uint8	Eth_Udma_CfgType::totalIngressFifoNum

uint8	Eth_Udma_CfgType::totalTxChanNum

uint8	Eth_Udma_CfgType::totalRxChanNum

uint8	Eth_Udma_CfgType::totalFlowNum

uint16	Eth_Udma_CfgType::totalProxyNum

uint16	Eth_Udma_CfgType::txCoreIrq

uint16	Eth_Udma_CfgType::rxCoreIrq

uint16	Eth_Udma_CfgType::rxMtuLength

Eth_DmaRingCfg	Eth_Udma_CfgType::EthDmaRingCfgOps

uint32	Eth_VirtualMacConfigType::ethfwRpcComChId

EthRemoteCfg_VirtPort	Eth_VirtualMacConfigType::remoteVirtPort

Eth_RpcCmdComplete	Eth_VirtualMacConfigType::rpcCmdComplete

boolean	Eth_VirtualMacConfigType::pollRecvMsgInEthMain

Eth_RpcFwRegistered	Eth_VirtualMacConfigType::fwRegisteredCb

EthVirtMacDmaTxChannelPair	Eth_VirtualMacConfigType::txChannelPair

EthVirtMacDmaTxChannelUnPair	Eth_VirtualMacConfigType::txChannelUnPair

EthVirtMacDmaFLowCfg	Eth_VirtualMacConfigType::dmaFLowCfg

EthVirtMacDmaFLowReset	Eth_VirtualMacConfigType::dmaFLowReset

uint8	Eth_HwTimerConfigType::hwTimerId

uint32	Eth_HwTimerConfigType::hwTimerCounter

uint32	Eth_HwTimerConfigType::hwTimerBaseAddr

uint32	Eth_ControlerConfigType::ctrlIdx

Eth_EnetType	Eth_ControlerConfigType::enetType

Eth_PortType	Eth_ControlerConfigType::macPort

uint32	Eth_ControlerConfigType::macAddrHigh

uint32	Eth_ControlerConfigType::macAddrLow

boolean	Eth_ControlerConfigType::useDefaultMac

Eth_MacConnectionType	Eth_ControlerConfigType::connType

boolean	Eth_ControlerConfigType::loopback

uint32	Eth_ControlerConfigType::hwLoopTimeout

boolean	Eth_ControlerConfigType::enableTxIrq

boolean	Eth_ControlerConfigType::enableRxIrq

boolean	Eth_ControlerConfigType::isPacketMemCacheable

boolean	Eth_ControlerConfigType::isRingMemCacheable

boolean	Eth_ControlerConfigType::isDescMemCacheable

boolean	Eth_ControlerConfigType::enableVirtualMac

uint16	Eth_ControlerConfigType::demEventNum

boolean	Eth_ControlerConfigType::enableRxIrqPacing

boolean	Eth_ControlerConfigType::enableTxIrqPacing

uint8	Eth_ControlerConfigType::totalHwTimerNum

uint8	Eth_ControlerConfigType::rxHwTimerIdx

uint8	Eth_ControlerConfigType::txHwTimerIdx

Eth_VirtualMacConfigType *	Eth_ControlerConfigType::virtualMacCfg

uint16 *	Eth_ControlerConfigType::demEventCfg

Eth_CpswConfigType *	Eth_ControlerConfigType::cpswCfg

Eth_Udma_CfgType *	Eth_ControlerConfigType::dmaCfgPtr

Eth_HwTimerConfigType *	Eth_ControlerConfigType::hwTimerCfgPtr

boolean *	Eth_ControlerConfigType::hwTimerDynPtr

Eth_MdioDelayNsecFunc	Eth_ControlerConfigType::mdioWriteLowDelayNsec

Eth_MdioDelayNsecFunc	Eth_ControlerConfigType::mdioWriteHighDelayNsec

Eth_MdioDelayNsecFunc	Eth_ControlerConfigType::mdioReadLowDelayNsec

Eth_MdioDelayNsecFunc	Eth_ControlerConfigType::mdioReadHighDelayNsec

Eth_ControlerConfigType *	Eth_ConfigType::pControler [2]

Macros
#define	ETH_VERSION_INFO_API (STD_ON)
	Enable/disable SPI get version info API.

#define	ETH_GLOBALTIMESUPPORT_API (STD_ON)
	Enable/disable Eth time sync related API

#define	ETH_DEV_ERROR_DETECT (STD_ON)
	Enable/disable Development Error Detection.

#define	ETH_GET_COUNTER_VALUES_API (STD_ON)
	Enable/disable Eth get counter values API

#define	ETH_GET_RX_STATS_API (STD_ON)
	Enable/disable Eth get RX stats count API

#define	ETH_GET_TX_STATS_API (STD_ON)
	Enable/disable Eth get TX stats count API

#define	ETH_GET_TX_ERROR_COUNTERSVALUES_API (STD_ON)
	Enable/disable Eth get TX error stats count API

#define	ETH_ZERO_COPY_API (STD_OFF)
	Enable/disable Eth Zero-Copy support related APIs

#define	ETH_HEADER_ACCESS_API (STD_OFF)
	Enable/disable Eth Tx/Rx Header Access related APIs

#define	ETH_TRAFFIC_SHAPING_API (STD_OFF)
	Enable/disable Eth Traffic Shaping related APIs

#define	ETH_GET_COUNTER_STATE_API (STD_OFF)
	Enable/disable Eth get Counter state API

#define	ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP (STD_OFF)
	Enable/disable Hardware Offloading for ICMP checksums.

#define	ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4 (STD_OFF)
	Enable/disable Hardware offloading for IPv4 Header checksums.

#define	ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP (STD_OFF)
	Enable/disable Hardware offloading for TCP checksums.

#define	ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP (STD_OFF)
	Enable/disable Hardware offloading for UDP checksums.

#define	ETH_REGISTER_READBACK_API (STD_ON)
	Enable/disable optional API Eth_RegisterReadback.

#define	ETH_TIMESTAMP_VIA_CPTS_EVENT_FIFO (STD_ON)
	Enable/disable Eth CPTS event FIFO.

#define	ETH_PHY_FAULT_DETECTION_ENABLE (STD_ON)
	Enable/disable Eth Phy fault detection.

#define	ETH_ENABLE_MII_API (STD_ON)
	Enable/disable Eth MII related API

#define	ETH_UPDATE_PHYS_ADDR_FILTER_API (STD_ON)
	Enable/disable optional API Eth_UpdatePhysAddrFilter.

#define	ETH_ENABLE_IRQ_PACING (STD_OFF)
	Enable/disable IRQ pacing feature.

#define	ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API (STD_OFF)
	Enable/disable optional API Eth_NotifyVirtmacMsgReceived.

#define	ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacSubscribeAllTraffic.

#define	ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacUnsubscribeAllTraffic.

#define	ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacSubscribeDstMac.

#define	ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacUnsubscribeDstMac.

#define	ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacAssociateIPv4Macaddr.

#define	ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacDisassociateIPv4Macaddr.

#define	ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacAddMcastAddr.

#define	ETH_VIRTUALMAC_DEL_MACADDR_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacDelAddr.

#define	ETH_VIRTUALMAC_ADD_VLAN_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacAddVlan.

#define	ETH_VIRTUALMAC_DEL_VLAN_API (STD_OFF)
	Enable/disable optional API Eth_DispatchVirtmacDelVlan.

#define	ETH_ETHIF_CBK_HEADER "EthIf_Cbk.h"
	EthIf Callback Header File to include inside the Eth driver.

#define	ETH_ISR_TYPE (ETH_ISR_CAT2)
	ISR type.

#define	ETH_OS_COUNTER_ID ((CounterType)OsCounter_0)
	Counter ID for counter used to count wait ticks.

#define	ETH_OS_COUNTER_FREQ (1000000000U)
	Frequency in Hz of the counter specified in ETH_OS_COUNTER_ID.

#define	ETH_INVALID_RING_ID (0xFFFFU)
	Eth Invalid Ring Id value.

#define	ETH_INVALID_EVENT_ID (0xFFFFU)
	Eth Invalid Event Id value.

#define	ETH_INVALID_CHAN_ID (0xFFFFU)
	Eth Invalid channel Id.

#define	ETH_INVALID_FLOW_ID (0xFFFFU)
	Eth Invalid Flow Id.

#define	ETH_INVALID_IRQ_ID (0xFFFFU)
	Eth Invalid IRQ value.

#define	ETH_DEM_NO_EVENT (0xFFFFU)
	Eth invalid DEM event ID

#define	ETH_VIRTUALMAC_SUPPORT (STD_OFF)
	Enable/disable Virtual MAC support.

#define	ETH_VIRTUALMAC_FWINFO_TIMEOUT (0U)
	Timeout value for Firmware Attach msg received from server.

enum	Eth_PortType { ETH_PORT_HOST_PORT = 0x00U , ETH_MAC_PORT_FIRST = 0x01U , ETH_PORT_MAC_PORT_1 = 0x01U , ETH_PORT_MAC_PORT_2 = 0x02U , ETH_PORT_MAC_PORT_3 = 0x03U , ETH_PORT_MAC_PORT_4 = 0x04U , ETH_PORT_MAC_PORT_5 = 0x05U , ETH_PORT_MAC_PORT_6 = 0x06U , ETH_PORT_MAC_PORT_7 = 0x07U , ETH_PORT_MAC_PORT_8 = 0x08U , ETH_PORT_MAC_PORT_LAST = ETH_PORT_MAC_PORT_8 }
	Port identifier. More...

enum	Eth_MacConnectionType { ETH_MAC_CONN_TYPE_RMII_10 = 0x01U , ETH_MAC_CONN_TYPE_RMII_100 = 0x02U , ETH_MAC_CONN_TYPE_RGMII_FORCE_100_HALF = 0x03U , ETH_MAC_CONN_TYPE_RGMII_FORCE_100_FULL = 0x04U , ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL = 0x05U , ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND = 0x06U }
	Type/Speed/Duplex connection type. More...

enum	Eth_EnetType { ETH_ENETTYPE_CPSW2G = 0x00U , ETH_ENETTYPE_CPSW9G = 0x01U , ETH_ENETTYPE_CPSW5G = 0x02U , ETH_ENETTYPE_CPSW3G = 0x03U , ETH_ENETTYPE_CPSWLAST }
	Enet Cpsw Type identifier. More...

enum	Eth_MdioOperModeType { ETH_MDIO_OPMODE_NORMAL = 0x00U , ETH_MDIO_OPMODE_MANUAL = 0x01U }
	MDIO operating mode. More...

typedef void(*	Eth_RpcCmdComplete) (uint8 CtrlIdx, uint8 sid, sint32 status)
	Application callback to indicate Rpc dispatch command completion.

typedef void(*	Eth_RpcFwRegistered) (uint8 CtrlIdx)
	Application callback to indicate Ethernet firmware registered with the Eth RPC client.

typedef Std_ReturnType(*	Eth_DmaRingCfg) (uint8 ctrlIdx, uint8 ringIdx)
	Mdio delay in nsec function pointer.

typedef void(*	Eth_MdioDelayNsecFunc) (void)
	Pair PSIL TX channel function pointer.

typedef Std_ReturnType(*	EthVirtMacDmaTxChannelPair) (uint8 ctrlIdx)
	Unpair PSIL TX channel function pointer.

typedef Std_ReturnType(*	EthVirtMacDmaTxChannelUnPair) (uint8 ctrlIdx)
	Flow config function pointer.

typedef Std_ReturnType(*	EthVirtMacDmaFLowCfg) (uint8 ctrlIdx)
	Flow reset function pointer.

typedef Std_ReturnType(*	EthVirtMacDmaFLowReset) (uint8 ctrlIdx)

const Eth_Udma_RingCfgType	Eth_Udma_RingCfg_0 [6U]

const Eth_Udma_EventCfgType	Eth_EventCfg_Ctrl_0 [2U]

const Eth_Udma_RingEventCfgType	Eth_RingEventCfg_Ctrl_0 [2U]

	VAR (uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[24576U]

	VAR (Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_Descriptor_0[16U]

	VAR (uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_BufferState_0[16U]

	VAR (Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_Queue_0[1U]

	VAR (Eth_Udma_RingDynType, ETH_VAR_NO_INIT) Eth_RingDyn_Ctrl_0[6U]

Std_ReturnType	AppUtils_EthRingCfg (uint8 ctrlIdx, uint8 Id)

#define	EthConf_EthCtrlConfig_EthConfig_0 (0U)
	Eth controller ID Configured controller ID(s)

#define	ETH_CTRL_ID_0 (0U)

#define	ETH_PRE_COMPILE_VARIANT (STD_ON)
	Eth configuration variant.

#define	ETH_LINK_TIME_VARIANT (STD_OFF)

#define	ETH_POST_BUILD_VARIANT (STD_OFF)

#define	ETH_CTRL_ID_MAX (1U)
	Eth max controller ID.

#define	NOP1 asm (" NOP ")
	NOP Macros Macros to insert "NOP" assembly instructions.

#define	NOP5 NOP1; NOP1; NOP1; NOP1; NOP1

#define	NOP10 NOP5; NOP5

#define	NOP20 NOP10; NOP10

#define	NOP30 NOP20; NOP10

#define	NOP40 NOP30; NOP10

#define	NOP50 NOP40; NOP10

#define	NOP100 NOP50; NOP50

#define	NOP200 NOP100; NOP100

#define	NOP300 NOP200; NOP100

#define	NOP400 NOP300; NOP100

#define	NOP500 NOP400; NOP100

#define	ETH_DMA_IR_SUPPORT (STD_ON)
	Eth DMA feature flag support.

#define	ETH_DMA_CQ_RING_SUPPORT (STD_ON)

#define	ETH_DMA_TEARDOWN_SUPPORT (STD_ON)

#define	ETH_DMA_PROXY_SUPPORT (STD_ON)

#define	ETH_DMA_RX_CH_SPERATE (STD_OFF)

#define	UDMA_DEVICE_ID_RING (235U)
	Eth DMA devices ID.

#define	UDMA_DEVICE_ID_UDMA (236U)

#define	UDMA_DEVICE_ID_PSIL (232U)

#define	UDMA_DEVICE_ID_IA (233U)

#define	UDMA_DEVICE_ID_IR (237U)

#define	UDMA_DEVICE_ID_CORE (250U)

#define	UDMA_DEVICE_ID_PROXY (234U)

#define	UDMA_TX_CHANNEL_PEER_OFFSET (0xf000U)
	Eth DMA peer and thread offset.

#define	UDMA_RX_CHANNEL_PEER_OFFSET (0x7000U)

#define	UDMA_SOURCE_THREAD_OFFSET (0x6000U)

#define	UDMA_DEST_THREAD_OFFSET (0xe000U)

#define	ETH_DMA_TX_BASE_REG (0x2aa00000U)
	Eth DMA base register address.

#define	ETH_DMA_RX_BASE_REG (0x2a800000U)

#define	ETH_DMA_RINGRT_BASE (0x2b800000U)

#define	ETH_DMA_RINGCFG_BASE (0x28440000U)

#define	ETH_DMA_INTAGGR_INTR_BASE (0x2a700000U)

#define	ETH_DMA_TXCRT_CHAN_CTL(CHAN)
	Eth DMA macro to calculate register address for DMA register address.

#define	ETH_DMA_TXCRT_CHAN_PEER8(CHAN)

#define	ETH_DMA_RXCRT_CHAN_CTL(CHAN)

#define	ETH_DMA_RXCRT_CHAN_PEER8(CHAN)

#define	ETH_DMA_RINGRT_RING_FDB(RING)

#define	ETH_DMA_RINGRT_RING_FOCC(RING)

#define	ETH_DMA_RINGRT_RING_RDB(RING)

#define	ETH_DMA_RINGRT_RING_ROCC(RING)

#define	ETH_DMA_RINGRT_RING_HWOCC(RING)

#define	ETH_DMA_RINGCFG_RING_SIZE(RING)

#define	ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET(VINT)

#define	ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR(VINT)

#define	ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET(VINT)

#define	ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR(VINT)

#define	ETH_DMA_INTAGGR_INTR_VINT_STATUSM(VINT)

#define	Eth_GetRingFDBReg(RingNum)

#define	Eth_GetRingFOCCReg(RingNum)

#define	Eth_GetRingRDBReg(RingNum)

#define	Eth_GetRingROCCReg(RingNum)

#define	Eth_GetRingHWOCCReg(RingNum)

#define	Eth_GetRingSizeReg(RingNum)

#define	Eth_GetTxChannelCtlRegAddress(ChanId)

#define	Eth_GetTxChannelPeer8RegAddress(ChanId)

#define	Eth_GetRxChannelCtlRegAddress(ChanId)

#define	Eth_GetRxChannelPeer8RegAddress(ChanId)

#define	ETH_CSL_PROXY0_TARGET0_DATA_BASE (0x2a500000U)

#define	ETH_CSL_PROXY_TARGET0_PROXY_CTL(PROXY)

#define	ETH_CSL_PROXY_TARGET0_PROXY_DATA_FIELD(PROXY)

#define	UDMA_WAIT_TEARDOWN_COUNTER (10000u)
	Eth DMA max teardown timeout.

#define	ETH_DEM_EVENT_SUPPORT (STD_OFF)
	ETH support DEM event feature.

#define	ETH_RX_MTU_HOST_PORT_LENGTH (1522U)
	Eth max MTU for host port in bytes This value need to equal max MTU for all ingress fifo buffer size.

#define	Eth_Cpsw_GetPhyMacRegAddr()
	Eth function like macro to access Eth general configuration.

#define	Eth_Cpsw_GetAleRegAddr()

#define	Eth_Cpsw_GetCptsRegAddr()

#define	Eth_Cpsw_GetMdioRegAddr()

#define	Eth_Cpsw_GetCtrlRegAddr()

#define	Eth_Cpsw_GetCppiClockFreq()

#define	Eth_Cpsw_GetCptsRefClockFreq()

#define	Eth_Cpsw_GetMdioBusClockFreq()

#define	Eth_Cpsw_GetMdioOpMode()

#define	Eth_Cpsw_GetMdioEnableInterrupt()

#define	Eth_GetDem_E_HARDWARE_ERROR(CtrlIndex)
	ETH DEM Error codes to report.

#define	Eth_GetDem_E_LATECOLLISION(CtrlIndex)

#define	Eth_GetDem_E_MULTIPLECOLLISION(CtrlIndex)

#define	Eth_GetDem_E_SINGLECOLLISION(CtrlIndex)

#define	Eth_GetDem_E_ALIGNMENT(CtrlIndex)

#define	Eth_GetDem_E_OVERSIZEFRAME(CtrlIndex)

#define	Eth_GetDem_E_UNDERSIZEFRAME(CtrlIndex)

#define	Eth_GetDem_E_CRC(CtrlIndex)

#define	Eth_GetDem_E_RX_FRAMES_LOST(CtrlIndex)

#define	Eth_GetDem_E_ACCESS(CtrlIndex)

#define	Eth_GetDem_E_TX_INTERNAL(CtrlIndex)

#define	Eth_IsVirtualMacModeEnable(CtrlIndex)
	Eth function like macro to access controler configuration.

#define	Eth_GetTxChannelThreadOffset(CtrlIndex)

#define	Eth_VirtMacGetEthFwRpcComChannelId(CtrlIndex)

#define	Eth_VirtMacGetEthPollRecvMsgInEthMain(CtrlIndex)

#define	Eth_VirtMacGetRpcCmdCompleteFuncPtr(CtrlIndex)

#define	Eth_VirtMacGetFwRegisterFuncPtr(CtrlIndex)

#define	Eth_VirtMacGetRemoteVirtPort(CtrlIndex)

#define	Eth_VirtMacGetDmaTxChannelPairAll(CtrlIdx)

#define	Eth_VirtMacGetDmaTxChannelUnpairAll(CtrlIdx)

#define	Eth_VirtMacGetDmaFlowCfgAll(CtrlIdx)

#define	Eth_VirtMacGetDmaFlowResetAll(CtrlIdx)

#define	Eth_GetTxEnableInterrupt(CtrlIndex)

#define	Eth_GetRxEnableInterrupt(CtrlIndex)

#define	Eth_GetEnetType(CtrlIndex)

#define	Eth_GetMacPortNum(CtrlIndex)

#define	Eth_GetMacAddressHigh(CtrlIndex)

#define	Eth_GetMacAddressLow(CtrlIndex)

#define	Eth_UseDefaultMacAddress(CtrlIndex)

#define	Eth_GetMiiConnectionType(CtrlIndex)

#define	Eth_GetLoopBackMode(CtrlIndex)

#define	Eth_GetHardwareLoopTimeout(CtrlIndex)

#define	Eth_IsPacketMemCacheable(CtrlIndex)

#define	Eth_IsRingMemCacheable(CtrlIndex)

#define	Eth_IsDescMemCacheable(CtrlIndex)

#define	Eth_GetRxMtuLength(CtrlIndex)

#define	Eth_GetTxChanStartNum(CtrlIndex)

#define	Eth_GetRxChanStartNum(CtrlIndex)

#define	Eth_GetEgressFifoTotalNum(CtrlIndex)

#define	Eth_GetIngressFifoTotalNum(CtrlIndex)

#define	Eth_GetRingTotalNum(CtrlIndex)

#define	Eth_GetTxChanTotalNum(CtrlIndex)

#define	Eth_GetRxChanTotalNum(CtrlIndex)

#define	Eth_GetFlowTotalNumber(CtrlIndex)

#define	Eth_GetEventTotalNum(CtrlIndex)

#define	Eth_GetRingEventTotalNum(CtrlIndex)

#define	Eth_GetTxDmaThresholdNum(CtrlIndex)

#define	Eth_GetRxDmaThresholdNum(CtrlIndex)

#define	Eth_GetEgressFifoPacketNum(CtrlIndex, FifoIdx)

#define	Eth_GetEgressFifoPacketSize(CtrlIndex, FifoIdx)

#define	Eth_GetIngressFifoPacketNum(CtrlIndex, FifoIdx)

#define	Eth_GetIngressFifoPacketSize(CtrlIndex, FifoIdx)

#define	Eth_GetEgressFifoPriorityAsignment(CtrlIndex, Prio)

#define	Eth_GetIngressFifoPriorirtyAsignment(CtrlIndex, Prio)

#define	Eth_GetEgressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx)

#define	Eth_GetEgressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx)

#define	Eth_GetEgressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx)

#define	Eth_GetEgressFifoQueueAddress(CtrlIndex, FifoIdx)

#define	Eth_GetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx)

#define	Eth_SetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val)

#define	Eth_GetIngressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx)

#define	Eth_GetIngressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx)

#define	Eth_GetIngressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx)

#define	Eth_GetIngressFifoQueueAddress(CtrlIndex, FifoIdx)

#define	Eth_GetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx)

#define	Eth_SetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val)

#define	Eth_GetEgressFifoCqIdx(CtrlIndex, FifoIdx)

#define	Eth_GetEgressFifoFqIdx(CtrlIndex, FifoIdx)

#define	Eth_GetIngressFifoCqIdx(CtrlIndex, FifoIdx)

#define	Eth_GetIngressFifoFqIdx(CtrlIndex, FifoIdx)

#define	Eth_GetTxChanId(CtrlIndex, ChIdx)

#define	Eth_GetTxChanTdCqRingIdx(CtrlIndex, ChIdx)

#define	Eth_GetTxChanDepth(CtrlIndex, ChIdx)

#define	Eth_GetRxChanId(CtrlIndex, ChIdx)

#define	Eth_GetRxChanTdCqRingIdx(CtrlIndex, ChIdx)

#define	Eth_GetRxChanFlowTotalNum(CtrlIndex, ChIdx)

#define	Eth_GetRxChanFlowStartNum(CtrlIndex, ChIdx)

#define	Eth_GetFlowId(CtrlIndex, FlowIdx)

#define	Eth_GetFlowCqRingIdx(CtrlIndex, FlowIdx)

#define	Eth_GetFlowFqRingIdx(CtrlIndex, FlowIdx)

#define	Eth_GetDynRingElemAddress(CtrlIndex, RingIdx)

#define	Eth_GetRingHwId(CtrlIndex, RingIdx)

#define	Eth_GetRingTotalElemNum(CtrlIndex, RingIdx)

#define	Eth_GetRingPriority(CtrlIndex, RingIdx)

#define	Eth_GetRingMemBaseAddress(CtrlIndex, RingIdx)

#define	Eth_GetRingEventRingIdx(CtrlIndex, RingEvtIdx)

#define	Eth_GetRingEventGlobalEventNum(CtrlIndex, RingEvtIdx)

#define	Eth_GetRingEventVirtBitNum(CtrlIndex, RingEvtIdx)

#define	Eth_GetRingEventEventIdx(CtrlIndex, RingEvtIdx)

#define	Eth_GetRingEventSrcOffsetNum(CtrlIndex, RingEvtIdx)

#define	Eth_GetEventCoreIntrNum(CtrlIndex, EvtIdx)

#define	Eth_GetEventVirtIntrNum(CtrlIndex, EvtIdx)

#define	Eth_GetEventIrIntrNum(CtrlIndex, EvtIdx)

#define	Eth_GetTxEventCoreIntrNum(CtrlIndex)

#define	Eth_GetRxEventCoreIntrNum(CtrlIndex)

#define	Eth_GetHwTimerTotalNum(CtrlIndex)

#define	Eth_GetHwTimerId(CtrlIndex, Index)

#define	Eth_GetHwTimerCounter(CtrlIndex, Index)

#define	Eth_GetHwTimerBaseAddr(CtrlIndex, Index)

#define	Eth_GetHwTimerDynRunningState(CtrlIndex, Index)

#define	Eth_SetHwTimerDynRunningState(CtrlIndex, Index, Val)

#define	Eth_GetRxIrqPacingEnable(CtrlIndex)

#define	Eth_GetTxIrqPacingEnable(CtrlIndex)

#define	Eth_GetRxHwTimerIdx(CtrlIndex)

#define	Eth_GetTxHwTimerIdx(CtrlIndex)

#define	Eth_GetIrqPacingEnable(CtrlIndex)

#define	Eth_GetProxyTotalNum(CtrlIndex)

#define	Eth_GetProxyThreadNum(CtrlIndex, ProxyIdx)

#define	Eth_GetProxyTargetRingNum(CtrlIndex, ProxyIdx)

#define	Eth_GetRingProxyIdx(CtrlIndex, RingIdx)

#define	Eth_GetRingMode(CtrlIndex, RingIdx)

#define	Eth_GetDmaRingCfg(CtrlIdx)

#define	ETH_START_SEC_CONST_UNSPECIFIED

#define	ETH_STOP_SEC_CONST_UNSPECIFIED

#define	ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128

#define	ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128

#define	ETH_START_SEC_VAR_NO_INIT_8

#define	ETH_STOP_SEC_VAR_NO_INIT_8

#define	ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED

#define	ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED

#define	ETH_START_SEC_CODE
	Ring configure via SciClient function.

#define	ETH_STOP_SEC_CODE

#define	Eth_GetMdioWriteLowBaseNsec()
	DelayNs (default value) in NOOP function/function like macro.

#define	Eth_GetMdioWriteHighBaseNsec()

#define	Eth_GetMdioReadLowBaseNsec()

#define	Eth_GetMdioReadHighBaseNsec()

#define	Eth_GetMdioWriteLowDelayNsec(CtrlIdx)
	DelayNs (generate by user input) in NOOP function/function like macro.

#define	Eth_GetMdioWriteHighDelayNsec(CtrlIdx)

#define	Eth_GetMdioReadLowDelayNsec(CtrlIdx)

#define	Eth_GetMdioReadHighDelayNsec(CtrlIdx)

Macro Definition Documentation

◆ ETH_VERSION_INFO_API

#define ETH_VERSION_INFO_API (STD_ON)

Enable/disable SPI get version info API.

◆ ETH_GLOBALTIMESUPPORT_API

#define ETH_GLOBALTIMESUPPORT_API (STD_ON)

Enable/disable Eth time sync related API

◆ ETH_DEV_ERROR_DETECT

#define ETH_DEV_ERROR_DETECT (STD_ON)

Enable/disable Development Error Detection.

◆ ETH_GET_COUNTER_VALUES_API

#define ETH_GET_COUNTER_VALUES_API (STD_ON)

Enable/disable Eth get counter values API

◆ ETH_GET_RX_STATS_API

#define ETH_GET_RX_STATS_API (STD_ON)

Enable/disable Eth get RX stats count API

◆ ETH_GET_TX_STATS_API

#define ETH_GET_TX_STATS_API (STD_ON)

Enable/disable Eth get TX stats count API

◆ ETH_GET_TX_ERROR_COUNTERSVALUES_API

#define ETH_GET_TX_ERROR_COUNTERSVALUES_API (STD_ON)

Enable/disable Eth get TX error stats count API

◆ ETH_ZERO_COPY_API

#define ETH_ZERO_COPY_API (STD_OFF)

Enable/disable Eth Zero-Copy support related APIs

◆ ETH_HEADER_ACCESS_API

#define ETH_HEADER_ACCESS_API (STD_OFF)

Enable/disable Eth Tx/Rx Header Access related APIs

◆ ETH_TRAFFIC_SHAPING_API

#define ETH_TRAFFIC_SHAPING_API (STD_OFF)

Enable/disable Eth Traffic Shaping related APIs

◆ ETH_GET_COUNTER_STATE_API

#define ETH_GET_COUNTER_STATE_API (STD_OFF)

Enable/disable Eth get Counter state API

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP (STD_OFF)

Enable/disable Hardware Offloading for ICMP checksums.

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4 (STD_OFF)

Enable/disable Hardware offloading for IPv4 Header checksums.

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP (STD_OFF)

Enable/disable Hardware offloading for TCP checksums.

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP (STD_OFF)

Enable/disable Hardware offloading for UDP checksums.

◆ ETH_REGISTER_READBACK_API

#define ETH_REGISTER_READBACK_API (STD_ON)

Enable/disable optional API Eth_RegisterReadback.

◆ ETH_TIMESTAMP_VIA_CPTS_EVENT_FIFO

#define ETH_TIMESTAMP_VIA_CPTS_EVENT_FIFO (STD_ON)

Enable/disable Eth CPTS event FIFO.

◆ ETH_PHY_FAULT_DETECTION_ENABLE

#define ETH_PHY_FAULT_DETECTION_ENABLE (STD_ON)

Enable/disable Eth Phy fault detection.

◆ ETH_ENABLE_MII_API

#define ETH_ENABLE_MII_API (STD_ON)

Enable/disable Eth MII related API

◆ ETH_UPDATE_PHYS_ADDR_FILTER_API

#define ETH_UPDATE_PHYS_ADDR_FILTER_API (STD_ON)

Enable/disable optional API Eth_UpdatePhysAddrFilter.

◆ ETH_ENABLE_IRQ_PACING

#define ETH_ENABLE_IRQ_PACING (STD_OFF)

Enable/disable IRQ pacing feature.

◆ ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API

#define ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API (STD_OFF)

Enable/disable optional API Eth_NotifyVirtmacMsgReceived.

◆ ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API

#define ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacSubscribeAllTraffic.

◆ ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API

#define ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacUnsubscribeAllTraffic.

◆ ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API

#define ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacSubscribeDstMac.

◆ ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API

#define ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacUnsubscribeDstMac.

◆ ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API

#define ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacAssociateIPv4Macaddr.

◆ ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API

#define ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacDisassociateIPv4Macaddr.

◆ ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API

#define ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacAddMcastAddr.

◆ ETH_VIRTUALMAC_DEL_MACADDR_API

#define ETH_VIRTUALMAC_DEL_MACADDR_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacDelAddr.

◆ ETH_VIRTUALMAC_ADD_VLAN_API

#define ETH_VIRTUALMAC_ADD_VLAN_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacAddVlan.

◆ ETH_VIRTUALMAC_DEL_VLAN_API

#define ETH_VIRTUALMAC_DEL_VLAN_API (STD_OFF)

Enable/disable optional API Eth_DispatchVirtmacDelVlan.

◆ ETH_ETHIF_CBK_HEADER

#define ETH_ETHIF_CBK_HEADER "EthIf_Cbk.h"

EthIf Callback Header File to include inside the Eth driver.

◆ ETH_ISR_TYPE

#define ETH_ISR_TYPE (ETH_ISR_CAT2)

ISR type.

◆ ETH_OS_COUNTER_ID

#define ETH_OS_COUNTER_ID ((CounterType)OsCounter_0)

Counter ID for counter used to count wait ticks.

◆ ETH_OS_COUNTER_FREQ

#define ETH_OS_COUNTER_FREQ (1000000000U)

Frequency in Hz of the counter specified in ETH_OS_COUNTER_ID.

◆ ETH_INVALID_RING_ID

#define ETH_INVALID_RING_ID (0xFFFFU)

Eth Invalid Ring Id value.

◆ ETH_INVALID_EVENT_ID

#define ETH_INVALID_EVENT_ID (0xFFFFU)

Eth Invalid Event Id value.

◆ ETH_INVALID_CHAN_ID

#define ETH_INVALID_CHAN_ID (0xFFFFU)

Eth Invalid channel Id.

◆ ETH_INVALID_FLOW_ID

#define ETH_INVALID_FLOW_ID (0xFFFFU)

Eth Invalid Flow Id.

◆ ETH_INVALID_IRQ_ID

#define ETH_INVALID_IRQ_ID (0xFFFFU)

Eth Invalid IRQ value.

◆ ETH_DEM_NO_EVENT

#define ETH_DEM_NO_EVENT (0xFFFFU)

Eth invalid DEM event ID

◆ ETH_VIRTUALMAC_SUPPORT

#define ETH_VIRTUALMAC_SUPPORT (STD_OFF)

Enable/disable Virtual MAC support.

◆ ETH_VIRTUALMAC_FWINFO_TIMEOUT

#define ETH_VIRTUALMAC_FWINFO_TIMEOUT (0U)

Timeout value for Firmware Attach msg received from server.

◆ EthConf_EthCtrlConfig_EthConfig_0

#define EthConf_EthCtrlConfig_EthConfig_0 (0U)

Eth controller ID Configured controller ID(s)

◆ ETH_CTRL_ID_0

#define ETH_CTRL_ID_0 (0U)

◆ ETH_PRE_COMPILE_VARIANT

#define ETH_PRE_COMPILE_VARIANT (STD_ON)

Eth configuration variant.

◆ ETH_LINK_TIME_VARIANT

#define ETH_LINK_TIME_VARIANT (STD_OFF)

◆ ETH_POST_BUILD_VARIANT

#define ETH_POST_BUILD_VARIANT (STD_OFF)

◆ ETH_CTRL_ID_MAX

#define ETH_CTRL_ID_MAX (1U)

Eth max controller ID.

◆ NOP1

#define NOP1 asm (" NOP ")

NOP Macros Macros to insert "NOP" assembly instructions.

◆ NOP5

#define NOP5 NOP1; NOP1; NOP1; NOP1; NOP1

◆ NOP10

#define NOP10 NOP5; NOP5

◆ NOP20

#define NOP20 NOP10; NOP10

◆ NOP30

#define NOP30 NOP20; NOP10

◆ NOP40

#define NOP40 NOP30; NOP10

◆ NOP50

#define NOP50 NOP40; NOP10

◆ NOP100

#define NOP100 NOP50; NOP50

◆ NOP200

#define NOP200 NOP100; NOP100

◆ NOP300

#define NOP300 NOP200; NOP100

◆ NOP400

#define NOP400 NOP300; NOP100

◆ NOP500

#define NOP500 NOP400; NOP100

◆ ETH_DMA_IR_SUPPORT

#define ETH_DMA_IR_SUPPORT (STD_ON)

Eth DMA feature flag support.

◆ ETH_DMA_CQ_RING_SUPPORT

#define ETH_DMA_CQ_RING_SUPPORT (STD_ON)

◆ ETH_DMA_TEARDOWN_SUPPORT

#define ETH_DMA_TEARDOWN_SUPPORT (STD_ON)

◆ ETH_DMA_PROXY_SUPPORT

#define ETH_DMA_PROXY_SUPPORT (STD_ON)

◆ ETH_DMA_RX_CH_SPERATE

#define ETH_DMA_RX_CH_SPERATE (STD_OFF)

◆ UDMA_DEVICE_ID_RING

#define UDMA_DEVICE_ID_RING (235U)

Eth DMA devices ID.

◆ UDMA_DEVICE_ID_UDMA

#define UDMA_DEVICE_ID_UDMA (236U)

◆ UDMA_DEVICE_ID_PSIL

#define UDMA_DEVICE_ID_PSIL (232U)

◆ UDMA_DEVICE_ID_IA

#define UDMA_DEVICE_ID_IA (233U)

◆ UDMA_DEVICE_ID_IR

#define UDMA_DEVICE_ID_IR (237U)

◆ UDMA_DEVICE_ID_CORE

#define UDMA_DEVICE_ID_CORE (250U)

◆ UDMA_DEVICE_ID_PROXY

#define UDMA_DEVICE_ID_PROXY (234U)

◆ UDMA_TX_CHANNEL_PEER_OFFSET

#define UDMA_TX_CHANNEL_PEER_OFFSET (0xf000U)

Eth DMA peer and thread offset.

◆ UDMA_RX_CHANNEL_PEER_OFFSET

#define UDMA_RX_CHANNEL_PEER_OFFSET (0x7000U)

◆ UDMA_SOURCE_THREAD_OFFSET

#define UDMA_SOURCE_THREAD_OFFSET (0x6000U)

◆ UDMA_DEST_THREAD_OFFSET

#define UDMA_DEST_THREAD_OFFSET (0xe000U)

◆ ETH_DMA_TX_BASE_REG

#define ETH_DMA_TX_BASE_REG (0x2aa00000U)

Eth DMA base register address.

◆ ETH_DMA_RX_BASE_REG

#define ETH_DMA_RX_BASE_REG (0x2a800000U)

◆ ETH_DMA_RINGRT_BASE

#define ETH_DMA_RINGRT_BASE (0x2b800000U)

◆ ETH_DMA_RINGCFG_BASE

#define ETH_DMA_RINGCFG_BASE (0x28440000U)

◆ ETH_DMA_INTAGGR_INTR_BASE

#define ETH_DMA_INTAGGR_INTR_BASE (0x2a700000U)

◆ ETH_DMA_TXCRT_CHAN_CTL

#define ETH_DMA_TXCRT_CHAN_CTL ( CHAN )

Value:

(0x00000000U + ((CHAN) * 0x1000U))

Eth DMA macro to calculate register address for DMA register address.

◆ ETH_DMA_TXCRT_CHAN_PEER8

#define ETH_DMA_TXCRT_CHAN_PEER8 ( CHAN )

Value:

(0x00000220U + ((CHAN) * 0x1000U))

◆ ETH_DMA_RXCRT_CHAN_CTL

#define ETH_DMA_RXCRT_CHAN_CTL ( CHAN )

Value:

(0x00000000U + ((CHAN) * 0x1000U))

◆ ETH_DMA_RXCRT_CHAN_PEER8

#define ETH_DMA_RXCRT_CHAN_PEER8 ( CHAN )

Value:

(0x00000220U + ((CHAN) * 0x1000U))

◆ ETH_DMA_RINGRT_RING_FDB

#define ETH_DMA_RINGRT_RING_FDB ( RING )

Value:

(0x00000010U + ((RING) * 0x1000U))

◆ ETH_DMA_RINGRT_RING_FOCC

#define ETH_DMA_RINGRT_RING_FOCC ( RING )

Value:

(0x00000018U + ((RING) * 0x1000U))

◆ ETH_DMA_RINGRT_RING_RDB

#define ETH_DMA_RINGRT_RING_RDB ( RING )

Value:

(0x00000010U + ((RING) * 0x1000U))

◆ ETH_DMA_RINGRT_RING_ROCC

#define ETH_DMA_RINGRT_RING_ROCC ( RING )

Value:

(0x00000018U + ((RING) * 0x1000U))

◆ ETH_DMA_RINGRT_RING_HWOCC

#define ETH_DMA_RINGRT_RING_HWOCC ( RING )

Value:

(0x00000020U + ((RING) * 0x1000U))

◆ ETH_DMA_RINGCFG_RING_SIZE

#define ETH_DMA_RINGCFG_RING_SIZE ( RING )

Value:

(0x00000048U + ((RING) * 0x100U))

◆ ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET

#define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET ( VINT )

Value:

(ETH_DMA_INTAGGR_INTR_BASE + 0x00000000U + ((VINT) * 0x1000U))

ETH_DMA_INTAGGR_INTR_BASE

#define ETH_DMA_INTAGGR_INTR_BASE

Definition Eth_Cfg.h:317

◆ ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR

#define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR ( VINT )

Value:

(ETH_DMA_INTAGGR_INTR_BASE + 0x00000008U + ((VINT) * 0x1000U))

◆ ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET

#define ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET ( VINT )

Value:

(ETH_DMA_INTAGGR_INTR_BASE + 0x00000010U + ((VINT) * 0x1000U))

◆ ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR

#define ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR ( VINT )

Value:

(ETH_DMA_INTAGGR_INTR_BASE + 0x00000018U + ((VINT) * 0x1000U))

◆ ETH_DMA_INTAGGR_INTR_VINT_STATUSM

#define ETH_DMA_INTAGGR_INTR_VINT_STATUSM ( VINT )

Value:

(ETH_DMA_INTAGGR_INTR_BASE + 0x00000020U + ((VINT) * 0x1000U))

◆ Eth_GetRingFDBReg

#define Eth_GetRingFDBReg ( RingNum )

Value:

(ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FDB((RingNum)))

ETH_DMA_RINGRT_RING_FDB

#define ETH_DMA_RINGRT_RING_FDB(RING)

Definition Eth_Cfg.h:329

ETH_DMA_RINGRT_BASE

#define ETH_DMA_RINGRT_BASE

Definition Eth_Cfg.h:315

◆ Eth_GetRingFOCCReg

#define Eth_GetRingFOCCReg ( RingNum )

Value:

(ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FOCC((RingNum)))

ETH_DMA_RINGRT_RING_FOCC

#define ETH_DMA_RINGRT_RING_FOCC(RING)

Definition Eth_Cfg.h:330

◆ Eth_GetRingRDBReg

#define Eth_GetRingRDBReg ( RingNum )

Value:

(ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_RDB((RingNum)))

ETH_DMA_RINGRT_RING_RDB

#define ETH_DMA_RINGRT_RING_RDB(RING)

Definition Eth_Cfg.h:331

◆ Eth_GetRingROCCReg

#define Eth_GetRingROCCReg ( RingNum )

Value:

(ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_ROCC((RingNum)))

ETH_DMA_RINGRT_RING_ROCC

#define ETH_DMA_RINGRT_RING_ROCC(RING)

Definition Eth_Cfg.h:332

◆ Eth_GetRingHWOCCReg

#define Eth_GetRingHWOCCReg ( RingNum )

Value:

(ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_HWOCC((RingNum)))

ETH_DMA_RINGRT_RING_HWOCC

#define ETH_DMA_RINGRT_RING_HWOCC(RING)

Definition Eth_Cfg.h:333

◆ Eth_GetRingSizeReg

#define Eth_GetRingSizeReg ( RingNum )

Value:

(ETH_DMA_RINGCFG_BASE + ETH_DMA_RINGCFG_RING_SIZE((RingNum)))

ETH_DMA_RINGCFG_BASE

#define ETH_DMA_RINGCFG_BASE

Definition Eth_Cfg.h:316

ETH_DMA_RINGCFG_RING_SIZE

#define ETH_DMA_RINGCFG_RING_SIZE(RING)

Definition Eth_Cfg.h:334

◆ Eth_GetTxChannelCtlRegAddress

#define Eth_GetTxChannelCtlRegAddress ( ChanId )

Value:

(ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_CTL((ChanId)))

ETH_DMA_TX_BASE_REG

#define ETH_DMA_TX_BASE_REG

Eth DMA base register address.

Definition Eth_Cfg.h:313

ETH_DMA_TXCRT_CHAN_CTL

#define ETH_DMA_TXCRT_CHAN_CTL(CHAN)

Eth DMA macro to calculate register address for DMA register address.

Definition Eth_Cfg.h:324

◆ Eth_GetTxChannelPeer8RegAddress

#define Eth_GetTxChannelPeer8RegAddress ( ChanId )

Value:

(ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_PEER8((ChanId)))

ETH_DMA_TXCRT_CHAN_PEER8

#define ETH_DMA_TXCRT_CHAN_PEER8(CHAN)

Definition Eth_Cfg.h:325

◆ Eth_GetRxChannelCtlRegAddress

#define Eth_GetRxChannelCtlRegAddress ( ChanId )

Value:

(ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_CTL((ChanId)))

ETH_DMA_RX_BASE_REG

#define ETH_DMA_RX_BASE_REG

Definition Eth_Cfg.h:314

ETH_DMA_RXCRT_CHAN_CTL

#define ETH_DMA_RXCRT_CHAN_CTL(CHAN)

Definition Eth_Cfg.h:326

◆ Eth_GetRxChannelPeer8RegAddress

#define Eth_GetRxChannelPeer8RegAddress ( ChanId )

Value:

(ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_PEER8((ChanId)))

ETH_DMA_RXCRT_CHAN_PEER8

#define ETH_DMA_RXCRT_CHAN_PEER8(CHAN)

Definition Eth_Cfg.h:327

◆ ETH_CSL_PROXY0_TARGET0_DATA_BASE

#define ETH_CSL_PROXY0_TARGET0_DATA_BASE (0x2a500000U)

◆ ETH_CSL_PROXY_TARGET0_PROXY_CTL

#define ETH_CSL_PROXY_TARGET0_PROXY_CTL ( PROXY )

Value:

(ETH_CSL_PROXY0_TARGET0_DATA_BASE + 0x00000000U + ((PROXY)*0x1000U))

ETH_CSL_PROXY0_TARGET0_DATA_BASE

#define ETH_CSL_PROXY0_TARGET0_DATA_BASE

Definition Eth_Cfg.h:354

◆ ETH_CSL_PROXY_TARGET0_PROXY_DATA_FIELD

#define ETH_CSL_PROXY_TARGET0_PROXY_DATA_FIELD ( PROXY )

Value:

(ETH_CSL_PROXY0_TARGET0_DATA_BASE + 0x00000200U + ((PROXY)*0x1000U))

◆ UDMA_WAIT_TEARDOWN_COUNTER

#define UDMA_WAIT_TEARDOWN_COUNTER (10000u)

Eth DMA max teardown timeout.

◆ ETH_DEM_EVENT_SUPPORT

#define ETH_DEM_EVENT_SUPPORT (STD_OFF)

ETH support DEM event feature.

◆ ETH_RX_MTU_HOST_PORT_LENGTH

#define ETH_RX_MTU_HOST_PORT_LENGTH (1522U)

Eth max MTU for host port in bytes This value need to equal max MTU for all ingress fifo buffer size.

◆ Eth_Cpsw_GetPhyMacRegAddr

#define Eth_Cpsw_GetPhyMacRegAddr ( )

Value:

( 0x40f00200U )

Eth function like macro to access Eth general configuration.

◆ Eth_Cpsw_GetAleRegAddr

#define Eth_Cpsw_GetAleRegAddr ( )

Value:

( 0x4603e000U )

◆ Eth_Cpsw_GetCptsRegAddr

#define Eth_Cpsw_GetCptsRegAddr ( )

Value:

( 0x4603d000U )

◆ Eth_Cpsw_GetMdioRegAddr

#define Eth_Cpsw_GetMdioRegAddr ( )

Value:

( 0x46000f00U )

◆ Eth_Cpsw_GetCtrlRegAddr

#define Eth_Cpsw_GetCtrlRegAddr ( )

Value:

( 0x46020000U )

◆ Eth_Cpsw_GetCppiClockFreq

#define Eth_Cpsw_GetCppiClockFreq ( )

Value:

( 333333333U )

◆ Eth_Cpsw_GetCptsRefClockFreq

#define Eth_Cpsw_GetCptsRefClockFreq ( )

Value:

( 1U )

◆ Eth_Cpsw_GetMdioBusClockFreq

#define Eth_Cpsw_GetMdioBusClockFreq ( )

Value:

( 2200000U )

◆ Eth_Cpsw_GetMdioOpMode

#define Eth_Cpsw_GetMdioOpMode ( )

Value:

( ETH_MDIO_OPMODE_MANUAL )

ETH_MDIO_OPMODE_MANUAL

@ ETH_MDIO_OPMODE_MANUAL

Definition Eth_Cfg.h:664

◆ Eth_Cpsw_GetMdioEnableInterrupt

#define Eth_Cpsw_GetMdioEnableInterrupt ( )

Value:

( TRUE )

◆ Eth_GetDem_E_HARDWARE_ERROR

#define Eth_GetDem_E_HARDWARE_ERROR ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

ETH_DEM_NO_EVENT

#define ETH_DEM_NO_EVENT

Eth invalid DEM event ID

Definition Eth_Cfg.h:223

ETH DEM Error codes to report.

◆ Eth_GetDem_E_LATECOLLISION

#define Eth_GetDem_E_LATECOLLISION ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_MULTIPLECOLLISION

#define Eth_GetDem_E_MULTIPLECOLLISION ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_SINGLECOLLISION

#define Eth_GetDem_E_SINGLECOLLISION ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_ALIGNMENT

#define Eth_GetDem_E_ALIGNMENT ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_OVERSIZEFRAME

#define Eth_GetDem_E_OVERSIZEFRAME ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_UNDERSIZEFRAME

#define Eth_GetDem_E_UNDERSIZEFRAME ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_CRC

#define Eth_GetDem_E_CRC ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_RX_FRAMES_LOST

#define Eth_GetDem_E_RX_FRAMES_LOST ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_ACCESS

#define Eth_GetDem_E_ACCESS ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

◆ Eth_GetDem_E_TX_INTERNAL

#define Eth_GetDem_E_TX_INTERNAL ( CtrlIndex )

Value:

( ETH_DEM_NO_EVENT )

◆ Eth_IsVirtualMacModeEnable

#define Eth_IsVirtualMacModeEnable ( CtrlIndex )

Value:

( FALSE )

Eth function like macro to access controler configuration.

◆ Eth_GetTxChannelThreadOffset

#define Eth_GetTxChannelThreadOffset ( CtrlIndex )

Value:

( 0xf000U )

◆ Eth_VirtMacGetEthFwRpcComChannelId

#define Eth_VirtMacGetEthFwRpcComChannelId ( CtrlIndex )

Value:

( 0xFFFFU )

◆ Eth_VirtMacGetEthPollRecvMsgInEthMain

#define Eth_VirtMacGetEthPollRecvMsgInEthMain ( CtrlIndex )

Value:

( FALSE )

◆ Eth_VirtMacGetRpcCmdCompleteFuncPtr

#define Eth_VirtMacGetRpcCmdCompleteFuncPtr ( CtrlIndex )

Value:

( (Eth_RpcCmdComplete)NULL_PTR )

Eth_RpcCmdComplete

void(* Eth_RpcCmdComplete)(uint8 CtrlIdx, uint8 sid, sint32 status)

Application callback to indicate Rpc dispatch command completion.

Definition Eth_Cfg.h:553

◆ Eth_VirtMacGetFwRegisterFuncPtr

#define Eth_VirtMacGetFwRegisterFuncPtr ( CtrlIndex )

Value:

( (Eth_RpcFwRegistered)NULL_PTR )

Eth_RpcFwRegistered

void(* Eth_RpcFwRegistered)(uint8 CtrlIdx)

Application callback to indicate Ethernet firmware registered with the Eth RPC client.

Definition Eth_Cfg.h:561

◆ Eth_VirtMacGetRemoteVirtPort

#define Eth_VirtMacGetRemoteVirtPort ( CtrlIndex )

Value:

( ETHREMOTECFG_SWITCH_PORT_1 )

◆ Eth_VirtMacGetDmaTxChannelPairAll

#define Eth_VirtMacGetDmaTxChannelPairAll ( CtrlIdx )

Value:

( (EthVirtMacDmaTxChannelPair)NULL_PTR )

EthVirtMacDmaTxChannelPair

Std_ReturnType(* EthVirtMacDmaTxChannelPair)(uint8 ctrlIdx)

Unpair PSIL TX channel function pointer.

Definition Eth_Cfg.h:570

◆ Eth_VirtMacGetDmaTxChannelUnpairAll

#define Eth_VirtMacGetDmaTxChannelUnpairAll ( CtrlIdx )

Value:

( (EthVirtMacDmaTxChannelUnpair)NULL_PTR )

◆ Eth_VirtMacGetDmaFlowCfgAll

#define Eth_VirtMacGetDmaFlowCfgAll ( CtrlIdx )

Value:

( (EthVirtMacDmaFLowCfg)NULL_PTR )

EthVirtMacDmaFLowCfg

Std_ReturnType(* EthVirtMacDmaFLowCfg)(uint8 ctrlIdx)

Flow reset function pointer.

Definition Eth_Cfg.h:576

◆ Eth_VirtMacGetDmaFlowResetAll

#define Eth_VirtMacGetDmaFlowResetAll ( CtrlIdx )

Value:

( (EthVirtMacDmaFLowReset)NULL_PTR )

EthVirtMacDmaFLowReset

Std_ReturnType(* EthVirtMacDmaFLowReset)(uint8 ctrlIdx)

Definition Eth_Cfg.h:579

◆ Eth_GetTxEnableInterrupt

#define Eth_GetTxEnableInterrupt ( CtrlIndex )

Value:

( TRUE )

◆ Eth_GetRxEnableInterrupt

#define Eth_GetRxEnableInterrupt ( CtrlIndex )

Value:

( TRUE )

◆ Eth_GetEnetType

#define Eth_GetEnetType ( CtrlIndex )

Value:

( ETH_ENETTYPE_CPSW2G )

ETH_ENETTYPE_CPSW2G

@ ETH_ENETTYPE_CPSW2G

Definition Eth_Cfg.h:643

◆ Eth_GetMacPortNum

#define Eth_GetMacPortNum ( CtrlIndex )

Value:

( ETH_PORT_MAC_PORT_1 )

ETH_PORT_MAC_PORT_1

@ ETH_PORT_MAC_PORT_1

Definition Eth_Cfg.h:593

◆ Eth_GetMacAddressHigh

#define Eth_GetMacAddressHigh ( CtrlIndex )

Value:

( 0xaabbccddU )

◆ Eth_GetMacAddressLow

#define Eth_GetMacAddressLow ( CtrlIndex )

Value:

( 0xeeffU )

◆ Eth_UseDefaultMacAddress

#define Eth_UseDefaultMacAddress ( CtrlIndex )

Value:

( TRUE )

◆ Eth_GetMiiConnectionType

#define Eth_GetMiiConnectionType ( CtrlIndex )

Value:

( ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND )

ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND

@ ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND

Definition Eth_Cfg.h:631

◆ Eth_GetLoopBackMode

#define Eth_GetLoopBackMode ( CtrlIndex )

Value:

( FALSE )

◆ Eth_GetHardwareLoopTimeout

#define Eth_GetHardwareLoopTimeout ( CtrlIndex )

Value:

( 32000U )

◆ Eth_IsPacketMemCacheable

#define Eth_IsPacketMemCacheable ( CtrlIndex )

Value:

( TRUE )

◆ Eth_IsRingMemCacheable

#define Eth_IsRingMemCacheable ( CtrlIndex )

Value:

( TRUE )

◆ Eth_IsDescMemCacheable

#define Eth_IsDescMemCacheable ( CtrlIndex )

Value:

( TRUE )

◆ Eth_GetRxMtuLength

#define Eth_GetRxMtuLength ( CtrlIndex )

Value:

( 1522U )

◆ Eth_GetTxChanStartNum

#define Eth_GetTxChanStartNum ( CtrlIndex )

Value:

( 30U )

◆ Eth_GetRxChanStartNum

#define Eth_GetRxChanStartNum ( CtrlIndex )

Value:

( 30U )

◆ Eth_GetEgressFifoTotalNum

#define Eth_GetEgressFifoTotalNum ( CtrlIndex )

Value:

( 1U )

◆ Eth_GetIngressFifoTotalNum

#define Eth_GetIngressFifoTotalNum ( CtrlIndex )

Value:

( 1U )

◆ Eth_GetRingTotalNum

#define Eth_GetRingTotalNum ( CtrlIndex )

Value:

( 6U )

◆ Eth_GetTxChanTotalNum

#define Eth_GetTxChanTotalNum ( CtrlIndex )

Value:

( 1U )

◆ Eth_GetRxChanTotalNum

#define Eth_GetRxChanTotalNum ( CtrlIndex )

Value:

( 1U )

◆ Eth_GetFlowTotalNumber

#define Eth_GetFlowTotalNumber ( CtrlIndex )

Value:

( 1U )

◆ Eth_GetEventTotalNum

#define Eth_GetEventTotalNum ( CtrlIndex )

Value:

( 2U )

◆ Eth_GetRingEventTotalNum

#define Eth_GetRingEventTotalNum ( CtrlIndex )

Value:

( 2U )

◆ Eth_GetTxDmaThresholdNum

#define Eth_GetTxDmaThresholdNum ( CtrlIndex )

Value:

( 1U )

◆ Eth_GetRxDmaThresholdNum

#define Eth_GetRxDmaThresholdNum ( CtrlIndex )

Value:

( 1U )

◆ Eth_GetEgressFifoPacketNum

#define Eth_GetEgressFifoPacketNum	(		CtrlIndex,
			FifoIdx )

Value:

( 16U )

◆ Eth_GetEgressFifoPacketSize

#define Eth_GetEgressFifoPacketSize	(		CtrlIndex,
			FifoIdx )

Value:

( 1522U )

◆ Eth_GetIngressFifoPacketNum

#define Eth_GetIngressFifoPacketNum	(		CtrlIndex,
			FifoIdx )

Value:

( 16U )

◆ Eth_GetIngressFifoPacketSize

#define Eth_GetIngressFifoPacketSize	(		CtrlIndex,
			FifoIdx )

Value:

( 1522U )

◆ Eth_GetEgressFifoPriorityAsignment

#define Eth_GetEgressFifoPriorityAsignment	(		CtrlIndex,
			Prio )

Value:

( 0U )

◆ Eth_GetIngressFifoPriorirtyAsignment

#define Eth_GetIngressFifoPriorirtyAsignment	(		CtrlIndex,
			Prio )

Value:

( 0U )

◆ Eth_GetEgressFifoDescAddress

#define Eth_GetEgressFifoDescAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx )

Value:

(&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)] )

◆ Eth_GetEgressFifoDescUserInfoAddress

#define Eth_GetEgressFifoDescUserInfoAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx )

Value:

(&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)].bufferInfo )

◆ Eth_GetEgressFifoBufferDataAddress

#define Eth_GetEgressFifoBufferDataAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx )

Value:

(&Eth_Ctrl_0_Egress_BufferMem_0[(DescIdx) * 1536U] )

◆ Eth_GetEgressFifoQueueAddress

#define Eth_GetEgressFifoQueueAddress	(		CtrlIndex,
			FifoIdx )

Value:

( Eth_Ctrl_0_Egress_Queue_0 )

◆ Eth_GetEgressFifoBufferState

#define Eth_GetEgressFifoBufferState	(	CtrlIndex,
		FifoIdx,
		BufferIdx )

Value:

( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] )

◆ Eth_SetEgressFifoBufferState

#define Eth_SetEgressFifoBufferState	(	CtrlIndex,
		FifoIdx,
		BufferIdx,
		Val )

Value:

( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] = Val )

◆ Eth_GetIngressFifoDescAddress

#define Eth_GetIngressFifoDescAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx )

Value:

(&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)] )

◆ Eth_GetIngressFifoDescUserInfoAddress

#define Eth_GetIngressFifoDescUserInfoAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx )

Value:

(&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)].bufferInfo )

◆ Eth_GetIngressFifoBufferDataAddress

#define Eth_GetIngressFifoBufferDataAddress	(	CtrlIndex,
		FifoIdx,
		DescIdx )

Value:

(&Eth_Ctrl_0_Ingress_BufferMem_0[(DescIdx) * 1536U] )

◆ Eth_GetIngressFifoQueueAddress

#define Eth_GetIngressFifoQueueAddress	(		CtrlIndex,
			FifoIdx )

Value:

( Eth_Ctrl_0_Ingress_Queue_0 )

◆ Eth_GetIngressFifoBufferState

#define Eth_GetIngressFifoBufferState	(	CtrlIndex,
		FifoIdx,
		BufferIdx )

Value:

( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] )

◆ Eth_SetIngressFifoBufferState

#define Eth_SetIngressFifoBufferState	(	CtrlIndex,
		FifoIdx,
		BufferIdx,
		Val )

Value:

( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] = Val )

◆ Eth_GetEgressFifoCqIdx

#define Eth_GetEgressFifoCqIdx	(		CtrlIndex,
			FifoIdx )

Value:

( 0U )

◆ Eth_GetEgressFifoFqIdx

#define Eth_GetEgressFifoFqIdx	(		CtrlIndex,
			FifoIdx )

Value:

( 2U )

◆ Eth_GetIngressFifoCqIdx

#define Eth_GetIngressFifoCqIdx	(		CtrlIndex,
			FifoIdx )

Value:

( 1U )

◆ Eth_GetIngressFifoFqIdx

#define Eth_GetIngressFifoFqIdx	(		CtrlIndex,
			FifoIdx )

Value:

( 3U )

◆ Eth_GetTxChanId

#define Eth_GetTxChanId	(		CtrlIndex,
			ChIdx )

Value:

( 30U )

◆ Eth_GetTxChanTdCqRingIdx

#define Eth_GetTxChanTdCqRingIdx	(		CtrlIndex,
			ChIdx )

Value:

( 4U )

◆ Eth_GetTxChanDepth

#define Eth_GetTxChanDepth	(		CtrlIndex,
			ChIdx )

Value:

( 128U )

◆ Eth_GetRxChanId

#define Eth_GetRxChanId	(		CtrlIndex,
			ChIdx )

Value:

( 30U )

◆ Eth_GetRxChanTdCqRingIdx

#define Eth_GetRxChanTdCqRingIdx	(		CtrlIndex,
			ChIdx )

Value:

( 5U )

◆ Eth_GetRxChanFlowTotalNum

#define Eth_GetRxChanFlowTotalNum	(		CtrlIndex,
			ChIdx )

Value:

( 1U )

◆ Eth_GetRxChanFlowStartNum

#define Eth_GetRxChanFlowStartNum	(		CtrlIndex,
			ChIdx )

Value:

( 60U )

◆ Eth_GetFlowId

#define Eth_GetFlowId	(		CtrlIndex,
			FlowIdx )

Value:

( 60U )

◆ Eth_GetFlowCqRingIdx

#define Eth_GetFlowCqRingIdx	(		CtrlIndex,
			FlowIdx )

Value:

( 1U )

◆ Eth_GetFlowFqRingIdx

#define Eth_GetFlowFqRingIdx	(		CtrlIndex,
			FlowIdx )

Value:

( 3U )

◆ Eth_GetDynRingElemAddress

#define Eth_GetDynRingElemAddress	(		CtrlIndex,
			RingIdx )

Value:

( &Eth_RingDyn_Ctrl_0[(RingIdx)] )

◆ Eth_GetRingHwId

#define Eth_GetRingHwId	(		CtrlIndex,
			RingIdx )

Value:

( Eth_Udma_RingCfg_0[(RingIdx)].hwId )

Eth_Udma_RingCfg_0

const Eth_Udma_RingCfgType Eth_Udma_RingCfg_0[6U]

Eth_Udma_RingCfgType::hwId

uint32 hwId

Definition Eth_Cfg.h:704

◆ Eth_GetRingTotalElemNum

#define Eth_GetRingTotalElemNum	(		CtrlIndex,
			RingIdx )

Value:

( Eth_Udma_RingCfg_0[(RingIdx)].size )

Eth_Udma_RingCfgType::size

uint32 size

Definition Eth_Cfg.h:706

◆ Eth_GetRingPriority

#define Eth_GetRingPriority	(		CtrlIndex,
			RingIdx )

Value:

( Eth_Udma_RingCfg_0[(RingIdx)].priority )

Eth_Udma_RingCfgType::priority

uint32 priority

Definition Eth_Cfg.h:708

◆ Eth_GetRingMemBaseAddress

#define Eth_GetRingMemBaseAddress	(		CtrlIndex,
			RingIdx )

Value:

( Eth_Udma_RingCfg_0[(RingIdx)].memPtr )

Eth_Udma_RingCfgType::memPtr

uint64 * memPtr

Definition Eth_Cfg.h:702

◆ Eth_GetRingEventRingIdx

#define Eth_GetRingEventRingIdx	(		CtrlIndex,
			RingEvtIdx )

Value:

( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].ringIdx )

Eth_RingEventCfg_Ctrl_0

const Eth_Udma_RingEventCfgType Eth_RingEventCfg_Ctrl_0[2U]

Eth_Udma_RingEventCfgType::ringIdx

uint8 ringIdx

Definition Eth_Cfg.h:748

◆ Eth_GetRingEventGlobalEventNum

#define Eth_GetRingEventGlobalEventNum	(		CtrlIndex,
			RingEvtIdx )

Value:

( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].globalEvent )

Eth_Udma_RingEventCfgType::globalEvent

uint32 globalEvent

Definition Eth_Cfg.h:754

◆ Eth_GetRingEventVirtBitNum

#define Eth_GetRingEventVirtBitNum	(		CtrlIndex,
			RingEvtIdx )

Value:

( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].virtBitNum )

Eth_Udma_RingEventCfgType::virtBitNum

uint8 virtBitNum

Definition Eth_Cfg.h:752

◆ Eth_GetRingEventEventIdx

#define Eth_GetRingEventEventIdx	(		CtrlIndex,
			RingEvtIdx )

Value:

( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].eventIdx )

Eth_Udma_RingEventCfgType::eventIdx

uint8 eventIdx

Definition Eth_Cfg.h:750

◆ Eth_GetRingEventSrcOffsetNum

#define Eth_GetRingEventSrcOffsetNum	(		CtrlIndex,
			RingEvtIdx )

Value:

( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].srcOffset )

Eth_Udma_RingEventCfgType::srcOffset

uint32 srcOffset

Definition Eth_Cfg.h:756

◆ Eth_GetEventCoreIntrNum

#define Eth_GetEventCoreIntrNum	(		CtrlIndex,
			EvtIdx )

Value:

( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum )

Eth_EventCfg_Ctrl_0

const Eth_Udma_EventCfgType Eth_EventCfg_Ctrl_0[2U]

Eth_Udma_EventCfgType::coreIntrNum

uint32 coreIntrNum

Definition Eth_Cfg.h:734

◆ Eth_GetEventVirtIntrNum

#define Eth_GetEventVirtIntrNum	(		CtrlIndex,
			EvtIdx )

Value:

( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum )

Eth_Udma_EventCfgType::virtIntrNum

uint32 virtIntrNum

Definition Eth_Cfg.h:736

◆ Eth_GetEventIrIntrNum

#define Eth_GetEventIrIntrNum	(		CtrlIndex,
			EvtIdx )

Value:

( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum )

Eth_Udma_EventCfgType::IrIntrNum

uint32 IrIntrNum

Definition Eth_Cfg.h:738

◆ Eth_GetTxEventCoreIntrNum

#define Eth_GetTxEventCoreIntrNum ( CtrlIndex )

Value:

( 80U )

◆ Eth_GetRxEventCoreIntrNum

#define Eth_GetRxEventCoreIntrNum ( CtrlIndex )

Value:

( 81U )

◆ Eth_GetHwTimerTotalNum

#define Eth_GetHwTimerTotalNum ( CtrlIndex )

Value:

( 0U )

◆ Eth_GetHwTimerId

#define Eth_GetHwTimerId	(		CtrlIndex,
			Index )

Value:

( 0xFFU )

◆ Eth_GetHwTimerCounter

#define Eth_GetHwTimerCounter	(		CtrlIndex,
			Index )

Value:

( 0xFFU )

◆ Eth_GetHwTimerBaseAddr

#define Eth_GetHwTimerBaseAddr	(		CtrlIndex,
			Index )

Value:

( 0xFFFFFFFFU )

◆ Eth_GetHwTimerDynRunningState

#define Eth_GetHwTimerDynRunningState	(		CtrlIndex,
			Index )

Value:

( FALSE )

◆ Eth_SetHwTimerDynRunningState

#define Eth_SetHwTimerDynRunningState	(	CtrlIndex,
		Index,
		Val )

Value:

( (void)(CtrlIndex) )

◆ Eth_GetRxIrqPacingEnable

#define Eth_GetRxIrqPacingEnable ( CtrlIndex )

Value:

( FALSE )

◆ Eth_GetTxIrqPacingEnable

#define Eth_GetTxIrqPacingEnable ( CtrlIndex )

Value:

( FALSE )

◆ Eth_GetRxHwTimerIdx

#define Eth_GetRxHwTimerIdx ( CtrlIndex )

Value:

( 255U )

◆ Eth_GetTxHwTimerIdx

#define Eth_GetTxHwTimerIdx ( CtrlIndex )

Value:

( 255U )

◆ Eth_GetIrqPacingEnable

#define Eth_GetIrqPacingEnable ( CtrlIndex )

Value:

( (Eth_GetTxIrqPacingEnable(CtrlIndex) == TRUE) || (Eth_GetRxIrqPacingEnable(CtrlIndex) == TRUE) )

Eth_GetRxIrqPacingEnable

#define Eth_GetRxIrqPacingEnable(CtrlIndex)

Definition Eth_Cfg.h:525

Eth_GetTxIrqPacingEnable

#define Eth_GetTxIrqPacingEnable(CtrlIndex)

Definition Eth_Cfg.h:526

◆ Eth_GetProxyTotalNum

#define Eth_GetProxyTotalNum ( CtrlIndex )

Value:

( 1U )

◆ Eth_GetProxyThreadNum

#define Eth_GetProxyThreadNum	(		CtrlIndex,
			ProxyIdx )

Value:

( 9U )

◆ Eth_GetProxyTargetRingNum

#define Eth_GetProxyTargetRingNum	(		CtrlIndex,
			ProxyIdx )

Value:

( 0U )

◆ Eth_GetRingProxyIdx

#define Eth_GetRingProxyIdx	(		CtrlIndex,
			RingIdx )

Value:

( Eth_Udma_RingCfg_0[(RingIdx)].proxyIdx )

Eth_Udma_RingCfgType::proxyIdx

uint32 proxyIdx

Definition Eth_Cfg.h:710

◆ Eth_GetRingMode

#define Eth_GetRingMode	(		CtrlIndex,
			RingIdx )

Value:

( Eth_Udma_RingCfg_0[(RingIdx)].ringMode )

Eth_Udma_RingCfgType::ringMode

uint32 ringMode

Definition Eth_Cfg.h:712

◆ Eth_GetDmaRingCfg

#define Eth_GetDmaRingCfg ( CtrlIdx )

Value:

( (Eth_DmaRingCfg)&AppUtils_EthRingCfg )

Eth_DmaRingCfg

Std_ReturnType(* Eth_DmaRingCfg)(uint8 ctrlIdx, uint8 ringIdx)

Mdio delay in nsec function pointer.

Definition Eth_Cfg.h:564

AppUtils_EthRingCfg

Std_ReturnType AppUtils_EthRingCfg(uint8 ctrlIdx, uint8 Id)

◆ ETH_START_SEC_CONST_UNSPECIFIED

#define ETH_START_SEC_CONST_UNSPECIFIED

◆ ETH_STOP_SEC_CONST_UNSPECIFIED

#define ETH_STOP_SEC_CONST_UNSPECIFIED

◆ ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128

#define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128

◆ ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128

#define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128

◆ ETH_START_SEC_VAR_NO_INIT_8

#define ETH_START_SEC_VAR_NO_INIT_8

◆ ETH_STOP_SEC_VAR_NO_INIT_8

#define ETH_STOP_SEC_VAR_NO_INIT_8

◆ ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED

#define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED

◆ ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED

#define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED

◆ ETH_START_SEC_CODE

#define ETH_START_SEC_CODE

Ring configure via SciClient function.

◆ ETH_STOP_SEC_CODE

#define ETH_STOP_SEC_CODE

◆ Eth_GetMdioWriteLowBaseNsec

#define Eth_GetMdioWriteLowBaseNsec ( )

Value:

    do { \
    NOP50;\
    NOP30;\
 } while(TRUE == FALSE)

DelayNs (default value) in NOOP function/function like macro.

◆ Eth_GetMdioWriteHighBaseNsec

#define Eth_GetMdioWriteHighBaseNsec ( )

Value:

    do { \
    NOP100;\
 } while(TRUE == FALSE)

◆ Eth_GetMdioReadLowBaseNsec

#define Eth_GetMdioReadLowBaseNsec ( )

Value:

    do { \
    NOP50;\
    NOP30;\
 } while(TRUE == FALSE)

◆ Eth_GetMdioReadHighBaseNsec

#define Eth_GetMdioReadHighBaseNsec ( )

Value:

    do  { \
    NOP100;\
    NOP50;\
    NOP30;\
 } while(TRUE == FALSE)

◆ Eth_GetMdioWriteLowDelayNsec

#define Eth_GetMdioWriteLowDelayNsec ( CtrlIdx )

Value:

    do { \
    NOP100;\
    NOP50;\
    NOP20;\
 } while(TRUE == FALSE)

DelayNs (generate by user input) in NOOP function/function like macro.

◆ Eth_GetMdioWriteHighDelayNsec

#define Eth_GetMdioWriteHighDelayNsec ( CtrlIdx )

Value:

    do { \
    NOP100;\
    NOP50;\
 } while(TRUE == FALSE)

◆ Eth_GetMdioReadLowDelayNsec

#define Eth_GetMdioReadLowDelayNsec ( CtrlIdx )

Value:

    do { \
    NOP100;\
    NOP50;\
    NOP20;\
 } while(TRUE == FALSE)

◆ Eth_GetMdioReadHighDelayNsec

#define Eth_GetMdioReadHighDelayNsec ( CtrlIdx )

Value:

    do { \
    NOP50;\
    NOP20;\
 } while(TRUE == FALSE)

Typedef Documentation

◆ Eth_RpcCmdComplete

typedef void(* Eth_RpcCmdComplete) (uint8 CtrlIdx, uint8 sid, sint32 status)

Application callback to indicate Rpc dispatch command completion.

Pointer to a function that is invoked to indicate completion of RPC dispatch call. The RPC command is identified by the sid

◆ Eth_RpcFwRegistered

typedef void(* Eth_RpcFwRegistered) (uint8 CtrlIdx)

Application callback to indicate Ethernet firmware registered with the Eth RPC client.

Ring DMA configure function pointer

◆ Eth_DmaRingCfg

typedef Std_ReturnType(* Eth_DmaRingCfg) (uint8 ctrlIdx, uint8 ringIdx)

Mdio delay in nsec function pointer.

◆ Eth_MdioDelayNsecFunc

typedef void(* Eth_MdioDelayNsecFunc) (void)

Pair PSIL TX channel function pointer.

◆ EthVirtMacDmaTxChannelPair

typedef Std_ReturnType(* EthVirtMacDmaTxChannelPair) (uint8 ctrlIdx)

Unpair PSIL TX channel function pointer.

◆ EthVirtMacDmaTxChannelUnPair

typedef Std_ReturnType(* EthVirtMacDmaTxChannelUnPair) (uint8 ctrlIdx)

Flow config function pointer.

◆ EthVirtMacDmaFLowCfg

typedef Std_ReturnType(* EthVirtMacDmaFLowCfg) (uint8 ctrlIdx)

Flow reset function pointer.

◆ EthVirtMacDmaFLowReset

typedef Std_ReturnType(* EthVirtMacDmaFLowReset) (uint8 ctrlIdx)

Enumeration Type Documentation

◆ Eth_PortType

enum Eth_PortType

Port identifier.

Depending on the CPSW Type (for example CPSW9G) multiple ports are supported. The specific port is identified using this enum

Enumerator
ETH_PORT_HOST_PORT	Host port
ETH_MAC_PORT_FIRST	First Eth port
ETH_PORT_MAC_PORT_1	MAC port 0
ETH_PORT_MAC_PORT_2	MAC port 1
ETH_PORT_MAC_PORT_3	MAC port 2
ETH_PORT_MAC_PORT_4	MAC port 3
ETH_PORT_MAC_PORT_5	MAC port 4
ETH_PORT_MAC_PORT_6	MAC port 5
ETH_PORT_MAC_PORT_7	MAC port 6
ETH_PORT_MAC_PORT_8	MAC port 7
ETH_PORT_MAC_PORT_LAST	Enum indicating last mac port

◆ Eth_MacConnectionType

enum Eth_MacConnectionType

Type/Speed/Duplex connection type.

Ethernet connections based on the type (MII, RMII, RGMII), speed (10Mbps, 100Mbps, 1Gbps) and duplexity (half, full).

Enumerator
ETH_MAC_CONN_TYPE_RMII_10	MAC connection type for 10Mbps RMII mode
ETH_MAC_CONN_TYPE_RMII_100	MAC connection type for 100Mbps RMII mode
ETH_MAC_CONN_TYPE_RGMII_FORCE_100_HALF	MAC connection type for forced half-duplex 100Mbps RGMII mode
ETH_MAC_CONN_TYPE_RGMII_FORCE_100_FULL	MAC connection type for forced full-duplex 100Mbps RGMII mode
ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL	MAC connection type for forced full-duplex 1000Mbps RGMII mode
ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND	MAC connection type for RGMII inband detection mode (speed determined based on received RGMII Rx clock)

◆ Eth_EnetType

enum Eth_EnetType

Enet Cpsw Type identifier.

Enet CPSW Type enumeration.

Enumerator
ETH_ENETTYPE_CPSW2G	CPSW 2-port switch with one host port and 1 external port
ETH_ENETTYPE_CPSW9G	CPSW 9-port switch with one host port and 8 external port
ETH_ENETTYPE_CPSW5G	CPSW 5-port switch with one host port and 4 external port
ETH_ENETTYPE_CPSW3G	CPSW 3-port switch with one host port and 2 external port
ETH_ENETTYPE_CPSWLAST	Enum used to identify the last supported CPSW Type. Used internally

◆ Eth_MdioOperModeType

enum Eth_MdioOperModeType

MDIO operating mode.

MDIO operating mode enumeration.

Enumerator
ETH_MDIO_OPMODE_NORMAL	Normal mode
ETH_MDIO_OPMODE_MANUAL	Manual mode (Used for software-emulated MDIO operations)

Function Documentation

◆ VAR() [1/5]

VAR	(	uint8	,
		ETH_VAR_NO_INIT_128	)

extern

◆ VAR() [2/5]

VAR	(	Eth_DescType	,
		ETH_VAR_NO_INIT_128	)

extern

◆ VAR() [3/5]

VAR	(	uint8	,
		ETH_VAR_NO_INIT	)

extern

◆ VAR() [4/5]

VAR	(	Eth_QueueType	,
		ETH_VAR_NO_INIT	)

extern

◆ VAR() [5/5]

VAR	(	Eth_Udma_RingDynType	,
		ETH_VAR_NO_INIT	)

extern

◆ AppUtils_EthRingCfg()

Std_ReturnType AppUtils_EthRingCfg	(	uint8	ctrlIdx,
		uint8	Id )

extern

Variable Documentation

◆ phyMacAddr

uint32 Eth_CpswConfigType::phyMacAddr

Mac address register address

◆ aleAddr

uint32 Eth_CpswConfigType::aleAddr

Address lookup engine register address

◆ cptsAddr

uint32 Eth_CpswConfigType::cptsAddr

Common platform time sync register address

◆ mdioAddr

uint32 Eth_CpswConfigType::mdioAddr

Mdio resgister address

◆ ctrlAddr

uint32 Eth_CpswConfigType::ctrlAddr

control register addresss

◆ cppiClockFreqHz

uint32 Eth_CpswConfigType::cppiClockFreqHz

Cpts clock frequency HZ

◆ enableMdioIrq

boolean Eth_CpswConfigType::enableMdioIrq

enable Mdio IRQ

◆ mdioBusFreqHz

uint32 Eth_CpswConfigType::mdioBusFreqHz

Mdio Bus frequency HZ

◆ mdioOpMode

Eth_MdioOperModeType Eth_CpswConfigType::mdioOpMode

MDIO Operating Mode (Normal/Manual)

◆ cptsRefClockFreq

uint32 Eth_CpswConfigType::cptsRefClockFreq

Cpts clock frequency reference value

◆ memPtr

uint64* Eth_Udma_RingCfgType::memPtr

Eth Udma ring memory

◆ hwId

uint32 Eth_Udma_RingCfgType::hwId

Eth Udma ring hw number

◆ size

uint32 Eth_Udma_RingCfgType::size

Eth Udma ring size

◆ priority

uint32 Eth_Udma_RingCfgType::priority

Eth Udma ring priority

◆ proxyIdx

uint32 Eth_Udma_RingCfgType::proxyIdx

Eth Udma ring proxy index

◆ ringMode

uint32 Eth_Udma_RingCfgType::ringMode

Eth Udma ring mode

◆ proxyId

uint32 Eth_Udma_ProxyCfgType::proxyId

Eth Udma proxy hw number

◆ targetNumRingId

uint32 Eth_Udma_ProxyCfgType::targetNumRingId

Eth Udma proxy target ring hw number

◆ coreIntrNum

uint32 Eth_Udma_EventCfgType::coreIntrNum

Eth Udma core interrupt number

◆ virtIntrNum

uint32 Eth_Udma_EventCfgType::virtIntrNum

Eth Udma virtual number

◆ IrIntrNum

uint32 Eth_Udma_EventCfgType::IrIntrNum

Eth Udma Ir Interrupt number

◆ ringIdx

uint8 Eth_Udma_RingEventCfgType::ringIdx

Ring index

◆ eventIdx

uint8 Eth_Udma_RingEventCfgType::eventIdx

Event index

◆ virtBitNum

uint8 Eth_Udma_RingEventCfgType::virtBitNum

Virtual bit number

◆ globalEvent

uint32 Eth_Udma_RingEventCfgType::globalEvent

Global event number

◆ srcOffset

uint32 Eth_Udma_RingEventCfgType::srcOffset

Source Irq offset

◆ cqRingIdx [1/2]

uint8 Eth_FifoRingMapCfgType::cqRingIdx

Completion queue index

◆ fqRingIdx [1/2]

uint8 Eth_FifoRingMapCfgType::fqRingIdx

Free queue index

◆ tdCqRingIdx

uint8 Eth_ChannelCfgType::tdCqRingIdx

Teardown completion queue index

◆ chId

uint16 Eth_ChannelCfgType::chId

Channel hardware Id

◆ cqRingIdx [2/2]

uint8 Eth_FlowCfgType::cqRingIdx

Completion queue index

◆ fqRingIdx [2/2]

uint8 Eth_FlowCfgType::fqRingIdx

Free queue index

◆ flowId

uint16 Eth_FlowCfgType::flowId

Flow hardware Id

◆ flowNum

uint8 Eth_ChannelFlowCfgType::flowNum

Eth flow number

◆ startFlowId

uint16 Eth_ChannelFlowCfgType::startFlowId

Eth Flow start ID

◆ fifoBufferPtr

uint8* Eth_FifoHandleType::fifoBufferPtr

Eth Fifo memory buffer

◆ descPtr

Eth_DescType* Eth_FifoHandleType::descPtr

Eth Fifo descriptor memory buffer

◆ queuePtr

Eth_QueueType* Eth_FifoHandleType::queuePtr

Eth Fifo descriptor queue memory buffer

◆ bufferState

uint8* Eth_FifoHandleType::bufferState

Eth Fifo buffer state memory buffer

◆ fifoNum

uint16 Eth_FifoHandleType::fifoNum

Eth Fifo number

◆ elemSize

uint16 Eth_FifoHandleType::elemSize

Eth Fifo element size

◆ pktSize

uint16 Eth_FifoHandleType::pktSize

Eth Fifo packet size

◆ totalSize

uint32 Eth_FifoHandleType::totalSize

Eth Fifo total memory buffer size

◆ eventCfgPtr

Eth_Udma_EventCfgType* Eth_Udma_CfgType::eventCfgPtr

Eth Udma event configuration pointer

◆ ringCfgPtr

Eth_Udma_RingCfgType* Eth_Udma_CfgType::ringCfgPtr

Eth Udma ring configuration pointer

◆ ringDynPtr

Eth_Udma_RingDynType* Eth_Udma_CfgType::ringDynPtr

Eth Udma ring dynamic pointer

◆ ringEvenCfgPtr

Eth_Udma_RingEventCfgType* Eth_Udma_CfgType::ringEvenCfgPtr

Eth Udma ring event configuration pointer

◆ egressFifoCfgPtr

Eth_FifoHandleType* Eth_Udma_CfgType::egressFifoCfgPtr

Eth egress configuration pointer

◆ ingressFifoCfgPtr

Eth_FifoHandleType* Eth_Udma_CfgType::ingressFifoCfgPtr

Eth ingress configuration pointer

◆ egressFifoRingMapCfgPtr

Eth_FifoRingMapCfgType* Eth_Udma_CfgType::egressFifoRingMapCfgPtr

Eth egress fifo ring map configuration pointer

◆ ingressFifoRingMapCfgPtr

Eth_FifoRingMapCfgType* Eth_Udma_CfgType::ingressFifoRingMapCfgPtr

Eth ingress fifo ring map configuration pointer

◆ egressFifoPrioAssignCfgPtr

uint8* Eth_Udma_CfgType::egressFifoPrioAssignCfgPtr

Eth egress fifo priority assignement configuration pointer

◆ ingressFifoPrioAssignCfgPtr

uint8* Eth_Udma_CfgType::ingressFifoPrioAssignCfgPtr

Eth ingress fifo priority assignement configuration pointer

◆ txChanCfgPtr

Eth_ChannelCfgType* Eth_Udma_CfgType::txChanCfgPtr

Eth tx channel configuration pointer

◆ rxChanCfgPtr

Eth_ChannelCfgType* Eth_Udma_CfgType::rxChanCfgPtr

Eth rx channel configuration pointer

◆ rxChanFlowCfgPtr

Eth_ChannelFlowCfgType* Eth_Udma_CfgType::rxChanFlowCfgPtr

Eth rx channel configuration pointer

◆ flowCfgPtr

Eth_FlowCfgType* Eth_Udma_CfgType::flowCfgPtr

Eth flow configuration pointer

◆ proxyCfgPtr

Eth_Udma_ProxyCfgType* Eth_Udma_CfgType::proxyCfgPtr

Eth proxy configuration pointer

◆ startTxNum

uint16 Eth_Udma_CfgType::startTxNum

Eth Udma Tx channel start

◆ startRxNum

uint16 Eth_Udma_CfgType::startRxNum

Eth Udma Rx channel start

◆ totalEventNum

uint8 Eth_Udma_CfgType::totalEventNum

Eth Udma total event number

◆ totalRingNum

uint8 Eth_Udma_CfgType::totalRingNum

Eth Udma total ring number

◆ totalRingEventNum

uint8 Eth_Udma_CfgType::totalRingEventNum

Eth Udma total ring event number

◆ txThresholdNum

uint8 Eth_Udma_CfgType::txThresholdNum

Eth Tx threhold number

◆ rxThresholdNum

uint8 Eth_Udma_CfgType::rxThresholdNum

Eth Rx threhold number

◆ totalEgressFifoNum

uint8 Eth_Udma_CfgType::totalEgressFifoNum

Eth Udma total egress number

◆ totalIngressFifoNum

uint8 Eth_Udma_CfgType::totalIngressFifoNum

Eth Udma total ingress number

◆ totalTxChanNum

uint8 Eth_Udma_CfgType::totalTxChanNum

Eth Udma total tx channel number

◆ totalRxChanNum

uint8 Eth_Udma_CfgType::totalRxChanNum

Eth Udma total rx channel number

◆ totalFlowNum

uint8 Eth_Udma_CfgType::totalFlowNum

Eth Udma total flow number

◆ totalProxyNum

uint16 Eth_Udma_CfgType::totalProxyNum

Eth Udma total proxy number

◆ txCoreIrq

uint16 Eth_Udma_CfgType::txCoreIrq

Eth Udma TX Core Irq number

◆ rxCoreIrq

uint16 Eth_Udma_CfgType::rxCoreIrq

Eth Udma RX Core Irq number

◆ rxMtuLength

uint16 Eth_Udma_CfgType::rxMtuLength

Eth Rx MTU length

◆ EthDmaRingCfgOps

Eth_DmaRingCfg Eth_Udma_CfgType::EthDmaRingCfgOps

Ring DMA configure function

◆ ethfwRpcComChId

uint32 Eth_VirtualMacConfigType::ethfwRpcComChId

CddIpc Communication channel

◆ remoteVirtPort

EthRemoteCfg_VirtPort Eth_VirtualMacConfigType::remoteVirtPort

eth remote virtual port

◆ rpcCmdComplete

Eth_RpcCmdComplete Eth_VirtualMacConfigType::rpcCmdComplete

Callback to inidcate completion of prior Eth_dispatchVirtmacXXX API

◆ pollRecvMsgInEthMain

boolean Eth_VirtualMacConfigType::pollRecvMsgInEthMain

Flag to enable Eth Rpc recv msg polling in Eth_main

◆ fwRegisteredCb

Eth_RpcFwRegistered Eth_VirtualMacConfigType::fwRegisteredCb

App Callback invoked on ethernet firmware registration is done

◆ txChannelPair

EthVirtMacDmaTxChannelPair Eth_VirtualMacConfigType::txChannelPair

App API to pair TX channel with PSIL thread

◆ txChannelUnPair

EthVirtMacDmaTxChannelUnPair Eth_VirtualMacConfigType::txChannelUnPair

App API to unpair TX channel with PSIL thread

◆ dmaFLowCfg

EthVirtMacDmaFLowCfg Eth_VirtualMacConfigType::dmaFLowCfg

App API to config DMA flow

◆ dmaFLowReset

EthVirtMacDmaFLowReset Eth_VirtualMacConfigType::dmaFLowReset

App API to reset DMA flow

◆ hwTimerId

uint8 Eth_HwTimerConfigType::hwTimerId

hw timer id

◆ hwTimerCounter

uint32 Eth_HwTimerConfigType::hwTimerCounter

hw timer counter

◆ hwTimerBaseAddr

uint32 Eth_HwTimerConfigType::hwTimerBaseAddr

hw timer base address

◆ ctrlIdx

uint32 Eth_ControlerConfigType::ctrlIdx

Controller index

◆ enetType

Eth_EnetType Eth_ControlerConfigType::enetType

CPSW Type identifier

◆ macPort

Eth_PortType Eth_ControlerConfigType::macPort

In native MAC mode ethDriver supports control of only one MAC port

◆ macAddrHigh

uint32 Eth_ControlerConfigType::macAddrHigh

4 high bytes Mac address

◆ macAddrLow

uint32 Eth_ControlerConfigType::macAddrLow

2 low bytes Mac address

◆ useDefaultMac

boolean Eth_ControlerConfigType::useDefaultMac

use default Mac

◆ connType

Eth_MacConnectionType Eth_ControlerConfigType::connType

MII connection type

◆ loopback

boolean Eth_ControlerConfigType::loopback

Loopback enable

◆ hwLoopTimeout

uint32 Eth_ControlerConfigType::hwLoopTimeout

hardware loop timeout

◆ enableTxIrq

boolean Eth_ControlerConfigType::enableTxIrq

enable tx IRQ

◆ enableRxIrq

boolean Eth_ControlerConfigType::enableRxIrq

enable Rx IRQ

◆ isPacketMemCacheable

boolean Eth_ControlerConfigType::isPacketMemCacheable

Packet memory is cacheable

◆ isRingMemCacheable

boolean Eth_ControlerConfigType::isRingMemCacheable

Ring memory is cacheable

◆ isDescMemCacheable

boolean Eth_ControlerConfigType::isDescMemCacheable

Descriptor memory is cacheable

◆ enableVirtualMac

boolean Eth_ControlerConfigType::enableVirtualMac

Enable Virtual MAC mode of operation

◆ demEventNum

uint16 Eth_ControlerConfigType::demEventNum

Dem event configuration number

◆ enableRxIrqPacing

boolean Eth_ControlerConfigType::enableRxIrqPacing

enable tx IRQ pacing

◆ enableTxIrqPacing

boolean Eth_ControlerConfigType::enableTxIrqPacing

enable Rx IRQ pacing

◆ totalHwTimerNum

uint8 Eth_ControlerConfigType::totalHwTimerNum

Eth total hardware number

◆ rxHwTimerIdx

uint8 Eth_ControlerConfigType::rxHwTimerIdx

Rx Hardware timer Idx

◆ txHwTimerIdx

uint8 Eth_ControlerConfigType::txHwTimerIdx

Tx Hardware timer Idx

◆ virtualMacCfg

Eth_VirtualMacConfigType* Eth_ControlerConfigType::virtualMacCfg

Virtual MAC config

◆ demEventCfg

uint16* Eth_ControlerConfigType::demEventCfg

DEM list pointer

◆ cpswCfg

Eth_CpswConfigType* Eth_ControlerConfigType::cpswCfg

Cpsw configuration pointer

◆ dmaCfgPtr

Eth_Udma_CfgType* Eth_ControlerConfigType::dmaCfgPtr

Cpsw configuration pointer

◆ hwTimerCfgPtr

Eth_HwTimerConfigType* Eth_ControlerConfigType::hwTimerCfgPtr

Hardware timer configuration pointer

◆ hwTimerDynPtr

boolean* Eth_ControlerConfigType::hwTimerDynPtr

Hardware timer dynamic data pointer

◆ mdioWriteLowDelayNsec

Eth_MdioDelayNsecFunc Eth_ControlerConfigType::mdioWriteLowDelayNsec

Write low signal delay in nanoseconds

◆ mdioWriteHighDelayNsec

Eth_MdioDelayNsecFunc Eth_ControlerConfigType::mdioWriteHighDelayNsec

Write high signal delay in nanoseconds

◆ mdioReadLowDelayNsec

Eth_MdioDelayNsecFunc Eth_ControlerConfigType::mdioReadLowDelayNsec

Read low signal delay in nanoseconds

◆ mdioReadHighDelayNsec

Eth_MdioDelayNsecFunc Eth_ControlerConfigType::mdioReadHighDelayNsec

Read low signal delay in nanoseconds

◆ pControler

Eth_ControlerConfigType* Eth_ConfigType::pControler[2]

Controller pointer list

◆ Eth_Udma_RingCfg_0

const Eth_Udma_RingCfgType Eth_Udma_RingCfg_0[6U]

extern

◆ Eth_EventCfg_Ctrl_0

const Eth_Udma_EventCfgType Eth_EventCfg_Ctrl_0[2U]

extern

◆ Eth_RingEventCfg_Ctrl_0

const Eth_Udma_RingEventCfgType Eth_RingEventCfg_Ctrl_0[2U]

extern

Introduction

Data Structures

Variables

Macros

Macro Definition Documentation

◆ ETH_VERSION_INFO_API

◆ ETH_GLOBALTIMESUPPORT_API

◆ ETH_DEV_ERROR_DETECT

◆ ETH_GET_COUNTER_VALUES_API

◆ ETH_GET_RX_STATS_API

◆ ETH_GET_TX_STATS_API

◆ ETH_GET_TX_ERROR_COUNTERSVALUES_API

◆ ETH_ZERO_COPY_API

◆ ETH_HEADER_ACCESS_API

◆ ETH_TRAFFIC_SHAPING_API

◆ ETH_GET_COUNTER_STATE_API

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP

◆ ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP

◆ ETH_REGISTER_READBACK_API

◆ ETH_TIMESTAMP_VIA_CPTS_EVENT_FIFO

◆ ETH_PHY_FAULT_DETECTION_ENABLE

◆ ETH_ENABLE_MII_API

◆ ETH_UPDATE_PHYS_ADDR_FILTER_API

◆ ETH_ENABLE_IRQ_PACING

◆ ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API

◆ ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API

◆ ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API

◆ ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API

◆ ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API

◆ ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API

◆ ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API

◆ ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API

◆ ETH_VIRTUALMAC_DEL_MACADDR_API

◆ ETH_VIRTUALMAC_ADD_VLAN_API

◆ ETH_VIRTUALMAC_DEL_VLAN_API

◆ ETH_ETHIF_CBK_HEADER

◆ ETH_ISR_TYPE

◆ ETH_OS_COUNTER_ID

◆ ETH_OS_COUNTER_FREQ

◆ ETH_INVALID_RING_ID

◆ ETH_INVALID_EVENT_ID

◆ ETH_INVALID_CHAN_ID

◆ ETH_INVALID_FLOW_ID

◆ ETH_INVALID_IRQ_ID

◆ ETH_DEM_NO_EVENT

◆ ETH_VIRTUALMAC_SUPPORT

◆ ETH_VIRTUALMAC_FWINFO_TIMEOUT

◆ EthConf_EthCtrlConfig_EthConfig_0

◆ ETH_CTRL_ID_0

◆ ETH_PRE_COMPILE_VARIANT

◆ ETH_LINK_TIME_VARIANT

◆ ETH_POST_BUILD_VARIANT

◆ ETH_CTRL_ID_MAX

◆ NOP1

◆ NOP5

◆ NOP10

◆ NOP20

◆ NOP30

◆ NOP40

◆ NOP50

◆ NOP100

◆ NOP200

◆ NOP300

◆ NOP400

◆ NOP500

◆ ETH_DMA_IR_SUPPORT

◆ ETH_DMA_CQ_RING_SUPPORT

◆ ETH_DMA_TEARDOWN_SUPPORT

◆ ETH_DMA_PROXY_SUPPORT

◆ ETH_DMA_RX_CH_SPERATE

◆ UDMA_DEVICE_ID_RING

◆ UDMA_DEVICE_ID_UDMA

◆ UDMA_DEVICE_ID_PSIL

◆ UDMA_DEVICE_ID_IA

◆ UDMA_DEVICE_ID_IR

◆ UDMA_DEVICE_ID_CORE

◆ UDMA_DEVICE_ID_PROXY

◆ UDMA_TX_CHANNEL_PEER_OFFSET