100#define ETH_ISR_VOID (0x00U)
102#define ETH_ISR_CAT1 (0x01U)
104#define ETH_ISR_CAT2 (0x02U)
117#define ETH_START_SEC_ISR_CODE
118#include "Eth_MemMap.h"
139#if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID)
141#elif (ETH_ISR_TYPE == ETH_ISR_CAT2)
164#if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID)
166#elif (ETH_ISR_TYPE == ETH_ISR_CAT2)
189#if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID)
214#if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID)
220#if (ETH_CTRL_ID_MAX > 0)
240#if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID)
241FUNC(
void, ETH_CODE_FAST) Eth_RxIrqHdlr_1(
void);
266#if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID)
267FUNC(
void, ETH_CODE_FAST) Eth_TxIrqHdlr_1(
void);
291#if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID)
292FUNC(
void, ETH_CODE_FAST) Eth_RxIrqPacingHdlr_1(
void);
294ISR(Eth_RxIrqPacingHdlr_1);
316#if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID)
317FUNC(
void, ETH_CODE_FAST) Eth_TxIrqPacingHdlr_1(
void);
319ISR(Eth_TxIrqPacingHdlr_1);
341#if (STD_ON == ETH_ENABLE_MII_API)
342#if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID)
344#elif (ETH_ISR_TYPE == ETH_ISR_CAT2)
349#define ETH_STOP_SEC_ISR_CODE
350#include "Eth_MemMap.h"
void Eth_MdioIrqHdlr(void)
ISR for MDIO interrupts of all controllers.
void Eth_RxIrqPacingHdlr_0(void)
ISR for RX pacing interrupts of the indexed controller 0.
void Eth_TxIrqPacingHdlr_0(void)
ISR for TX pacing interrupts of the indexed controller 0.
void Eth_TxIrqHdlr_0(void)
ISR for frame transmission interrupts of the indexed controller 0.
void Eth_RxIrqHdlr_0(void)
ISR for frame reception interrupts of the indexed controller 0.