- Attention
- See also FreeRTOS, NO RTOS for list of CPU specific supported and unsupported features.
Features Supported
- Register a interrupt callback to a specific CPU number
- Ability to pass user specific argument to the interrupt callback
- Enable, disable, restore and clear specific CPU interrupts
- Enable, disable, restore global CPU interrupt
- For ARM R5,
- Ability to specify interrupt as FIQ or IRQ, level or pulse
- Ability to specify interrupt priority
Features NOT Supported
See also FreeRTOS, NO RTOS for list of unsupported features.
Important Usage Guidelines
- For ARM R5,
- TI VIM is the interrupt controller that is supported.
- HwiP_disable, HwiP_restore, HwiP_enable only affect state of IRQ. FIQ state is not changed
- Refer ARMv7-R Architecture reference manual and SOC TRM for more details.
- On AM65X,
CPU type | Valid interrupt numbers | Valid interrupt priorities |
R5F | 0 .. 511 | 0 (highest) .. 15 (lowest) |
Example Usage
Include the below file to access the APIs,
Example ISR,
void myISR(void *args)
{
}
Example to register a ISR for CPU interrupt 10,
Example to disable and restore interrupts across a crtical section
API
APIs for HW Interrupts