HW Interrupts

Table of Contents

• Features Supported
• Features NOT Supported
• Important Usage Guidelines
• Example Usage
• API

Attention

See also FreeRTOS, NO RTOS for list of CPU specific supported and unsupported features.

Features Supported

• Register a interrupt callback to a specific CPU number
• Ability to pass user specific argument to the interrupt callback
• Enable, disable, restore and clear specific CPU interrupts
• Enable, disable, restore global CPU interrupt
• For ARM R5,
  • Ability to specify interrupt as FIQ or IRQ, level or pulse
  • Ability to specify interrupt priority
• For ARM M4,
  • Ability to specify interrupt priority
  • Ability to specify systick ISR and NVIC external interrupt ISR
• For ARM A53,
  • Ability to specify interrupt priority
  • Nested Interrupts
  • Ability to specify interrupt as level or pulse

Features NOT Supported

See also FreeRTOS, NO RTOS for list of unsupported features.

Important Usage Guidelines

• For ARM R5,
  • TI VIM is the interrupt controller that is supported.
  • HwiP_disable, HwiP_restore, HwiP_enable only affect state of IRQ. FIQ state is not changed
  • To enable save/restore FPU context in FIQ, uncomment macro EN_SAVE_RESTORE_FPU_CONTEXT in source/kernel/dpl/HwiP.h (Disabled by default)
  • Refer ARMv7-R Architecture reference manual and SOC TRM for more details.
• For ARM M4,
  • ARM NVIC is the interrupt controller that is supported.
  • Interrupt numbers 0 to 15 are for internal interrupts, like reset (1), NMI (2), fault handlers (3-6), SVC (11), PendSV (14), SysTick (15)
  • Interrupt numbers 16 to 80 are used as external NVIC interrupts. The TRM will document M4F interrupt numbers as xxx_M4FSSx_COREx_NVIC_IN_n. This corresponds to interrupt number (16 + n) at NVIC and (16 + n) is used as input to the HwiP APIs
  • Refer ARMv7-M Architecture reference manual and SOC TRM for more details.
• For ARM A53,
  • GIC V3 is the interrupt controller that is supported.
  • Interrupt numbers 0-15 are for SGI, 16-31 for PPI and 32-255 for SPI.
  • Refer ARMv8-A Architecture reference manual and SOC TRM for more details.
• On AM64X,

  CPU type	Valid interrupt numbers	Valid interrupt priorities
  R5F	0 .. 511	0 (highest) .. 15 (lowest)
  M4F	15 .. 79	0 (highest) .. 7 (lowest)
  A53	0 .. 255	0 (highest) .. 14 (lowest)

• Note

  For ARM A53, the effective lowest usable interrupt priority is 14 (not 15). The GIC Priority Mask Register (ICC_PMR_EL1) is initialized to 15 in HwiP_init, which masks all interrupts at priority level 15 or lower. Therefore, priority 15 should not be used.

Example Usage

Include the below file to access the APIs,

#include <stdio.h>
#include <kernel/dpl/HwiP.h>

Example ISR,

void myISR(void *args)
{
    /* my ISR */
}

Example to register a ISR for CPU interrupt 10,

    HwiP_Params hwiParams;
    HwiP_Object hwiObj;
 
    HwiP_Params_init(&hwiParams);
    /* for R5F, interrupt #10 at VIM */
    hwiParams.intNum = 10; 
    /* for M4F, external interrupt #10 at NVIC is 
       16 internal interrupts + external interrupt number at NVIC 
       i.e hwiParams.intNum = 16 + 10; 
     */
    hwiParams.callback = myISR;
    hwiParams.args = NULL;
 
    HwiP_construct(&hwiObj, &hwiParams);

Example to disable and restore interrupts across a crtical section

    uintptr_t oldIntState;
 
    oldIntState = HwiP_disable();
 
    /* critical section */
 
    HwiP_restore(oldIntState);

API

APIs for HW Interrupts