Introduction
This example shows a simple application, which setups the CPU and the underlying RTOS or no-RTOS environment on the supported SOC.
The example does the below
- Setup a timer with system tick of 1ms, setup MPU and cache (if available)
- Create a RTOS task (in RTOS example)
- Trigger a ISR and signal a semaphore from ISR to main task
- Show usage of clock delay
- Show usage of cache APIs
- Show usage of heap APIs
Supported Combinations
- Attention
- A53 NORTOS, A53 FREERTOS and A53 FREERTOS SMP support is experimental and is NOT supported by TI.
Parameter | Value |
CPU + OS | r5fss0-0 nortos |
r5fss0-0 freertos |
m4fss0-0 nortos |
m4fss0-0 freertos |
a53ss0-0 nortos |
a53ss0-0 freertos |
a53ss0-0 freertos-smp |
Toolchain | ti-arm-clang |
arm.gnu.aarch64-none |
Board | am64x-evm, am64x-sk |
Example folder | examples/kernel/dpl/dpl_demo/ |
Steps to Run the Example
See Also
Driver Porting Layer (DPL)
Sample Output
Shown below is a sample output when the application is run,
[DPL] Hwi post ...
[DPL] Hwi post ... DONE !!!
[DPL] Sleep for 100 msecs ...
[DPL] Sleep ... DONE (Measured time = 100000 usecs, CPU cycles = 80000055 ) !!!
[DPL] Running cache operations ...
[DPL] Running cache operations ... DONE !!!
[DPL] Heap free size = 1984 bytes
[DPL] Allocated 1023 bytes @ 0x80010440, heap free size = 896 bytes
[DPL] Free'ed 1023 bytes @ 0x80010440, heap free size = 1984 bytes
All tests have passed!