62 #include <drivers/hw_include/cslr.h>
63 #include <drivers/hw_include/cslr_gpio.h>
79 #define GPIO_PIN_LOW (0U)
81 #define GPIO_PIN_HIGH (1U)
89 #define GPIO_DIRECTION_OUTPUT (0U)
90 #define GPIO_DIRECTION_INPUT (1U)
99 #define GPIO_TRIG_TYPE_NONE (0U)
101 #define GPIO_TRIG_TYPE_RISE_EDGE (1U)
103 #define GPIO_TRIG_TYPE_FALL_EDGE (2U)
105 #define GPIO_TRIG_TYPE_BOTH_EDGE (3U)
109 #define GPIO_MAX_BANKS (9U)
111 #define GPIO_MAX_PIN_PER_BANK (16U)
113 #define GPIO_MAX_PIN_PER_INSTANCE (GPIO_MAX_BANKS * GPIO_MAX_PIN_PER_BANK)
116 #define GPIO_BANKS_PER_REG (2U)
118 #define GPIO_PINS_PER_REG (GPIO_BANKS_PER_REG * GPIO_MAX_PIN_PER_BANK)
121 #define GPIO_PINS_PER_REG_SHIFT (5U)
123 #define GPIO_PINS_PER_BANK_SHIFT (4U)
126 #define GPIO_GET_BANK_INDEX(pinNum) (((uint32_t) pinNum) >> GPIO_PINS_PER_BANK_SHIFT)
128 #define GPIO_GET_REG_INDEX(pinNum) (((uint32_t) pinNum) >> GPIO_PINS_PER_REG_SHIFT)
130 #define GPIO_GET_BIT_POS(pinNum) (pinNum - ((GPIO_GET_REG_INDEX(pinNum)) << GPIO_PINS_PER_REG_SHIFT))
132 #define GPIO_GET_BIT_MASK(pinNum) (((uint32_t) 1U) << GPIO_GET_BIT_POS(pinNum))
134 #define GPIO_GET_BANK_BIT_POS(pinNum) (pinNum - ((GPIO_GET_BANK_INDEX(pinNum)) << GPIO_PINS_PER_BANK_SHIFT))
136 #define GPIO_GET_BANK_BIT_MASK(pinNum) (((uint32_t) 1U) << GPIO_GET_BANK_BIT_POS(pinNum))
303 uint32_t intrStatus);
311 uint32_t regIndex, regVal;
312 volatile CSL_GpioRegs* hGpio = (
volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
316 CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIndex].SET_DATA, regVal);
323 uint32_t regIndex, regVal;
324 volatile CSL_GpioRegs* hGpio = (
volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
328 CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIndex].CLR_DATA, regVal);
336 uint32_t regIndex, bitPos;
337 volatile CSL_GpioRegs* hGpio = (
volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
341 intrStatus = CSL_FEXTR(hGpio->BANK_REGISTERS[regIndex].INTSTAT, bitPos, bitPos);
348 uint32_t regIndex, regVal;
349 volatile CSL_GpioRegs* hGpio = (
volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
354 CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIndex].INTSTAT, regVal);
361 uint32_t intrStatus, regIdx = bankNum >> 1U;
362 volatile CSL_GpioRegs* hGpio = (
volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
364 intrStatus = CSL_REG32_RD(&hGpio->BANK_REGISTERS[regIdx].INTSTAT);
369 intrStatus &= 0xFFFFU;
378 uint32_t regIdx = bankNum >> 1U;
379 volatile CSL_GpioRegs* hGpio = (
volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
382 intrStatus &= 0xFFFFU;
387 CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIdx].INTSTAT, intrStatus);