This example generates a 1b and 2b ECC error for DDR from R5. The M4 enables the ESM instances (MAIN ESM0 and MCU ESM0). On generating an ECC error from R5, the M4 receives the interrupt from MCU ESM (through the MAIN ESM error signal output routed to the MCU ESM). On receiving the interrupt M4 signals R5 (via IPC) to take corrective action.
Parameter | Value |
---|---|
CPU + OS | r5fss0-0 nortos |
m4fss0-0 nortos | |
Toolchain | ti-arm-clang |
Board | am64x-evm, am64x-sk |
Example folder | examples/drivers/ddr/ddr_ecc_test_mcu_esm/ |
Shown below is a sample output when the application is run,