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AM64x MCU+ SDK
09.00.00
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47 #ifndef INCLUDE_SDL_ECC_H_
48 #define INCLUDE_SDL_ECC_H_
55 #if defined(SOC_AM263X)
58 #if defined(SOC_AM273X) || defined(SOC_AWR294X)
59 #include <sdl/esm/v1/sdl_esm.h>
61 #if defined(SOC_AM64X) || defined(SOC_AM243X)
74 #if defined(SOC_AM263X)
76 #define SDL_SOC_ECC_AGGR (0U)
77 #define SDL_R5FSS0_CORE0_ECC_AGGR (1U)
78 #define SDL_R5FSS0_CORE1_ECC_AGGR (2U)
79 #define SDL_R5FSS1_CORE0_ECC_AGGR (3U)
80 #define SDL_R5FSS1_CORE1_ECC_AGGR (4U)
81 #define SDL_HSM_ECC_AGGR (5U)
82 #define SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR (6U)
83 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (7U)
84 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (8U)
85 #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (9U)
86 #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (10U)
87 #define SDL_CPSW3GCSS_ECC_AGGR (11U)
88 #define SDL_ECC_MEMTYPE_MAX (SDL_CPSW3GCSS_ECC_AGGR + 1U)
91 #define SDL_R5SS0_CPU0_TCM (0U)
92 #define SDL_R5SS1_CPU0_TCM (1U)
94 #define SDL_R5FSS0_CORE0_ATCM0 (1U)
95 #define SDL_R5FSS0_CORE0_B0TCM0 (3U)
96 #define SDL_R5FSS0_CORE0_B1TCM0 (5U)
98 #define SDL_R5FSS0_CORE1_ATCM1 (2U)
99 #define SDL_R5FSS0_CORE1_B0TCM1 (4U)
100 #define SDL_R5FSS0_CORE1_B1TCM1 (6U)
102 #define SDL_R5FSS1_CORE0_ATCM0 (7U)
103 #define SDL_R5FSS1_CORE0_B0TCM0 (9U)
104 #define SDL_R5FSS1_CORE0_B1TCM0 (11U)
106 #define SDL_R5FSS1_CORE1_ATCM1 (8U)
107 #define SDL_R5FSS1_CORE1_B0TCM1 (10U)
108 #define SDL_R5FSS1_CORE1_B1TCM1 (12U)
110 #define SDL_TPCC0 (2)
113 #if defined(SOC_AM273X) || defined(SOC_AWR294X)
114 #define SDL_R5FSS0_CORE0_ECC_AGGR (0U)
115 #define SDL_R5FSS0_CORE1_ECC_AGGR (1U)
116 #define SDL_MSS_ECC_AGG_MSS (2U)
117 #define SDL_DSS_ECC_AGG (3U)
118 #define SDL_MSS_MCANA_ECC (4U)
119 #define SDL_MSS_MCANB_ECC (5U)
120 #define SDL_CPSW3GCSS_ECC_AGGR (6U)
121 #define SDL_ECC_MEMTYPE_MAX (SDL_CPSW3GCSS_ECC_AGGR + 1U)
123 #define SDL_TCM_PARITY_ATCM0 (1U)
124 #define SDL_TCM_PARITY_ATCM1 (2U)
125 #define SDL_TCM_PARITY_B0TCM0 (3U)
126 #define SDL_TCM_PARITY_B0TCM1 (4U)
127 #define SDL_TCM_PARITY_B1TCM0 (5U)
128 #define SDL_TCM_PARITY_B1TCM1 (6U)
131 #define SDL_TPCC0A (2U)
132 #define SDL_TPCC0B (3U)
133 #define SDL_DSS_TPCCA (4U)
134 #define SDL_DSS_TPCCB (5U)
135 #define SDL_DSS_TPCCC (6U)
138 #if defined(SOC_AM64X) || defined(SOC_AM243X)
139 #define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR (0u)
140 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (1u)
141 #define SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR (2u)
142 #define SDL_ECC_AGGR1 (3u)
143 #define SDL_ECC_AGGR0 (4u)
144 #define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (5u)
145 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (6u)
146 #define SDL_DMASS0_DMSS_AM64_ECCAGGR (7u)
147 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (8u)
148 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (9u)
149 #define SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR (10u)
150 #define SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR (11u)
151 #define SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR (12u)
152 #define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR (13u)
153 #define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR (14u)
154 #define SDL_GICSS0_GIC500SS_1_2_ECC_AGGR (15u)
155 #define SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR (16u)
156 #define SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR (17u)
157 #define SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A__ECC_AGGR (18u)
158 #define SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR (19u)
159 #define SDL_DMSC0_DMSC_LITE_ECC_AGGR_TXMEM (20u)
160 #define SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_TXMEM (21u)
161 #define SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR (22u)
162 #define SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR (23u)
163 #define SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR (24u)
164 #define SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR (25u)
165 #define SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR (26u)
166 #define SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR (27u)
167 #define SDL_MCU_M4FSS0_BLAZAR_ECCAGGR (28u)
168 #define SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR (29u)
169 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM (30u)
170 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM (31u)
171 #define SDL_VTM0_K3VTM_N16FFC_ECCAGGR (32u)
172 #define SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR (33u)
173 #define SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR (34u)
174 #define SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR (35u)
175 #define SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR (36u)
176 #if defined(SOC_AM64X)
177 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0 (37u)
178 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC (38u)
179 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 (39u)
180 #define SDL_ECC_MEMTYPE_MAX (SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 + 1U)
182 #if defined(SOC_AM243X)
183 #define SDL_ECC_MEMTYPE_MAX (SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR + 1U)
190 #if defined(SOC_AM273X) || defined(SOC_AWR294X) || defined(SOC_AM263X)
192 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID)
194 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID)
196 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID)
198 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID)
200 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID)
202 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID)
204 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
207 #if defined(SOC_AM64X) || defined(SOC_AM243X)
208 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID)
210 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_RAM_ID)
212 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_RAM_ID)
214 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_RAM_ID)
216 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_RAM_ID)
218 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_RAM_ID)
220 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
311 typedef struct SDL_ECC_InitConfig_s
324 typedef struct SDL_ECC_InjectErrorConfig_s
338 typedef struct SDL_ECC_ErrorInfo_s
415 uint32_t selfTestTimeOut);
526 uint64_t bitErrorOffset,
527 uint32_t bitErrorGroup);
528 #if defined(SOC_AM263X)
549 int32_t SDL_cleartcmStatusRegs(uint32_t clearVal);
551 #if defined(SOC_AM273X)|| defined(SOC_AWR294X)
571 void SDL_ECC_dss_l2_parity_init(
void);
582 void SDL_ECC_dss_l2_parity_errorInject(uint32_t injectError, uint32_t injectErrAdd, uint32_t
value);
594 void SDL_ECC_DSP_Aggregated_EDC_Errors(uint32_t exception_mask_flag);
603 int32_t SDL_ECC_dss_l1p_edc_CMD_EN(
void);
612 int32_t SDL_ECC_dss_l1p_CMD_SUSP(
void);
621 int32_t SDL_ECC_dss_l2_edc_CMD_EN(
void);
630 int32_t SDL_ECC_dss_l2_CMD_SUSP(
void);
641 void SDL_ECC_IDMA1_transfer(uint32_t srcAddr, uint32_t destAddr);
658 uint32_t paramregvalue,
void(* SDL_ECC_ErrorCallback_t)(uint32_t errorSrc, uint32_t address)
Definition: sdl_ecc.h:297
Definition: sdl_ecc.h:312
int32_t SDL_ECC_initMemory(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType)
Initializes Memory to be ready for ECC error detection. Assumes ECC is already enabled.
SDL_ECC_MemSubType memSubType
Definition: sdl_ecc.h:342
uint32_t numRams
Definition: sdl_ecc.h:313
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
Definition: sdl_ecc.h:253
int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig)
Injects ECC error at specified location Assumes ECC is already enabled.
int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc)
Acknowledge the ECC interrupt.
uint32_t chkGrp
Definition: sdl_ecc.h:330
Header file contains enumerations, structure definitions and function declarations for SDL Error Sign...
uint32_t SDL_Ecc_AggrEDCErrorSubType
This enumerator defines the types of possible EDC errors.
Definition: V1/sdl_ip_ecc.h:190
int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType, SDL_ECC_staticRegs *pStaticRegs)
Gets the static registers for the specified ECC instance.
@ SDL_ECC_AGGR_TYPE_INJECT_ONLY
Definition: sdl_ecc.h:235
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE
Definition: sdl_ecc.h:255
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
Definition: sdl_ecc.h:251
int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig, uint32_t selfTestTimeOut)
Runs self test by injecting and error and monitor response Assumes ECC is already enabled.
uint32_t bitErrorGroup
Definition: sdl_ecc.h:350
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE
Definition: sdl_ecc.h:257
SDL_Ecc_AggrIntrSrc intrSrc
Definition: sdl_ecc.h:344
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT
Definition: sdl_ecc.h:259
Header file contains enumerations, structure definitions and function declarations for SDL COMMON int...
Definition: sdl_ecc.h:325
@ SDL_INJECT_ECC_NO_ERROR
Definition: sdl_ecc.h:249
uint32_t value
Definition: tisci_otp_revision.h:2
uint32_t * pErrMem
Definition: sdl_ecc.h:326
This structure contains the static register group for Ecc aggregator used by the SDL_ecc_aggrReadStat...
Definition: V1/sdl_ip_ecc.h:310
@ SDL_ECC_AGGR_TYPE_FULL_FUNCTION
Definition: sdl_ecc.h:237
void(* SDL_ECC_VIMDEDVector_t)(void)
Definition: sdl_ecc.h:300
SDL_ECC_InjectErrorType
ECC Inject error types.
Definition: sdl_ecc.h:247
int32_t SDL_ECC_initEsm(const SDL_ESM_Inst esmInstType)
Initializes an module for usage with ECC module.
uint64_t bitErrorOffset
Definition: sdl_ecc.h:352
uint32_t flipBitMask
Definition: sdl_ecc.h:328
SDL_ECC_AggregatorType
Definition: sdl_ecc.h:234
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT
Definition: sdl_ecc.h:261
@ SDL_ECC_RAM_ID_TYPE_INTERCONNECT
Definition: sdl_ecc.h:276
uint32_t SDL_Ecc_AggrIntrSrc
This enumerator defines the types of possible ECC errors.
Definition: V1/sdl_ip_ecc.h:181
int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc, SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType)
Retrieves the ECC error information for the specified ESM error. If it isn't an ECC error or the ECC ...
Definition: sdl_ecc.h:339
SDL_ECC_MemSubType * pMemSubTypeList
Definition: sdl_ecc.h:316
uint32_t SDL_ECC_MemSubType
This enumerator indicate ECC memory Sub Type.
Definition: sdl_ecc.h:285
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT
Definition: sdl_ecc.h:263
int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents)
Clears N pending interrupts for the specified memtype, subtype and interrupt source.
uint32_t injectBitErrCnt
Definition: sdl_ecc.h:348
int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_ECC_ErrorInfo_t *pErrorInfo)
Retrieves the ECC error information for the specified memtype and interrupt source.
uint32_t bitErrCnt
Definition: sdl_ecc.h:346
SDL_ECC_MemType eccMemType
Definition: sdl_ecc.h:340
void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType, uint32_t errorSrc, uint32_t address, uint32_t ramId, uint64_t bitErrorOffset, uint32_t bitErrorGroup)
Application provided external callback function for ECC handling Called inside the reference function...
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT
Definition: sdl_ecc.h:265
SDL_ECC_RamIdType
Definition: sdl_ecc.h:273
@ SDL_ECC_RAM_ID_TYPE_WRAPPER
Definition: sdl_ecc.h:274
uint32_t SDL_ECC_MemType
This enumerator indicate ECC memory type.
Definition: sdl_ecc.h:292
int32_t SDL_ECC_init(SDL_ECC_MemType eccMemType, const SDL_ECC_InitConfig_t *pECCInitConfig)
Initializes ECC module for ECC detection.
int32_t SDL_ECC_tpccParity(SDL_ECC_MemType eccMemType, uint32_t bitValue, uint32_t paramregvalue, uint32_t regval)
Injects TPCC Parity error.