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AM64x MCU+ SDK
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66 #define PCIE_MAX_PERIPHS (4U)
72 #define PCIE_MAX_MSI_IRQ (32U)
78 #define PCIE_MAX_MSIX_IRQ (2048U)
485 typedef struct Pcie_BarCfg_s {
510 typedef struct Pcie_IbTransCfg_s {
529 typedef struct Pcie_AtuRegionParams_s
689 uint32_t *vendorId, uint32_t *deviceId);
uint32_t lowerBaseAddr
Definition: pcie/pcie.h:216
Pcie_RegisterMsixIsrParams specifies the parameters to register an ISR for MSIX.
Definition: pcie/pcie.h:263
Pcie_Attrs * attrs
Definition: pcie/pcie.h:416
Pcie_MsixIsr isr
Definition: pcie/pcie.h:265
@ PCIE_EP_MODE
Definition: pcie/pcie.h:89
@ PCIE_LTSSM_CFG_LINKWD_ACEPT
Definition: pcie/pcie.h:446
uint32_t upperBaseAddr
Definition: pcie/pcie.h:197
@ PCIE_LTSSM_CFG_COMPLETE
Definition: pcie/pcie.h:449
@ PCIE_LTSSM_LPBK_ENTRY
Definition: pcie/pcie.h:464
void * cfgBase
Definition: pcie/pcie.h:116
Pcie_Config gPcieConfig[]
Externally defined driver configuration array.
uint32_t lowerTargetAddr
Definition: pcie/pcie.h:222
uint8_t barxc
Definition: pcie/pcie.h:501
PCIe atributes.
Definition: pcie/pcie.h:323
@ PCIE_BAR_RSVD
Definition: pcie/pcie.h:140
Pcie_IbAtuCfg specifies the Inbound ATU configurations for PCIe.
Definition: pcie/pcie.h:210
uint32_t barCfg
Definition: pcie/pcie.h:228
uint16_t size
Definition: tisci_boardcfg.h:1
uint32_t barNumber
Definition: pcie/pcie.h:545
@ PCIE_LTSSM_RCVRY_EQ3
Definition: pcie/pcie.h:473
@ PCIE_LTSSM_RCVRY_IDLE
Definition: pcie/pcie.h:454
Pcie_AtuRegionMatchMode matchMode
Definition: pcie/pcie.h:541
uint32_t lowerTargetAddr
Definition: pcie/pcie.h:565
@ PCIE_TLP_TYPE_MEM
Definition: pcie/pcie.h:170
void Pcie_close(Pcie_Handle handle)
Function to close PCIe peripheral specified by PCIe handle.
uint32_t ibOffsetAddr
Definition: pcie/pcie.h:518
PCIe MSIx table entry.
Definition: pcie/pcie.h:300
uint32_t upperTargetAddr
Definition: pcie/pcie.h:203
Pcie_Mode operationMode
Definition: pcie/pcie.h:327
int32_t Pcie_LtssmCtrl(Pcie_Handle handle, uint8_t enable)
Enable/disable PCIe link training.
@ PCIE_TLP_TYPE_CFG
Definition: pcie/pcie.h:172
uint32_t intNum
Definition: pcie/pcie.h:256
@ PCIE_LTSSM_RCVRY_SPEED
Definition: pcie/pcie.h:452
@ PCIE_LTSSM_LPBK_EXIT_TIMEOUT
Definition: pcie/pcie.h:467
uint16_t index
Definition: tisci_rm_proxy.h:3
The Pcie_DeviceCfg is used to specify device level configuration of the driver instance.
Definition: pcie/pcie.h:114
@ PCIE_LTSSM_HOT_RESET_ENTRY
Definition: pcie/pcie.h:468
PCIe device configuration.
Definition: pcie/pcie.h:389
Pcie_BarType
These are the possible values for Type BAR configuration.
Definition: pcie/pcie.h:138
Definition: pcie/pcie.h:310
uint32_t upperBaseAddr
Definition: pcie/pcie.h:218
Inbound traslation configuration info The Pcie_IbTransCfg is used to configure the Inbound Translatio...
Definition: pcie/pcie.h:510
@ PCIE_LTSSM_L1_IDLE
Definition: pcie/pcie.h:458
@ PCIE_LTSSM_RCVRY_LOCK
Definition: pcie/pcie.h:451
@ PCIE_ATU_REGION_DIR_OUTBOUND
Definition: pcie/pcie.h:160
uint8_t barxa
Definition: pcie/pcie.h:503
Pcie_MsixTbl * epMsixTbl
Definition: pcie/pcie.h:361
uint32_t msiRingNum
Definition: pcie/pcie.h:343
Pcie_ObAtuCfg * obAtu
Definition: pcie/pcie.h:333
uint32_t regionIndex
Definition: pcie/pcie.h:212
Pcie_BarMem memSpace
Definition: pcie/pcie.h:497
@ PCIE_ATU_REGION_MATCH_MODE_BAR
Definition: pcie/pcie.h:182
@ PCIE_LTSSM_LPBK_EXIT
Definition: pcie/pcie.h:466
uint32_t upperTargetAddr
Definition: pcie/pcie.h:224
Pcie_AtuRegionDir
Enum to select PCIe ATU(Address translation unit) region direction(Inbound or Outbound)....
Definition: pcie/pcie.h:159
int32_t Pcie_setLanes(Pcie_Handle handle)
Set number of PCIe lanes as configured.
Pcie_TlpType
This enum is used to select PCIe TLP(Transaction layer packet) type while configuring inbound or outb...
Definition: pcie/pcie.h:169
uint32_t lowerBaseAddr
Definition: pcie/pcie.h:550
Pcie_BarPref
These are the possible values for Prefetch BAR configuration.
Definition: pcie/pcie.h:129
@ PCIE_TLP_TYPE_IO
Definition: pcie/pcie.h:171
int32_t Pcie_cfgEP(Pcie_Handle handle)
Configure Pcie for EP (End Point) operation. PCIe mode setting is NOT done here (Pcie_setInterfaceMod...
@ PCIE_LTSSM_DETECT_WAIT
Definition: pcie/pcie.h:444
Pcie_Location
Enumeration for PCIe access type remote/local.
Definition: pcie/pcie.h:428
Pcie_MsiIsr isr
Definition: pcie/pcie.h:247
@ PCIE_LTSSM_DISABLED_IDLE
Definition: pcie/pcie.h:462
@ PCIE_LTSSM_POLL_CONFIG
Definition: pcie/pcie.h:442
void(* Pcie_MsixIsr)(void *arg, uint32_t msixData)
Function pointer for the PCIe MSIx ISR.
Definition: pcie/pcie.h:239
@ PCIE_GEN3
Definition: pcie/pcie.h:101
#define PCIE_MAX_MSI_IRQ
Maximum PCIe MSI interrupts supported.
Definition: pcie/pcie.h:72
@ PCIE_LEGACY_EP_MODE
Definition: pcie/pcie.h:90
uint32_t regionWindowSize
Definition: pcie/pcie.h:220
Pcie_DeviceCfgBaseAddr * Pcie_handleGetBases(Pcie_Handle handle)
Get the device base address info for the PCIe peripheral.
@ PCIE_LTSSM_CFG_IDLE
Definition: pcie/pcie.h:450
Pcie_DeviceCfgBaseAddr * bases
Definition: pcie/pcie.h:376
uint32_t msiGlobalEventNum
Definition: pcie/pcie.h:341
void * arg
Definition: pcie/pcie.h:267
PCIe BAR configuration info.
Definition: pcie/pcie.h:485
uint32_t msixRingNum
Definition: pcie/pcie.h:355
uint32_t ibStartAddrHi
Definition: pcie/pcie.h:516
int32_t Pcie_setInterfaceMode(Pcie_Handle handle, Pcie_Mode mode)
Set interfac mode (RC/EP)
@ PCIE_BAR_MEM_IO
Definition: pcie/pcie.h:150
Pcie_LtssmState
Enumeration for possible values for encoding LTSSM state.
Definition: pcie/pcie.h:437
@ PCIE_BAR_TYPE64
Definition: pcie/pcie.h:141
uint32_t regionWindowSize
Definition: pcie/pcie.h:560
Pcie_TlpType tlpType
Definition: pcie/pcie.h:535
Pcie_BarType type
Definition: pcie/pcie.h:495
@ PCIE_LTSSM_LPBK_ACTIVE
Definition: pcie/pcie.h:465
uint32_t ibStartAddrLo
Definition: pcie/pcie.h:514
Pcie_Handle Pcie_open(uint32_t index)
This function opens a given PCIe peripheral.
@ PCIE_LTSSM_PRE_DETECT_QUIET
Definition: pcie/pcie.h:443
@ PCIE_BAR_MEM_MEM
Definition: pcie/pcie.h:149
@ PCIE_BAR_NON_PREF
Definition: pcie/pcie.h:130
Pcie_Mode
These are the possible values for PCIe mode.
Definition: pcie/pcie.h:88
@ PCIE_LTSSM_L2_IDLE
Definition: pcie/pcie.h:459
uint32_t vector_ctrl
Definition: pcie/pcie.h:306
@ PCIE_LTSSM_RCVRY_RCVRCFG
Definition: pcie/pcie.h:453
@ PCIE_LTSSM_DISABLED_ENTRY
Definition: pcie/pcie.h:461
PCIe MSI Isr control structure.
Definition: pcie/pcie.h:280
uint32_t intNum
Definition: pcie/pcie.h:274
uint32_t msixIntNum
Definition: pcie/pcie.h:357
void * devParams
Definition: pcie/pcie.h:122
uint8_t * msiRingMem
Definition: pcie/pcie.h:351
@ PCIE_GEN2
Definition: pcie/pcie.h:100
@ PCIE_RC_MODE
Definition: pcie/pcie.h:91
uint32_t dataReserved
Definition: pcie/pcie.h:120
PCIe configuration for initalization.
Definition: pcie/pcie.h:401
Pcie_Gen
Enumeration for PCIE generations.
Definition: pcie/pcie.h:98
uint32_t msixGlobalEventNum
Definition: pcie/pcie.h:353
This Structure defines the ATU region parameters.
Definition: pcie/pcie.h:530
uint32_t upperTargetAddr
Definition: pcie/pcie.h:570
int32_t Pcie_getMemSpaceReserved(Pcie_Handle handle, uint32_t *resSize)
Pcie_getMemSpaceReserved returns amount of reserved space between beginning of hardware's data area a...
Pcie_ObAtuCfg specifies the Outbound ATU configurations for PCIe.
Definition: pcie/pcie.h:189
uint32_t msixIrqEnableFlag
Definition: pcie/pcie.h:359
@ PCIE_LOCATION_REMOTE
Definition: pcie/pcie.h:430
uint32_t obAtuNum
Definition: pcie/pcie.h:335
int32_t Pcie_atuRegionConfig(Pcie_Handle handle, Pcie_Location location, uint32_t atuRegionIndex, const Pcie_AtuRegionParams *atuRegionParams)
Configure address translation registers.
uint32_t deviceNum
Definition: pcie/pcie.h:325
@ PCIE_LTSSM_DETECT_QUIET
Definition: pcie/pcie.h:438
void * arg
Definition: pcie/pcie.h:249
Pcie_AtuRegionDir regionDir
Definition: pcie/pcie.h:531
#define PCIE_MAX_PERIPHS
Maximum PCIe devices supported by the driver.
Definition: pcie/pcie.h:66
void * dataBase
Definition: pcie/pcie.h:118
uint32_t lowerTargetAddr
Definition: pcie/pcie.h:201
int32_t Pcie_cfgRC(Pcie_Handle handle)
Configure Pcie for RC (Root Complex) operation. PCIe mode setting is NOT done here (Pcie_setInterface...
int32_t Pcie_cfgBar(Pcie_Handle handle, const Pcie_BarCfg *barCfg)
Configure a BAR Register (32 bits)
Pcie_TlpType tlpType
Definition: pcie/pcie.h:193
@ PCIE_LTSSM_DISABLED
Definition: pcie/pcie.h:463
@ PCIE_GEN1
Definition: pcie/pcie.h:99
Pcie_Gen gen
Definition: pcie/pcie.h:329
uint32_t base
Definition: pcie/pcie.h:491
int32_t Pcie_waitLinkUp(Pcie_Handle handle)
Wait for PCIe link training to complete.
@ PCIE_LTSSM_CFG_LINKWD_START
Definition: pcie/pcie.h:445
@ PCIE_LTSSM_CFG_LANENUM_WAIT
Definition: pcie/pcie.h:447
char mode[32]
Definition: tisci_pm_core.h:1
@ PCIE_ATU_REGION_DIR_INBOUND
Definition: pcie/pcie.h:161
void(* Pcie_MsiIsr)(void *arg, uint32_t msiData)
Function pointer for the PCIe MSI ISR.
Definition: pcie/pcie.h:234
uint32_t regionIndex
Definition: pcie/pcie.h:191
uint8_t * msixRingMem
Definition: pcie/pcie.h:365
Pcie_RegisterMsiIsrParams specifies the parameters to register an ISR for MSI.
Definition: pcie/pcie.h:245
uint32_t regionWindowSize
Definition: pcie/pcie.h:199
@ PCIE_LTSSM_L0
Definition: pcie/pcie.h:455
uintptr_t addr
Definition: pcie/pcie.h:302
@ PCIE_LTSSM_POLL_COMPLIANCE
Definition: pcie/pcie.h:441
Pcie_Location location
Definition: pcie/pcie.h:487
uint32_t lowerBaseAddr
Definition: pcie/pcie.h:195
uint8_t idx
Definition: pcie/pcie.h:499
uint32_t gPcieConfigNum
Externally defined driver configuration array size.
int32_t Pcie_checkLinkParams(Pcie_Handle handle)
Verify if the link parameters is established as configured.
uint32_t numLanes
Definition: pcie/pcie.h:331
uint8_t region
Definition: pcie/pcie.h:520
uint32_t ibAtuNum
Definition: pcie/pcie.h:339
@ PCIE_LOCATION_LOCAL
Definition: pcie/pcie.h:429
void * Pcie_Handle
Driver handle returned by Pcie_open() call.
Definition: pcie/pcie.h:107
uint32_t msiIrqEnableFlag
Definition: pcie/pcie.h:347
Pcie_Object * object
Definition: pcie/pcie.h:415
ISR and arguement list for MSIx.
Definition: pcie/pcie.h:290
Pcie_MsiIsrCtrl * msiIsrCtrl
Definition: pcie/pcie.h:349
@ PCIE_LTSSM_L2_WAKE
Definition: pcie/pcie.h:460
uint32_t barAperture
Definition: pcie/pcie.h:226
PCIE global configuration array.
Definition: pcie/pcie.h:414
#define PCIE_MAX_MSIX_IRQ
Maxmium number of MSIx interrupts supported.
Definition: pcie/pcie.h:78
@ PCIE_BAR_PREF
Definition: pcie/pcie.h:131
Pcie_TlpType tlpType
Definition: pcie/pcie.h:214
@ PCIE_LTSSM_L0S
Definition: pcie/pcie.h:456
PCIe driver object.
Definition: pcie/pcie.h:372
Pcie_MsixIsrCtrl * msixIsrCtrl
Definition: pcie/pcie.h:363
Pcie_Mode mode
Definition: pcie/pcie.h:489
uint32_t msiIntNum
Definition: pcie/pcie.h:345
Pcie_DeviceCfg dev
Definition: pcie/pcie.h:403
@ PCIE_BAR_TYPE32
Definition: pcie/pcie.h:139
uint8_t ibBar
Definition: pcie/pcie.h:512
@ PCIE_LTSSM_CFG_LANENUM_ACEPT
Definition: pcie/pcie.h:448
@ PCIE_LTSSM_RCVRY_EQ0
Definition: pcie/pcie.h:470
Pcie_AtuRegionMatchMode
Enum to select address or BAR match mode.
Definition: pcie/pcie.h:180
int32_t Pcie_getMemSpaceRange(Pcie_Handle handle, void **base, uint32_t *size)
Returns the PCIe Internal Address Range for the memory space. This range is used for accessing memory...
Pcie_BarMem
These are the possible values for Memory BAR configuration.
Definition: pcie/pcie.h:148
Pcie_Handle handle
Definition: pcie/pcie.h:374
@ PCIE_ATU_REGION_MATCH_MODE_ADDR
Definition: pcie/pcie.h:181
@ PCIE_LTSSM_RCVRY_EQ1
Definition: pcie/pcie.h:471
void Pcie_init(void)
This function initializes the PCIe module.
uint32_t upperBaseAddr
Definition: pcie/pcie.h:555
uint32_t enableRegion
Definition: pcie/pcie.h:539
Pcie_BarPref prefetch
Definition: pcie/pcie.h:493
@ PCIE_LTSSM_L123_SEND_EIDLE
Definition: pcie/pcie.h:457
Pcie_IbAtuCfg * ibAtu
Definition: pcie/pcie.h:337
@ PCIE_LTSSM_RCVRY_EQ2
Definition: pcie/pcie.h:472
int32_t Pcie_getVendorId(Pcie_Handle handle, Pcie_Location location, uint32_t *vendorId, uint32_t *deviceId)
Get vendor ID and device ID of Pcie Device.
@ PCIE_LTSSM_HOT_RESET
Definition: pcie/pcie.h:469
@ PCIE_LTSSM_POLL_ACTIVE
Definition: pcie/pcie.h:440
uint32_t data
Definition: pcie/pcie.h:304
uint32_t cfgDone
Definition: pcie/pcie.h:378
@ PCIE_LTSSM_DETECT_ACT
Definition: pcie/pcie.h:439