sdl_ecc.h

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/*
 * SDL ECC
 *
 * Software Diagnostics Library module for ECC
 *
 *  Copyright (c) Texas Instruments Incorporated 2022-2023
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
 
#ifndef INCLUDE_SDL_ECC_H_
#define INCLUDE_SDL_ECC_H_
 
#include <stdint.h>
#include <stdbool.h>
 
#include "sdl_common.h"
#include <sdl/ecc/sdl_ip_ecc.h>
#if defined(SOC_AM263X)
#include <sdl/esm/v0/sdl_esm.h>
#endif
#if defined(SOC_AM273X) || defined(SOC_AWR294X)
#include <sdl/esm/v1/sdl_esm.h>
#endif
#if defined(SOC_AM64X) || defined(SOC_AM243X)
#include <sdl/esm/v0/sdl_esm.h>
#endif
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef enum {
    SDL_ECC_AGGR_TYPE_INJECT_ONLY = 1,
    SDL_ECC_AGGR_TYPE_FULL_FUNCTION = 2,
} SDL_ECC_AggregatorType;
 
 
typedef enum {
    SDL_INJECT_ECC_NO_ERROR = 0,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE = 1,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE = 2,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE = 3,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE = 4,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT = 5,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT = 6,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT = 7,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT = 8,
} SDL_ECC_InjectErrorType;
 
 
typedef enum {
    SDL_ECC_RAM_ID_TYPE_WRAPPER = 0,
    SDL_ECC_RAM_ID_TYPE_INTERCONNECT = 1,
} SDL_ECC_RamIdType;
 
typedef uint32_t SDL_ECC_MemType;
 
#if defined(SOC_AM263X)
 
#define SDL_SOC_ECC_AGGR                                            (0U)
#define SDL_R5FSS0_CORE0_ECC_AGGR                                   (1U)
#define SDL_R5FSS0_CORE1_ECC_AGGR                                   (2U)
#define SDL_R5FSS1_CORE0_ECC_AGGR                                   (3U)
#define SDL_R5FSS1_CORE1_ECC_AGGR                                   (4U)
#define SDL_HSM_ECC_AGGR                                            (5U)
#define SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR                         (6U)
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (7U)
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (8U)
#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (9U)
#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (10U)
#define SDL_CPSW3GCSS_ECC_AGGR                                      (11U)
#define SDL_ECC_MEMTYPE_MAX                                         (SDL_CPSW3GCSS_ECC_AGGR + 1U)
 
/* Parity */
#define SDL_R5SS0_CPU0_TCM          (0U)
#define SDL_R5SS1_CPU0_TCM          (1U)
/* SDL_R5SS0_CPU0_TCM */
#define SDL_R5FSS0_CORE0_ATCM0      (1U)
#define SDL_R5FSS0_CORE0_B0TCM0     (3U)
#define SDL_R5FSS0_CORE0_B1TCM0     (5U)
/* SDL_R5SS0_CPU10_TCM */
#define SDL_R5FSS0_CORE1_ATCM1      (2U)
#define SDL_R5FSS0_CORE1_B0TCM1     (4U)
#define SDL_R5FSS0_CORE1_B1TCM1     (6U)
/* SDL_R5SS1_CPU0_TCM */
#define SDL_R5FSS1_CORE0_ATCM0      (7U)
#define SDL_R5FSS1_CORE0_B0TCM0     (9U)
#define SDL_R5FSS1_CORE0_B1TCM0     (11U)
/* SDL_R5SS1_CPU1_TCM */
#define SDL_R5FSS1_CORE1_ATCM1      (8U)
#define SDL_R5FSS1_CORE1_B0TCM1     (10U)
#define SDL_R5FSS1_CORE1_B1TCM1     (12U)
/* TPCC */
#define SDL_TPCC0                   (2)
#endif
 
#if defined(SOC_AM273X) || defined(SOC_AWR294X)
#define SDL_R5FSS0_CORE0_ECC_AGGR                                   (0U)
#define SDL_R5FSS0_CORE1_ECC_AGGR                                   (1U)
#define SDL_MSS_ECC_AGG_MSS                                         (2U)
#define SDL_DSS_ECC_AGG                                             (3U)
#define SDL_MSS_MCANA_ECC                                           (4U)
#define SDL_MSS_MCANB_ECC                                           (5U)
#define SDL_CPSW3GCSS_ECC_AGGR                                      (6U)
#define SDL_ECC_MEMTYPE_MAX                                         (SDL_CPSW3GCSS_ECC_AGGR + 1U)
/* TCM PARITY */
#define SDL_TCM_PARITY_ATCM0        (1U)
#define SDL_TCM_PARITY_ATCM1        (2U)
#define SDL_TCM_PARITY_B0TCM0       (3U)
#define SDL_TCM_PARITY_B0TCM1       (4U)
#define SDL_TCM_PARITY_B1TCM0       (5U)
#define SDL_TCM_PARITY_B1TCM1       (6U)
 
/* TPCC */
#define SDL_TPCC0A          (2U)
#define SDL_TPCC0B          (3U)
#define SDL_DSS_TPCCA       (4U)
#define SDL_DSS_TPCCB       (5U)
#define SDL_DSS_TPCCC       (6U)
#endif
 
#if defined(SOC_AM64X) || defined(SOC_AM243X)
#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR                                                                                               (0u)
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM                                                                                               (1u)
#define SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR                                                                                         (2u)
#define SDL_ECC_AGGR1                                                                                                                   (3u)
#define SDL_ECC_AGGR0                                                                                                                   (4u)
#define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR                                                                                              (5u)
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR                                                                                             (6u)
#define SDL_DMASS0_DMSS_AM64_ECCAGGR                                                                                                        (7u)
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM                                                                                               (8u)
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR                                                                                         (9u)
#define SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR                                                                                   (10u)
#define SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR                                                                                   (11u)
#define SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR                                                                                             (12u)
#define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR                                                                                        (13u)
#define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR                                                                                       (14u)
#define SDL_GICSS0_GIC500SS_1_2_ECC_AGGR                                                                                            (15u)
#define SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR                                                                                        (16u)
#define SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR                                                                                       (17u)
#define SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A__ECC_AGGR                                                                       (19u)
#define SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR                                                                                               (19u)
#define SDL_DMSC0_DMSC_LITE_ECC_AGGR_TXMEM                                                                                            (20u)
#define SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_TXMEM                                                                                       (21u)
#define SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR                                                                                           (22u)
#define SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR                                                                                             (23u)
#define SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR                                                                                             (24u)
#define SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR                                                                                         (25u)
#define SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR                                                                                           (26u)
#define SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR                                                                                   (27u)
#define SDL_MCU_M4FSS0_BLAZAR_ECCAGGR                                                                                                   (28u)
#define SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR                                                                                                 (29u)
#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM                                                                           (30u)
#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM                                                                           (31u)
#define SDL_VTM0_K3VTM_N16FFC_ECCAGGR                                                                                     (32u)
#define SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR                                                                              (33u)
#define SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR                                                                              (34u)
#define SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR                                                                              (35u)
#define SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR                                                                              (36u)
#if defined(SOC_AM64X)
#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0               (37u)
#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC             (38u)
#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1               (39u)
#define SDL_ECC_MEMTYPE_MAX                                                                                               (SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 + 1U)
#endif
#if defined(SOC_AM243X)
#define SDL_ECC_MEMTYPE_MAX                                                                                               (SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR + 1U)
#endif
#endif
 
/* The following are the memory sub type for Memory type
   SDL_ECC_MEMTYPE_MCU_R5F0_CORE & SDL_ECC_MEMTYPE_MCU_R5F1_CORE */
/* Keeping for backward-compatibility. Recommend to use RAM_ID directly from sdlr_soc_ecc_aggr.h file */
#if defined(SOC_AM273X) || defined(SOC_AWR294X) || defined(SOC_AM263X)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
#endif
 
#if defined(SOC_AM64X) || defined(SOC_AM243X)
#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_RAM_ID)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
#endif
 
typedef uint32_t SDL_ECC_MemSubType;
 
typedef void (*SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address);
 
typedef void (*SDL_ECC_VIMDEDVector_t) (void);
 
 
typedef struct SDL_ECC_InitConfig_s
{
    uint32_t numRams;
    SDL_ECC_MemSubType *pMemSubTypeList;
} SDL_ECC_InitConfig_t;
 
typedef struct SDL_ECC_InjectErrorConfig_s
{
    uint32_t *pErrMem;
    uint32_t flipBitMask;
    uint32_t chkGrp;
}  SDL_ECC_InjectErrorConfig_t;
 
typedef struct SDL_ECC_ErrorInfo_s
{
    SDL_ECC_MemType eccMemType;
    SDL_ECC_MemSubType memSubType;
    SDL_Ecc_AggrIntrSrc intrSrc;
    uint32_t bitErrCnt;
    uint32_t injectBitErrCnt;
    uint32_t bitErrorGroup;
    uint64_t bitErrorOffset;
} SDL_ECC_ErrorInfo_t;
 
int32_t SDL_ECC_initEsm (const SDL_ESM_Inst esmInstType);
 
int32_t SDL_ECC_init (SDL_ECC_MemType eccMemType,
                        const SDL_ECC_InitConfig_t *pECCInitConfig);
 
int32_t SDL_ECC_initMemory (SDL_ECC_MemType eccMemType,
                               SDL_ECC_MemSubType memSubType);
 
int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType,
                            SDL_ECC_MemSubType memSubType,
                            SDL_ECC_InjectErrorType errorType,
                            const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig,
                            uint32_t selfTestTimeOut);
 
int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType,
                               SDL_ECC_MemSubType memSubType,
                               SDL_ECC_InjectErrorType errorType,
                               const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig);
 
int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType,
                                   SDL_ECC_staticRegs *pStaticRegs);
 
int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType,
                                SDL_Ecc_AggrIntrSrc intrSrc,
                                SDL_ECC_ErrorInfo_t *pErrorInfo);
 
int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType,
                        SDL_Ecc_AggrIntrSrc intrSrc);
 
int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc,
                                SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType);
 
int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType,
                                  SDL_Ecc_AggrIntrSrc intrSrc,
                                  SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents);
 
void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType,
                                         uint32_t errorSrc,
                                         uint32_t address,
                                         uint32_t ramId,
                                         uint64_t bitErrorOffset,
                                         uint32_t bitErrorGroup);
#if defined(SOC_AM263X)
 
int32_t SDL_ECC_tcmParity(SDL_ECC_MemType eccMemType,
                              SDL_ECC_MemSubType memSubType,
                              uint32_t bitValue);
int32_t SDL_cleartcmStatusRegs(uint32_t clearVal);
#endif
#if defined(SOC_AM273X)|| defined(SOC_AWR294X)
 
int32_t SDL_ECC_tcmParity(SDL_ECC_MemSubType memSubType,
                              uint32_t bitValue);
#endif
 
 
int32_t SDL_ECC_tpccParity(SDL_ECC_MemType eccMemType,
                              uint32_t bitValue,
                              uint32_t paramregvalue,
                              uint32_t regval);
 
#ifdef __cplusplus
}
#endif  /* extern "C" */
 
#endif